Method for fabricating a semiconductor-on-insulator structure for radio frequency applications

Abstract

Method for manufacturing a semiconductor-on-insulator structure for radio frequency applications. The present invention relates to a method for manufacturing a semiconductor-on-insulator structure (10), the method comprising the steps of: - providing an FD-SOI substrate (1) which, from its bottom to its top, comprises in sequence: a single-crystal substrate (2) having a resistivity between 500 Ω.cm and 30 kΩ.cm, an interstitial oxygen content (Oi) between 20 at.ppma and 40 at.ppma, and having an N-type doping or a P-type doping; an electrically insulating layer (3) having a thickness between 20 nm and 400 nm; a single-crystal layer (4) having a P-type doping; - heat-treating the FD-SOI substrate (1) at a temperature greater than or equal to 1175 °C for a time greater than or equal to 1 hour to form a P-N junction (5) in the substrate. The present invention also relates to such a semiconductor-on-insulator structure.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor-on-insulator structure, in particular for radio frequency applications. The present invention also relates to a semiconductor-on-insulator structure obtained by implementing this method. Background Art

[0002] A semiconductor-on-insulator structure is a multi-layer structure that includes a substrate typically made of silicon, an electrically insulating layer (usually an oxide layer such as a silicon oxide layer) disposed on the substrate, and a semiconductor layer (usually a silicon layer) disposed on the insulating layer.

[0003] When the semiconductor material is silicon, such a structure is called a "semiconductor-on-insulator" structure (SeOI), in particular "silicon-on-insulator" (SOI).

[0004] In existing SOI structures, a structure called a "fully depleted silicon-on-insulator" (FD-SOI) structure is commonly used for digital applications. The FD-SOI structure is characterized by the presence of a thin oxide layer disposed on a silicon support substrate and a very thin semiconductor layer disposed on the oxide layer, called the SOI layer.

[0005] The oxide layer is located between the substrate and the SOI layer. The oxide layer is then called "buried", and the "buried oxide" is called "BOX".

[0006] The SOI layer allows the formation of a conductive channel in the FD-SOI structure.

[0007] Due to the low thickness and uniformity of the BOX layer and the SOI layer, the conductive channel does not need to be doped, so the structure can operate in a fully depleted mode.

[0008] Compared with a structure without a BOX layer, the FD-SOI structure has improved electrostatic characteristics. The BOX layer reduces the parasitic capacitance between the source and the drain, and also allows significant reduction of any electron leakage from the conductive channel to the substrate by restricting the electron flow in the conductive channel, thereby reducing any current loss and improving the performance capabilities of the structure.

[0009] The FD-SOI structure is compatible with radio frequency (RF) applications, but still suffers from electrical losses occurring in the substrate.

[0010] To compensate for these electrical losses and improve the RF performance capabilities, it is known to use a substrate with a high resistivity, in particular a substrate of the SOI type, which is commonly called an "HR substrate" (high resistivity substrate). This HR substrate is advantageously combined with a charge trapping layer (or "rich well layer").

[0011] However, this type of substrate is not compatible with transistors having a threshold voltage (back-bias voltage) that must be controlled through the back gate. In fact, the presence of this layer containing trapped charges hinders reverse biasing (applying a potential difference to the back side).

[0012] The scientific publication entitled "Low loss Si-substrates enhanced using buried PN junctions for RF Applications" (M. Rack, L. Nyssens, and J-P. Raskin, IEEE Electron device letters, Vol. 40, No. 5) describes the formation of P-N junctions laterally disposed below the electrically insulating layer of a substrate intended for RF applications.

[0013] Lateral is understood to mean that two regions doped P and N respectively are disposed at the same depth in the substrate, where the junction between said regions is substantially perpendicular to the main surface of the substrate. Such a junction is obtained by implanting phosphorus throughout the substrate for N-type doping, then locally implanting boron through a mask in order to form the P-doped region, and then performing a heat treatment to activate the dopants.

[0014] Although doped semiconductors are good conductors, the junction allows almost no current to pass through, thus preventing the propagation of parasitic electric fields.

[0015] As described in the scientific publication, one drawback resulting from the lateral arrangement of the P-N junction is that it requires a photolithography step for forming the mask and two implantation steps, which represent significant additional costs. Summary of the Invention

[0016] The object of the present invention is to propose a method for manufacturing a semiconductor-on-insulator structure that allows overcoming the above-mentioned drawbacks.

[0017] The object of the present invention is to propose such a manufacturing method for an FD-SOI structure having good RF performance capabilities.

[0018] To this end, the present invention proposes a method for manufacturing a semiconductor-on-insulator structure, the method comprising the following steps:

[0019] - Providing an FD-SOI substrate, the FD-SOI substrate comprising, from its bottom to its top, in sequence:

[0020] · A single-crystal semiconductor substrate having a resistivity in the range between 500 Ω.cm and 30 kΩ.cm, an interstitial oxygen content in the range between 20 old (old) ppma and 40 old ppma, and having a first P-type doping or a first N-type doping;

[0021] · An electrical insulating layer having a thickness in the range of 20 nm and 400 nm;

[0022] ● A single-crystalline semiconductor layer having a P-type doping;

[0023] - Heat-treating the FD-SOI substrate at a temperature greater than or equal to 1175 °C for a time greater than or equal to 1 hour to form a P-N junction at a determined depth in the single-crystalline semiconductor substrate relative to the electrical insulating layer in such a way that

[0024] · By diffusing P-type dopants from the single-crystalline semiconductive layer through the electrical insulating layer in the substrate; and

[0025] · If the substrate has a P-type doping, forming thermal donors in the substrate by precipitation of interstitial oxygen;

[0026] To form a first N-type doped region extending between the bottom of the substrate and the P-N junction and a second P-doped region located between the first region and the electrical insulating layer in the substrate.

[0027] The main technique for measuring interstitial oxygen in silicon of a semiconductor substrate is infrared absorption using Fourier Transform Infrared (FTIR) spectroscopy.

[0028] FTIR measurements provide an absorption coefficient α due to interstitial oxygen OX value. According to the method specifically described in the literature entitled “A Study of Oxygen Precipitation in Heavily Doped Silicon” (1989), Graupner, Robert Kurt, Dissertations and Theses, Thesis 1218, based on this absorption coefficient α OX to calculate the interstitial oxygen concentration.

[0029] According to this method, by multiplying the absorption coefficient α OX by a conversion factor to obtain an oxygen concentration that is part of the total number of atoms in atoms per cm 3 cubed (at / cm3) or in parts per million by atoms (ppma).

[0030] The oxygen concentration (old ppma) mentioned in the present invention is obtained by using the first of the four conversion factors given in the following list, called “old ASTM” (American Society for Testing), expressed as ppma:

[0031]

[0032] According to other aspects, the manufacturing method of the present invention has the following different features, either individually or according to their technically possible combinations:

[0033] - The single-crystal substrate is made of silicon and / or the single-crystal layer is a silicon layer;

[0034] - The FD-SOI substrate is obtained by transferring a layer of a donor substrate to a recipient substrate according to the following steps:

[0035] - Supply:

[0036] · A donor substrate, the donor substrate including a single-crystal semiconductor layer with P-type doping, and a weakening zone located in the single-crystal silicon layer, the weakening zone defining the layer to be transferred; and

[0037] · A single-crystal semiconductor recipient substrate, the single-crystal semiconductor recipient substrate having a resistivity ranging between 500 Ω·cm and 30

[0038] kΩ·cm, an interstitial oxygen content ranging between 20 at.ppm and 40 at.ppm, and P-type doping or N-type doping;

[0039] - Bonding the donor substrate to the recipient substrate through an electrically insulating layer, the thickness of the electrically insulating layer ranging between 20 nm and 400 nm;

[0040] - Separating the donor substrate along the weakening zone to form the FD-SOI substrate;

[0041] - The FD-SOI substrate is obtained by transferring a layer of a donor substrate to a recipient substrate according to the following steps:

[0042] - Supply:

[0043] ● A donor substrate, the donor substrate including a single-crystal semiconductor layer with P-type doping; and

[0044] ● A single-crystal semiconductor recipient substrate, the single-crystal semiconductor recipient substrate having a resistivity ranging between 500 Ω·cm and 30

[0045] kΩ·cm, an interstitial oxygen content ranging between 20 at.ppm and 40 at.ppm, and P-type doping or N-type doping;

[0046] - Bonding the donor substrate to the recipient substrate through an electrically insulating layer, the thickness of the electrically insulating layer ranging between 20 nm and 400 nm;

[0047] - Thinning the donor substrate from the surface opposite to the receiving substrate to form a transfer layer, so as to obtain the FD-SOI substrate;

[0048] - The embrittlement zone is formed by implanting atomic species in the donor substrate to define the transfer layer;

[0049] - The single crystal layers of the receiving substrate and the donor substrate are P-doped with boron;

[0050] - The P-N junction is formed at a depth ranging from 1 μm to 5 μm from the electrical insulating layer;

[0051] - The electrical insulating layer includes a silicon oxide layer.

[0052] The present invention also relates to a semiconductor-on-insulator structure, which is directly obtained by implementing the manufacturing method as described above, wherein the semiconductor-on-insulator structure sequentially includes from its bottom to its top:

[0053] - A single crystal semiconductor substrate having a resistivity ranging from 500 Ω·cm to 30 kΩ·cm, an interstitial oxygen content ranging from 20 at.ppm to 40 at.ppm, and including:

[0054] ● A first region including N-type doping; and

[0055] ● A second region disposed on the first region, including P-type doping, and the second region is separated from the first region by a P-N junction;

[0056] - An electrical insulating layer;

[0057] - A single crystal semiconductor layer including P-type doping.

[0058] According to other aspects, the structure of the present invention has the following different features individually or according to their technically possible combinations:

[0059] - The single crystal semiconductor layer is P-doped with boron;

[0060] - The P-N junction is located at a depth ranging from 1 μm to 5 μm from the electrical insulating layer;

[0061] - The electrical insulating layer includes a silicon oxide layer;

[0062] - The single crystal substrate is made of silicon and / or the single crystal layer is a silicon layer. Description of the Drawings

[0063] Other advantages and features of the present invention will become apparent upon reading the following description with reference to the following drawings, which are provided by way of illustrative and non-limiting examples, wherein:

[0064] - Figure 1 is a view of an FD-SOI substrate;

[0065] - Figure 2 is a view of a semiconductor-on-insulator structure including a P-N junction according to the present invention;

[0066] - Figure 3 is a view illustrating the doping inversion of a portion of a single-crystal substrate having a high resistivity;

[0067] - Figure 4 is a view illustrating the diffusion of dopants from a single-crystal layer through an underlying electrically insulating layer;

[0068] - Figure 5A is a view illustrating the formation of a embrittlement zone by implanting atomic species in a donor substrate according to a first embodiment;

[0069] - Figure 5B is a view illustrating the bonding of a donor substrate to a receiving substrate according to a first embodiment;

[0070] - Figure 5C is a view illustrating the detachment of the donor substrate along the embrittlement zone and the transfer of the layer from the donor substrate to the receiving substrate according to a first embodiment;

[0071] - Figure 6A is a view illustrating the bonding of a donor substrate to a receiving substrate according to a second embodiment;

[0072] - Figure 6B is a view illustrating the thinning of the donor substrate from the surface opposite to the receiving substrate to form a transfer layer;

[0073] - Figure 7 is a graph of the gain HD2 of a semiconductor-on-insulator structure having a P-N junction or not having a P-N junction in a substrate having a high resistivity;

[0074] - Figure 8 is a graph of the gain S21 of a semiconductor-on-insulator structure having a P-N junction or not having a P-N junction in a substrate having a high resistivity;

[0075] - Figure 9 is a graph of the resistivity of a semiconductor-on-insulator structure having a P-N junction or not having a P-N junction in a substrate having a high resistivity. Detailed Description

[0076] The present invention relates to a method for manufacturing a semiconductor-on-insulator structure and such a structure.

[0077] The manufacturing method of the present invention allows for the fabrication of a semiconductor-on-insulator structure that includes a P-N junction conferring good radio-frequency characteristics to the structure and is carried out in a simple and inexpensive manner.

[0078] An FD-SOI substrate (schematically shown using reference numeral 1 in Figure 1 the drawings) is initially provided, which substrate comprises, from its bottom to its top, a single-crystal semiconductor substrate 2, an electrically insulating layer 3, and a single-crystal semiconductive layer 4 in sequence.

[0079] The single-crystal substrate 2 is a substrate having a high resistivity and thus has a resistivity in the range between 500 Ω.cm and 30 kΩ.cm.

[0080] Furthermore, the single-crystal substrate 2 is a substrate having a large amount of oxygen and thus has an interstitial oxygen content (Oi) in the range between 20 at.ppma and 40 at.ppma. The oxygen is trapped in the structure of the single-crystal substrate, more specifically in the interstices located between the grains of the material forming the single-crystal substrate, and is thus referred to as "interstitial oxygen".

[0081] The single-crystal substrate having a high resistivity and a large amount of interstitial oxygen is also referred to as an HR HiOi (which is a combination of the abbreviations for "high resistivity" and "high oxygen") substrate.

[0082] Preferably, the single-crystal substrate is made of silicon.

[0083] The single-crystal substrate has P-type doping or N-type doping.

[0084] In the case of N-type doping, the single-crystal substrate 2 is preferably doped with phosphorus, and more preferably, the single-crystal substrate is made of silicon doped with phosphorus.

[0085] In the case of P-type doping, the single-crystal substrate 2 is preferably doped with boron, and more preferably, the single-crystal substrate is made of silicon doped with boron.

[0086] The thickness of the electrically insulating layer 3 (also referred to as the BOX layer since it is disposed between the underlying single-crystal substrate 2 and the overlying single-crystal layer 4) is in the range between 20 nm and 400 nm.

[0087] Preferably, the electrically insulating layer 3 comprises a silicon oxide layer.

[0088] The single-crystal layer 3 has P-type doping.

[0089] Preferably, the single-crystal layer is a silicon layer.

[0090] According to the method of the present invention, the FD-SOI substrate is heat-treated at a temperature of greater than or equal to 1175 °C for a time of greater than or equal to 1 hour.

[0091] During said heat treatment, a P-N junction (reference numeral 5) is formed in the single-crystalline substrate 2 at a defined depth relative to the electrically insulating layer 3, as Figure 2 illustrated.

[0092] More specifically, the heat treatment results in the following phenomena.

[0093] On the one hand, the P-type dopants of the single-crystalline layer diffuse into the single-crystalline substrate through the electrically insulating layer in the region of the substrate adjacent to the electrically insulating layer.

[0094] On the other hand, when the single-crystalline substrate is P-doped, the doping type in the single-crystalline substrate 2 is inverted.

[0095] Combining these two phenomena creates in the substrate a region 6 called the first region, which extends from the base of the single-crystalline substrate to the P-N junction and is N-doped due to the inversion of the doping type. The P-N junction then marks the boundary between the first region 6 of the single-crystalline substrate and the remaining region 7 called the second region, which extends from the P-N junction to the electrically insulating layer 3 and remains P-doped, where the diffusion of the P-type dopants in this second region has compensated for the inversion of the doping type.

[0096] When the single-crystalline substrate is N-doped, the above-mentioned phenomenon of diffusion of P-type dopants in the second region occurs. However, the phenomenon of inversion of the doping type does not occur. Therefore, the first region remains N-doped.

[0097] Regardless of the initial doping type of the single-crystalline substrate, at the end of the heat treatment, the single-crystalline substrate includes a P-N junction separating a first N-doped region (adjacent to the base of the substrate) from a second P-doped region (adjacent to the electrically insulating layer).

[0098] Due to the following three characteristics, a P-N junction can be formed:

[0099] - P-doping of the single-crystalline layer 4;

[0100] - The heat treatment temperature is greater than or equal to 1175 °C and the time is greater than or equal to 1 hour; and

[0101] - In the case of a P-type doped single-crystalline substrate, the high interstitial oxygen concentration of the single-crystalline substrate 2.

[0102] The presence of a P-N junction associated with the high resistivity of the single-crystal substrate 2 (ranging between 500 Ω.cm and 30 kΩ.cm) allows obtaining a structure that exhibits very good radio-frequency characteristics. These characteristics will be described throughout the rest of this document. Adjusting these three features allows controlling the formation of the P-N junction, in particular controlling its depth in the single-crystal substrate 2 from the electrical insulation layer 3.

[0103] Adjust the parameters of the method (such as the three features mentioned above) so as to form a P-N junction at a depth ranging between 1 μm and 5 μm from the electrical insulation layer.

[0104] In the case of a P-type single-crystal substrate, heat treatment causes interstitial oxygen precipitation in the single-crystal substrate 2, thus forming sulfur oxide SxOy thermal donors, which have excess charges for doping the material of the single-crystal substrate and thereby invert its doping. The first phenomenon is schematically shown in Figure 3 and Figure 3 the doping of the material of the single-crystal substrate by the thermal donors is shown using an upward vertical arrow 8.

[0105] Furthermore, regardless of whether the single-crystal substrate is N-type doped or P-type doped, heat treatment causes dopants (such as boron) in the single-crystal layer 4 to diffuse through a sufficiently thin electrical insulation layer 3 into the single-crystal substrate 2. These dopants can also be used to control the formation of the P-N junction, in particular controlling its depth in the single-crystal substrate from the electrical insulation layer. The second phenomenon is schematically shown in Figure 4 and Figure 4 the diffusion of the dopants through the electrical insulation layer is shown using a downward vertical arrow 9.

[0106] In the case of a P-type doped single-crystal substrate, the combination of this second phenomenon with the first phenomenon results in the formation of a first region of N-doped substrate and the formation of a second P-doped region located between the first region and the electrical insulation layer, as shown in Figure 2 the semiconductor-on-insulator structure 10 of

[0107] The method of the present invention provides the advantage of allowing these two phenomena to occur due to the three features listed above without the need for additional processing steps. In particular, different from the lateral P-N junctions described in the article by M. Rack et al. mentioned above, forming a P-N junction in the thickness of the substrate in the present invention does not require any local injection of dopants or any mask deposited on the substrate.

[0108] According to a preferred embodiment, an FD-SOI substrate is obtained by transferring a layer of a donor substrate to a receiving substrate.

[0109] According to Figure 5A , Figure 5B and Figure 5CThe first alternative of the embodiment illustrated in Figure 5A is as illustrated.

[0110] The single-crystalline layer 24 to be transferred is preferably a silicon layer.

[0111] The single-crystalline receiving substrate 30, preferably made of silicon, is also provided with a resistivity in the range between 500 Ω·cm and 30 kΩ·cm, an interstitial oxygen content (Oi) in the range between 20 at.ppm and 40 at.ppm, and a P-type or N-type doping.

[0112] Reference Figure 5B is then made, and the donor substrate 20 is bonded to the receiving substrate 30 through an electrically insulating layer 22, the thickness of the electrically insulating layer 22 being in the range between 20 nm and 400 nm. The electrically insulating layer 22 is then located between the donor substrate 20 and the receiving substrate 30.

[0113] The electrically insulating layer 22 can originate from the donor substrate or from the acceptor substrate, i.e., it can initially be located on the donor substrate or on the acceptor substrate before bonding.

[0114] Reference Figure 5C is then made, and the donor substrate 20 is separated along the embrittlement zone 23 to obtain an FD-SOI substrate.

[0115] Preferably, according to the SmartCut TM method, the layer 24 is transferred from the donor substrate 20 to the receiving substrate 30, wherein an embrittlement zone 23 is formed by implanting atomic species such as hydrogen atoms and / or helium atoms into the donor substrate, and then the donor substrate is separated along the embrittlement zone.

[0116] According to Figure 6A and Figure 6B the second alternative of this embodiment as illustrated, a donor substrate 20 is provided that includes a single-crystalline semiconductive layer 21 with P-type doping (preferably a silicon layer).

[0117] The single-crystalline semiconductor layer 21 is preferably a silicon layer.

[0118] The single-crystalline receiving substrate 30, preferably made of silicon, is also provided with a resistivity in the range between 500 Ω·cm and 30 kΩ·cm, an interstitial oxygen content (Oi) in the range between 20 at.ppm and 40 at.ppm, and a P-type doping or an N-type doping.

[0119] Reference Figure 6A, and then the donor substrate 20 is bonded to the acceptor substrate 30 through the electrical insulation layer 22, and the thickness of the electrical insulation layer 22 ranges between 20 nm and 400 nm. The electrical insulation layer 22 is then located between the donor substrate 20 and the acceptor substrate 30.

[0120] The electrical insulation layer 22 can be derived from the donor substrate or from the acceptor substrate, i.e., it can initially be located on the donor substrate or on the acceptor substrate before bonding.

[0121] Reference Figure 6B , and then the donor substrate 20 is thinned from the surface opposite to the acceptor substrate to form the transfer layer 24, so as to obtain the FD - SOI substrate 1.

[0122] Reference attached Figure 7 、 Figure 8 and Figure 9 illustrates the good radio - frequency characteristics of the semiconductor - on - insulator structure obtained by the foregoing method.

[0123] Figure 7 is a graph showing the gain HD2 (dBm) of the semiconductor - on - insulator structure with or without a P - N junction in a substrate having a high resistivity

[0124] The gain HD2 corresponds to the second harmonic measured at a frequency of 900 MHz.

[0125] More specifically, HD2 is the harmonic generated by the substrate, which can interfere with the operation of radio - frequency devices including the structure according to the present invention. The weaker HD2 is, the more insulating the substrate is. HD2 is measured on a coplanar line having an input point and an output point. At the input point, power P in (dBm) is applied, and at the output, power P out is measured, which is decomposed into several harmonics, in particular including HD1 (which corresponds to the power approximately equal to the input power measured at the output) and HD2 (which corresponds to the harmonic generated by the substrate).

[0126] According to Figure 7 the graph, the gain HD2 (curve C1) obtained for the structure including a P - N junction is less than the gain (curve C2) obtained for the structure without a P - N junction. This downward shift of curve C2 relative to curve C1 corresponds to a loss of approximately 10 dBm.

[0127] Therefore, the high - resistivity substrate of the structure with a P - N junction is more electrically insulating than the high - resistivity substrate of the structure without a P - N junction.

[0128] Figure 8 is a graph showing the variation of the gain S21 (dB) of the semiconductor - on - insulator structure with or without a P - N junction with frequency (Hz).

[0129] The gain S21 corresponds to a crosstalk or noise measurement (referred to as "crosstalk"), which reflects the ability of any component to communicate through the substrate compared to other components, and thus represents the insulating performance ability of the substrate.

[0130] According to Figure 8 the graph, between 1e+3 Hz and 1e+8 Hz, a decrease in the gain S21 (curve C3) obtained for the structure including a P-N junction is observed compared to the gain (curve C4) obtained for a junction without a P-N structure. This decrease of curve C4 compared to curve C3 corresponds to a reduced noise.

[0131] Figure 9 is a graph showing the variation of the resistivity (ohm.cm) of a semiconductor-on-insulator structure with or without a P-N junction in a substrate having a high resistivity as a function of frequency (Hz).

[0132] According to Figure 9 the graph, the resistivity (curve C5) obtained for the structure including a P-N junction is greater than the resistivity (curve C6) obtained for the structure without a P-N junction. This downward shift of curve C5 compared to curve C6 corresponds to a loss of approximately 1200 ohm.cm.

[0133] This confirms the fact that the substrate with a high resistivity of the structure having a P-N junction is more electrically insulating than the structure without a P-N junction.

[0134] Therefore, Figure 7 、 Figure 8 and Figure 9 the graphs show that the radio frequency performance ability of the semiconductor-on-insulator structure of the present invention including a P-N junction is significantly improved compared to the structure without a P-N junction.

Claims

1. A method for manufacturing a semiconductor-on-insulator structure, the method comprising the steps of: - Providing an FD-SOI substrate, the FD-SOI substrate comprising, from its bottom to its top, in sequence: · A single-crystalline semiconductor substrate having a resistivity in the range of 500 Ω.cm and 30 kΩ.cm, an interstitial oxygen content in the range of 20 at.ppma and 40 at.ppma, and having a first P-type doping or a first N-type doping; · An electrically insulating layer having a thickness in the range of 20 nm and 400 nm; · A single-crystalline semiconductor layer having a P-type doping; - Heat-treating the FD-SOI substrate at a temperature greater than or equal to 1175 °C for a time greater than or equal to 1 hour to form a P-N junction in the single-crystalline semiconductor substrate at a determined depth relative to the electrically insulating layer in the following manner, i.e., · By diffusing P-type dopants from the single-crystalline semiconductor layer through the electrically insulating layer in the FD-SOI substrate; and · If the single-crystalline semiconductor substrate has a P-type doping, forming thermal donors in the single-crystalline semiconductor substrate by precipitation of interstitial oxygen; To form a first region having an N-type doping extending between the bottom of the single-crystalline semiconductor substrate and the P-N junction and a second region having a P-type doping located between the first region and the electrically insulating layer in the single-crystalline semiconductor substrate.

2. The method according to claim 1, wherein The single-crystalline semiconductor substrate is made of silicon and / or the single-crystalline semiconductor layer is a silicon layer.

3. The method according to claim 1 or claim 2, wherein The FD-SOI substrate is obtained by transferring a layer to be transferred of a donor substrate to a receiving substrate according to the following steps: - Supplying: · The donor substrate, the donor substrate comprising a single-crystalline semiconductor layer having a P-type doping, and a brittle region located in the single-crystalline semiconductor layer, the brittle region defining the layer to be transferred; And · A single-crystalline semiconductor receiving substrate having a resistivity in the range of 500 Ω.cm and 30 kΩ.cm, an interstitial oxygen content in the range of 20 at.ppma and 40 at.ppma, and a first P-type doping or a first N-type doping; - Bonding the donor substrate to the receiving substrate through an electrically insulating layer having a thickness in the range of 20 nm and 400 nm; - Separating the donor substrate along the brittle region to form the FD-SOI substrate.

4. The method according to claim 1 or claim 2, wherein The FD-SOI substrate is obtained by transferring a transfer layer of a donor substrate to a receiving substrate according to the following steps: - Supplying: · The donor substrate, the donor substrate comprising a single-crystalline semiconductor layer having a P-type doping; And · A single-crystalline semiconductor receiving substrate having a resistivity in the range of 500 Ω.cm and 30 kΩ.cm, an interstitial oxygen content in the range of 20 at.ppma and 40 at.ppma, and a P-type doping or an N-type doping; - Bonding the donor substrate to the acceptor substrate through an electrically insulating layer, the thickness of the electrically insulating layer ranging between 20 nm and 400 nm; - Thinning the donor substrate from the surface opposite to the acceptor substrate to form a transfer layer to obtain the FD - SOI substrate.

5. The method according to claim 3, wherein The embrittlement region is formed by implanting atomic species in the donor substrate to define the layer to be transferred.

6. The method according to claim 3, wherein The single - crystal semiconductor layers of the acceptor substrate and the donor substrate are P - doped with boron.

7. The method according to claim 1 or claim 2, wherein The P - N junction is formed at a depth ranging between 1 µm and 5 µm from the electrically insulating layer.

8. The method according to claim 1 or claim 2, wherein The electrically insulating layer includes a silicon oxide layer.

9. A semiconductor-on-insulator structure directly obtained by implementing the method according to any one of claims 1 to 8, wherein, The semiconductor - on - insulator structure includes, from its bottom to its top, in sequence: - A single - crystal semiconductor substrate having a resistivity ranging between 500 Ω.cm and 30 kΩ.cm, an interstitial oxygen content ranging between 20 old ppma and 40 old ppma, and including: · A first region including N - type doping; and · A second region disposed on the first region, including P - type doping, the second region being separated from the first region by a P - N junction; - An electrically insulating layer; - A single - crystal semiconductor layer including P - type doping.

10. The semiconductor-on-insulator structure according to claim 9, wherein, The single - crystal semiconductor layer is P - doped with boron.

11. The semiconductor-on-insulator structure according to claim 9 or claim 10, wherein, The P - N junction is located at a depth ranging between 1 µm and 5 µm from the electrically insulating layer.

12. The semiconductor-on-insulator structure according to claim 9 or claim 10, wherein, The electrically insulating layer includes a silicon oxide layer.

13. The semiconductor-on-insulator structure according to claim 9 or claim 10, wherein The single - crystal semiconductor substrate is made of silicon and / or the single - crystal semiconductor layer is a silicon layer.

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