Housing, optoelectronic semiconductor device, and manufacturing method

Abstract

A housing (2) for an optoelectronic semiconductor device (1) is proposed, which has - a housing body (21) having a chip mounting side (22), - at least two electrical conductor structures (23) in and / or at the housing body (21), and - a plurality of drainage structures (24) at the chip mounting side (22), where - the electrical conductor structures (23) form electrical contact surfaces (25) for at least one optoelectronic semiconductor chip (3) at the chip mounting side (22), and - the drainage structures (24) are configured as a conveying mechanism for a liquid encapsulation material (40) towards the electrical contact surfaces (25).

Description

Technical Field

[0001] A housing for an optoelectronic semiconductor device, an optoelectronic semiconductor device, and a method for manufacturing an optoelectronic semiconductor device are provided. Summary of the Invention

[0002] The object to be achieved is to provide an optoelectronic semiconductor device having high efficiency.

[0003] This object is achieved in particular by a housing, an optoelectronic semiconductor device, and a method for manufacturing an optoelectronic semiconductor device having the features of the present invention. Preferred refinements are the subject matter of the following description.

[0004] In at least one embodiment, a housing for an optoelectronic semiconductor device preferably comprises:

[0005] - A housing body having a chip mounting side,

[0006] - At least two conductor structures, such as electrical leads or conductor frame components, in and / or on the housing body, and

[0007] - A plurality of drainage structures at the chip mounting side,

[0008] wherein

[0009] - The conductor structures form electrical contact surfaces for at least one optoelectronic semiconductor chip at the chip mounting side, and

[0010] - The drainage structures are configured as conveying mechanisms for a preferably liquid encapsulation material towards the electrical contact surfaces.

[0011] Furthermore, an optoelectronic semiconductor device is provided which preferably comprises a housing as described in connection with one or more of the above embodiments. Thus, the features of the optoelectronic semiconductor device are also disclosed for the housing and vice versa.

[0012] In at least one embodiment, the optoelectronic semiconductor device comprises:

[0013] - A housing,

[0014] - At least one optoelectronic semiconductor chip on the electrical contact surfaces, and

[0015] - A reflective encapsulation part formed from a liquid encapsulation material,

[0016] wherein

[0017] - The encapsulation part reaches below at least one optoelectronic semiconductor chip and can preferably expose at least a majority or completely the side surfaces of at least one semiconductor chip.

[0018] Furthermore, a method for manufacturing an optoelectronic semiconductor device is proposed, as described in connection with one or more of the above-described embodiments. Thus, the features of the optoelectronic semiconductor device are also disclosed for the method and vice versa.

[0019] In at least one embodiment, the method is for manufacturing one or more optoelectronic semiconductor devices according to at least one of the above-described embodiments and preferably comprises the following steps, especially in a given order:

[0020] A) Producing a housing,

[0021] B) Mounting at least one optoelectronic semiconductor chip onto an electrical contact surface, and

[0022] C) Establishing an encapsulation,

[0023] wherein

[0024] - applying an encapsulation material for producing the encapsulation in a liquid state in one or more landing zones,

[0025] - one or more landing zones are located next to the optoelectronic semiconductor chip when viewed in a top view,

[0026] - a drainage structure extends through or starts in one or more landing zones, and

[0027] - the encapsulation material reaches the optoelectronic semiconductor chip from one or more landing zones through the drainage structure, especially by means of capillary action.

[0028] Furthermore, a mold, also referred to as a Mold, for manufacturing a housing is proposed, as proposed in connection with one or more of the above-described embodiments. Thus, the features of the housing and the method are also disclosed for the mold and vice versa.

[0029] The housing described herein is especially based on the following technical problem, namely that the third generation 4014_LED of the SYNIOS E4014 family of the manufacturer Osram Opto Semiconductors GmbH, i.e., especially a light-emitting diode, abbreviated as LED, should have a 10% higher efficiency than the second generation.

[0030] In addition to increasing the brightness by using brighter LED chips, the absorption losses in the LED package should also be consistently reduced. For this purpose, the loss chain for the generated light is determined by means of multiple measurements and optical simulations. For example, it has been determined that white TiO 2 The encapsulation reflects better than white epoxy molding compound, abbreviated as EMC.

[0031] When the ESD protection diode is not in the TiO 2When hidden beneath the thick layer formed by the encapsulation part, the ESD protection diode also absorbs light. ESD stands for ElectroStatic Discharge, i.e., electrostatic discharge. It is also known that gold wires absorb light. Metal surfaces, even those with a silver coating, absorb light and thus should be covered with TiO of the same thickness 2 by the encapsulation part. It is also known that large flat surfaces can hardly be covered with a TiO 2 encapsulation layer because the TiO 2 carrying silicone resin extends upward at the chip edge and the housing edge and only forms a small layer thickness on the exposed surface.

[0032] It is also known that the reflective wall close to the LED chip absorbs more light and ages faster than the reflective wall farther from the chip. It has also been determined that a flat reflective wall reflects better than a steep one. Accordingly, it can be achieved that an LED chip with a fixed preset size centered in a symmetric chamber emits more light from the device than when the chip is placed asymmetrically.

[0033] In particular, the underside of a sapphire LED chip is specularly reflective, yet usually not up to the outermost edge. If a sapphire LED chip is placed on a metal pad, then the conductor frame made of metal, also referred to as LDF metal, absorbs a part of the light emitted from the chip at the edge. Therefore, it is advantageously achieved that the underside of the chip is wetted with TiO 2 silicone resin at the non-specularly reflective part. And the side surface of the sapphire chip should preferably not be wetted with TiO 2 encapsulation part because adverse retroreflection will occur in the LED chip. The solder for fixing the semiconductor chip is preferably surrounded by a reflective encapsulation part in the circumferential direction in the lateral direction, especially in direct contact.

[0034] The following LED design is described here, which allows the chip edge on the underside to be completely wetted with a TiO 2 silicone resin encapsulation part and exposes the side surface of the chip here.

[0035] The following embodiments preferably relate to a sapphire LED flip chip, which is sufficiently ESD-stable and which neither requires an ESD protection diode nor connection wires, but is soldered. Differently, however, other LED chips can also be used.

[0036] As an alternative to the design described here, the flip chip is placed on a closed frame made of epoxy molding compound, abbreviated as EMC. The applied TiO 2 silicone resin then does not reach beneath the chip but waits at the frame. This particularly brings the following disadvantages:

[0037] - The solder is encapsulated and the flux cannot evaporate freely.

[0038] - The solder paste can be quenched and solder balls can be generated.

[0039] - The EMC is not as good as TiO 2 The silicone resin is so reflective.

[0040] - Optical simulations show that optically it is advantageous for the solder to be encapsulated opaquely. This is not achieved with the EMC frame.

[0041] - The flux residue under the LED chip cannot be cleaned well due to the frame.

[0042] The designs described here for the housing and for the semiconductor device achieve beneficial effects especially through the following technical features, where the technical features can be implemented individually, in any combination or all together:

[0043] - There is a defined TiO 2 Injection landing area. The area in the housing chamber facing away from the chip is highly rounded, whereby no TiO 2 Encapsulant accumulates.

[0044] - The drainage structure will preferably contain a dispersed TiO of at least one silicone resin 2 Encapsulant is directly guided from the injection landing area to the chip. The drainage structure is, for example, in principle an inner edge of approximately 90°, which directly guides from the landing area to the chip, preferably by making full use of capillary action.

[0045] - The inner long side of the housing can also be used as a drainage path. Thus, TiO 2 Encapsulant also reaches the small drainage structures optionally present at the long sides of the chip. This is a special case because the construction form, such as LEDs of the E4014 family, is usually narrow.

[0046] - The chip should be placed on the drainage structure such that the drainage structure can also be used as a stand-off when soldering the chip.

[0047] - The drainage structure extends at least partially or completely radially with respect to the chip.

[0048] - The drainage structure is as narrow as technically possible.

[0049] - The drainage structure is as sharp-angled as technically possible on the long side in order to achieve high capillary action.

[0050] - The drainage structures are of the same height at the end where the chip is placed. Thus, the rocking or flipping of the chip can be prohibited.

[0051] -Preferably, there are at least three drainage structures, whereby the chip can be stably placed and not flipped. The following advantages can be obtained from the foregoing technical features, for example, individually or in combination:

[0052] -TiO 2 The encapsulation part causes, under the full utilization of capillary action, most of the flow to where the encapsulation material should flow, that is, under the chip.

[0053] -The regions in the chamber of the housing that are away from the chip are rounded to a large extent, as long as these edges are not included in the drainage path.

[0054] -The drainage structure simultaneously forms a support for chip soldering. A height of 60 μm to 80 μm, including the boundary values, is preferred. Thus, the final solder thickness is fixedly set and is independent of the solder volume in a large area.

[0055] -The open radial arrangement of the drainage structure has the beneficial effect that the solder paste squeezed in width remains connected to the main solder volume under the chip and can be pulled back under the chip again during melting. It should be mentioned here that the solder paste typically undergoes a volume shrinkage of about 50% during melting, because most of the low-density flux evaporates and only metals, such as SnAgCu, remain in the solidified solder joint, although typically only less than 20% by weight of flux is contained in the solder paste.

[0056] -The open radial arrangement of the drainage structure allows the flux to evaporate easily. Thus, generally less flux remains in the chamber.

[0057] -The open radial arrangement of the drainage structure results in a better cleaning result of the flux residues, because the cleaning liquid can reach the solder part more easily during cleaning.

[0058] Thus, the above technical features of the housing described here are particularly used to line the chip with TiO 2 encapsulation part from below to maximize the optical efficiency, English: efficacy. Optical simulation shows that the solder should be surrounded as thickly as possible and optically sealed around.

[0059] It is desirable to use as wide a range of materials, especially silicone resins, to implement the TiO 2 encapsulation bottom filling process. In an alternative TiO 2 bottom filling design, the process effectiveness is highly related to the silicone resin used and its viscosity. The design described here with a drainage path and avoiding undesired silicone resin collection grooves can make the TiO 2 bottom filling process more tolerant to some material properties, such as viscosity and / or wetting angle.

[0060] According to at least one embodiment, two or more conductor structures are configured as electrical conductor structures. For example, the electrical conductor structures are provided for electrically contacting at least one optoelectronic semiconductor chip. In the manufactured semiconductor device, the electrical conductor structures serve as external electrical contacts.

[0061] According to at least one embodiment, one or more conductor structures are configured as thermal conductor structures. That is, the thermal conductor structures are provided for dissipating heat from at least one optoelectronic semiconductor chip. For this purpose, at least one thermal conductor structure is electrically insulated from the electrical conductor structures. In particular, at least one thermal conductor structure is at zero potential.

[0062] Whenever conductor structures are mentioned below, the relevant statements preferably relate to at least one thermal conductor structure as well as electrical conductor structures.

[0063] According to at least one embodiment, the conductor structures, i.e., preferably at least one thermal conductor structure and electrical conductor structures, are each formed by metallic conductor frame components. For example, the conductor structures are produced from a metal sheet by stamping. As an alternative to the metallic conductor frame components, the conductor structures can also be realized by a coating, in particular a metallic coating, on a carrier such as ceramic. In this case, the conductor structures are, for example, electroplated coatings for electrical connection surfaces and / or printed conductors.

[0064] According to at least one embodiment, the conductor frame components are mechanically connected to one another by the housing body. That is, in the absence of the housing body, there is no fixed mechanical connection between the conductor frame components.

[0065] According to at least one embodiment, the drainage structures are each partially formed by edges. The edges are in particular formed by adjacent faces of the housing body. The angle of these faces at the edge is preferably at least 60° or 75° and / or at most 110° or 95°. In particular, a right angle or an approximately right angle exists between the relevant faces at the edge.

[0066] Thereby, the drainage structures are in this case faces that are adjacent at approximately right angles. The drainage structures are thus particularly affected by capillary forces at the edges. In addition, liquid encapsulation material can be guided along the edges.

[0067] This drainage structure formed by sharp edges is preferably delimited by a raised portion, for example by a strip, which rises above the chip mounting side. The strip is preferably integrally formed with the housing body. Such a strip has, for example, a rectangular, trapezoidal or semi-circular cross-section or a combination of these in a cross-sectional view. In particular, the strip is formed by a rectangle in a cross-sectional view and is followed by an arcuate structure in the direction away from the chip mounting side. In other words, the strip can delimit a respective pair of drainage structures.

[0068] According to at least one embodiment, the drainage structures each comprise or consist of two or more than two slats, wherein the slats protrude above the remaining components on the chip mounting side. The slats are preferably constructed integrally with the housing body.

[0069] If there are multiple slats for each drainage structure, the slats can extend parallel or approximately parallel to each other within the associated drainage structure. The slats for the associated drainage structure can define a rectangular or trapezoidal channel in cross-section. The slats of the associated drainage structure can be connected to each other in a U-shape in a top view of the chip mounting side at the electrical contact surface.

[0070] According to at least one embodiment, the housing body has a chamber which forms a reflection groove. The reflection groove is preferably formed by the side walls of the housing body all around. That is to say, the side walls can surround the chip mounting side all around. The chip mounting side is, for example, the bottom surface of the chamber, in particular the flat area of the bottom surface which is flush with the conductor structure and / or planar and connected to the conductor structure all around.

[0071] According to at least one embodiment, the drainage structure, in particular the slat, has a smaller height than the reflection groove and thus than the side wall. Preferably, the side wall and thus the reflection groove is higher than the drainage structure and than the slat, at least 10 times or 20 times or 50 times.

[0072] According to at least one embodiment, the drainage structure, in particular the slat, is configured as a support surface for at least one optoelectronic semiconductor chip. That is to say, at least one optoelectronic semiconductor chip is conventionally placed flat on the drainage structure, in particular on the slat.

[0073] It is feasible that the drainage structure, in particular the slat, has a constant, unchanging height above the chip mounting side. Alternatively, the drainage structure, in particular the slat, can have a variable height and in particular have different heights in the area designed as a support surface for at least one semiconductor chip, for example a smaller or larger height.

[0074] According to at least one embodiment, there are a total of at least three or four or six and / or at most 24 or 12 or eight slats. That is to say, the housing includes only a relatively small number of slats and corresponding drainage structures.

[0075] According to at least one embodiment, the slat and / or the drainage structure terminate near the electrical contact surface. For example, the spacing between the electrical contact surface and the associated drainage structure and / or slat is at least 5 μm or 10 μm or 30 μm and / or at most 0.1 mm or 50 μm. Thereby, a space-saving arrangement can be achieved, in which the semiconductor chip can be reliably placed in the housing.

[0076] Alternatively, the drainage structure and / or the slat can be flush with the electrical contact surface.

[0077] According to at least one embodiment, at least one drain structure and / or slat terminates in the region between the electrical contact surfaces. This applies in particular to shorter drain structures which can extend from a longer side wall. Such a drain structure and / or slat extending into the region between the electrical contact surfaces can extend further under the optoelectronic semiconductor chip to be mounted than a longer drain structure and / or slat.

[0078] According to at least one embodiment, the drain structures and / or slats are separate, non-connected structures. In particular, the drain structures and / or slats do not form a surrounding edge or frame around at least one semiconductor chip. That is to say, all drain structures and / or slats can extend radially towards the electrical contact surfaces or towards the region between the electrical contact surfaces.

[0079] According to at least one embodiment, the side wall of the housing body transitions locally or continuously along the entire circumference of the chip mounting side into the chip mounting side. The side wall and the chip mounting side can form a rounded portion with a radius of curvature of, for example, at least 1 mm, in particular at least 2 mm or at least 3 mm, when viewed in a cross-section perpendicular to the electrical contact surfaces.

[0080] Alternatively, it is feasible that the side wall of the housing body transitions into the chip mounting side with a sharp edge locally or along the entire circumference of the chip mounting side. Such a sharp edge can form one of the drain structures. In particular, such a sharp transition between the side wall and the chip mounting side is present along the long side of the reflection groove.

[0081] According to at least one embodiment, the housing is rectangular or approximately rectangular in a top view of the chip mounting side, i.e., in the manner of a rectangle with rounded corners.

[0082] According to at least one embodiment, the electrical contact surfaces are arranged symmetrically along the longitudinal axis of the housing body when viewed in a top view. Alternatively, the contact surfaces can also be arranged asymmetrically.

[0083] According to at least one embodiment, at least two, in particular exactly two, drain structures extend along the longitudinal axis, and at least two further, in particular exactly two further, preferably shorter drain structures are oriented transversely to the longitudinal axis. That is to say, the drain structures can have a cross-shaped geometry when viewed in a top view, where preferably no drain structure is present at the center of the relevant cross. The relevant cross can have beams extending at right angles in a top view, which are formed by the drain structures.

[0084] According to at least one embodiment, a relatively short drainage structure oriented transversely to the longitudinal axis is provided for guiding the liquid encapsulation material from the longer side wall of the chamber towards the intermediate space between the electrical contact surfaces. For this purpose, the drainage structure preferably deflects the flow extending along the side wall, which consists of the liquid encapsulation material, towards the contact surfaces.

[0085] According to at least one embodiment, at least one or all drainage structures extending along the longitudinal axis of the housing body terminate spaced apart from the side wall. That is to say, there is a gap between the relevant drainage structure and the associated side wall, in which the thickness of the housing body can be smaller than in the region of the relevant drainage structure. It is feasible that at least one relevant drainage structure also terminates on the particularly flat chip mounting side and thus does not extend to the optional, for example rounded, chamber end.

[0086] According to at least one embodiment, at least one or all drainage structures extending along the longitudinal axis of the housing body terminate at or in the associated side wall. That is to say, at least one relevant drainage structure can transition without a gap, in particular continuously, into the associated side wall along the longitudinal axis.

[0087] The drainage structures oriented transversely to the longitudinal axis preferably terminate in or at the respectively associated side wall.

[0088] According to at least one embodiment of the semiconductor device, the encapsulation is made of a reflective material. Preferably, the encapsulation appears white to the observer. The reflectivity of the encapsulation in the visible spectral range is preferably at least 80% or 90% or 95%.

[0089] According to at least one embodiment, at least one optoelectronic semiconductor chip is a light-emitting diode, abbreviated as LED, or a laser diode, abbreviated as LD. In the semiconductor device, different types of semiconductor chips can, for example, be configured to emit different colors.

[0090] According to at least one embodiment, the semiconductor chip or all semiconductor chips are placed flat on all drainage structures or each flat on at least three or at least four drainage structures.

[0091] According to at least one embodiment, the strip defining the drainage structure has a height of at least 10 μm or 30 μm or 60 μm and / or at most 200 μm or 100 μm or 80 μm. In particular, the height of the relevant strip with respect to the chip mounting side is between 30 μm and 100 μm, including the boundary values.

[0092] According to at least one embodiment, the lower side of at least one optoelectronic semiconductor chip facing the chip mounting side is completely or at least largely covered by a reflective encapsulation together with a bonding agent and together with a drainage structure. At least largely, for example, means at least 95% or 98% or 99% or 99.8%. The bonding agent is preferably solder or includes solder here. Alternatively, the bonding agent can also be a conductive adhesive.

[0093] According to at least one embodiment, the bonding agent is completely or largely surrounded laterally by the encapsulation in a direction parallel to the chip mounting side. Preferably, the bonding agent is directly covered by the encapsulation.

[0094] According to at least one embodiment, the encapsulation consists of a matrix material, in particular silicone resin, and of reflective particles, in particular of metal oxides, such as TiO 2 or by means of metal oxides, such as TiO 2 constitutes. Thereby, the encapsulation is preferably white and has a high reflectivity.

[0095] According to at least one embodiment, the housing body is made of an epoxy material, preferably of a white epoxy material. The material of the housing body has a lower reflectivity compared to the encapsulation. It is feasible that the material of the housing body is not completely light-tight, but semi-transparent. Alternatively, the housing body can also be made of an unsaturated polyester, such as UP resin.

[0096] According to at least one embodiment, at least one optoelectronic semiconductor chip is a sapphire flip chip or the semiconductor chip is such a chip.

[0097] According to at least one embodiment, all electrical connection surfaces of the semiconductor chip are associated with the electrical contact surfaces of the housing in a one-to-one correspondence.

[0098] Alternatively, a plurality of connection surfaces can be arranged on a common contact surface.

[0099] According to at least one embodiment, the sapphire substrate of the semiconductor chip faces away from the chip mounting side. That is, the semiconductor layer sequence of at least one semiconductor chip faces the chip mounting side.

[0100] According to at least one embodiment, at least one optoelectronic semiconductor chip includes a mirror at the lower side facing the chip mounting side. The mirror can be a metal mirror or a dielectric mirror or a hybrid form composed of them.

[0101] According to at least one embodiment, the mirror is spaced apart from the edge of the lower side of the associated semiconductor chip. The region of the lower side not covered by the mirror is preferably completely or largely covered by the encapsulation. Thereby, due to the encapsulation, a high reflectivity is also ensured in the region of the lower side where there is no mirror.

[0102] According to at least one embodiment, the semiconductor device further includes a filling part that covers at least one optoelectronic semiconductor chip and touches the encapsulation part. When observed in a top view of the chip mounting side, the filling part preferably surrounds the semiconductor chip around. At least one semiconductor chip is preferably completely covered by the filling part, just like the encapsulation part.

[0103] According to at least one embodiment, the filling part contains one or more light-emitting materials, such that the semiconductor chip especially generates blue light and the semiconductor device can generally be configured to emit white light.

[0104] According to at least one embodiment, the semiconductor device does not have a protection diode for preventing electrostatic discharge to prevent damage and / or the semiconductor device does not have bonding wires. That is, at least one optoelectronic semiconductor chip can be the only chip in the reflection groove, such that only the optoelectronic semiconductor chip can exist.

[0105] According to at least one embodiment, the encapsulation material for producing the encapsulation part is applied to the landing area in a liquid state. The landing area is located next to the optoelectronic semiconductor chip when observed in a top view.

[0106] According to at least one embodiment, the landing area covers the drainage structure. The landing area is partially, preferably mostly, located next to the drainage structure here. The drainage structure extends through the landing area and / or starts in the landing area. Alternatively, it is feasible that the landing area is completely located next to the drainage structure, especially in the gap between the drainage structure and the side wall, especially when observed along the longitudinal axis of the housing. That is, the landing area can be located in the area where at least one of the affiliated drainage structures is interrupted.

[0107] According to at least one embodiment, the encapsulation material is guided from the landing area to the optoelectronic semiconductor chip through the drainage structure, especially by means of capillary action. Thereby, the encapsulation material especially extends along the edges formed by the strips that define the drainage structure.

[0108] According to at least one embodiment, the housing is manufactured by means of casting, spraying, and / or extrusion. Here, a mold, which is "mold" in English, is preferably used. The mold forms the negative mold of the chip mounting side, the reflection groove, and the drainage structure.

[0109] According to at least one embodiment, the encapsulation material is applied only in the area of the landing area by means of injection in step C). Here, the unintentional splashing of the encapsulation material landing outside the landing area in the housing is not considered. The distance between the landing area and at least one optoelectronic semiconductor chip is preferably at least 0.3 mm or 0.4 mm and / or at most 1 mm or 0.7 mm, in order to achieve a space-saving arrangement and to prevent contamination caused by the encapsulation material at the optoelectronic semiconductor chip. Description of the Drawings

[0110] Hereinafter, the housing described herein, the optoelectronic semiconductor device described herein, the mold (English: mold) described herein, and the method described herein will be described in detail with reference to the drawings according to the embodiments. The same reference numerals denote the same elements in the respective drawings. However, as long as not otherwise specified herein, the proportional relationships are not shown, and rather, for better understanding, individual elements may be shown exaggeratedly.

[0111] The drawings show:

[0112] Figure 1 A schematic perspective view showing an embodiment of the housing described herein;

[0113] Figure 2 Showing Figure 1 Details of the housing in

[0114] Figure 3 And 4 Showing other details of the housing in Figure 1 with a semiconductor chip mounted;

[0115] Figure 5 Showing Figure 1 A schematic sectional view of the housing in

[0116] Figure 6 A schematic perspective view showing a mold for manufacturing an embodiment of the housing described herein;

[0117] Figure 7 Showing Figure 6 Details of the mold in

[0118] Figure 8 A schematic top view showing an embodiment of the housing described herein;

[0119] Figure 9 Showing Figure 8 A schematic sectional view of the housing in

[0120] Figure 10 Showing Figure 8 Schematic details of the view in

[0121] Figure 11 A schematic three-dimensional sectional view showing an embodiment of the optoelectronic semiconductor device described herein;

[0122] Figures 12 to 15 A schematic top view showing an embodiment of the housing described herein;

[0123] Figure 16 A schematic top view showing an embodiment of the optoelectronic semiconductor device described herein;

[0124] Figures 17 to 19 Schematic cross-sectional view showing an embodiment of the housing described herein;

[0125] Figure 20 Schematic view showing a reflective encapsulation part and encapsulation material for the optoelectronic semiconductor device described herein;

[0126] Figure 21 and 23 Schematic cross-sectional view showing an embodiment of the optoelectronic semiconductor device described herein;

[0127] Figure 22 Schematic view showing an embodiment of an optoelectronic semiconductor chip for the semiconductor device described herein;

[0128] Figure 24 Block diagram showing an embodiment of the method for manufacturing an optoelectronic semiconductor device described herein;

[0129] Figure 25 Schematic top view showing an embodiment of the housing described herein;

[0130] Figure 26 Showing for Figure 25 Schematic perspective view of the conductor frame of the housing;

[0131] Figure 27 Showing for Figure 25 Schematic top view of the conductor frame composite of the conductor frame;

[0132] Figures 28 to 32 Showing Figure 25 Different schematic side views of the housing;

[0133] Figure 33 Showing for Figure 25 Schematic top view of the partially sprayed conductor frame composite of the housing; and

[0134] Figures 34 to 36 Schematic top view showing other embodiments of the housing described herein. Detailed Description

[0135] In Figures 1 to 5 an embodiment of the housing 2 is described. The housing 2 includes a housing body 21 with a chamber 27. The chamber 27 is bounded by surrounding side walls 28 which transition into an approximately flat chip mounting side 22 at the rounded chamber end 48.

[0136] Integrated in the housing body 21 are two electrical conductor structures 23, which are formed by conductor frame components. Instead of conductor frame components, it is also possible to apply electrical printed conductors on the housing body 21, as can also be the case in all other embodiments. Electrical contact surfaces 25 are formed by the electrical conductor structures 23.

[0137] Via landing areas 44 for an encapsulating material (not shown), a plurality of drainage structures 24 extend substantially along the longitudinal axis A, which are defined by slats 26. The slats 26 bulge above the chip mounting side 22 and are integrally connected to the housing body 21. The drainage structures 24 and the slats 26 extend radially with respect to the position of the semiconductor chip 3 to be arranged in the housing 2, which is only shown in Figure 3 and 4 and extend radially.

[0138] An edge 49 is defined by the slat 26 and the chip mounting side 22. There is approximately a right angle at the edge 49. If an encapsulating material (not shown) for the encapsulation 4 to be established later in the housing 2 is applied in the landing area 44, then the encapsulating material is guided along the edge 49 towards the electrical contact surface 25 and guided under the semiconductor chip 3.

[0139] Viewed in a top view, the slats 26 for the drainage structures 24 extend, for example, cross-shaped, wherein the central region of the cross does not have a drainage structure 24. The drainage structures 24 serve as supports for the semiconductor chip 3.

[0140] Viewed in a cross-section, the slat 26 has a rectangular base, followed by an approximately semi-circular dome. Other shapes of the slat 26 are also possible.

[0141] At the end of the chamber 27, there are relatively flat regions 48. The longer slats 26 start from these regions 48. The shorter slats 26 project from the longer side walls 28 of the chamber 27. Here, the longer side walls 28 optionally transition into the chip mounting side 22 at an acute angle at another edge 47. Alternatively, there can also be a rounded portion in the transition region towards the chip mounting side 22.

[0142] Especially visible in Figure 4 it can be seen that the shorter slats 26 starting from the longer side walls 28 are formed to rise at the side walls 28. Thereby, it is achieved that the encapsulating material does not slosh above the slats 26, but is guided towards the semiconductor chip 3. It is possible that the shorter slats 26 have a rounded portion along the edge 49 towards the side walls 28. The shorter slats 26 are optional.

[0143] With Figures 1 to 5In contrast to the illustration in, this additional edge 47 is annularly disposed around the chamber 27. Alternatively, a relatively flat region 48 may be present annularly around the chamber 27. The same applies to all other embodiments.

[0144] In Figure 6 and 7 the mold 7 is described, by means of which in particular a Figures 1 to 5 housing 2 can be manufactured. The mold 7 is in particular a casting mold or a compression mold. The mold 7 has a groove 72 for the chamber 27 of the housing 2. A plurality of channels 71 for the strip 26 of the housing 2 are present in the groove 72. By means of such a mold 7, the drainage structure 24 can be effectively manufactured. For example, the chip mounting side 22 is manufactured by grinding at the upper side of the groove 72 and the channels 71 are produced by milling. In the same way, correspondingly configured molds 7 can be used for manufacturing all other embodiments.

[0145] In Figures 8 to 10 another embodiment of the housing 2 is described. The housing 2 includes a housing body 21 having a chamber 27. The chamber 27 is delimited by surrounding side walls 28, which transition into a flat or approximately flat chip mounting side 22 at the rounded chamber end 48.

[0146] The strip 26 forms a channel 41, which delimits the drainage structure 24, and in particular due to capillary forces, an encapsulating material (not shown) is guided from the landing zone 44 through the drainage structure towards the electrical contact surface 25. The landing zone 44 is preferably an injection landing zone, such that the encapsulating material is in particular only to be applied in a targeted manner in the region of the landing zone from a nozzle (not shown).

[0147] Along the longitudinal axis A, additionally and optionally, there are further, laterally extending and shorter drainage structures 24 for the drainage structure 24. The shorter drainage structures 24 can guide the encapsulating material towards the electrical contact surface 25. The encapsulating material does not reach the longer drainage structures 24 and is guided along the side walls 28. Thereby, the shorter drainage structures 24 are not associated with their own landing zones 44 for the encapsulating material.

[0148] Due to the large radius of curvature of the rounded chamber end 48, a large-volume accumulation of the encapsulating material in the region of the chamber end 48 is prevented.

[0149] Furthermore, Figures 1 to 5 the embodiments of Figures 8 to 10 correspondingly apply to

[0150] In Figure 11 an embodiment of the optoelectronic semiconductor device 1 is shown, which preferably includes Figures 1 to 5 or Figures 8 to 10 the housing 2.

[0151] In Figure 11 an unrecognizable drainage structure, a optoelectronic semiconductor chip 3 is arranged. The semiconductor chip 3 is preferably an LED chip, for example for generating blue light. The semiconductor chip 3 is preferably a flip chip. The semiconductor chip 3 is fixed to the housing 2 by means of a connecting agent 6, which is in particular solder or an adhesive.

[0152] In order to reduce absorption losses at the housing 2 and at the connecting agent 6, a potting part 4 with a high reflectivity is introduced between the semiconductor chip 3 and the chip mounting side 22. The potting part 4 is limited to the lower side 32 of the semiconductor chip 3 such that the side faces 34 of the semiconductor chip 3 are exposed. The potting part 4 reflects light particularly better than the housing base body 21, wherein the potting part 4 and the housing base body 21 can be white.

[0153] Furthermore, the semiconductor chip 3 is preferably embedded in a filling part 5, which can fill the chamber 27 and which preferably contains a light-emitting material.

[0154] In Figures 12 to 14 different exemplary construction possibilities of the end region of the drainage structure 24 in the region close to the electrical contact surfaces are illustrated. Figures 8 to 10 The drainage structure 24 of Figures 12 to 14 can be present in all embodiments of the housing 2, in particular in the embodiments of Figures 8 to 10

[0155] According to Figure 12 , the strips 26 extend parallel to each other and are connected at their ends by a U-shaped structure as viewed in a plan view of the chip mounting side 22, which is shown shaded in Figure 12 . The U-shaped structure can have the same height as the strips 26 or can alternatively have a reduced height.

[0156] According to Figure 13 , the strips 26 terminate without a connecting structure.

[0157] In Figure 14 it is illustrated that the strips 26 flare funnel-shaped in the end region, shown shaded. In the remaining regions, the strips 26 can extend parallel to each other. The end region can be limited to the region covered by the semiconductor chip not shown in Figure 7 .

[0158] In accordance with Figure 15 ​In an embodiment of the housing 2, the housing base body 21 is shaped square when viewed in plan view. The area for a semiconductor chip (not shown) is arranged centrally. Four drainage structures 24 are arranged around said area, the drainage structures extending radially towards said area. Each drainage structure 24 is associated with its own landing area 44. The rounded chamber ends 48 surround the chamber 27 when viewed in plan view. Furthermore, the corners of the chamber 27, also when viewed in plan view, are preferably likewise rounded.

[0159] In Figure 15 the construction form used, the drainage structures 24 can be configured according to Figures 1 to 5 or also according to Figures 8 to 10 construction.

[0160] In Figure 16 an embodiment of the semiconductor device 1 there are a plurality of semiconductor chips 3. This is also feasible in all other embodiments.

[0161] Furthermore, in Figure 16 it can be seen that a plurality of drainage structures 24 can originate from the sole landing area 44. Here, each semiconductor chip 3 can be associated with a long drainage structure 4 starting directly from the associated landing area 44 and, optionally, a short drainage structure 24 starting especially from a non-shown side wall of the chamber. Furthermore, as an option, it is feasible that additional drainage structures 24 extend between adjacent semiconductor chips 3.

[0162] Furthermore, Figure 16 the housing 2 of the embodiment is preferably equivalent to the housing 2 of Figures 1 to 5 8 to 10 or 15.

[0163] Figures 17 to 19 show different construction possibilities for the cross-section of the drainage structure 24 as it can exist in all embodiments, especially in the housing 2 of Figures 8 to 10 the housing 2.

[0164] According to Figure 17 , the slats 26 and the channels 41 formed between the slats are formed rectangularly or squarely in cross-section. The edges transition into each other as sharply as possible at right angles or approximately at right angles.

[0165] In contrast, according to Figure 18 , the sides of the slats 26 extend at an angle of less than 90° to the rest of the chip mounting side 22 so that the housing base body 21 can be manufactured more effectively. The angle towards the channel 41 is, for example, at least 75° or 80° or 85° and / or at most 89°. On the side facing away from the channel 41, the angle can be smaller, for example at least 15° or 30° and / or at most 75° or 60° or 45° or 35°.

[0166] InFigure 19 As shown in Figure 19 , the strip 26 has a rounded profile outside the channel 41. Thereby, the capillary force can be kept restricted to the channel 41.

[0167] As in all other embodiments, the typical dimensions of the drainage structure 24 are as follows:

[0168] - The strip 26 has a height of at least 30 μm and / or at most 100 μm.

[0169] - The width of the strip 26 is at least 10 μm or 20 μm and / or at most 200 μm or 80 μm.

[0170] - The average width of the optionally present channel 41 is at least 20 μm or 40 μm and / or at most 100 μm or 60 μm.

[0171] In Figure 20 the encapsulating material 40 and the encapsulation 4 are schematically shown. The encapsulating material and the encapsulation are composed of a matrix material 42, in particular silicone, and of reflective particles 43, such as titanium dioxide.

[0172] It is feasible that, during the manufacture of the encapsulation 4, the encapsulating material acts wettingly or slightly wettingly with respect to the housing basic body 21 and thus with respect to the drainage structure 24, such that the contact angle of the encapsulating material can be set, for example, to be less than 85° or 75° and alternatively or additionally greater than 50° or 65°.

[0173] In Figure 21 the embodiment of the semiconductor device 1, the semiconductor chip 3 is an LED chip and consists of a substrate 30, preferably a substrate made of sapphire, and of a semiconductor layer sequence 35 having an active region 36, preferably a semiconductor layer sequence 35 made of AlInGaN. A mirror 37 is preferably present on the side facing away from the substrate 30, however the mirror does not extend completely up to the side surface 34 of the semiconductor chip 3. The emission side 33 of the semiconductor chip 3 faces away from the housing 2 and is preferably formed by the substrate 30.

[0174] The semiconductor chip 3 lies partly flat on the drainage structure 24, such that the spacing between the electrical connection surface at the lower side 32 of the semiconductor chip 3 and the electrical contact surface 25 is preset by the drainage structure 24. The lower side 32 and the side surface 34 are separated by sharp edges. The semiconductor chip 3 is fixed to the housing 2 by means of an adhesive 6, preferably solder.

[0175] The adhesive 6 is covered by the encapsulation 4 all around. The lower side 32 is completely covered by the adhesive 6 together with the drainage structure 24 and the encapsulation 4. Thereby, at the sites where the drainage structure 24 is absent, the encapsulation 4 extends up to the edge of the lower side 32, however preferably the side surface 34 is left exposed.

[0176] Figure 21The housing 2 is preferably constructed as described in connection with Figures 1 to 5 , 8 to 10, 11 or 15.

[0177] The exemplary semiconductor chip 3 is shown in more detail in Figure 22 . Here, the internal electrical wiring of the semiconductor chip 3 is not illustrated. In Figure 22 it is particularly visible that the semiconductor chip 3 has an area 38 at the lower side 32 near the side 34 that is not covered by the mirror 37.

[0178] In embodiments of the semiconductor device 1, the area 38 is completely or at least mostly covered by the encapsulation 4, such that a high reflectivity can also be achieved in the area 38 and the radiation emitted from the area 38 is redirected by the encapsulation 4 towards the radiation exit side of the semiconductor device 1. The side 34 remains without the encapsulation 4 here.

[0179] According to Figure 21 , the strip 26 terminates abruptly towards the contact surface 25, in particular at an angle of 90° or approximately 90° to the chip mounting side 22. In contrast, according to Figure 23 , the strip 26 can be continuous and relatively flat, for example at an angle of at least 20° and / or at most 70° to the chip mounting side 22. Furthermore, Figure 23 the embodiment of Figure 21 is equivalent to

[0180] In Figure 24 an embodiment of a manufacturing method for the semiconductor device 1 is described.

[0181] In a first step S1, the housing 2 is manufactured, for example by extrusion, injection or die casting. Multiple housings 2 can be produced simultaneously, and the housings can exist in the form of a composite.

[0182] Next, in step S2, at least one semiconductor chip 3 is mounted.

[0183] Subsequently, the encapsulation 4 is produced. For this purpose, the encapsulation material 40 is applied to the landing area 44, in particular by injection or spraying or, for example, by means of at least one nozzle, not shown. Due to capillary forces, the encapsulation material 40 is guided through the drainage structure 24 to the semiconductor chip 3 and covers the lower side of the semiconductor chip. Next, the encapsulation material 40 is thermally cured, for example.

[0184] In an optional method step S4, the filling 5 is produced, also see Figure 11 .

[0185] In Figures 25 to 33Another embodiment of the housing 2 is described. The housing 2 includes a drainage structure 24 that is, for example, cross-shaped in a top view, and the drainage structure is formed by slats 26 respectively. In addition, as in all other embodiments as well, the housing 2 can have a position marking 82. The position marking 82 is located, for example, at the upper corner of the housing 2 so that the orientation of the housing can be well recognized when the housing 2 is installed.

[0186] Unlike Figure 1 the housing 2 of Figure 25 the housing additionally has a thermal conductor structure 29 for two electrical conductor structures 23. The thermal conductor structure 29 is integrated in the same conductor frame 8 as the electrical conductor structures 23, see also Figure 26 . For example, the thermal conductor structure 29 is centrally arranged between the electrical conductor structures 23. Two slats extending transversely to the longitudinal axis can terminate at the thermal conductor structure 29.

[0187] The conductor frame 8 is, for example, half-etched, see Figure 8 . That is, the outwardly visible surface of the conductor frame 8 at the chip mounting side 22 can be shaped differently from that at the housing bottom side 20, see also Figure 29 and 30 , in Figure 29 and 30 the housing body 21 is shown as a transparent body for illustrative purposes. Here, Figure 29 is a view towards the housing bottom side 20 and Figure 30 is a view towards the chip mounting side 22. In Figure 28 the housing body 21 is shown as opaque again and the housing bottom side 20 is shown. Such a half-etched conductor frame 8 can correspondingly also be used in all other embodiments.

[0188] In Figure 31 a side view of the lateral side 85 of the housing body 21 is described. The lateral side 85 can be rectangular when observed in a top view. Optionally, welding control structures 83 are respectively present at two mutually opposite lateral sides 85. The welding control structures 83 are realized in particular by recesses that laterally protrude from the housing bottom side 20 in the conductor frame 8. Thereby, the welding control structures 83 are integrally formed with the electrical conductor structures 23 and are located at the lateral extension of the electrical conductor structures 23. In contrast, according to Figure 1 , the welding control structures are paired and located at the longitudinal sides of the housing body 21.

[0189] In the area next to the welding control structure 83, the conductor frame 8 can have its maximum thickness, as well as in the areas of the electrical conductor structure 23 and the thermal conductor structure 29. In all other areas, the conductor frame 8 can be thinner due to half-etching. Preferably, at the underside 20 of the conductor frame 8, the lateral side 83 at the edge of the underside 20 is only reached in the area of the welding control structure 83.

[0190] It is feasible that the thermal conductor structure 29 is narrower along the longitudinal axis than the chip mounting side 22 at the underside 20 of the housing.

[0191] The conductor frame design, as illustrated in particular in Figure 26 can also be understood as a mesh design, English Mesh-Design. Here, the electrical contact surfaces 23, 25 for the semiconductor chip 3 are connected to the corresponding welding control structures 83 at the lateral sides 85. This design can minimize the thermo-mechanical stress applied at the chip solder joints.

[0192] In addition, through this design, it can be achieved that the conductor frame 8 is hidden as much as possible under the material of the housing body 21, so that possible corrosion damage at the conductor frame 8 does not cause an optical change in the light-emitting characteristics of the semiconductor device 1. In addition, this design makes the conductor frame structure on the panel plane flexible, so that the housing sealability can be higher than in the conventional QFN design.

[0193] The design of the conductor frame 8 also reduces the mechanical, chemical, and optical interactions between the materials used in the housing 2. Thereby, the development of new devices and the search for materials are simplified and accelerated.

[0194] In Figure 32 it can be seen that separate connecting tabs 81 of the conductor frame 8 are exposed at the longitudinal side 84 of the housing body 21. Via these connecting tabs 81, the adjacent conductor frames 8 in the conductor frame composite 80 are mechanically connected to each other, also see Figure 27 . That is to say, in the conductor frame composite 80, the conductor structures 23, 29 are still short-circuited and integrally connected to each other. The connecting tab 81 is preferably spaced apart from the underside 20 of the housing, however, it can be in the same plane as the electrical contact surface 25 at the chip mounting side 22.

[0195] When manufacturing the housing 2, it is preferably first to provide the conductor frame composite 80 and then to establish the housing body 21 as a connected body part, also referring to Figure 33 . Then, it is divided into individual housings 2, where the connecting tab 81 is separated.

[0196] Such a conductor frame 8, as elaborated in particular in connection with Figure 26 can also be used in all other embodiments of the housing 2.

[0197] In addition, the embodiments for Figures 1 to 24 correspondingly apply to Figures 25 to 33 .

[0198] In Figure 34 another embodiment of the housing 2 is shown. Here, the slats 26 are arranged crosswise, for example. Different from that in Figure 1 , the slats 26 extending along the longitudinal axis A are spaced apart from the side walls 28 and thus still terminate within the chamber 28. In particular, the drainage structure 24 also terminates within the flat chip mounting side 22 and also in front of the chamfered chamber end 48, for example.

[0199] The shorter sides of the cross of the drainage structures 24, 26 along the longitudinal axis A can cause the encapsulation material 40 for the encapsulation 4, for example an injection encapsulation material such as TiO 2 silicone, to be able to be injected into the flat area, in particular onto the chip mounting side 22 and only then to come into contact with the drainage structures 24, 26. That is to say, the landing area 44 can be located along the longitudinal axis A between the shortened drainage structures 24, 26 and the associated chamber end 48 or the associated side wall 48. This results in the semiconductor chip 3 being more evenly underfilled with the encapsulation material 40.

[0200] Such shortened drainage structures 24, 26 can also be used in all the remaining embodiments.

[0201] In addition, Figures 25 to 33 the embodiments for Figure 34 correspondingly apply to

[0202] In Figure 35 the embodiment shown, the thermal conductor structure 29 can also be narrower than the electrical contact block 23 along the longitudinal axis A. Here, all the conductor structures 23, 29 can have the same extent in a direction perpendicular to the longitudinal axis A and be flush with each other. The same is also feasible in all other embodiments.

[0203] In addition, Figures 25 to 34 the embodiments for Figure 35 correspondingly apply to

[0204] In contrast, the thermal conductor structure 29 can also be widened and, for example, extend along the longitudinal axis A beyond the extension of the electrical conductor structure 23 by at least 1.5 times or at least 2 times and / or at most 5 times or at most 3 times. This applies in particular in the case where the electrical conductor structure 23 is provided for accommodating bonding wires for electrically connecting at least one optoelectronic semiconductor chip 3. The same is also feasible in all other embodiments.

[0205] In addition, Figures 25 to 35 the embodiments forFigure 36 。

[0206] The components shown in the figures preferably follow one another in a given order, in particular directly following one another, provided that this is not stated otherwise. Components that do not touch in the figures preferably have a spacing from one another. Provided that lines are shown parallel to one another, the associated surfaces are preferably also oriented parallel to one another. Furthermore, the relative positions of the components shown in the figures are correctly described, provided that this is not stated otherwise.

[0207] The invention described here is not restricted by the description according to the embodiments. Rather, the invention includes any new features and any combination of features, which in particular includes any combination of features in the embodiments, even if the features or the combination itself is not given in detail in the embodiments.

[0208] This application claims the priority of German Patent Applications 10 2020 100 542.3 and 10 2020 106 250.8, the disclosures of which are incorporated herein by reference.

[0209] List of reference signs

[0210] 1 optoelectronic semiconductor device

[0211] 2 housing

[0212] 20 underside of the housing

[0213] 21 housing body

[0214] 22 chip mounting side of the housing body

[0215] 23 electrical conductor structure

[0216] 24 drainage structure

[0217] 25 electrical contact surface

[0218] 26 slats of the drainage structure

[0219] 27 chamber (reflection trough)

[0220] 28 side walls of the chamber

[0221] 29 thermal conductor structure

[0222] 3 optoelectronic semiconductor chip

[0223] 30 sapphire substrate

[0224] 31 electrical connection surface

[0225] 32 underside of the semiconductor chip

[0226] 33 emission side of the semiconductor chip

[0227] Side of the 34 semiconductor chip

[0228] 35 semiconductor layer sequence

[0229] 36 active region

[0230] 37 mirror

[0231] 38 Region on the lower side not covered by the mirror

[0232] 4 Reflective encapsulation part

[0233] 40 Encapsulation material

[0234] 41 Channel

[0235] 42 Substrate material

[0236] 43 Reflective particles

[0237] 44 Landing area for the encapsulation material

[0238] 47 Additional edge

[0239] 48 Rounded chamber end

[0240] 49 Edge

[0241] 5 Filling part

[0242] 6 Adhesive

[0243] 7 Mold

[0244] 71 Channel for the drainage structure

[0245] 72 Groove for the chamber

[0246] 8 Conductor frame

[0247] 80 Conductor frame composite

[0248] 81 Connecting piece

[0249] 82 Position marking

[0250] 83 Welding control structure

[0251] 84 Longitudinal side of the housing body

[0252] 85 Transverse side of the housing body

[0253] A Longitudinal axis

[0254] S Method step

Claims

1. A housing (2) for an optoelectronic semiconductor device (1), having - a housing body (21) having a chip mounting side (22), - at least two conductor structures (23) in and / or at the housing body (21), and - a plurality of drainage structures (24) at the chip mounting side (22), wherein - the electrical conductor structures (23) form electrical contact surfaces (25) for at least one optoelectronic semiconductor chip (3) at the chip mounting side (22), and - the drainage structures (24) are configured as conveying means for a liquid encapsulation material (40) towards the electrical contact surfaces (25), - the drainage structures (24) are each integrally formed with the housing body (21), and - the drainage structures (24) each include a strip (26) and the strips (26) each protrude above the rest of the chip mounting side (22).

2. The housing (2) according to claim 1, further comprising at least one thermal conductor structure (29), wherein the at least one thermal conductor structure (29) and the electrical conductor structures (23) are each formed by a metallic conductor frame member, wherein the conductor frame members are mechanically connected to each other by the housing body (21).

3. The housing (2) according to claim 1 or 2, wherein the drainage structures (24) are each formed by at least one edge at the strip (26).

4. The housing (2) according to claim 1 or 2, wherein the drainage structures (24) are each formed by at least two of the strips (26) and the strips (26) define a channel (41), and within the associated drainage structure (24), the strips extend parallel to each other with a tolerance of at most 10°.

5. The housing (2) according to claim 3, wherein the cross-section of the strip (26) is rectangular or trapezoidal or domed, or a hybrid shape composed of these shapes.

6. The housing (2) according to claim 4, wherein the cross-section of the strip (26) is rectangular or trapezoidal or domed, or a hybrid shape composed of these shapes.

7. The housing (2) according to claim 1 or 2, wherein the housing body (21) has a chamber (27) which forms a reflection trough, wherein the reflection trough is formed by side walls (28) of the housing body (21) all around and the side walls (28) surround the chip mounting side (22).

8. The housing (2) according to claim 7, wherein the side walls (28) continuously transition into the chip mounting side (22) such that the side walls (28) and the chip mounting side (22) locally or all around form a rounded portion having a radius of curvature of at least 1 mm in a cross-section perpendicular to the electrical contact surfaces (25).

9. The housing (2) according to claim 7, the housing is rectangular or approximately rectangular when viewed in a plan view of the chip mounting side (22), In a top view of the chip mounting side (22), two of the drainage structures (24) in the drainage structure (24) extend along the longitudinal axis (A) of the housing body (21), and two other drainage structures (24) are oriented transversely to the longitudinal axis (A).

10. The housing (2) according to claim 9, wherein the two other drainage structures (24) are shorter.

11. The housing (2) according to claim 9, wherein the drainage structure (24) oriented transversely to the longitudinal axis (A) is provided for guiding the liquid encapsulation material (40) from the longer side wall (28) of the chamber (27) towards the intermediate space between the electrical contact surfaces (25).

12. The housing (2) according to claim 11, wherein at least one of the drainage structures (24) extending along the longitudinal axis (A) of the housing body (21) terminates spaced apart from the side wall (28).

13. An optoelectronic semiconductor device (1), having - the housing (2) according to any one of claims 1 to 12, - at least one optoelectronic semiconductor chip (3) on the electrical contact surface (25), and - a reflective encapsulation (4) produced from a liquid encapsulation material (40), wherein - the encapsulation (4) extends under the at least one optoelectronic semiconductor chip (3) and can expose the side surface (34) of the at least one semiconductor chip (3) mostly or completely.

14. The optoelectronic semiconductor device (1) according to claim 13, wherein the at least one optoelectronic semiconductor chip (3) lies flat on all the drainage structures (24) or at least three of the drainage structures (24).

15. The optoelectronic semiconductor device (1) according to claim 13 or 14, wherein the lower side (32) of the at least one optoelectronic semiconductor chip (3) facing the chip mounting side (22) is completely covered by the reflective encapsulation (4) together with the adhesive (6) and together with the drainage structures (24), wherein the adhesive (6) is solder or comprises solder and / or wherein the adhesive (6) is completely or mostly covered by the encapsulation (4) all around in a direction parallel to the chip mounting side (22).

16. The optoelectronic semiconductor device (1) according to claim 13 or 14, wherein the encapsulation (4) consists of a matrix material (42) and reflective particles (43) and is white, wherein the at least one optoelectronic semiconductor chip (3) is a sapphire flip chip such that all the electrical connection surfaces (31) of the semiconductor chip (3) are associated with the electrical contact surfaces (25) in a one-to-one correspondence, and wherein the sapphire substrate (30) of the semiconductor chip (3) faces away from the chip mounting side (22).

17. The optoelectronic semiconductor device (1) according to claim 16, wherein the drainage structure (24) has a height of at least 10 μm or 30 μm or 60 μm and / or at most 200 μm or 100 μm or 80 μm above the chip mounting side (22).

18. The optoelectronic semiconductor device (1) according to claim 17, wherein the drainage structure (24) has a height between 30 μm and 100 μm above the chip mounting side (22), including the boundary values.

19. The optoelectronic semiconductor device (1) according to claim 13 or 14, which comprises a housing (2) according to at least claim 2, wherein the at least one optoelectronic semiconductor chip (3) is mounted not only on the electrical conductor structure (23) but also on at least one thermal conductor structure (29), and wherein the thermal conductor structure (29) is electrically separated from the electrical conductor structure (23) and does not have an electrical function.

20. The optoelectronic semiconductor device (1) according to claim 13 or 14, wherein the at least one optoelectronic semiconductor chip (3) includes a mirror (37) at the lower side (32) facing the chip mounting side (22), wherein the mirror (37) terminates spaced apart from the edge of the lower side (32) and the region (38) of the lower side (32) not covered by the mirror (37) is completely or mostly covered by the encapsulation (4).

21. The optoelectronic semiconductor device (1) according to claim 13 or 14, which further comprises a filling (5) that covers the at least one optoelectronic semiconductor chip (3) and touches the encapsulation (4) and surrounds the encapsulation in a top view of the chip mounting side (22).

22. The optoelectronic semiconductor device (1) according to claim 21, wherein the filling (5) contains one or more light-emitting materials.

23. The optoelectronic semiconductor device (1) according to claim 22, wherein the semiconductor chip (3) emits blue light.

24. The optoelectronic semiconductor device (1) according to claim 23, the semiconductor device (1) being configured to emit white light.

25. A method for manufacturing an optoelectronic semiconductor device (1) according to any one of claims 13 to 24, having the following steps in a given order: A) producing the housing (2), B) mounting the at least one optoelectronic semiconductor chip (3) on the electrical contact surface (25), and C) establishing the encapsulation (4), wherein - applying an encapsulation material (40) for producing the encapsulation (4) in a liquid state in a landing zone (44), - the landing zone (44) being located next to the optoelectronic semiconductor chip (3) in a top view, - the drainage structure (24) extending through the landing zone (44) or starting in the landing zone (44), and - the encapsulation material (40) reaching the optoelectronic semiconductor chip (3) from the landing zone (44) through the drainage structure (24).

26. The method according to claim 25, wherein the encapsulation material (40) reaches the optoelectronic semiconductor chip (3) from the landing zone (44) through the drainage structure (24) by means of capillary action.

27. The method according to claim 25 or 26, wherein the housing (2) is produced in step A) by means of casting, spraying and / or extrusion such that the drainage structure (24) is produced integrally with the housing body (21) and from the same material without a bonding agent.

28. The method according to claim 25 or 26, wherein the encapsulation material (40) is applied in step C) only in the region of the landing zone (44) by means of injection.

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