Active discharge system for capacitor and vehicle

Abstract

The present invention provides an active discharge system and vehicle for a capacitor. The active discharge system includes a battery and a discharge capacitor, and further includes: a discharge resistor R12, one end of which is connected to the discharge capacitor; an NMOS transistor T2, the drain of which is connected to the other end of the discharge resistor R12 and the source of which is grounded; a trigger circuit, which is connected to the gate of the NMOS transistor T2 and externally connected to a trigger signal; a protection circuit, which is respectively connected to the trigger circuit and the discharge resistor R12; when the trigger signal changes from a high level to a low level, the trigger circuit sends a high level signal to the NMOS transistor T2 based on the low level trigger signal, and the NMOS transistor T2 is turned on to release the energy of the discharge capacitor; the trigger circuit includes a third input terminal; an NMOS transistor T6; a second comparator, the second positive input of which is connected to a voltage source VCC, the second negative input of which is connected to the source of the NMOS transistor T6, and the second output of which is connected to the gate of the NMOS transistor T2. After adopting the above technical solution, fast reset and fast shutdown are possible, and the protection blanking time can be adjusted by RC parameter configuration.

Description

Technical Field

[0001] The present invention relates to the field of vehicle control, and in particular to an active discharge system for capacitors and a vehicle. Background Art

[0002] With the rapid development of new energy vehicles, users have put forward various requirements for the user experience of new energy vehicles. In the vehicle, capacitors are connected to both ends of the battery to store energy.

[0003] When the battery circuit is disconnected, since it is not disconnected from the capacitor, the capacitor will discharge the battery energy after storing enough energy.

[0004] Therefore, a new active discharge system and vehicle for capacitors are needed, which can protect the discharge resistor in a short time and actively release the energy in the capacitor. Summary of the Invention

[0005] In order to overcome the above technical defects, the purpose of the present invention is to provide an active discharge system and vehicle for capacitors, which can be quickly reset and shut down, and the protection blanking time can be adjusted through RC parameter configuration.

[0006] The present invention discloses an active discharge system for a capacitor, comprising a battery and a discharge capacitor connected to both ends of the battery. The active discharge system further comprises:

[0007] A discharge resistor R12, one end of which is connected to the discharge capacitor;

[0008] NMOS transistor T2, the drain is connected to the other end of the discharge resistor R12, and the source is grounded;

[0009] The trigger circuit is connected to the gate of the NMOS transistor T2 and is externally connected to a trigger signal;

[0010] The protection circuit is connected to the trigger circuit and the discharge resistor R12 respectively;

[0011] When the trigger signal changes from a high level to a low level, the trigger circuit sends a high level signal to the NMOS transistor T2 based on the low level trigger signal, and the NMOS transistor T2 is turned on to release the energy of the discharge capacitor. The trigger circuit includes:

[0012] A third input terminal receives a trigger signal;

[0013] NMOS transistor T6, the gate of which is connected to the third input terminal and the source of which is grounded;

[0014] The second comparator includes a second positive input, a second negative input, and a second output. The second positive input is connected to a voltage source VCC, the second negative input is connected to the drain of the NMOS transistor T6, the second output is connected to the gate of the NMOS transistor T2, and the second output serves as the first output terminal of the trigger circuit.

[0015] Preferably, the protection circuit includes:

[0016] Voltage source VCC;

[0017] A first input terminal connected to a first output terminal of the trigger circuit;

[0018] NMOS transistor T3, the gate of which is connected to the first input terminal and the source of which is grounded;

[0019] A first comparator includes a first positive input, a first negative input, and a first output, wherein the first positive input is connected to the voltage source VCC, the first negative input is connected to the drain of the NMOS transistor T3, and the first output is connected to the second input terminal of the trigger circuit;

[0020] When the first output terminal of the trigger circuit outputs a high level signal, the NMOS tube T3 sets the first negative input to a low level, and the first output of the first comparator sets the first output to a high level, so that the first output terminal of the trigger circuit outputs a low level.

[0021] Preferably, the trigger circuit further includes:

[0022] NMOS transistor T7, whose gate is connected to the first output of the first comparator, whose source is connected to the drain of NMOS transistor T6, and whose drain is connected to the voltage source VCC;

[0023] Resistor R27, one end of which is connected to the drain of NMOS transistor T6, and the other end of which is connected to the source of NMOS transistor T7;

[0024] Resistor R9, one end of which is connected to the drain of NMOS transistor T7, and the other end of which is connected to the voltage source VCC;

[0025] a resistor R8, one end of which is connected to the voltage source VCC, and the other end of which is connected to the second negative phase input;

[0026] a resistor R25 having one end connected to the second negative phase input and the other end grounded;

[0027] Capacitor C1, one end of which is grounded, and the other end of which is connected to the second negative phase input;

[0028] a resistor R18, one end of which is connected to the second non-inverting input and the other end of which is grounded;

[0029] A resistor R4, one end of which is connected to the second non-inverting input, and the other end of which is connected to the voltage source VCC;

[0030] The resistor R31 has one end connected to the voltage source VCC and the other end connected to the second output.

[0031] The ratio of resistor R25 to resistor R8 is greater than the ratio of resistor R18 to resistor R4, the resistance of resistor R9 is much smaller than the parallel sum of resistor R8 and resistor R25, and the resistance of resistor R27 is much smaller than the parallel sum of resistor R8 and resistor R25 or is zero.

[0032] Preferably, the protection circuit includes:

[0033] Resistor R6, one end of which is connected to capacitor C8;

[0034] Resistor R7, one end of which is connected to capacitor C8 and the other end of which is grounded;

[0035] Capacitor C10 is connected in parallel across resistor R7;

[0036] Resistor R23, one end of which is connected to the voltage source VCC;

[0037] One end of the Schottky diode SD3 is connected to the other end of the resistor R23;

[0038] One end of the Schottky diode SD2 is connected to the other end of the Schottky diode SD3;

[0039] A resistor R21 has one end connected to the voltage source VCC and the other end connected to the other end of the Schottky diode SD2;

[0040] A resistor R13, one end of which is grounded, and the other end of which is connected to the first non-inverting input;

[0041] a resistor R19, one end of which is connected to the voltage source VCC, and the other end of which is connected to the first non-inverting input;

[0042] A resistor R11, one end of which is connected to the drain of the NMOS transistor T3, and the other end of which is connected to the first negative phase input;

[0043] Capacitor C5, one end of which is grounded, and the other end of which is connected to resistor R11;

[0044] Resistor R20, one end of which is grounded and the other end of which is connected to resistor R11;

[0045] Resistor R10, one end of which is connected to the voltage source VCC, and the other end of which is connected to the first negative phase input.

[0046] The ratio of the resistor R20 to the resistor R10 is greater than the ratio of the resistor R13 to the resistor R19 , and the ratio of the parallel sum of the resistor R20 and the resistor R1 to the resistor R10 is less than the ratio of the resistor R13 to the resistor R19 .

[0047] Preferably, the protection circuit is replaced with the following configuration, including:

[0048] An NMOS transistor T5, having a gate connected to the first input terminal and a source connected to the first non-inverting input of the first comparator;

[0049] An NMOS transistor T9, having a gate connected to the first input terminal and a source connected to the first negative input of the first comparator;

[0050] Schottky diode SD2, with its cathode connected to the source of NMOS transistor T5 and its anode connected to voltage source VCC;

[0051] a resistor R11, one end of which is connected to the voltage source VCC, and the other end of which is connected to the first negative input of the first comparator;

[0052] A resistor R12', one end of which is grounded, and the other end of which is connected to the first negative input of the first comparator;

[0053] Resistor R13, one end of which is grounded, and the other end of which is connected to the drain of NMOS transistor T9;

[0054] Resistor R24, one end of which is grounded, and the other end of which is connected to the drain of NMOS transistor T5;

[0055] Capacitor C5, one end of which is grounded, and the other end is connected to resistor R11.

[0056] The voltage across the resistor R12 ′ is smaller than the voltage across the resistor R24 ​​and smaller than the voltage across the resistor R13 .

[0057] Preferably, the active discharge system further comprises: a time delay circuit connected to the trigger circuit and externally connected to a trigger signal, wherein the time delay circuit comprises:

[0058] NMOS transistor T4, the gate receives the trigger signal and the source is grounded;

[0059] The voltage source VCC is connected to the drain of the NMOS transistor T4;

[0060] Capacitor C3, one end of which is grounded, and the other end of which is connected to the voltage source VCC;

[0061] Resistor R1, one end of which is connected to the voltage source VCC;

[0062] Resistor R15, one end of which is connected to the voltage source VCC, and the other end of which is connected to the capacitor C3;

[0063] A third comparator includes a third positive-phase input, a third negative-phase input, and a third output, wherein the third positive-phase input is connected to the resistor R1, and the third negative-phase input is connected to the drain of the NMOS transistor T4;

[0064] When the trigger signal changes from a high level to a low level, NMOS transistor T4 is disconnected, and capacitor C3 discharges within a hysteresis time. After the hysteresis time, the potential at the connection point between resistor R15 and the third negative input is greater than the potential at the connection point between resistor R1 and the third positive input, causing the third output of the third comparator to be low, thereby sending a low-level signal to the trigger circuit.

[0065] Preferably, the delay circuit further includes:

[0066] a resistor R17 having one end connected to the third negative phase input and the other end grounded;

[0067] A resistor R5, one end of which is connected to the third non-inverting input and the other end of which is grounded;

[0068] Capacitor C2, one end of which is connected to the third non-inverting input and the other end of which is grounded;

[0069] a resistor R16, one end of which is connected to the voltage source VCC, and the other end of which is connected to the third output;

[0070] Resistor R5, one end of which is grounded, and the other end of which is connected to the third positive input of the third comparator.

[0071] The ratio of the resistor R17 to the resistor R15 is greater than the ratio of the resistor R5 to the resistor R1.

[0072] The present invention also discloses a vehicle, comprising the active discharge system as described above.

[0073] Compared with the existing technology, the above technical solution has the following beneficial effects:

[0074] Can provide millisecond-level fast protection to prevent the discharge resistor from overheating;

[0075] The protection blanking time is adjustable and can be configured through RC parameters;

[0076] The trigger circuit has pulse width limitation and can be reset and shut down quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 A schematic structural diagram of an active discharge system in accordance with a preferred embodiment of the present invention;

[0078] Figure 2 A schematic diagram of a circuit design of a trigger circuit according to a preferred embodiment of the present invention;

[0079] Figure 3 A schematic diagram of a circuit design of a trigger circuit according to another preferred embodiment of the present invention;

[0080] Figure 4a A schematic diagram of a circuit design of a protection circuit according to a preferred embodiment of the present invention;

[0081] Figure 4b A schematic diagram of a circuit design of another protection circuit according to a preferred embodiment of the present invention;

[0082] Figure 5 A schematic diagram of a circuit design of an active discharge system in accordance with a preferred embodiment of the present invention;

[0083] Figure 6 A schematic diagram of a trigger signal of an active discharge circuit, a discharge condition of a discharge capacitor, and an output signal of the trigger circuit in accordance with a preferred embodiment of the present invention;

[0084] Figure 7 A schematic diagram of a circuit design of a delay circuit in accordance with a preferred embodiment of the present invention;

[0085] Figure 8a A schematic diagram of a signal output by a delay circuit when a trigger signal switches between high and low levels in accordance with a preferred embodiment of the present invention;

[0086] Figure 8b Schematic diagram of the output signal of the delay circuit when the trigger signal switches between high and low levels in accordance with a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0087] The advantages of the present invention are further described below with reference to the accompanying drawings and specific embodiments.

[0088] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0089] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0090] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining."

[0091] In the description of the present invention, it should be understood that the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0092] In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal communication between two components. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances.

[0093] In the following description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention and have no specific meaning. Therefore, "module" and "component" can be used interchangeably.

[0094] See Figure 1, is a structural diagram of an active discharge system for a capacitor in accordance with a preferred embodiment of the present invention. In this embodiment, the active discharge system is used to controllably release the energy of the capacitor. Therefore, the active discharge system includes a battery and a discharge capacitor connected to both ends of the battery (or macroscopically understood as connected to the battery). In order to quickly and controllably consume the energy of the discharge capacitor, the active discharge system also includes: a discharge resistor R12, one end of which is connected to the discharge capacitor; an NMOS transistor T2, the drain of which is connected to the other end of the discharge resistor R12 and the source is grounded; a trigger circuit, which is connected to the gate of the NMOS transistor T2 and is externally connected to a trigger signal; and a protection circuit, which is respectively connected to the trigger circuit and the discharge resistor R12. It can be understood that when the battery circuit is disconnected, a trigger signal will be generated to indicate the occurrence of the event, especially when the trigger signal changes from a high level to a low level, the trigger circuit sends a high level signal to the NMOS transistor T2 based on the low level trigger signal, and the NMOS transistor T2 is turned on, so that the circuits at both ends of the discharge capacitor are turned on, thereby releasing the energy therein. To achieve the above technical effects, refer to Figure 2 In a preferred embodiment, the trigger circuit includes: a third input terminal for receiving a trigger signal; a control chip U1 (whose model may be TLC555), including a trigger terminal (Trig), a threshold terminal (Thresh), and an output terminal (Out). The trigger terminal is connected to the third input terminal to receive the trigger signal. When the trigger signal changes to a low level and is less than the threshold voltage of the control chip U1 output by the threshold terminal, the control chip U1 will control the output terminal to output a high level signal, thereby realizing the requirement that the trigger circuit outputs a high level based on a low level.

[0095] Furthermore, the trigger circuit further includes: a capacitor C3, one end of which is connected to the third input terminal; a resistor R5, one end of which is connected to the other end of the capacitor C3 and the other end of which is connected to the trigger terminal; a voltage source VCC; a resistor R2, one end of which is connected to the voltage source VCC and the other end of which is connected to the trigger terminal; a capacitor C2, one end of which is grounded and the other end of which is connected to the trigger terminal; a voltage source VCC; a resistor R1, one end of which is connected to the voltage source VCC and the other end of which is connected to the trigger terminal; a capacitor C4, one end of which is grounded and the other end of which is connected to the reset terminal of the control chip U1; a resistor R3, one end of which is connected to the voltage source VCC and the other end of which is connected to the reset terminal; a capacitor C1, one end of which is grounded and the other end of which is connected to the voltage terminal of the control chip U1; and a discharge terminal of the control chip U1 connected to the threshold terminal. In the initial state, the trigger signal is high, the NMOS transistor T1 is turned on, the reset terminal (Reset) is low, the control chip U1 is in the reset state, the output terminal (OUT) of the control chip U1 is low, and the voltage of the capacitor C2 is reduced to 0 through the discharge terminal (Disch). When the trigger signal transitions from high to low, NMOS transistor T1 turns off, the reset terminal (Reset) transitions from low to high, and the trigger terminal (Trig) temporarily transitions from high to low. Capacitor C2 begins charging from zero, and the output terminal (OUT) goes high. Resistor R2 charges capacitor C3, quickly returning the trigger terminal (Trig) to a high level (VCC). Resistor R3 then charges capacitor C2 until the threshold terminal (Thresh) exceeds the threshold voltage, causing the output terminal (OUT) to transition from a high level to a low level. The output pulse width is adjustable by adjusting the values ​​of resistor R1 and capacitor C2. When the discharge trigger signal returns to a high level, NMOS transistor T1 turns on, resetting control chip U1. Capacitor C2 rapidly discharges to zero through the discharge terminal (Disch). Capacitor C3 is clamped by SD1, and the trigger terminal (Trig) remains at a high level (VCC).

[0096] See Figure 3, shows another circuit design for a trigger circuit. In this embodiment, the trigger circuit includes: a third input terminal for receiving a trigger signal; an NMOS transistor T6, with its gate connected to the third input terminal and its source grounded; and a second comparator, including a second positive input, a second negative input, and a second output. The second positive input is connected to the voltage source VCC, the second negative input is connected to the drain of the NMOS transistor T6, and the second output is connected to the gate of the NMOS transistor T2, with the second output serving as the first output terminal. When the third input terminal receives a low level, the NMOS transistor T6 is disconnected, causing its source to be low. The second negative input of the second comparator, connected to the source of the NMOS transistor T6, is also low. When the second positive input is connected to the power supply terminal P10V and remains high, the second output of the second comparator is high. The second output then serves as the first output terminal. The protection circuit receives this high level signal, and the NMOS transistor T2 connected to the second output also receives this high level signal, causing the NMOS transistor T2 to conduct and release the energy of the discharge capacitor. When the third input terminal receives a normal high level of the battery, the NMOS transistor T6 is turned on, so that its source is set to high (and the voltage is higher than 10V). The second negative input of the second comparator connected to the source of the NMOS transistor T6 is set to high. When the second positive input is connected to the power supply terminal P10V and is always in a high state (but lower than the source voltage of the NMOS transistor T6), the second output of the second comparator is low. The NMOS transistor T2 connected to the second output will also receive the low-level signal and be disconnected.

[0097] Furthermore, the trigger circuit further includes: an NMOS transistor T7, having a gate connected to the first output of the first comparator, a source connected to the drain of the NMOS transistor T6, and a drain connected to the voltage source VCC; a resistor R27, having one end connected to the drain of the NMOS transistor T6 and the other end connected to the source of the NMOS transistor T7; a resistor R9, having one end connected to the drain of the NMOS transistor T7 and the other end connected to the voltage source VCC; a resistor R8, having one end connected to the voltage source VCC and the other end connected to the second negative phase input; a resistor R25, having one end connected to the second negative phase input and the other end connected to ground; a capacitor C1, having one end connected to ground and the other end connected to the second negative phase input; a resistor R18, having one end connected to the second positive phase input and the other end connected to ground; a resistor R4, having one end connected to the second positive phase input and the other end connected to the voltage source VCC; and a resistor R31, having one end connected to the voltage source VCC and the other end connected to the second output. In the above embodiment, the resistors R4 and R25 function as voltage dividers. Furthermore, in the initial state, the trigger signal is high, NMOS transistor T6 is turned on, and because the resistance of resistor R27 is much smaller than the parallel sum of resistors R8 and R25 or zero, the voltage of capacitor C1 is Vc0. The voltage at the second negative input terminal of the second comparator is the voltage of capacitor C1, and the voltage at the second positive input terminal of the second comparator is the voltage of the voltage divided by R18 and R4, V+, with V+>Vc0. Since NMOS transistor T8 is turned on, the second output of the second comparator is low. When the trigger signal changes from high to low, NMOS transistors T6 and T8 are turned off. Since V+ is greater than the voltage of capacitor C1, the second comparator outputs a high level. The voltage divider circuit of resistors R8 and R25 charges capacitor C1. When the voltage of C1 is greater than V+, the second comparator flips, outputting a low level and maintaining it. The duration of the high-level pulse output is adjustable by the R and C parameters. When the trigger signal goes high again, NMOS transistors T6 and T8 turn on, the second comparator outputs a low level, and capacitor C1 quickly discharges to Vc0 for reset. The gate input of NMOS transistor T7 receives a protection signal (active high). When the protection signal is high, NMOS transistor T7 turns on, quickly charging capacitor C1 through resistor R9 to a voltage greater than V+, and outputting a low level.

[0098] In a preferred embodiment, the protection circuit includes a voltage source VCC; a first input terminal connected to the first output terminal of the trigger circuit, receiving a change in the level signal of the first output terminal after a change within the trigger circuit; an NMOS transistor T3, with a gate connected to the first input terminal and a source connected to ground; and a first comparator including a first positive input, a first negative input, and a first output, wherein the first positive input is connected to the voltage source VCC, the first negative input is connected to the drain of the NMOS transistor T3, and the first output is connected to the second input terminal of the trigger circuit. When the first output terminal of the trigger circuit outputs a high-level signal, the NMOS transistor T3 is disconnected, causing the first negative input connected to the source of the NMOS transistor T3 to be low. The first output of the first comparator is high due to being connected to the voltage source VCC, resulting in a high-level output of the first comparator. After the high-level signal is fed back to the trigger circuit, the trigger circuit, based on the high-level signal, converts its internal output for the new high-level signal into a low-level output at the first output terminal. Figure 6 In other words, the trigger circuit will go through the process of outputting a high-level signal to a low-level signal. When it outputs a high-level signal, the two ends of the discharge capacitor are connected and the energy is released. When it converts to outputting a low level, the two ends of the discharge capacitor are disconnected, and the discharge capacitor enters the energy storage state again. The time that the trigger circuit maintains the output high level is the time that current flows through the discharge resistor R12. Controlling this time can prevent the discharge resistor R12 from overheating and being damaged.

[0099] More preferably, see Figure 4aThe protection circuit includes: a resistor R6, one end of which is connected to the capacitor C8; a resistor R7, one end of which is connected to the capacitor C8 and the other end is grounded; a capacitor C10, connected in parallel to both ends of the resistor R7; a resistor R23, one end of which is connected to the voltage source VCC; a Schottky diode SD3, one end of which is connected to the other end of the resistor R23; a Schottky diode SD2, one end of which is connected to the other end of the Schottky diode SD3; a resistor R21, one end of which is connected to the voltage source VCC and the other end of which is connected to the other end of the Schottky diode SD2; a resistor R13, one end of which is grounded and the other end of which is connected to the first positive-phase input; a resistor R19, one end of which is connected to the voltage source VCC and the other end of which is connected to the first positive-phase input; a resistor R11, one end of which is connected to the drain of the NMOS transistor T3 and the other end of which is connected to the first negative-phase input; a capacitor C5, one end of which is grounded and the other end of which is connected to the resistor R11; and a resistor R20, one end of which is grounded and the other end of which is connected to the resistor R11. Schottky diodes SD3 and SD2 serve as clamping protection. Furthermore, in the initial state, the trigger signal is high, the discharge drive signal is low, NMOS transistor T3 is off, and the first negative input voltage of the first comparator is the voltage of capacitor C5 (divided by resistors R10 and R20). The first positive input of the first comparator is the voltage divided by resistors R19 and R13. If the first positive input of the first comparator is less than the first negative input of the first comparator, the first comparator outputs a low level. In the normal discharge state, the discharge drive signal is high, NMOS transistor T3 is on, and the voltage of capacitor C5 begins to discharge until it reaches the voltage of the parallel sum of resistors R11 and R20, divided by R10. Since the voltage of capacitor C8 remains essentially unchanged, the voltage across resistor R7 changes proportionally with the decrease in the high voltage, and the voltage of the first positive input of the first comparator also decreases. During the discharge process, the voltage of the first positive input of the first comparator remains lower than the voltage of the first negative input of the first comparator, and the first comparator outputs a low level. In the abnormal discharge state, the voltage of the first positive input of the first comparator remains unchanged or decreases significantly slowly. When the voltage of capacitor C5 drops below the voltage of the first positive input of the first comparator, the first comparator flips and outputs a high-level protection signal.

[0100] See Figure 5 , which is the circuit design of the entire discharge circuit. Another protection circuit design is adopted, and reference is made to Figure 4bIn this embodiment, the protection circuit is replaced with the following configuration, including: an NMOS transistor T5, with its gate connected to the first input terminal and its source grounded; an NMOS transistor T9, with its gate connected to the first input terminal, its source connected to the voltage source VCC, and its drain connected to the first negative input of the first comparator; a Schottky diode SD2, with its cathode connected to the source of the NMOS transistor T5 and its anode connected to the voltage source VCC. The protection circuit also includes a resistor R6, one end of which is connected to a capacitor C8; a resistor R7, one end of which is connected to the capacitor C8 and its other end is grounded; a capacitor C10 connected in parallel across resistor R7; a capacitor C8, one end of which is connected between resistors R6 and R7 and its other end is connected to the first positive input of the first comparator; and a resistor R11, one end of which is connected to the voltage source VCC and its other end is connected to the first negative input of the first comparator. When the signal at the first input terminal is high, the voltage source VCC is divided by the resistor R11 to the first negative input, the NMOS transistor T9 is turned on, and the voltage source VCC is divided by the resistor R10 to the first negative input, while the first positive input is only the voltage source VCC divided by the resistor R21. The first negative input of the first comparator is high, so that the first output is low. When the signal at the first input terminal changes from high to low, the voltage source VCC is divided by the resistor R11 to the first negative input, the first positive input is the voltage source VCC divided by the resistor R21, and the capacitor C8 is discharged, so that the first negative input of the first comparator is low, so that the first output is high. However, as the capacitor C8 is discharged, the first negative input of the first comparator is high, so that the first output is low. Therefore, the first comparator outputs a high level only for a certain period of time, which plays a protective role. In other words, because the voltage across resistor R12' is less than the voltage across resistor R24, which is less than the voltage across resistor R13, and the time constant of the RC circuit formed by the parallel connection of capacitor C5, resistors R12', and R11 is relatively large, the voltage at the first positive input of the first comparator remains lower than the voltage at the first negative input of the first comparator during normal discharge. In the initial state, when the trigger signal is high, NMOS transistors T5 and T9 are turned on, capacitor C5 is connected to the first negative input of the first comparator, and the voltage equals the voltage across resistor R13. The first positive input of the first comparator is the voltage across resistor R24, which is higher than the voltage across resistor R24, and the first output of the first comparator is low. When the trigger signal is low, NMOS transistors T5 and T9 are turned off, the voltage across capacitor C8 remains unchanged, and the first positive input of the first comparator changes with the discharge high voltage. Resistors R7 and R6 serve as discharge voltage sampling resistors. The voltage across capacitor C5 is discharged through resistors R11 and R12'.When the high voltage discharges normally, the voltage on the first non-inverting input of the first comparator decreases, the voltage on capacitor C5 remains higher than the first non-inverting input of the first comparator, and the first output of the first comparator is low. When the high voltage discharge is abnormal, that is, it cannot discharge or discharges slowly, the voltage on the first non-inverting input of the first comparator remains unchanged or changes slowly. During the decreasing process, the voltage on capacitor C5 intersects with the first non-inverting input voltage of the first comparator, causing the first comparator to flip and output a high-level protection signal. When the trigger signal returns to a high level again, NMOS transistors T5 and T9 turn on, quickly returning to the reset state.

[0101] To achieve the effect of time delay, in this embodiment, a time delay circuit is further included, which is connected to the trigger circuit so that the trigger circuit will indirectly receive the trigger signal. Figure 7 The delay circuit specifically includes: an NMOS transistor T4, whose gate receives a trigger signal and whose source is grounded; a voltage source VCC connected to the drain of the NMOS transistor T4; a capacitor C3, one end of which is grounded and the other end is connected to the voltage source VCC; a resistor R1, one end of which is connected to the voltage source VCC; a resistor R15, one end of which is connected to the voltage source VCC and the other end is connected to the capacitor C3; a third comparator, including a third positive input, a third negative input, and a third output, wherein the third positive input is connected to the resistor R1, and the third negative input is connected to the drain of the NMOS transistor T4. When the trigger signal is a high-level signal (or changes from a low level to a high level), the NMOS transistor T4 is in the on state, so that its drain has current. At the same time, due to the connection of the capacitor C3, the current charges the capacitor C3, so that the third negative input is low, and the third positive input is connected to the power supply terminal P10V through the resistor R1, so that the third positive input is high, and the third output of the third comparator is high. There is no delay from the receipt of the high-level trigger signal to the third output being high, that is, there is no lag in the rising edge stage of the trigger signal (see Figure 8a On the other hand, when the trigger signal changes from a high level to a low level, the NMOS transistor T4 is disconnected, and the capacitor C3 will discharge within a hysteresis time, forming a charging circuit from the voltage source VCC, the resistor R15 to the capacitor C3. At this time, since the resistance of the resistor R15 is greater than the resistance of the resistor R1, the potential at the connection point between the resistor R15 and the third negative input is greater than the potential at the connection point between the resistor R1 and the third positive input, that is, the third output of the third comparator is set low, sending a low-level signal to the trigger circuit. In other words, during the falling edge of the trigger signal, although the output to the trigger circuit is ultimately low, since the capacitor C3 discharges within the hysteresis time (see Figure 8b ), the setting of the third negative phase input to high will be delayed, so that the low-level signal sent by the delay circuit lags behind the trigger signal, further playing a delay role.

[0102] In a preferred embodiment, the delay circuit further includes: a resistor R17, one end of which is connected to the third negative input and the other end is grounded; a resistor R5, one end of which is connected to the third positive input and the other end is grounded; a capacitor C2, one end of which is connected to the third positive input and the other end is grounded; and a resistor R16, one end of which is connected to the voltage source VCC and the other end is connected to the third output. Furthermore, a resistor R5, one end of which is grounded and the other end of which is connected to the third positive input of the third comparator, wherein the ratio of the resistor R17 to the resistor R15 is greater than the ratio of the resistor R5 to the resistor R1. In the initial state, the trigger signal is high, the NMOS transistor T4 is turned on, the voltage on the capacitor C3 is 0, the third negative input voltage of the third comparator is 0, the third positive input voltage of the third comparator is VCC, the voltage divided by the resistor R1 and the resistor R5, V+, and the third output of the third comparator is high. When the trigger signal transitions from high to low, NMOS transistor T4 turns off, and voltage source VCC charges capacitor C3 via the voltage divider circuit formed by resistors R15 and R17. When the voltage on capacitor C3 exceeds V+, the third output of the third comparator flips to a low level. This implements a delayed output function, with the delay time adjustable by the R and C parameters. When the trigger signal transitions high again, NMOS transistor T4 turns on, rapidly discharging capacitor C3 to zero, and the third output of the third comparator returns to a high level.

[0103] After having the active discharge system in any of the above embodiments, it can be applied to a vehicle.

[0104] It should be noted that the embodiments of the present invention have better practicability and do not impose any form of limitation on the present invention. Any technician familiar with the field may use the technical content disclosed above to change or modify it into an equivalent effective embodiment. However, any modification or equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. An active discharge system for a capacitor, comprising a battery and a discharge capacitor connected to both ends of the battery, characterized in that: The active discharge system further comprises: a discharge resistor R12, one end of which is connected to the discharge capacitor; NMOS transistor T2, the drain of which is connected to the other end of the discharge resistor R12, and the source of which is grounded; a trigger circuit connected to the gate of the NMOS transistor T2 and externally connected to a trigger signal, wherein the trigger signal is generated when the battery circuit is disconnected; A protection circuit is connected to the trigger circuit and the discharge resistor R12 respectively; When the trigger signal changes from a high level to a low level, the trigger circuit sends a high level signal to the NMOS transistor T2 based on the low level trigger signal, and the NMOS transistor T2 is turned on, so that the circuits at both ends of the discharge capacitor are turned on to release the energy of the discharge capacitor, wherein the trigger circuit includes: A third input terminal, receiving the trigger signal; NMOS transistor T6, the gate of which is connected to the third input terminal and the source of which is grounded; The second comparator includes a second positive input, a second negative input, and a second output. The second positive input is connected to a voltage source VCC, the second negative input is connected to the drain of the NMOS transistor T6, the second output is connected to the gate of the NMOS transistor T2, and the second output serves as the first output terminal of the trigger circuit.

2. The active discharge system according to claim 1, wherein: The protection circuit comprises: The voltage source VCC; a first input terminal connected to the first output terminal of the trigger circuit; NMOS transistor T3, the gate of which is connected to the first input terminal and the source of which is grounded; A first comparator includes a first positive input, a first negative input, and a first output, wherein the first positive input is connected to the voltage source VCC, the first negative input is connected to the drain of the NMOS transistor T3, and the first output is connected to the second input terminal of the trigger circuit; When the first output terminal of the trigger circuit outputs a high level signal, the NMOS transistor T3 sets the first negative input to a low level, and the first output of the first comparator sets the first output to a high level, so that the first output terminal of the trigger circuit outputs a low level.

3. The active discharge system according to claim 2, wherein: The trigger circuit further includes: an NMOS transistor T7, whose gate is connected to the first output of the first comparator, whose source is connected to the drain of the NMOS transistor T6, and whose drain is connected to the voltage source VCC; Resistor R27, one end of which is connected to the drain of NMOS transistor T6, and the other end of which is connected to the source of NMOS transistor T7; Resistor R9, one end of which is connected to the drain of NMOS transistor T7, and the other end of which is connected to the voltage source VCC; a resistor R8, one end of which is connected to the voltage source VCC, and the other end of which is connected to the second negative phase input; a resistor R25, one end of which is connected to the second negative phase input and the other end of which is grounded; A capacitor C1, one end of which is grounded, and the other end of which is connected to the second negative phase input; a resistor R18, one end of which is connected to the second non-inverting input and the other end of which is grounded; a resistor R4, one end of which is connected to the second non-inverting input, and the other end of which is connected to the voltage source VCC; The resistor R31 has one end connected to the voltage source VCC and the other end connected to the second output. The ratio of resistor R25 to resistor R8 is greater than the ratio of resistor R18 to resistor R4, the resistance of resistor R9 is much smaller than the parallel sum of resistor R8 and resistor R25, and the resistance of resistor R27 is much smaller than the parallel sum of resistor R8 and resistor R25 or is zero.

4. The active discharge system according to claim 2, wherein: The protection circuit comprises: Resistor R6, one end of which is connected to capacitor C8; Resistor R7, one end of which is connected to capacitor C8 and the other end of which is grounded; A capacitor C10 is connected in parallel to both ends of the resistor R7; Resistor R23, one end of which is connected to the voltage source VCC; a Schottky diode SD3 , one end of which is connected to the other end of the resistor R23 ; a Schottky diode SD2, one end of which is connected to the other end of the Schottky diode SD3; a resistor R21, one end of which is connected to the voltage source VCC, and the other end of which is connected to the other end of the Schottky diode SD2; A resistor R13, one end of which is grounded, and the other end of which is connected to the first non-inverting input; a resistor R19, one end of which is connected to the voltage source VCC, and the other end of which is connected to the first non-inverting input; a resistor R11, one end of which is connected to the drain of the NMOS transistor T3, and the other end of which is connected to the first negative phase input; Capacitor C5, one end of which is grounded, and the other end of which is connected to the resistor R11; A resistor R20, one end of which is grounded, and the other end of which is connected to the resistor R11; Resistor R10, one end of which is connected to the voltage source VCC, and the other end of which is connected to the first negative phase input. The ratio of the resistor R20 to the resistor R10 is greater than the ratio of the resistor R13 to the resistor R19 , and the ratio of the parallel sum of the resistor R20 and the resistor R1 to the resistor R10 is less than the ratio of the resistor R13 to the resistor R19 .

5. The active discharge system according to claim 4, characterized in that: The protection circuit is replaced with the following configuration, including: An NMOS transistor T5, having a gate connected to the first input terminal and a source connected to the first non-inverting input of the first comparator; An NMOS transistor T9, having a gate connected to the first input terminal and a source connected to the first negative input of the first comparator; a Schottky diode SD2 , having a cathode connected to the source of the NMOS transistor T5 and an anode connected to the voltage source VCC; a resistor R11, one end of which is connected to the voltage source VCC, and the other end of which is connected to the first negative input of the first comparator; A resistor R12', one end of which is grounded, and the other end of which is connected to the first negative input of the first comparator; Resistor R13, one end of which is grounded, and the other end of which is connected to the drain of NMOS transistor T9; Resistor R24, one end of which is grounded, and the other end of which is connected to the drain of NMOS transistor T5; Capacitor C5, one end of which is grounded, and the other end of which is connected to the resistor R11. The voltage across the resistor R12 ′ is smaller than the voltage across the resistor R24 ​​and smaller than the voltage across the resistor R13 .

6. The active discharge system according to claim 1, wherein: The active discharge system further includes a time delay circuit connected to the trigger circuit and connected to an external trigger signal, wherein the time delay circuit includes: NMOS transistor T4, the gate of which receives the trigger signal and the source of which is grounded; A voltage source VCC is connected to the drain of the NMOS transistor T4; Capacitor C3, one end of which is grounded, and the other end of which is connected to the voltage source VCC; a resistor R1, one end of which is connected to the voltage source VCC; a resistor R15, one end of which is connected to the voltage source VCC, and the other end of which is connected to the capacitor C3; A third comparator includes a third positive-phase input, a third negative-phase input, and a third output, wherein the third positive-phase input is connected to the resistor R1, and the third negative-phase input is connected to the drain of the NMOS transistor T4; When the trigger signal changes from a high level to a low level, the NMOS transistor T4 is disconnected, and the capacitor C3 is discharged within a hysteresis time. After the hysteresis time, the potential at the connection point between the resistor R15 and the third negative phase input is greater than the potential at the connection point between the resistor R1 and the third positive phase input, so that the third output of the third comparator is set low, thereby sending a low-level signal to the trigger circuit.

7. The active discharge system according to claim 6, characterized in that: The delay circuit further includes: a resistor R17, one end of which is connected to the third negative phase input and the other end of which is grounded; a resistor R5, one end of which is connected to the third non-inverting input and the other end of which is grounded; a capacitor C2, one end of which is connected to the third non-inverting input and the other end of which is grounded; a resistor R16, one end of which is connected to the voltage source VCC, and the other end of which is connected to the third output; Resistor R5, one end of which is grounded, and the other end of which is connected to the third positive input of the third comparator. The ratio of the resistor R17 to the resistor R15 is greater than the ratio of the resistor R5 to the resistor R1.

8. A vehicle, characterized in that: The invention comprises an active discharge system as described in any one of claims 1 to 7.

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