Design method and design system of digital waveguide devices based on algorithm fusion

Abstract

The present invention provides a design method and a design system for digital waveguide devices based on algorithm fusion, and the design method includes the following steps: according to the design requirements, determine the device function, optimization target and set the initial structure; divide the design area into discrete pixel points, use the topology optimization algorithm to optimize the dielectric constant of the pixel points, and perform binarization or multi-valued processing on the dielectric constant to obtain the topological structure; according to the minimum feature size of the process, re-divide the design area into discrete pixel blocks that meet the preparation requirements; perform binarization or multi-valued replacement on the pixel blocks of the design area one by one to obtain the initial digital waveguide structure; according to the device function, optimize the initial digital waveguide structure until the optimization target or termination condition is reached. The technical solution of the present invention expands the design method and design dimension of on-chip photonic devices, making the design more efficient.

Description

Technical Field

[0001] The present invention belongs to the technical field of on-chip photonic device design, and in particular relates to a design method and a design system for a digital waveguide device based on algorithm fusion. Background Art

[0002] The unit pixel size of digital waveguide structures (generally greater than 90 nm×90 nm) is usually determined according to the minimum feature size or process node of laboratory equipment. The binary search algorithm is a brute force search method commonly used in the design of digital waveguide structures. This method modifies the pixel properties of the design area one by one and saves the structure with better performance. Since only a limited number of pixel parameters are modified each time, this method has a huge computational overhead and is dependent on the initial structure. Although researchers may be able to obtain devices with good performance after multiple attempts and modifications to the initial structure, this greatly increases the time cost of the design. In addition, when the functional complexity of the device or the number of pixels increases sharply, it is difficult for researchers to find a suitable initial structure to obtain satisfactory device performance.

[0003] Topology optimization algorithm is a design method commonly used for analog waveguide structures. Compared with digital waveguide structures, the unit pixel size of analog waveguides is often much smaller (generally less than 40 nm×40 nm). Therefore, the analog waveguide structure optimized by the topology optimization algorithm can be composed of "arbitrary" topological shapes. Compared with the brute force search method or other heuristic algorithms of digital waveguides, the topology optimization algorithm only needs two simulations to determine the optimization direction of all pixels. However, in the actual preparation process, irregular analog waveguide structures are often difficult to prepare accurately, which will lead to a large difference between the performance of the actual device and the simulated performance.

[0004] In general, digital waveguide structures are easier to prepare and have higher error tolerance than analog waveguide structures optimized by topology optimization methods. Although the binary search method can be applied to digital waveguide structures, its algorithm has huge computational overhead and is dependent on the initial structure. The efficient topology optimization algorithm is an optimization algorithm for analog waveguide structures and cannot be directly applied to the design of digital waveguide structures. Summary of the invention

[0005] In view of the above technical problems, the present invention discloses a design method and a design system for digital waveguide devices based on algorithm fusion. The design method adopts the fusion of topology optimization algorithm and binary search algorithm to achieve efficient design of digital waveguide devices.

[0006] To this end, the technical solution adopted by the present invention is:

[0007] A design method and a design system for a digital waveguide device based on algorithm fusion, comprising the following steps:

[0008] Step S1, determining device functions, optimizing targets, and setting initial structures according to design requirements;

[0009] Step S2, dividing the design area into discrete pixel points, optimizing the dielectric constant of the pixel points using a topology optimization algorithm, and performing binarization or multi-valued processing on the dielectric constant to obtain a topological structure;

[0010] Step S3, re-dividing the design area into discrete pixel blocks that meet the manufacturing requirements according to the minimum feature size of the process; wherein the minimum feature size of the process is generally greater than 90 nm; and the size of the pixel block is greater than the size of the pixel point;

[0011] Step S4, performing binary or multi-value replacement on pixel blocks in the design area one by one to obtain an initial digital waveguide structure;

[0012] Step S5, according to the device performance, the initial digital waveguide structure is optimized by using a binary search algorithm, a brute force search method or a heuristic algorithm until the optimization target or the termination condition is reached.

[0013] Wherein, in step S2, the topology optimization algorithm is any inverse design method of an analog waveguide structure.

[0014] Furthermore, the minimum characteristic size of the pixel is 10 nm - 40 nm.

[0015] The binarization or multi-valued processing in step S2 specifically refers to biasing the dielectric constant of the pixel point to one of the dielectric constants of two or more different materials. The binarization or multi-valued replacement in step S4 is to replace the material attribute of the pixel area with a material closer to the optimization target by comparing the effects of two or more different replacement materials on the optimization target.

[0016] By adopting this technical solution, through the combination of topology optimization algorithm and binary search method, efficient design of digital waveguide structure can be achieved, which is expected to solve the problems that structures optimized by traditional topology optimization algorithm are difficult to accurately prepare and the binary search method has huge computational overhead and high dependence on the initial structure.

[0017] As a further improvement of the present invention, in step S1, the initial structure includes input and output waveguide positions, material properties of the device, and design area shape and size.

[0018] As a further improvement of the present invention, in step S5, the optimizing the initial digital waveguide structure includes but is not limited to optimizing the material properties, etching depth and pixel block shape of the pixel blocks of the initial digital waveguide structure.

[0019] As a further improvement of the present invention, the digital waveguide device based on algorithm fusion is made of silicon on insulator, III-V materials or polymers.

[0020] The present invention also discloses a design system for digital waveguide devices based on algorithm fusion, which comprises:

[0021] A design target input unit, used to determine the device function optimization target and set the initial structure according to the design requirements;

[0022] The dielectric constant optimization unit is used to divide the design area into discrete pixel points, optimize the dielectric constant of the pixel points using a topology optimization algorithm, and perform binary or multi-valued processing on the dielectric constant to obtain a topological structure;

[0023] A reset unit, used to re-divide the design area into discrete pixel blocks that meet the manufacturing requirements according to the minimum feature size of the process; wherein the minimum feature size of the process is generally greater than 90 nm; and the size of the pixel block is greater than the size of the pixel point;

[0024] A replacement unit, used for performing binary or multi-value replacement on pixel blocks in the design area one by one to obtain an initial digital waveguide structure;

[0025] The waveguide structure optimization unit is used to optimize the initial digital waveguide structure according to the device function by using a binary search algorithm, a brute force search method or a heuristic algorithm until the optimization target or the termination condition is reached.

[0026] Furthermore, the minimum characteristic size of the pixel is 10 nm - 40 nm.

[0027] As a further improvement of the present invention, the initial structure includes basic parameter settings of input and output waveguide positions, material properties of the device, and shape and size of the design area.

[0028] As a further improvement of the present invention, the optimizing the initial digital waveguide structure includes optimizing the material properties, etching depth and pixel block shape of the pixel blocks of the initial digital waveguide structure.

[0029] The present invention discloses a computer-readable storage medium, which includes a computer program. When the computer program runs on an electronic device, the electronic device executes the design method of a digital waveguide device based on algorithm fusion as described in any one of the above.

[0030] The present invention discloses a device, which comprises: a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the design method of a digital waveguide device based on algorithm fusion as described in any one of the above items is implemented.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The technical solution of the present invention can effectively solve the problems of the difficulty in accurately preparing the structure of the topology optimization algorithm, the huge computational overhead of the binary search algorithm, and the high dependence on the initial structure. It expands the design method and design dimension of on-chip photonic devices, makes the design more efficient, and supplements the existing digital waveguide device design method. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure of a dual-mode 3dB power beam splitter in an embodiment of the present invention, wherein (a) is a top view, (b) is a cross-sectional view of the input waveguide, and (c) is a cross-sectional view of the output waveguide.

[0034] Figure 2 Schematic diagram of the optimization process of the dual-mode 3dB power splitter according to an embodiment of the present invention. (a) is a schematic diagram of the topology optimization process, and (b) is a schematic diagram of the digitalization process of converting a non-manufacturable topological structure into a manufacturable digital structure and optimizing it.

[0035] Figure 3 The field intensity distribution diagram and transmission spectrum diagram of the dual-mode 3dB power splitter of the embodiment of the present invention. Among them, (a)-(h) respectively represent the field intensity distribution diagrams of the TE0 and TE1 mode light sources in the final optimized structure at different wavelengths (1580 nm, 1730 nm, 1880 nm and 2030 nm), (i), (j) and (k) are the output waveguide-1 transmission spectra of the topological optimized structure, the initial digital structure and the final optimized structure.

[0036] Figure 4 The device performance diagram of the dual-mode 3dB power beam splitter optimized by the conventional binary search method for the comparative example of the present invention. Among them, (a) is the device structure diagram, (b) and (c) are the field intensity distribution diagrams of the TE0 and TE1 mode light sources, and (d) is the transmission spectrum diagram of the output waveguide-1. DETAILED DESCRIPTION

[0037] The preferred embodiments of the present invention are described in further detail below.

[0038] The following is an explanation of the implementation of the present invention through specific embodiments. It should be noted that the diagrams and parameters provided in this embodiment only show components related to the present invention, rather than the materials, number of components, shapes and sizes in actual implementation.

[0039] Example 1

[0040] An ultra-wideband dual-mode 3dB power beam splitter is designed on a top silicon layer with a thickness of 220 nm, a silicon dioxide insulator with a thickness of 2 um, and an oxide capping layer with a thickness of 0.6 um. The schematic diagram is shown in the figure. Figure 1 As shown, the specific steps include the following

[0041] Step S1: According to the design requirements, determine the function of the digital waveguide structure, optimize the target and set the initial structure.

[0042] The function of the device is to split the TE0 and TE1 mode light sources in equal proportion. The optimization target is the sum of the transmittance of the TE0 and TE1 mode light sources with a wavelength of 1550 nm -2000 nm in the output waveguide-1. Figure 1 As shown in Figure 1, the device consists of an input port, two output ports and a design area in the middle. The width of the input and output waveguides is 1.2 um, and the gap between the two output waveguides is 0.48 um. The thickness of the buried layer and the cover layer are 2 um and 0.6 um respectively. The material properties are set as follows: Figure 1 As shown in the figure, the design area size is 5.4 um × 2.88 um. To prove the effectiveness of the method of the present invention, Figure 2 As shown in (a), the initial shape of the design area consists of a symmetrical random structure.

[0043] Step S2, dividing the design area into discrete pixels (20 nm × 20 nm), optimizing the dielectric constant of the pixels using a topology optimization algorithm, and binarizing the dielectric constant to obtain a topological structure;

[0044] In this step, the design area is divided into 270×144 small areas by discrete pixel points (20 nm × 20 nm). In this example, silicon and silicon dioxide are selected as binary materials. Figure 2 In the optimization process of the topology optimization algorithm shown in (a), the dielectric constant of each small pixel will be updated and eventually biased to the dielectric constant of silicon or silicon dioxide. Based on the above steps, an irregular topology structure will be optimized. Figure 3 As shown in the transmission spectrum of (i), whether it is TE0 mode or TE1 mode, the additional loss and crosstalk of the topological structure in the wavelength range of 1550 nm - 2100 nm are less than 0.36 dB and -19.6 dB respectively. Figure 2 As shown in the partial enlargement of (b), the unit pixel point of the topological structure (20 nm × 20nm) is very fine and exceeds the photolithography size of the existing process. In addition, although this nearly "arbitrary" topological structure can obtain extremely superior device performance, it is not feasible for preparation.

[0045] Step S3, re-dividing the design area into discrete pixel blocks suitable for laboratory preparation according to the minimum feature size prepared in the laboratory.

[0046] The topological structure unit pixel of step S2 is too fine and extremely irregular to be prepared experimentally. Here, 120 nm is selected as the minimum feature size in the laboratory. Figure 2 As shown in (b), the design area is re-divided into 45×24 equal-sized, discrete pixel blocks (120 nm × 120 nm) that meet the process requirements. Each pixel block has 36 equal-sized pixels, which are composed of two different materials. Since the dual-mode 3dB power splitter is a symmetrical structure, the 45×12 matrix A can represent the state of all pixels in the design area.

[0047] Step S4, binarizing and replacing the pixels in the design area one by one, thereby obtaining an initial digital structure.

[0048] Binarization replacement specific steps: Each element of matrix A is set to 3 discrete values ​​(0, 1 and 2) to represent 3 different states (filled with silicon, filled with silicon dioxide and untreated). In the initial state, the value of all elements of matrix A is 2. Figure 2 As shown in (b), one of the pixel blocks is taken as an example to illustrate the details of the binary replacement. When the filling material of the pixel block is silicon (silicon dioxide), the numerical size of the device's optimization target is Goal-1 (Goal-2). If Goal-1 > Goal-2, the element of the matrix A corresponding to the pixel point will be updated from 2 to 0, and the structure of Goal-1 will be maintained. If Goal-1 < Goal-2, the element of the corresponding matrix A will be changed from 2 to 1, and the structure of Goal-2 will be retained. By replacing the 2s of matrix A with 0 or 1 one by one, the topological structure of step S2 is changed to the initial digital structure (the specific structure is detailed in Figure 2 (b)), the device transmission efficiency is as follows Figure 3(j) As shown. For the TE0 (TE1) mode of the initial digital structure, the additional loss and crosstalk of the device at wavelengths of 1665 (1614) nm ~ 2050 nm are less than 1.0 dB and -23.0 (-14.9) dB, respectively. Compared with the topological structure of step S2, the device performance of the initial digital structure is slightly reduced, but the minimum feature size preparation requirements can be guaranteed in the experiment.

[0049] Step S5, according to the function of the digital waveguide structure, a binary search algorithm is used to optimize the material properties of the pixel blocks of the initial digital waveguide structure until the optimization target or the termination condition is reached.

[0050] Although the brute force replacement method in step S4 will lead to a decrease in device performance, the initial digital structure generated in step S4 is a good initial condition for the binary search method. Using the initial digital structure as the initial condition of the binary search algorithm, the algorithm can perform a brute force search on the design area at a higher device performance starting point.

[0051] After the binary search algorithm is optimized, the device performance is further improved, and the device transmission efficiency is shown in the figure below. Figure 3 (k) shows that the TE0 (TE1) mode of the final optimized dual-mode 3dB power splitter can maintain an additional loss of less than 0.96 (0.78) dB and a crosstalk of less than -18.5 (-22.2) dB in the wavelength range of 1575 nm - 2030 nm. Figure 3 (a)-(h) The field intensity distribution diagrams at different wavelengths show that the final optimized device has almost no mode conversion in the TE0 and TE1 mode light sources over such a wide wavelength range. Compared with the device performance in step S4, the device in this step has a larger bandwidth and smaller additional loss.

[0052] Comparative Example

[0053] Figure 4 The device structure, field intensity distribution and transmission spectrum of the dual-mode 3dB power splitter optimized by the traditional binary search method. Based on the same initial structure, the device optimized by the traditional binary search method can only keep the additional loss and crosstalk of the TE0 mode and TE1 mode less than 1.5 dB and -16.1 dB respectively in the wavelength range of 1628 nm - 1881 nm. Figure 3 From the transmission efficiency of the dual-mode 3dB power splitter of (k), it can be seen that the bandwidth of the dual-mode 3dB power splitter designed by the method of the embodiment of the present invention is much larger than that of the comparative example, and can maintain lower additional loss and crosstalk at a bandwidth of 455 nm.

[0054] Therefore, the embodiments of the present invention can effectively solve the problem that the structure of the traditional topology optimization algorithm is difficult to accurately prepare and the binary search algorithm is highly dependent on the initial structure, and expand the design method and design dimension of on-chip photonic devices.

[0055] The embodiment of the present invention further discloses a design system for a digital waveguide device based on algorithm fusion, which includes:

[0056] A design target input unit, used to determine the device function optimization target and set the initial structure according to the design requirements;

[0057] The dielectric constant optimization unit is used to divide the design area into discrete pixel points, optimize the dielectric constant of the pixel points using a topology optimization algorithm, and perform binary or multi-valued processing on the dielectric constant to obtain a topological structure;

[0058] A reset unit, used to re-divide the design area into discrete pixel blocks that meet the manufacturing requirements according to the minimum feature size of the process; wherein the minimum feature size of the process is generally greater than 90 nm; and the size of the pixel block is greater than the size of the pixel point;

[0059] A replacement unit, used for performing binary or multi-value replacement on pixel blocks in the design area one by one to obtain an initial digital waveguide structure;

[0060] The waveguide structure optimization unit is used to optimize the initial digital waveguide structure according to the device function by using a binary search algorithm, a brute force search method or a heuristic algorithm until the optimization target or the termination condition is reached.

[0061] Furthermore, the minimum characteristic size of the pixel is 10 nm - 40 nm.

[0062] Furthermore, the initial structure includes input and output waveguide positions, buried layers, cover layers, transmission waveguides, material properties of the design region, and basic parameter settings.

[0063] Furthermore, the optimizing the initial digital waveguide structure includes optimizing the material properties, etching depth and pixel block shape of the pixel blocks of the initial digital waveguide structure.

[0064] An embodiment of the present invention discloses a computer-readable storage medium, which includes a computer program. When the computer program runs on an electronic device, the electronic device executes the design method of a digital waveguide device based on algorithm fusion as described in any one of the above.

[0065] An embodiment of the present invention discloses a device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method for designing a digital waveguide device based on algorithm fusion as described in any one of the above items is implemented.

[0066] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A design method for digital waveguide devices based on algorithm fusion, characterized in that: It includes the following steps: Step S1, determining device functions, optimizing targets, and setting initial structures according to design requirements; Step S2, dividing the design area into discrete pixel points, optimizing the dielectric constant of the pixel points using a topology optimization algorithm, and performing binarization or multi-valued processing on the dielectric constant to obtain a topological structure; Step S3, re-dividing the design area into discrete pixel blocks that meet the manufacturing requirements according to the minimum feature size of the process; Step S4, performing binary or multi-value replacement on pixel blocks in the design area one by one to obtain an initial digital waveguide structure; Step S5, according to the device function, the initial digital waveguide structure is optimized by using a binary search algorithm, a brute force search method or a heuristic algorithm until the optimization target or the termination condition is reached.

2. The design method of digital waveguide device based on algorithm fusion according to claim 1, characterized in that: The digital waveguide device based on algorithm fusion is made of silicon on insulator, III-V materials or polymers.

3. The design method of digital waveguide device based on algorithm fusion according to claim 1, characterized in that: In step S1, the initial structure includes the input and output waveguide positions, the material properties of the device, and the shape and size of the design area.

4. The design method of digital waveguide device based on algorithm fusion according to claim 1, characterized in that: In step S5, the optimizing the initial digital waveguide structure includes optimizing the material properties, etching depth and pixel block shape of the pixel blocks of the initial digital waveguide structure.

5. A digital waveguide device design system based on algorithm fusion, characterized in that: It includes: A design target input unit, used to determine the device function optimization target and set the initial structure according to the design requirements; The dielectric constant optimization unit is used to divide the design area into discrete pixel points, optimize the dielectric constant of the pixel points using a topology optimization algorithm, and perform binary or multi-valued processing on the dielectric constant to obtain a topological structure; the reset unit is used to re-divide the design area into discrete pixel blocks that meet the preparation requirements according to the minimum feature size of the process; A replacement unit, used for performing binary or multi-value replacement on pixel blocks in the design area one by one to obtain an initial digital waveguide structure; The waveguide structure optimization unit is used to optimize the initial digital waveguide structure according to the device function by using a binary search algorithm, a brute force search method or a heuristic algorithm until the optimization target or the termination condition is reached.

6. The design system of digital waveguide devices based on algorithm fusion according to claim 5, characterized in that: The initial structure includes basic parameter settings such as input and output waveguide positions, device material properties, and design area shape and size.

7. The digital waveguide device design system based on algorithm fusion according to claim 5, characterized in that: The optimizing the initial digital waveguide structure includes optimizing the material properties, etching depth and pixel block shape of the pixel blocks of the initial digital waveguide structure.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a computer program, and when the computer program is executed on an electronic device, the electronic device executes the method for designing a digital waveguide device based on algorithm fusion as described in any one of claims 1 to 4.

9. A device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for designing a digital waveguide device based on algorithm fusion as claimed in any one of claims 1 to 4 is implemented.

Images