Trigger merging method, device, equipment, medium and program product applied to chip design

Abstract

The present disclosure provides a trigger merging method, device, equipment, medium and program product applied to chip design. Among them, the trigger merging method applied to chip design includes: performing preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design; receiving merging constraint information in response to the preliminary gate-level netlist generated by the preliminary synthesis; and re-synthesizing the preliminary gate-level netlist according to the merging constraint information to achieve the trigger merging. Therefore, through the preliminary synthesis of the selection optimization results of all unit triggers, combined with the re-synthesis based on the merging constraint information, a higher trigger merging rate can be achieved, thereby reducing the number of triggers in the multi-trigger module to a minimum, thereby reducing the chip power consumption.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a trigger merging method, device, equipment, medium and program product applied to chip design. Background Art

[0002] With the development of integrated circuit technology, the integration of chips has increased rapidly, and the scale has continued to expand, which has brought about the problem of excessive power consumption. Chip design is mainly divided into front-end implementation and back-end implementation. Front-end implementation is the process from algorithm to RTL (Register Transfer Level), and back-end implementation is the process from RTL to generating GDS layout files (i.e., database files in GDSII stream format). Excessive chip power consumption will cause problems such as continuous heating, reduced reliability, and shorter battery life. At present, ultra-large-scale SoC (i.e. System on Chip) chips are usually composed of multiple IPs or sub-modules. The design characteristics of different sub-modules vary greatly, and the existing back-end design technology generally adopts a general back-end design process, which makes it difficult to optimize chip power consumption. Summary of the invention

[0003] 1. Technical issues to be resolved

[0004] In order to solve at least one of the technical problems existing in the chip design scheme in the prior art, such as the inability to propose a corresponding design method based on the design characteristics of the chip module to minimize the power consumption after the chip is implemented, the present invention provides a trigger merging method, device, equipment, medium and program product applied to chip design, so as to provide an improved trigger merging scheme that can be implemented in the chip back end.

[0005] (II) Technical solution

[0006] A first aspect of the present disclosure provides a trigger merging method applied to chip design, which includes: performing preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design; receiving merging constraint information in response to a preliminary gate-level netlist generated by the preliminary synthesis; and re-synthesizing the preliminary gate-level netlist according to the merging constraint information to achieve the trigger merging.

[0007] According to an embodiment of the present disclosure, before performing preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design, it also includes: enabling all the unit triggers in response to a received register transfer level instruction; and traversing each unit trigger among all the unit triggers to generate the selection optimization results.

[0008] According to an embodiment of the present disclosure, in the traversal of each unit trigger among all the unit triggers to generate the selection optimization result, it includes: when a unit trigger among all the unit triggers corresponds to the logical function of at least one multi-bit trigger among all the preset multi-bit triggers, determining the one unit trigger as the unit trigger in the selection optimization result.

[0009] According to an embodiment of the present disclosure, the traversal of each unit trigger among all the unit triggers to generate the selection optimization result also includes: when a unit trigger among all the unit triggers does not correspond to the logical function of each multi-bit trigger among all the preset multi-bit triggers, disabling the one unit trigger.

[0010] According to an embodiment of the present disclosure, performing preliminary synthesis on the selection optimization results of all unit flip-flops applied to the chip design includes: performing a merging operation on all unit flip-flops in the selection optimization results to generate a preliminary gate-level netlist.

[0011] According to an embodiment of the present disclosure, in the receiving of merge constraint information in response to the preliminary gate-level netlist generated by the preliminary synthesis, it includes: in response to the preliminary gate-level netlist, receiving merge strength constraints, bit width waste constraints and multi-bit trigger selection constraints as the merge constraint information.

[0012] According to an embodiment of the present disclosure, before receiving merging constraint information in response to the preliminary gate-level netlist generated by the preliminary synthesis, the method further includes: generating the multi-bit trigger selection constraint according to the bit width selection information and type selection information of the multi-bit trigger.

[0013] According to an embodiment of the present disclosure, in the re-synthesizing the preliminary gate-level netlist according to the merge constraint information to realize the trigger merging, it includes: performing a merging operation on all unit triggers in the preliminary gate-level netlist according to the merge strength constraint, the bit width waste constraint and the multi-bit trigger selection constraint, generating a merged gate-level netlist corresponding to the preliminary gate-level netlist, and completing the trigger merging.

[0014] The second aspect of the present disclosure provides a trigger merging method applied to chip design, which includes a preliminary synthesis module, a constraint receiving module and a re-synthesis module. The preliminary synthesis module is used to perform preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design; the constraint receiving module is used to receive merging constraint information in response to the preliminary gate-level netlist generated by the preliminary synthesis; and the re-synthesis module is used to re-synthesize the preliminary gate-level netlist according to the merging constraint information to achieve the trigger merging.

[0015] The third aspect of the present disclosure provides an electronic device, comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors execute the control method of the above-mentioned electronic device.

[0016] A fourth aspect of the present disclosure further provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to execute the control method of the electronic device described above.

[0017] The fifth aspect of the present disclosure also provides a computer program product, including a computer program, which implements the control method of the above electronic device when executed by a processor.

[0018] (III) Beneficial effects

[0019] The present disclosure provides a trigger merging method, apparatus, equipment, medium and program product for chip design. The trigger merging method for chip design includes: performing preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design; receiving merging constraint information in response to the preliminary gate-level netlist generated by the preliminary synthesis; and re-synthesizing the preliminary gate-level netlist according to the merging constraint information to achieve the trigger merging. Therefore, by preliminary synthesis of the selection optimization results of all unit triggers, combined with re-synthesis based on the merging constraint information, a higher trigger merging rate can be achieved, thereby reducing the number of triggers in the multi-trigger module to a minimum, thereby reducing chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A technical principle diagram of a merging solution of a trigger merging technology in the prior art is shown;

[0021] Figure 2 The clock tree network structure of multiple trigger modules implemented by the trigger merging technology in the prior art is shown;

[0022] Figure 3 An application scenario diagram of a trigger merging method applied to chip design according to an embodiment of the present disclosure is schematically shown;

[0023] Figure 4A A flowchart of a trigger merging method applied to chip design according to an embodiment of the present disclosure is schematically shown;

[0024] Figure 4B A flowchart schematically shows another application scenario of the trigger merging method applied to chip design according to an embodiment of the present disclosure;

[0025] Figure 4C A flowchart schematically illustrates another application scenario of the trigger merging method applied to chip design according to an embodiment of the present disclosure;

[0026] Figure 4D A schematic diagram of a multi-trigger module clock tree network structure of a trigger merging method applied to chip design according to an embodiment of the present disclosure is shown;

[0027] Figure 5 A structural block diagram schematically shows a trigger merging device for controlling an electronic device applied to chip design according to an embodiment of the present disclosure; and

[0028] Figure 6 A block diagram of an electronic device suitable for implementing a trigger merging method for controlling an electronic device and applying it to chip design according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0030] It should be noted that the implementation methods not shown or described in the drawings or the text of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of various elements and methods are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0031] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure.

[0032] Moreover, the shapes and sizes of the components in the figures do not reflect the real size and proportion, but only illustrate the contents of the embodiments of the present disclosure. In addition, in the claims, any reference symbols between brackets shall not be constructed as limiting the claims.

[0033] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0034] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element or the order of manufacturing methods. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0035] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and set in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into multiple submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose. Furthermore, in a unit claim that lists several devices, several of these devices may be embodied by the same hardware item.

[0036] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: the claimed disclosure requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, the disclosed aspects lie in less than all the features of the single embodiment disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present disclosure.

[0037] Chip design is also called integrated circuit design (IC design for short), or very large-scale integrated circuit design (VLSI design), which refers to the design process targeting integrated circuits and very large-scale integrated circuits. Integrated circuit design involves the establishment of models for electronic devices (such as transistors, resistors, capacitors, etc.) and interconnection lines between devices. All devices and interconnections need to be placed on a piece of semiconductor substrate material. These components are placed on a single silicon substrate through semiconductor device manufacturing processes (such as photolithography, etc.) to form a circuit. Among them, chip design is divided into front-end design and back-end design. There is no unified and strict boundary between front-end design (also called logic design) and back-end design (also called physical design). The design related to the process is the back-end design.

[0038] Triggers are one of the most commonly used units in the back-end design of chip design. When performing RTL design, sometimes in order to improve performance, multi-stage pipelines may be divided or parallel methods may be used. After physical synthesis of the RTL code designed in this way, more triggers will appear in the netlist, which is called a multi-trigger module. A large number of triggers in this module will make its clock network complex, resulting in higher power consumption overhead on the clock network. At the same time, the trigger itself will also have a higher power consumption overhead, so the total power consumption of the multi-trigger module is proportional to the number of its triggers. Specifically, the clock network of the chip is composed of triggers and buffers on the clock tree. A large number of triggers in the module will make its clock network complex, resulting in higher power consumption overhead on the clock network. At the same time, the trigger itself will also have a higher power consumption overhead, so the total power consumption of the multi-trigger module is proportional to the number of its triggers. The power consumption on the entire clock network is composed of two parts: one is the power consumption of the trigger itself; the other is the power consumption of the buffer on the clock tree. Among them, the power consumption of the clock network P clock_network It can be expressed as the following expression:

[0039] P clock_network =P flop +P tree (1)

[0040] Where P flop is the power consumption of the trigger itself, P tree Represents the power consumption of all buffer units on the clock tree. The power consumption of the trigger itself and the clock buffer unit are proportional to the number of triggers in the module. The more triggers there are, the greater the power consumption of the entire clock network. Therefore, it is necessary to consider merging the triggers in the module.

[0041] The existing trigger merging technology usually refers to merging the unit triggers in the module into two or more triggers to reduce the number of triggers. Figure 1 The technical principle of the existing trigger merging solution shown in the figure is mainly to merge the single-bit triggers in the module into multi-bit triggers during the back-end implementation, thereby reducing the number of buffers and clock leaf nodes on the clock tree. Figure 1 Each rectangular unit shown represents a trigger (i.e., a unit trigger), and each triangular unit represents a buffer on the clock tree. Before the merger, there are 8 unit triggers (i.e., unit triggers T1-T8) and 4 clock buffers (i.e., buffers B1-B4) on the clock tree network 100, while after the merger, there are only 3 triggers (i.e., 2 2-bit triggers T12 and T34, 1 4-bit trigger T5678) and 1 clock buffer (i.e., B1-4) on the clock tree network 100′.

[0042] However, the existing technologies often cannot achieve a high trigger merging rate, so the effect of trigger merging cannot meet expectations, or even differs greatly from expectations. At present, the back-end design of existing multi-trigger modules often uses a common process, which makes the current trigger merging technology have the following main disadvantages:

[0043] 1. Unable to achieve a high trigger merging rate: Due to the influence of trigger merging constraints (the tool will default to a low merging strength and does not allow waste of bit width) and the unit and multi-bit trigger types in the process library (the tool cannot identify unit triggers that cannot be merged), the existing technology often cannot achieve a high merging rate when merging triggers, which is generally around 70%-80%.

[0044] 2. The power consumption after module implementation is high: If the existing technology is used for physical design, without trigger merging or with a low merging rate, the dynamic power consumption and total power consumption of the multi-trigger module will increase significantly, which will have a negative impact on chip design. For details, please refer to the previous formula (1) and related descriptions. The power consumption on the clock network of the multi-trigger module is proportional to the number of triggers.

[0045] 3. The clock tree structure is complex and the network is huge: For multi-flip-flop modules where the flip-flops account for about 30% of the total number of standard cells, using traditional technology for back-end design will lead to a significant increase in the number of clock tree nodes, a doubling of the number of buffers on the clock network, and increased clock deviation. Figure 2 The clock tree network structure of the multi-trigger module implemented by the prior art shown in the figure shows that the clock trees thereof are of different lengths and uneven, and there is a large clock deviation.

[0046] Therefore, in order to solve at least one of the technical problems existing in the chip design scheme in the prior art, such as the inability to propose a corresponding design method based on the design characteristics of the chip module to minimize the power consumption after the chip is implemented, the present disclosure provides a trigger merging method, device, equipment, medium and program product applied to chip design, so as to try to merge the unit triggers in the multi-trigger module into multi-bit triggers, while reducing the module power consumption and optimizing the effect through a better clock tree network.

[0047] Figure 3 An application scenario diagram of a trigger merging method applied to chip design according to an embodiment of the present disclosure is schematically shown.

[0048] like Figure 3 As shown, the application scenario 300 according to this embodiment may include terminal devices 301, 302, 303, a network 304 and a server 305. The network 304 is used to provide a medium for a communication link between the terminal devices 301, 302, 303 and the server 305. The network 304 may include various connection types, such as wired, wireless communication links or optical fiber cables, etc.

[0049] Users can use terminal devices 301, 302, 303 to interact with server 305 through network 304 to receive or send messages, etc. Various communication client applications can be installed on terminal devices 301, 302, 303, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social platform software, etc. (only examples).

[0050] The terminal devices 301 , 302 , and 303 may be various electronic devices having a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop computers, and desktop computers, etc.

[0051] The server 305 may be a server that provides various services, such as a background management server (only an example) that provides support for websites browsed by users using the terminal devices 301, 302, and 303. The background management server may analyze and process the received data such as user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal device.

[0052] It should be noted that the trigger merging method for chip design provided in the embodiment of the present disclosure can generally be executed by the server 305. Accordingly, the trigger merging device for chip design provided in the embodiment of the present disclosure can generally be set in the server 305. The trigger merging method for chip design provided in the embodiment of the present disclosure can also be executed by a server or server cluster that is different from the server 305 and can communicate with the terminal devices 301, 302, 303 and / or the server 305. Accordingly, the trigger merging device for chip design provided in the embodiment of the present disclosure can also be set in a server or server cluster that is different from the server 305 and can communicate with the terminal devices 301, 302, 303 and / or the server 305.

[0053] It should be understood that Figure 3 The number of terminal devices, networks and servers in the embodiment is only for illustration. Any number of terminal devices, networks and servers may be provided according to implementation requirements.

[0054] The following will be based on Figure 3 The scene described by Figure 4A to Figure 6 The trigger merging method applied to chip design in the disclosed embodiment is described in detail.

[0055] Figure 4A The flowchart of the trigger merging method applied to chip design according to an embodiment of the present disclosure is schematically shown.

[0056] like Figure 4A As shown, the trigger merging method applied to chip design in this embodiment includes operations S401 to S403.

[0057] like Figure 4A As shown, the first aspect of the present disclosure provides a trigger merging method applied to chip design, which includes:

[0058] In operation S401, a preliminary synthesis is performed on the selection optimization results of all unit flip-flops applied to the chip design;

[0059] In operation S402, in response to the preliminary gate-level netlist generated by the preliminary synthesis, receiving merging constraint information; and

[0060] In operation S403, the preliminary gate-level netlist is synthesized again according to the merging constraint information to implement the trigger merging.

[0061] The selection optimization result is the selection optimization result for all unit triggers applied to chip design, which can generally include some unit triggers among all unit triggers determined after selection optimization, wherein the selection optimization process is mainly used to screen out other unit triggers that are not suitable for preliminary synthesis among all unit triggers, and generate some unit triggers suitable for preliminary synthesis as the above-mentioned selection optimization result. Among them, the preliminary synthesis process can be understood as the merging operation process for some unit triggers determined by the above-mentioned selection optimization result. Therefore, the preliminary screening of all unit triggers is achieved, thereby further improving the overall merging rate of triggers.

[0062] The process of preliminary synthesis execution merging can be an operation process of mapping the unit triggers corresponding to the above-mentioned selection optimization results through a synthesis tool (such as an EDA tool) to form a preliminary gate-level netlist containing only unit triggers. Therefore, the preliminary gate-level netlist is a netlist corresponding to all the unit triggers in the selection optimization results formed by the above-mentioned unit trigger mapping process. Among them, the unit triggers in the preliminary gate-level netlist are the same as the unit triggers in the selection optimization results.

[0063] The merge constraint information is the constraint content for re-synthesizing all the unit triggers in the preliminary gate-level netlist, and the constraint content is mainly used to improve the merging rate of re-merging. The preliminary gate-level netlist can be re-synthesized through the merge constraint information. Re-synthesis can be understood as the operation of re-merging the various unit triggers in the preliminary gate-level netlist through the corresponding synthesis tool, and the synthesis operation can be performed through a synthesis tool such as Genus.

[0064] According to the constraint content of the above-mentioned merge constraint information, the synthesis tool is used to perform a re-synthesized merging process on the unit triggers of the preliminary gate-level netlist, so as to further merge the unit triggers of the preliminary gate-level netlist to form a netlist structure with multi-bit triggers, thereby achieving a further improvement in the merging rate of all unit triggers based on the selection optimization processing of the above-mentioned unit triggers.

[0065] Therefore, through the preliminary synthesis of the selection optimization results of all unit triggers, combined with the re-synthesis based on the merging constraint information, a higher trigger merging rate can be achieved, thereby reducing the number of triggers in the multi-trigger module to a minimum, thereby reducing chip power consumption.

[0066] Obviously, the present disclosure provides an improved hybrid multi-bit trigger merging scheme. As described below, this merging scheme method can be implemented in the RTL synthesis stage by adjusting the trigger merging constraints (including optimizing the multi-bit trigger selection) and optimizing the unit trigger selection. Among them, in the RTL synthesis stage, the main factors affecting the trigger merging may include the trigger merging constraints such as optimizing the multi-bit trigger selection and the unit trigger selection. In order to enable those skilled in the art to better understand the above-mentioned merging scheme, a clearer and more complete description will be given below.

[0067] Figure 4B A flowchart schematically illustrates another application scenario of the trigger merging method applied to chip design according to an embodiment of the present disclosure; Figure 4C A flowchart schematically illustrates another application scenario of the trigger merging method applied to chip design according to an embodiment of the present disclosure; Figure 4D A clock tree network structure diagram of multiple trigger modules according to a trigger merging method applied to chip design according to an embodiment of the present disclosure is schematically shown.

[0068] like Figures 4A-4D As shown, according to an embodiment of the present disclosure, before performing preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design in operation S401, it also includes:

[0069] In response to receiving a register transfer level instruction, enabling all of the single-bit flip-flops; and

[0070] Each unit trigger in all the unit triggers is traversed to generate the selection optimization result.

[0071] After the chip architecture design is basically complete, further RTL code translation operations are required. Specifically, algorithms such as MATLAB can be translated into RTL code through text editors. For the modules to be synthesized for all unit triggers applied to chip design, register transfer level instructions are computer-readable control instructions corresponding to RTL codes, which are used as control instructions for electronic design automation tools (such as EDA tools) to perform synthesis operations. Among them, the module to be synthesized can be a 5G channel processing unit that uses multi-stage pipelines and parallel structures to improve processing performance. RTL code is a description of the circuit written in hardware description language in chip design, and its purpose is to provide electronic design automation tools such as EDA tools for synthesis to generate design netlists. Among them, RTL code can be used as the above-mentioned register transfer level instructions.

[0072] In operations S411-S412 and operations S421-S423, in response to the received register transfer level instructions of the RTL design code for the circuit description of the module to be synthesized, the process of selecting and optimizing all unit triggers can be started. First, all unit triggers corresponding to the chip design in the process library are started, so that all unit triggers are in an enabled state and can realize the corresponding logical functions.

[0073] Then, all enabled unit triggers are traversed one by one, and each unit trigger is selected in turn to determine whether it can be used for subsequent preliminary synthesis operations, so as to generate a selection optimization result with all unit triggers that can be used for preliminary synthesis operations, thereby realizing the unit trigger selection optimization process.

[0074] In this way, other unit triggers that are not suitable for preliminary synthesis can be screened out, achieving preliminary screening of all unit triggers, thereby corresponding to subsequent synthesis processing and further improving the overall merging rate of triggers.

[0075] like Figures 4A-4D As shown, according to an embodiment of the present disclosure, in traversing each unit trigger of all the unit triggers to generate the selection optimization result, it includes:

[0076] When one unit trigger among all the unit triggers corresponds to the logic function of at least one multi-bit trigger among all the preset multi-bit triggers, the one unit trigger is determined as the unit trigger in the selection optimization result.

[0077] like Figures 4A-4D As shown, according to an embodiment of the present disclosure, in traversing each unit trigger of all the unit triggers to generate the selection optimization result, it also includes:

[0078] When one unit flip-flop among all the unit flip-flops does not correspond to the logic function of each multi-bit flip-flop among all the preset multi-bit flip-flops, the one unit flip-flop is disabled.

[0079] In operations S431-S433, for the selection optimization process of all unit triggers, it is necessary to traverse each unit trigger to determine whether there is a multi-bit trigger corresponding to its logical function. If so, it is considered that the unit trigger can be merged, and if not, this unit trigger is disabled. The specific unit trigger selection optimization process is described as follows:

[0080] In the disclosed embodiment, one of the conditions for a successful merging of triggers is that the logical functions before and after the merging do not change. Among them, the synthesis tool (such as the Genus tool) provided in the embodiment of the present disclosure first maps the circuit described by the RTL code (or hardware description language) into a netlist containing only unit triggers (i.e., the above-mentioned preliminary gate-level netlist N1) during the merging process, and then merges the unit triggers in the netlist into multi-bit triggers. Since the synthesis tool enables all unit triggers under the default configuration, not all unit triggers can be merged. The method for determining whether a unit trigger can be merged is to check whether there is a multi-bit trigger corresponding to its logical function in the process library. If there is, it is considered that the unit trigger can be merged, and if not, it is considered that the unit trigger cannot be merged. For example, in the 12nm process library, there is a special unit trigger with a logic function of selecting one of two inputs, and the multi-bit trigger therein does not have a corresponding logic function type. If this special unit trigger is used in the unit trigger selected for chip design, it is easy to cause merging failure, resulting in a reduced merging rate. The unit trigger without the corresponding logic function is screened out and disabled, and the unit trigger with the corresponding logic function is generated. The selection optimization result, that is, the process of optimizing the selection of the unit trigger, can significantly improve the merging rate.

[0081] The specific unit trigger selection optimization involves traversing all the selected unit triggers one by one, and judging one by one whether there is a multi-bit trigger corresponding to the logical function of the selected unit trigger in the current process library. As long as there is a multi-bit trigger corresponding to the logical function, it means that the unit trigger can be merged. On the contrary, if there is no multi-bit trigger corresponding to the logical function of the unit trigger in the current process library, it means that the unit trigger cannot be merged and should be set to disabled. After completing the traversal process of all unit triggers, a selection optimization result with all mergeable unit triggers can be generated, and all non-mergeable unit triggers are disabled.

[0082] Through the above-mentioned unit trigger selection optimization process, preliminary screening of all unit triggers before merging is achieved, so that the unit triggers obtained through screening are eligible for merging, and unit triggers whose logical functions do not correspond to multi-bit triggers are disabled, thereby achieving preliminary screening of all unit triggers, thereby further improving the overall merging rate of the triggers in response to subsequent comprehensive processing.

[0083] like Figures 4A-4D As shown, according to an embodiment of the present disclosure, in operation S401, performing preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design includes:

[0084] A merging operation is performed on all unit flip-flops in the selection optimization result to generate a preliminary gate-level netlist.

[0085] In operation S413 and operations S431-S424, all the unit triggers that can be merged in the selection optimization results are preliminarily synthesized, and an optimized gate-level netlist N1 can be generated as a preliminary gate-level netlist, and the preliminary gate-level netlist N1 is a netlist with only unit triggers. Among them, since all the unit triggers that cannot be merged are disabled in the above-mentioned selection optimization process, all the unit triggers in the preliminary gate-level netlist N1 obtained by the preliminary synthesis can find multi-bit triggers of corresponding logical functions in the process library. Among them, the preliminary gate-level netlist N1 is synthesized after the previous unit trigger selection optimization, and all the unit triggers are the logical function types that can be merged obtained after screening.

[0086] With the help of the above-mentioned preliminary synthesis processing, the unit triggers in the preliminary gate-level netlist N1 are all mergeable unit triggers. Moreover, the preliminary gate-level netlist N1 can not only accelerate the processing speed of subsequent synthesis operations, but also ensure that more unit triggers can be merged, thereby significantly improving the overall merging rate.

[0087] like Figures 4A-4D As shown, according to an embodiment of the present disclosure, in operation S402, in response to the preliminary gate-level netlist generated by the preliminary synthesis, receiving the merge constraint information includes:

[0088] In response to the preliminary gate-level netlist, a merging strength constraint, a bit width waste constraint, and a multi-bit flip-flop selection constraint are received as the merging constraint information.

[0089] In operation S414 and operation S425, the merge constraint information in the embodiment of the present disclosure is the optimized trigger merge constraint content. In the embodiment of the present disclosure, the constraint setting content that affects the merge rate includes the bit width waste constraint, which can be understood as whether to turn on the setting of allowing waste of bits, and the merge strength constraint can be understood as high, medium or low trigger merge strength, and different merge strengths correspond to different merge degrees. The setting of the merge constraint information after optimization can achieve a higher merge rate. The above-mentioned constraints on allowing waste of bits and the constraints on the trigger merge strength can affect the overall merge rate of the embodiment of the present disclosure.

[0090] Among them, the trigger merging strength (which can correspond to high, medium or low merging strength) is a key consideration affecting the merging rate. Setting the trigger merging strength constraint to high merging strength means that the trigger merging rate is placed at a higher weight, and setting it to low merging strength means that other results such as timing are placed at a higher weight. In the embodiment of the present disclosure, considering that the preliminary gate-level netlist N1 involves unit triggers that match the logical functions, in order to further improve the overall merging rate, the trigger merging strength can be set to a high merging strength constraint to optimize the setting of the merging strength constraint. In addition, in the comprehensive operation of trigger merging, it is defaulted that the waste of bit width is not allowed, but if the number of bits of mergable triggers is an odd number (such as 3), a 2-bit trigger and a unit trigger will be selected by default, and the merging rate at this time is 66.6%; however, if the waste of bit width is allowed, the above situation will be merged into a 4-bit trigger and waste one bit, and the merging rate at this time is 100%. Among them, allowing the waste of trigger bit width can be understood as merging 3 unit triggers into 1 4-bit trigger, and 1 bit of the 4-bit trigger is not used, that is, 1 bit is wasted. In other words, wasting 1 bit means that 1 bit is not used, for example, a 4-bit flip-flop only uses 3 bits. In the disclosed embodiment, considering that the preliminary gate-level netlist N1 involves unit flip-flops with matching logic functions, in order to further improve the overall merging rate, the bit width of the wasted flip-flop can be set as a constraint that allows bit width waste, thereby optimizing the setting of the bit width waste constraint.

[0091] In summary, by optimizing the merge strength constraint setting in the embodiment of the present disclosure to a high merge strength and optimizing the bit width waste constraint setting to allow waste of trigger bit width, a higher merge rate of subsequent merges can be achieved.

[0092] like Figures 4A-4D As shown, according to an embodiment of the present disclosure, before receiving the merge constraint information in response to the preliminary gate-level netlist generated by the preliminary synthesis in operation S402, the process further includes:

[0093] The multi-bit trigger selection constraint is generated according to the bit width selection information and the type selection information of the multi-bit trigger.

[0094] In operation S414 and operation S425, at least 4 types of multi-bit triggers can be provided in the process library of the embodiment of the present disclosure, such as 2-bit, 4-bit, 6-bit, 8-bit and other types of multi-bit triggers. According to the fact that the clock network power consumption of the aforementioned multi-trigger module is proportional to the number of its triggers, the multi-bit trigger selection constraints mainly involve the type constraints of the multi-bit triggers selected by merging, mainly for the optimization of the following two aspects: bit width selection information and type selection information. Among them, the selection can be understood as the choice of what type of multi-bit trigger to use, which can be a type of multi-bit trigger among 2-bit, 4-bit, 6-bit, and 8-bit, or a mixture of different types of multi-bit triggers of 2, 4, 6, and 8 bits. The merging rate and power consumption optimization degree obtained by different configurations are also different.

[0095] The bit width selection information can be understood as information about the bit width selection of multi-bit triggers. Among them, the larger the bit width selected by the information, the fewer the number of triggers after merging. For example, if there are 8 unit triggers that need to be merged, if they are merged into 2-bit triggers, the number of merged triggers is 4, and if they are merged into 8-bit triggers, the number of merged triggers is 1. Therefore, in the embodiment of the present disclosure, the bit width selection information of the trigger can be optimized to be set to a large bit width selection. In addition, the type selection information involves the information of the type selection of the multi-bit trigger, that is, whether to use a single type of multi-bit trigger or to mix and use a variety of multi-bit triggers with different bit widths. If a single type of multi-bit trigger is used (such as only 8 bits), when the unit triggers that need to be merged in the module are less than 8 (such as 7 unit triggers) and the trigger bit width is not allowed to be wasted, the direct merger will fail, resulting in a reduced merger rate. In the embodiment of the present disclosure, 2, 4, 6, 8-bit and other types of multi-bit triggers can be mixed, such as 7 unit triggers can be merged into 1 6-bit trigger. Therefore, the type selection information in the embodiment of the present disclosure can be optimized to be set as a mixed multi-type multi-bit trigger selection, such as a mixed use of different types of multi-bit triggers such as 2, 4, 6, 8 bits, etc.

[0096] In order to further optimize the multi-bit trigger selection constraints in the merge constraint information, multiple types of multi-bit triggers can be mixed and the multi-bit trigger selection can be optimized according to the large bit width selection, thereby further improving the merging rate of subsequent comprehensive processing.

[0097] like Figures 4A-4D As shown, according to an embodiment of the present disclosure, in operation S403, the preliminary gate-level netlist is synthesized again according to the merge constraint information to implement the trigger merging, including:

[0098] A merge operation is performed on all unit flip-flops in the preliminary gate-level netlist according to the merge strength constraint, the bit width waste constraint and the multi-bit flip-flop selection constraint, a merged gate-level netlist corresponding to the preliminary gate-level netlist is generated, and the flip-flop merge is completed.

[0099] By means of the above-mentioned preliminary synthesis based on the RTL code, a preliminary gate-level netlist N1 without multi-bit triggers is obtained, and then the preliminary gate-level netlist N1 is synthesized for the second time to obtain the final gate-level netlist N2 as a merged gate-level netlist, wherein the actual trigger merging process can occur during the second synthesis process. Specifically, in operations S415-S416 and operations S426-S428, according to the merging strength constraints of high merging strength involved in the aforementioned merging constraint information, the bit width waste constraints that allow bit width waste, and the multi-bit trigger selection constraints of the mixed multi-type multi-bit triggers of the maximum bit width selection, the synthesis process is performed for all the unit triggers in the preliminary gate-level netlist N1, and a secondary synthesis can be achieved, thereby generating a gate-level netlist N2 with multi-bit triggers, thereby completing the entire trigger merging process. Finally, timing optimization can also be performed on the basis of this netlist N2.

[0100] Therefore, through the preliminary synthesis of the selection optimization results of all unit triggers and the re-synthesis based on the merging constraint information, a higher trigger merging rate can be achieved, thereby reducing the number of triggers in the multi-trigger module to a minimum, thereby reducing chip power consumption.

[0101] In order to enable those skilled in the art to have a clearer understanding of the effectiveness of the above-mentioned trigger merging method provided in the embodiments of the present disclosure, the above-mentioned trigger merging method for improving the hybrid multi-bit trigger merging process is applied to a commercial SoC chip as a specific embodiment 1 (Scheme 1) of the present disclosure, and a merging comparison effect between the traditional merging scheme 2 before improvement (i.e., Scheme 2) and the unmerged scheme 3 (Scheme 3) is obtained as shown in Table 1 below.

[0102] Table 1

[0103]

[0104]

[0105] Among them, as shown in Table 1, the results obtained after RTL synthesis using Example 1 of the trigger merging scheme of the above-mentioned embodiment of the present invention show that when only 1-bit trigger is used, there are 633,361 triggers in the module, while the merging rate of trigger merging using the traditional merging scheme 2 before improvement is 78.06%. The merging rate achieved by trigger merging using Example 1 of the above-mentioned trigger merging scheme proposed in the embodiment of the present invention is the highest, which is 94.65%.

[0106] In addition, for the above-mentioned embodiment 1 of the present invention, since the above-mentioned improved trigger merging scheme is adopted, its corresponding clock tree synthesis results also show excellent beneficial effects, as shown in the following Table 2, which is the data analysis results of the clock tree synthesis between Scheme 1 of the above-mentioned embodiment 1 of the present invention, the traditional merging scheme 2 before improvement, and the unmerged scheme 3.

[0107] Table 2

[0108] Solution 3 Solution 2 Solution 1 Number of clock leaf nodes 633061 215062 114948 Number of clock buffers 21568 7888 5058 Clock tree levels 19 19 18 Insertion delay (ps) 394～538 395～493 433～495 Maximum clock deviation (ps) 144 98 62 Scan chain length before reorganization (um) 9857012 5910583 4307236 Scan chain length after reorganization (um) 3472637 3004081 2778619 Clock tree power consumption (mW) 512.3 258.6 203.4

[0109] Obviously, after using the trigger merging method of scheme 1 of the embodiment of the present disclosure, the clock tree quality of the multi-trigger module has been significantly improved, and the leaf nodes of the clock tree, the number of buffers, the number of clock tree levels, the maximum clock deviation, the scan chain routing length, and the clock tree power consumption have all been significantly reduced. Among them, the merging process after using the above scheme 1 to optimize the trigger merging has the highest degree of optimization, and the clock tree power consumption is reduced by 60.3% compared to when no trigger merging is performed. In addition, the following Figure 4D As shown, the clock tree structure of the scheme 1 corresponding to the embodiment 1 of the present disclosure is also significantly improved. Figure 2 The clock skew of the traditional merging scheme 2 is shown to be significantly reduced, and the clock tree length is very uniform.

[0110] Therefore, the above trigger merging scheme of the embodiment of the present disclosure provides an improved hybrid multi-bit trigger merging processing method, which can significantly improve the trigger merging rate of the multi-trigger module and greatly reduce the number of triggers. Moreover, the technical solution can be effectively applied to Soc chips to achieve great optimization of the clock tree structure and power consumption of the multi-trigger module.

[0111] Obviously, the trigger merging method described above in the embodiment of the present disclosure can effectively solve the technical problem in the prior art that the trigger merging rate cannot be effectively improved, and a higher trigger merging rate is achieved by improving the trigger merging process, and the number of triggers in the multi-trigger module is minimized, thereby reducing the power consumption of the chip. Moreover, in view of the situation in the prior art where a higher trigger merging rate cannot be achieved due to the influence of trigger merging constraints, etc., a merging rate of more than 90% is achieved through the improved trigger merging process of the present disclosure, which greatly reduces the number of triggers inside the module; in addition, in view of the problem of high power consumption after module implementation in the prior art, the improved trigger merging process described above can greatly reduce the power consumption of the module and significantly improve the PPA (Power, Performance and Area) index of the chip; for the situation where the clock tree structure is complex and the network is huge, based on the above-mentioned Figure 4DFrom the clock tree structure shown, it can be seen that based on the technical content of the present disclosure by improving the merging process, the clock tree network of the multi-trigger module can be effectively optimized.

[0112] It can be seen that the above-mentioned trigger merging method of the embodiment of the present disclosure can improve the merging rate by adjusting the trigger merging constraints, which can be specifically achieved based on the influence of the merging constraint information on the trigger merging rate. In addition, the merging rate can be further improved by optimizing the selection of unit triggers. Moreover, by analyzing the functional mapping relationship between unit triggers and multi-bit triggers in the process library, unit triggers that cannot be merged are eliminated, which significantly improves the overall merging rate. Finally, by optimizing the selection of multi-bit triggers, analyzing the merging process of triggers in electronic design automation tools, and using a mixture of different types of multi-bit triggers such as 2, 4, 6, and 8 bits for comprehensive processing of trigger merging, the highest merging rate currently available in this field (exceeding 90%) is achieved.

[0113] Based on the common understanding of those skilled in the art, the above-mentioned trigger merging scheme of the embodiment of the present invention achieves an extremely high trigger merging rate (far exceeding the existing merging rate of less than 80%) by improving the traditional trigger merging scheme with respect to merging constraints and trigger selection, thereby greatly improving the trigger merging rate. At the same time, it also reduces chip power consumption and optimizes the clock tree network structure, thereby actually achieving unexpected technical effects.

[0114] Based on the above-mentioned trigger merging method applied to chip design, the present disclosure also provides a trigger merging device applied to chip design. Figure 5 The device is described in detail.

[0115] Figure 5 The structure block diagram of a trigger merging device applied to chip design according to an embodiment of the present disclosure is schematically shown.

[0116] like Figure 5 As shown, the trigger merging device 500 applied to chip design in this embodiment includes a preliminary synthesis module 510 , a constraint receiving module 520 and a re-synthesis module 530 .

[0117] The preliminary synthesis module 510 is used to perform preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design. In one embodiment, the preliminary synthesis module 510 can be used to perform the operation S401 described above, which will not be repeated here. ;

[0118] The constraint receiving module 520 is used to receive merge constraint information in response to the preliminary gate-level netlist generated by the preliminary synthesis. In one embodiment, the constraint receiving module 520 can be used to perform the operation S402 described above, which will not be described in detail here.

[0119] The re-synthesis module 430 is used to re-synthesize the preliminary gate-level netlist according to the merging constraint information to implement the trigger merging. In one embodiment, the re-synthesis module 430 can be used to perform the operation S403 described above, which will not be described in detail here.

[0120] According to an embodiment of the present disclosure, any multiple modules of the preliminary synthesis module 510, the constraint receiving module 520 and the re-synthesis module 530 can be combined into one module for implementation, or any one of the modules can be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the preliminary synthesis module 510, the constraint receiving module 520 and the re-synthesis module 530 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or can be implemented by hardware or firmware such as any other reasonable way of integrating or packaging the circuit, or implemented in any one of the three implementation methods of software, hardware and firmware or in any appropriate combination of any of them. Alternatively, at least one of the preliminary synthesis module 510, the constraint receiving module 520 and the re-synthesis module 530 can be at least partially implemented as a computer program module, and when the computer program module is run, the corresponding function can be executed.

[0121] Figure 6 A block diagram of an electronic device suitable for implementing a trigger merging method applied to chip design according to an embodiment of the present disclosure is schematically shown.

[0122] like Figure 6 As shown, the electronic device 600 according to an embodiment of the present disclosure includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage part 608 into a random access memory (RAM) 603. The processor 601 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 601 may also include an onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0123] In RAM 603, various programs and data required for the operation of electronic device 600 are stored. Processor 601, ROM 602 and RAM 603 are connected to each other through bus 604. Processor 601 performs various operations of the method flow according to the embodiment of the present disclosure by executing the program in ROM 602 and / or RAM 603. It should be noted that the program can also be stored in one or more memories other than ROM 602 and RAM 603. Processor 601 can perform various operations of the method flow according to the embodiment of the present disclosure by executing the program stored in the one or more memories.

[0124] According to an embodiment of the present disclosure, the electronic device 600 may further include an input / output (I / O) interface 605, which is also connected to the bus 604. The electronic device 600 may further include one or more of the following components connected to the I / O interface 605: an input portion 606 including a keyboard, a mouse, etc.; an output portion 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage portion 608 including a hard disk, etc.; and a communication portion 609 including a network interface card such as a LAN card, a modem, etc. The communication portion 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed, so that a computer program read therefrom is installed into the storage portion 608 as needed.

[0125] The present disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or may exist independently without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present disclosure is implemented.

[0126] According to an embodiment of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, for example, may include but is not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, an apparatus or a device. For example, according to an embodiment of the present disclosure, a computer-readable storage medium may include the ROM 602 and / or RAM 603 described above and / or one or more memories other than ROM 602 and RAM 603.

[0127] The embodiment of the present disclosure also includes a computer program product, which includes a computer program, and the computer program contains program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to enable the computer system to implement the method provided by the embodiment of the present disclosure.

[0128] The above functions defined in the system / device of the embodiment of the present disclosure are performed when the computer program is executed by the processor 601. According to the embodiment of the present disclosure, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0129] In one embodiment, the computer program may rely on tangible storage media such as optical storage devices, magnetic storage devices, etc. In another embodiment, the computer program may also be transmitted and distributed in the form of signals on a network medium, and downloaded and installed through the communication part 609, and / or installed from a removable medium 611. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0130] In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 609, and / or installed from the removable medium 611. When the computer program is executed by the processor 601, the above functions defined in the system of the embodiment of the present disclosure are performed. According to the embodiment of the present disclosure, the system, device, apparatus, module, unit, etc. described above can be implemented by a computer program module.

[0131] According to an embodiment of the present disclosure, the program code for executing the computer program provided by the embodiment of the present disclosure can be written in any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level process and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, Java, C++, python, "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on the remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect through the Internet).

[0132] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0133] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0134] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

[0135] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0136] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A trigger merging method applied to chip design, wherein: include: Performing preliminary synthesis on the selection optimization results of all unit flip-flops applied to the chip design; In response to the preliminary gate-level netlist generated by the preliminary synthesis, receiving merging constraint information; as well as Resynthesize the preliminary gate-level netlist according to the merging constraint information to realize the merging of the triggers; Before performing preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design, the method further includes: In response to the received register transfer level instruction, enabling all the unit triggers; and traversing each unit trigger of all the unit triggers to generate the selection optimization result; Wherein, in traversing each unit trigger of all the unit triggers to generate the selection optimization result, it includes: When one of the unit triggers among all the unit triggers corresponds to the logic function of at least one multi-bit trigger among all the preset multi-bit triggers, determining the one unit trigger as the unit trigger in the selection optimization result; When one of the unit flip-flops among all the unit flip-flops does not correspond to the logic function of each multi-bit flip-flop among all the preset multi-bit flip-flops, disabling the one unit flip-flop; Wherein, in response to the preliminary gate-level netlist generated by the preliminary synthesis, receiving the merge constraint information includes: In response to the preliminary gate-level netlist, a merging strength constraint, a bit width waste constraint, and a multi-bit flip-flop selection constraint are received as the merging constraint information.

2. The method according to claim 1, wherein: The performing of preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design includes: A merging operation is performed on all unit flip-flops in the selection optimization result to generate a preliminary gate-level netlist.

3. The method according to claim 1, wherein: Before receiving the merge constraint information in response to the preliminary gate-level netlist generated by the preliminary synthesis, the method further includes: The multi-bit trigger selection constraint is generated according to the bit width selection information and the type selection information of the multi-bit trigger.

4. The method according to claim 1, wherein: The step of re-synthesizing the preliminary gate-level netlist according to the merging constraint information to realize the trigger merging includes: A merge operation is performed on all unit flip-flops in the preliminary gate-level netlist according to the merge strength constraint, the bit width waste constraint and the multi-bit flip-flop selection constraint, a merged gate-level netlist corresponding to the preliminary gate-level netlist is generated, and the flip-flop merge is completed.

5. A trigger merging device applied to chip design, wherein: include: A preliminary synthesis module, used to perform preliminary synthesis on the selection optimization results of all unit triggers applied to the chip design; A constraint receiving module, configured to receive merge constraint information in response to a preliminary gate-level netlist generated by the preliminary synthesis; as well as A re-synthesis module, used for re-synthesizing the preliminary gate-level netlist according to the merging constraint information to realize the merging of the triggers; The preliminary synthesis module is further used to enable all the unit triggers in response to the received register transfer level instruction; and traverse each unit trigger of all the unit triggers to generate the selection optimization result; The preliminary synthesis module is further configured to determine, when one of the unit triggers among all the unit triggers corresponds to the logic function of at least one multi-bit trigger among all the preset multi-bit triggers, the one unit trigger as the unit trigger in the selection optimization result; The preliminary synthesis module is further used to disable the one unit trigger among all the unit triggers when the one unit trigger among all the unit triggers does not correspond to the logic function of each multi-bit trigger among all the preset multi-bit triggers; The constraint receiving module is further used to receive, in response to the preliminary gate-level netlist, a merging strength constraint, a bit width waste constraint, and a multi-bit trigger selection constraint as the merging constraint information.

6. An electronic device, wherein: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors execute the method according to any one of claims 1 to 4.

7. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to execute the method according to any one of claims 1 to 4.

8. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

Images