Scan driving circuit, display panel and display device

Abstract

An embodiment of the present application discloses a scan drive circuit, comprising n scan drive units arranged in sequence and cascaded, each scan drive unit receiving a clock signal and outputting a scan signal under the control of the clock signal. During a frame of image display period, each scan signal includes two scan pulses separated by a preset time length to control the corresponding pixel unit to receive image display data within the time period corresponding to the two scan pulses. The scan drive circuit disclosed in the present application increases the charging time of the pixel unit when a high refresh rate display panel displays an image, so that the pixel unit has sufficient time to receive image display data, ensures the display stability of the pixel unit, and optimizes the pixel charging process. The embodiment of the present application also discloses a display panel and a display device including the aforementioned scan drive circuit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to applications in scan drive circuits, display panels, and display devices. Background Art

[0002] Gate Driver Less (GDL) technology utilizes the LCD panel's existing array manufacturing process to fabricate the horizontal scan line driver circuitry on the substrate surrounding the display area, replacing the need for an external integrated circuit (IC) to drive the horizontal scan lines. GDL technology reduces the soldering process required for external ICs, making LCD panels more suitable for narrow-bezel or borderless display products.

[0003] Dual Line Gate (DLG) technology involves simultaneously turning on two adjacent scan lines and outputting the same data. This means that both rows of pixels receive the same image display data. This reduces resolution while increasing the refresh rate. However, the increased refresh rate reduces the pixel pre-charge time, resulting in a lower sustain voltage, which can lead to pixel display anomalies. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present application provides a scan driving circuit that maintains pixel voltage stability.

[0005] A scan drive circuit includes n scan drive units arranged in sequence and cascaded, and M clock signals, where n and M are integers greater than or equal to 1. Each scan drive unit receives a clock signal and, under the control of the clock signal, outputs a scan signal. The scan signal is output to a scan line in a display area and controls the corresponding pixel unit connected to the scan line to receive image display data for image display. During a frame of image display, the clock signal controls each scan drive unit to output a scan signal. Each scan signal includes two scan pulses separated by a preset time interval, controlling the corresponding pixel unit to receive image display data during the time period corresponding to the two scan pulses.

[0006] Optionally, the voltage of the scan pulse is used to start the pixel unit and receive image display data, the scan pulse lasts for a first duration, and the clock signal includes a plurality of continuous pulses and each pulse lasts for the first duration.

[0007] Optionally, the display area includes a plurality of scan lines arranged along a first direction and a plurality of data lines arranged along a second direction, the second direction being perpendicular to the first direction. A plurality of pixel units arranged in an array are arranged in rows along the first direction and connected to one of the scan lines to receive a scan signal, and a plurality of pixel units are arranged in columns along the second direction and connected to one of the data lines to receive image display data. Of the M clock signals, the i-th clock signal and the (i+1)-th clock signal have the same phase, where 1≤i<M, and i is an odd number. The two clock signals with the same phase control the corresponding scan drive units to simultaneously output scan signals, and the two simultaneously output scan signals control the corresponding two rows of pixel units to receive the same image display data.

[0008] Optionally, the display period of a frame of image has a first display duration (F), and the first duration is 2*F / n.

[0009] Optionally, the Kth scan driving unit receives the K-4th scan signal output by the K-4th scan driving unit to control the Kth scan driving unit to output the Kth scan signal. The Kth scan driving unit receives the K+8th scan signal output by the K+8th scan driving unit to control the Kth scan driving unit to stop outputting the Kth scan signal, wherein 5≤K≤n.

[0010] Optionally, the Kth scan driving unit includes a pull-up control module, a pull-up module, and a first node, wherein the pull-up control module and the pull-up module are electrically connected to the first node. The pull-up control module receives a K-4th scan signal output by the K-4th scan driving unit and, under control of the K-4th scan signal, pulls up the voltage of the first node to a first potential. When the voltage of the first node is at the first potential, the pull-up module receives a clock signal and outputs the Kth scan signal from the scan signal output terminal.

[0011] Optionally, the Kth scan drive unit further includes a pull-down control module and a pull-down module, the pull-down control module being electrically connected to the first node and the low voltage potential end, and the pull-down module being electrically connected to the scan signal output end and the low voltage potential end. The pull-down control module receives the K+8th scan signal output by the K+8th scan drive unit and, under the control of the K+8th scan signal, pulls down the voltage of the first node to a second potential. The pull-down module is configured to receive the K+8th scan signal output by the K+8th scan drive unit and, under the control of the K+8th scan signal, control the scan signal output end to be connected to the low voltage potential end, thereby controlling the output of the Kth scan signal to stop.

[0012] Optionally, the pull-up control module includes a first transistor, the gate and source of the first transistor are connected to the K-4 level transmission signal, and the drain is electrically connected to the first node. The pull-up module includes a second transistor, the gate of the second transistor is electrically connected to the first node, the source is connected to the clock signal, and the drain is electrically connected to the scan signal output terminal. The pull-down control module includes a third transistor, the gate of the third transistor is connected to the K+8 level scan signal, the source is electrically connected to the first node, and the drain is electrically connected to the low voltage potential terminal. The pull-down module includes a fourth transistor, the gate of the fourth transistor is connected to the +8 level scan signal, the source is connected to the scan signal output terminal, and the drain is connected to the low voltage potential terminal.

[0013] Optionally, the scan driving unit further includes a voltage-stabilizing capacitor, one end of the voltage-stabilizing capacitor is connected to the first node and the other end is connected to the scan signal output end, for controlling the stability of the scan signal output.

[0014] The present application also provides a display panel, comprising a plurality of pixel units arranged in a matrix and the aforementioned scanning driving circuit, wherein the scanning driving circuit drives the pixel units to display images based on a gate output control signal output by a display control circuit and a data signal output by a data driving circuit based on a source output control signal output by the display control circuit.

[0015] The present application also provides a display device, including a supporting frame, a power module and the aforementioned display panel, the power module provides power voltage for the display panel to display images, and the display panel and the power module are fixed to the supporting frame.

[0016] Compared with the existing technology, the scanning driving circuit provided in this application can improve the charging time of the pixel unit when the high refresh rate display panel displays images, so that the pixel unit has sufficient time to receive image display data, ensure the display stability of the pixel unit, and optimize the pixel charging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic structural diagram of a display device provided in the first embodiment of the present application;

[0019] Figure 2 The second embodiment of this application provides Figure 1 The side structure diagram of the display module is shown in the figure;

[0020] Figure 3 for Figure 2 The schematic diagram of the planar layout structure of the display module is shown in the figure;

[0021] Figure 4 The third embodiment of this application provides Figure 3 A schematic diagram of the circuit structure of the middle scan drive circuit;

[0022] Figure 5 for Figure 4 Equivalent circuit diagram of the GDL unit in;

[0023] Figure 6 for Figure 4 Schematic diagram of the GDL unit cascade;

[0024] Figure 7 A timing diagram of scanning signal output of a dual-line gate circuit provided in the fourth embodiment of the present application;

[0025] Figure 8 This is a timing diagram of the scanning signal output of the dual-line gate circuit provided in the fifth embodiment of the present application.

[0026] Explanation of the accompanying symbols: display device-100, display module-10, data driving circuit-11, scanning driving circuit-12, display panel-13, display control circuit-14, pixel unit-15, backlight module-17, first direction-F1, second direction-F2, scanning lines-G1~Gn, data lines-S1~Sm, horizontal synchronization signal-Hsyn, vertical synchronization signal-Vsyn, gate output control signal-Cg, source output control signal-Cs, clock signal-CLK, scanning driving unit-140, scanning signal-G(1)~ G(n), power module-20, support frame-30, array substrate-131, liquid crystal layer-132, color filter substrate-133, pull-up control module-141, pull-up module-142, pull-down control module-143, pull-down module-144, first node-Q(N) voltage-stabilizing capacitor-C(N), scan signal output end-GOUT, first transistor-T1, second transistor-T2, third transistor-T3, fourth transistor-T4, first charging period-t1, second charging period-t2, start signal-STV, low voltage potential-Vss. DETAILED DESCRIPTION

[0027] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0028] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers of the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application include direct and indirect connections (couplings) unless otherwise specified. The directional terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0029] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the description, claims, and drawings of this application are used to distinguish different objects, rather than to describe a specific order.

[0030] In addition, the terms "include", "may include", "include", or "may include" used in this application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "include" or "include" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. In addition, when describing the embodiments of the present application, "may" is used to indicate "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] See also Figure 1 , Figure 1This is a schematic diagram of the structure of a display device 100 provided in the first embodiment of the present application. The display device 100 includes a display module 10, a power module 20, and a support frame 30. The display module 10 and the power module 20 are fixed to the support frame 30. The power module 20 is located on the back side of the display module 10, i.e., the non-display side of the display module 10. The power module 20 is used to provide the power supply voltage for the display module 10 to display images. The support frame 30 provides a secure and protective function for the display module 10 and the power module 20.

[0033] See also Figure 2 , Figure 2 The second embodiment of this application provides Figure 1 FIG. 1 is a schematic diagram of the side structure of the display module 10 .

[0034] The display module 10 includes a display panel 13 and a backlight module (BM) 17. The backlight module 17 provides light for display to the display panel 13. The display panel 13 then emits light in response to the image signal to be displayed. The power module 20 provides the power supply voltage for the display panel 13 to display images. The support frame 30 secures and protects the display panel 13 and the power module 20.

[0035] The display module 10 also includes other elements or components, such as a signal processor module and a signal sensing module.

[0036] In an exemplary embodiment, the display panel 13 may be a liquid crystal display panel or other types of display panels, which are not shown in this application.

[0037] Taking a liquid crystal display panel as an example, the display panel 13 includes an array substrate (AS) 131, a color film substrate (CF) 133, and a liquid crystal layer 132 sandwiched between the array substrate 131 and the color film substrate 133. Driver elements disposed on the array substrate 131 and the color film substrate 133 generate corresponding electric fields based on data signals, thereby driving the liquid crystal molecules in the liquid crystal layer 132 to rotate and emit light of corresponding brightness to display images.

[0038] See also Figure 3 , Figure 3 for Figure 2 FIG. 1 is a schematic diagram of the planar layout structure of the display module 10.

[0039] like Figure 3As shown, the display area of ​​the display panel 13 includes a plurality of gate lines G1 to Gn extending along a first direction F1 and a plurality of data lines S1 to Sm extending along a second direction F2 arranged in a grid pattern. The first direction F1 and the second direction F2 are perpendicular to each other.

[0040] A plurality of pixel units 15 are disposed at the intersections of the plurality of scan lines G1-Gn and the data lines S1-Sm. The pixel units 15 are arranged in rows along a first direction F1 and connected to one of the scan lines to receive scan signals. The pixel units 15 are arranged in columns along a second direction F2 and connected to one of the data lines to receive image display data. In this embodiment, the pixel units 15 are denoted as P11-P1m, P21-P2m, ..., Pn1-Pnm.

[0041] The scan lines G1 to Gn are connected to the scan driving circuit 12 and receive scan signals from the scan driving circuit 12. The data lines S1 to Sm are connected to the data driving circuit 11 and are used to receive image signals or data signals (Data) provided by the data driving circuit 11 and stored and transmitted in the form of grayscale values ​​and convert them into corresponding analog voltage values.

[0042] Under the control of the scan lines G1 to Gn, the pixel unit 15 receives the data voltage corresponding to the grayscale value in the data signal Data provided by the data lines S1 to Sm during a predetermined time period, and accordingly drives the liquid crystal layer 132 to deflect the corresponding angle, thereby emitting light of corresponding brightness according to the corresponding deflection angle of the received backlight, so as to achieve image display according to the image signal emitting light of corresponding brightness.

[0043] The display module 10 also includes a data driver circuit 11, a scan driver circuit 12, and a display control circuit 14. The display control circuit 14 receives an original data signal representing image information, a synchronization clock signal CLK, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source within the display module 10. The display control circuit 14 then outputs a gate output control signal Cg for controlling the scan driver circuit 12, a source output control signal Cs for controlling the data driver circuit 11, and an adjusted data signal Data representing image information. In this embodiment, the display control circuit 14 performs data adjustment processing on the original data signal to obtain an adjusted data signal Data, and transmits the adjusted data signal Data to the data driver circuit 11.

[0044] The scan drive circuit 12 receives the gate output control signal Cg output by the display control circuit 14 and outputs a scan signal to each scan line G1 to Gn. The data drive circuit 11 receives the source output control signal Cs output by the display control circuit 14 and outputs a data signal Data for driving the elements in each pixel unit 15 in the display panel 13 to perform image display to each data line S1 to Sm. The data signal Data provided to the display panel 13 is an analog grayscale voltage. The scan drive circuit 12 outputs a scan signal, and the image signal is output from the data drive circuit 11. The voltage corresponding to the driving data signal is applied to the driving element in the pixel unit 15, thereby driving the liquid crystal molecules to perform image display. The scan drive circuit 12 is arranged in the non-display area of ​​the display panel 13 and is used to control the pixel unit 15 arranged in the display panel 13 to display an image.

[0045] See also Figure 4 , Figure 4 The third embodiment of this application provides Figure 3 FIG. 1 is a schematic diagram of the circuit structure of the scanning driving circuit 12. Figure 4 As shown, the scan driving circuit 12 includes n cascaded scan driving units 140, M clock signals CLK1-CLKM, a start signal STV, and a low voltage potential VSS, where n and M are integers greater than or equal to 1. For ease of description, the scan driving unit 140 is hereinafter represented by a GDL unit.

[0046] Each of the n GDL units outputs a scanning signal to a scanning line in the display module 10 . During one frame of image display, the n GDL units output n scanning signals, namely G( 1 ) to G(n).

[0047] In this embodiment, eight clock signals are used as an example, i.e., M = 8. The first through eighth clock signals CLK1, CLK8, provide the scan drive timing for the GDL unit output drive signals. The display control circuit 14 outputs a start signal STV, which serves as the enable signal for the first GDL unit GDL1. The remaining GDL units receive the scan signals output by the cascaded GDL units as their start signals. The low voltage potential VSS provides a low voltage for various nodes and signals within the GDL units.

[0048] In an exemplary embodiment, the scan driving circuit 12 may also be controlled by using other numbers of clock signals, which is not limited in this application.

[0049] See also Figure 5 , Figure 5 for Figure 4 The equivalent circuit diagram of the GDL unit in . Figure 5As shown, taking the Kth GDL unit as an example, where 5≤K≤n, the Kth GDL unit includes a pull-up control module 141, a pull-up module 142, a pull-down control module 143, a pull-down module 144, a first node Q(K) and a stabilizing capacitor C(K).

[0050] The pull-up control module 141 is connected to the first node Q(K) and receives the K-4th scan signal G(K-4) output by the K-4th GDL unit. The pull-up control module 141 uses the K-4th scan signal G(K-4) to pull up the potential of the first node Q(K) to the first potential.

[0051] The pull-up module 142 is connected to the i-th clock signal CLK(i) (1≤i≤M), the first node Q(K) and the output node GOUT. When the voltage of the first node Q(K) is a first potential, it is used to receive the i-th clock signal CLK(i) to control the scan signal output terminal GOUT to output the K-th level scan signal G(K), where the first potential is a high level.

[0052] The pull-down control module 143 is connected to the K+8th scan signal G(K+8), the first node Q(K) and the low voltage potential VSS, and is used to pull down the potential of the first node Q(K) to a second potential under the control of the K+8th scan signal G(K+8), where the second potential is the low voltage potential VSS.

[0053] The pull-down module 144 is connected to the K+8th scan signal G(K+8) and the scan signal output terminal GOUT. Under the control of the K+8th scan signal G(K+8), the scan signal output terminal GOUT is controlled to be connected to the low voltage potential terminal VSS to control the Kth scan signal G(K) to stop outputting.

[0054] The voltage-stabilizing capacitor C(K) is connected between the first node Q(K) and the scan signal output terminal GOUT. Due to the setting of the voltage-stabilizing capacitor C(K), when the pull-up control module 141 stops pulling up the voltage of the first node Q(K), the voltage of the first node Q(K) will be maintained for a period of time to control the complete output of the Kth scan signal and make the output of the Kth scan signal G(K) stable.

[0055] Specifically, the pull-up control module 141 includes a first transistor T1, the gate and source of which are connected to the input terminal (not labeled) of the K-4th scan signal G(K-4), and the drain of which is electrically connected to the first node Q(K). The pull-up module 142 includes a second transistor T2, the source of which receives the i-th clock signal CLK(i), the gate of which is connected to the first node Q(K), and the drain of which is connected to the scan signal output terminal GOUT. The pull-down control module 143 includes a third transistor T3, the source of which is connected to the first node Q(K), the gate of which is connected to the output terminal (not labeled) of the K+8th scan signal G(K+8), and the drain of which is connected to the low voltage potential VSS. The pull-down module 144 includes a fourth transistor T4, the source of which is connected to the scan signal output terminal GOUT, the gate of which is connected to the output terminal (not labeled) of the K+8th scan signal G(K+8), and the drain of which is connected to the low voltage potential VSS.

[0056] See also Figure 6 , Figure 6 for Figure 4 Schematic diagram of GDL unit cascade. Figure 6 As shown, taking the Kth GDL unit as an example, where 5≤K≤n, the Kth GDL unit outputs the Kth scan signal G(K) for pulling up the node voltage in the K+4th GDL unit to control the K+4th GDL unit to output the K+4th scan signal G(K+4), and is also used to pull down the node voltage in the K-8th GDL unit to control the K-8th GDL unit to stop outputting the K-8th scan signal G(K-8).

[0057] Taking the 9th GDL unit GDL9 as an example, the 9th GDL unit GDL9 outputs the 9th scan signal G(9) for pulling up the node voltage in the 13th GDL unit GDL13 to control the 13th GDL unit GDL13 to output the 13th scan signal G(13), and is also used to pull down the node voltage in the 1st GDL unit to control the 1st GDL unit GDL1 to stop outputting the 1st scan signal G(1).

[0058] That is to say, the Kth GDL unit simultaneously receives the K-4th scan signal G(K-4) and the K+8th scan signal G(K+8), receives the K-4th scan signal G(K-4) output by the K-4th scan signal and is used to pull up the node voltage in the Kth GDL unit to control the output of the Kth scan signal G(K), and receives the K+8th scan signal G(K+8) output by the K+8th scan driving unit and is used to pull down the node voltage in the Kth GDL unit to control the Kth GDL unit to stop outputting the Kth scan signal G(K).

[0059] Taking the fifth GDL unit GDL5 as an example, the fifth GDL unit receives the first scan signal G(1) and the thirteenth scan signal G(13) simultaneously. The first scan signal G(1) is received to pull up the node voltage in the fifth GDL unit to control the output of the fifth scan signal G(5). The thirteenth scan signal G(13) is received to pull down the node voltage in the fifth GDL unit to control the fifth GDL unit to stop outputting the fifth scan signal G(5).

[0060] By controlling the pull-down of the scan signal of the current GDL unit by outputting the scan signal of 8 GDL units at intervals, the scan signal output by the current GDL unit has a longer time, so that the pixel controlled by the current scan signal has sufficient pre-charge time to receive the data signal Data.

[0061] See also Figure 7 , Figure 7 This is a timing diagram of the scanning signal output of the dual-line gate circuit provided in the fourth embodiment of the present application. Figure 7 As shown, the dual line gate (DLG) circuit means that two adjacent rows of scan lines are turned on at the same time and output the same data, that is, two rows of pixels display the same content. For example, in a 4K (3840×2160) display panel, each frame of the image originally needs to scan a total of 2160 lines, that is, scan 2160 times, and 60 frames can be scanned per second, that is, the refresh rate is 60Hz. However, with DLG technology, it now only needs to scan 1080 times, which reduces the time by half, thereby achieving 120 frames per second, that is, the refresh rate is 120Hz, which improves the refresh rate of the image display.

[0062] However, due to the increase in refresh rate, the time it takes for the pixel unit to receive the data signal Data is reduced. Specifically, when 60Hz is used for refresh, that is, 60 frames of images are displayed in one second, the display time of one frame of image is F = 1 / 60s. In a 4K display panel, the time to scan a row of pixel units is H1 = F / 2160, H1 = 7.4us, and the pixel unit pre-charge time is 2H1 = 14.8um, that is, the pixel unit pre-charge time is 14.8us. When 120Hz is used for refresh, the time to scan a row of pixel units is H2 = 3.7um, and the pixel unit pre-charge time is 2H2 = 7.4us, that is, the pixel unit pre-charge time is 7.4us. At this time, the actual pre-charge time of the pixel unit is halved, which leads to a reduction in the pixel unit pre-charge time, a reduction in the pixel unit maintenance voltage, and abnormal pixel display.

[0063] See also Figure 8 , Figure 8 A dual-line gate circuit scanning signal output timing diagram is provided for the fifth embodiment of the present application. Figure 8As shown, the scan driver circuit 12 uses DLG technology to output scan signals, that is, two adjacent rows of scan signals control the corresponding two adjacent rows of pixel units to receive the same data. When M clock signals control the output of scan signals, the i-th clock signal CLKi and the i+1-th clock signal CLKi+1 are in phase, where 1≤i<M and i is an odd number. The two clock signals with the same phase control the corresponding scan driver units to output scan signals simultaneously, and the two simultaneously output scan signals control the corresponding two rows of pixel units to receive the same image display data.

[0064] Taking eight clock signals CLK as an example for control, among the eight clock signals, the first clock signal CLK1 and the second clock signal CLK2 have the same phase, controlling the simultaneous output of two scan signals to control the corresponding two rows of pixel units to receive the same image display data. The third clock signal CLK3 and the fourth clock signal CLK4 have the same phase, controlling the simultaneous output of two scan signals to control the corresponding two rows of pixel units to receive the same image display data. The fifth clock signal CLK5 and the sixth clock signal CLK6 have the same phase, controlling the simultaneous output of two scan signals to control the corresponding two rows of pixel units to receive the same image display data. The seventh clock signal CLK7 and the eighth clock signal CLK8 have the same phase, controlling the simultaneous output of two scan signals to control the corresponding two rows of pixel units to receive the same image display data. The two clock signals with the same phase control the corresponding scan driver units to simultaneously output scan signals, and the two simultaneously output scan signals control the corresponding two rows of pixel units to receive the same image display data. During a frame of image display, the clock signal CLK controls each scan driver unit to output a corresponding scan signal. Each scan signal includes two scan pulses separated by a preset time interval, controlling the corresponding pixel unit to receive image display data during the time period corresponding to the two scan pulses. The scan pulse is used to activate the pixel units in the corresponding row and receive image display data. The duration of a scan pulse is 2 hours, where 2 hours = 7.4 μm. The total duration of a scan pulse of a scan signal is 4 hours, where 4 hours = 14.8 μm. The clock signal CLK controls the output of the scan signal, and the duration of the output pulse signal is also 4 hours.

[0065] For example, taking the first scanning signal G(1) as an example, the first scanning signal is pulled down by the ninth scanning signal G(9), so that the first scanning signal has two scanning pulses, and the first row of pixel units is controlled to receive the corresponding data signal Data through the two scanning pulses. In the first charging period t1, which is the first pulse period, the charging time of the first row of pixel units is 2H, which is 7.4us. In the second charging period t2, which is the second pulse period, the charging time of the first row of pixel units is 2H, which is 7.4us, so that the total charging time of the first row of pixel units is 4H, which is 14.8s.

[0066] In an exemplary embodiment, the scan driving circuit 12 may also be used in other high refresh rate display modules to optimize pixel display effects for the display modules, and this application does not impose any limitation thereto.

[0067] The scan drive circuit 12 provided in the embodiment of the present application enables the pixel unit to have sufficient time to receive the data signal Data when the display module uses the DLG technology to increase the refresh rate from 60Hz to 120Hz, thereby avoiding pixel charging abnormalities caused by refreshing using the DLG technology, ensuring the stable display of the pixel unit, and optimizing the pixel charging process.

[0068] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A scan driving circuit, comprising n scan driving units and M clock signals arranged in sequence and connected in cascade, where n and M are integers greater than or equal to 1, each of the scan driving units receiving one of the clock signals and outputting a scan signal under the control of the clock signal, the scan signal being output to a scan line in a display area and controlling a pixel unit connected to the scan line to receive image display data for image display; It is characterized by: During a frame image display period, the clock signal controls each of the scan driving units to output the scan signal, each of the scan signals including two scan pulses separated by a preset time interval, so as to control the corresponding pixel unit to receive the image display data during the time periods corresponding to the two scan pulses; The Kth scan drive unit and the K+1th scan drive unit are used to simultaneously output the scan signal to control two adjacent rows of pixel units to simultaneously receive the image display data for image display, wherein the Kth scan drive unit is used to receive the K-4th scan signal output by the K-4th scan drive unit and the K+8th scan signal output by the K+8th scan drive unit, and is used to start outputting the Kth scan signal under the control of the K-4th scan signal, and stop outputting the Kth scan signal under the control of the K+8th scan signal, the output process of the Kth scan signal includes a first pulse period and a second pulse period, and the Kth scan signal controls the pixel unit to charge in the first pulse period and the second pulse period respectively, wherein 5≤K≤n.

2. The scan driving circuit according to claim 1, wherein: The voltage of the scan pulse is used to start the pixel unit and receive the image display data. The scan pulse lasts for a first time period. The clock signal includes a plurality of continuous pulses and each pulse lasts for the first time period.

3. The scanning driving circuit according to claim 2, wherein: The display area includes a plurality of scan lines arranged along a first direction and a plurality of data lines arranged along a second direction, the second direction being perpendicular to the first direction, a plurality of pixel units arranged in an array are arranged in rows along the first direction and connected to one of the scan lines to receive the scan signal, and a plurality of pixel units are arranged in columns along the second direction and connected to one of the data lines to receive the image display data; Among the M clock signals, the i-th clock signal and the i+1-th clock signal have the same phase, 1≤i<M, and i is an odd number; the two clock signals with the same phase control the corresponding scan driving units to output the scan signals at the same time, and the two scan signals output at the same time control the corresponding two rows of pixel units to receive the same image display data.

4. The scan driving circuit according to claim 3, wherein: The Kth scan driving unit includes a pull-up control module, a pull-up module and a first node, wherein the pull-up control module and the pull-up module are electrically connected to the first node; The pull-up control module receives the K-4th scanning signal output by the K-4th scanning driving unit, and pulls up the voltage of the first node to a first potential under the control of the K-4th scanning signal. When the voltage of the first node is the first potential, the pull-up module receives the clock signal and outputs a Kth scanning signal from the scanning signal output terminal.

5. The scan driving circuit according to claim 4, wherein: The Kth scan driving unit further includes a pull-down control module and a pull-down module, wherein the pull-down control module is electrically connected to the first node and the low voltage potential end, and the pull-down module is electrically connected to the scan signal output end and the low voltage potential end; The pull-down control module receives the K+8th scanning signal output by the K+8th scanning driving unit, and pulls down the voltage of the first node to a second potential under the control of the K+8th scanning signal; The pull-down module is used to receive the K+8th scanning signal output by the K+8th scanning driving unit, and under the control of the K+8th scanning signal, controls the scanning signal output end to be connected to the low voltage potential end to control the Kth scanning signal to stop outputting.

6. The scan driving circuit according to claim 5, wherein: The pull-up control module includes a first transistor, the gate and source of the first transistor are connected to the K-4 level transmission signal, and the drain is electrically connected to the first node; The pull-up module includes a second transistor, wherein the gate of the second transistor is electrically connected to the first node, the source is connected to the clock signal, and the drain is electrically connected to the scan signal output terminal; The pull-down control module includes a third transistor, wherein the gate of the third transistor is connected to the K+8th scanning signal, the source is electrically connected to the first node, and the drain is electrically connected to the low voltage potential end; The pull-down module includes a fourth transistor, the gate of the fourth transistor is connected to the +8th scanning signal, the source is connected to the scanning signal output end, and the drain is connected to the low voltage potential end.

7. The scan driving circuit according to claim 6, wherein: The scan driving unit further includes a voltage-stabilizing capacitor, one end of which is connected to the first node, and the other end of which is connected to the scan signal output end, for controlling the output stability of the scan signal.

8. A display panel, characterized in that: It includes a plurality of pixel units arranged in a matrix and a scanning driving circuit as described in any one of claims 1 to 7, wherein the scanning driving circuit drives the pixel units to display images according to a gate output control signal output by a display control circuit and a data signal output by a data driving circuit according to a source output control signal output by the display control circuit.

9. A display device, characterized in that: The display device comprises a supporting frame, a power module and the display panel as claimed in claim 8, wherein the power module provides power voltage for the display panel to display images, and the display panel and the power module are fixed to the supporting frame.

Images