A double-layer passivated depletion-mode MIS-HEMT device and a method for preparing the same

Abstract

The present invention discloses a double-layer passivated depletion-type MIS-HEMT device and a preparation method thereof, the method comprising: sequentially growing an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer on a substrate; forming an isolation region of the device on both sides of the sample obtained in the previous step; growing a Si passivation layer on the upper surface of the AlGaN barrier layer, and forming a layer of SiO on the surface of the Si passivation layer by a thermal oxidation process. 2 oxide layer, thus forming Si‑SiO 2 Double-layer passivation structure; etching away the SiO on both sides of the gate area 2 Oxide layer and Si passivation layer; SiO is deposited on the entire sample surface 2 The invention forms a Si passivation layer between the gate oxide and the semiconductor, and forms Si-SiO by thermal oxidation. 2 The double-layer passivation structure effectively reduces the interface state between the gate dielectric and the barrier layer, reduces the negative drift of the device threshold voltage, avoids the failure problem of existing devices caused by gate instability, and realizes a depletion-mode MIS-HEMT device with excellent reliability.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a double-layer passivation depletion-type MIS-HEMT device and a preparation method thereof. Background Art

[0002] The research and application of GaN materials are the forefront and hotspot of global semiconductor research. It is a new type of semiconductor material for the development of microelectronic devices and optoelectronic devices. Together with SiC, diamond and other semiconductor materials, it is known as the third generation of semiconductor materials after the first generation of Ge and Si semiconductor materials, and the second generation of GaAs and InP compound semiconductor materials. Compared with the first and second generation semiconductor materials, GaN materials have the advantages of high bandgap width, high breakdown voltage, high thermal conductivity, high electron saturation velocity and high electron mobility. Therefore, GaN devices can withstand higher voltages and higher operating temperatures. It has broad application prospects in the fields of high voltage, high power, wireless communications, etc.

[0003] As one of the representatives of GaN devices, AlGaN / GaN MIS-HEMT devices suppress gate leakage and improve the gate voltage swing and microwave power performance of the device by introducing a metal-oxide-semiconductor structure into the gate of traditional HEMT devices.

[0004] However, due to the existence of fixed charges between the gate and the oxide layer of the existing GaN HEMT device, the positive fixed charges will reduce the gate barrier, causing the threshold voltage of the device to drift negatively, thus requiring a higher reverse voltage to turn off the device. Especially for depletion-type devices, as normally-on devices, they are already turned on when no voltage is applied to the gate, and the device transfer characteristic curve drifts negatively, increasing the power consumption of the device in the off state. At the same time, due to the generation or introduction of oxygen and water vapor during the growth of the gate oxide, the surface of the barrier layer is partially oxidized, which will aggravate the interface state between the gate oxide and the barrier layer. During the process of applying electrical stress to the device, the interface state captures or releases electrons, which will also cause a significant drift in the threshold voltage of the HEMT device, which is very detrimental to the long-term reliability of the device.

[0005] In addition, since GaN materials grow in a non-thermodynamic equilibrium state during epitaxial growth, a large number of defects and dangling bonds are generated on the surface of GaN materials. These defect states and dangling bonds can capture or release electrons. Under the special working conditions of high voltage and high power of GaN devices, hot carrier effects are prone to occur, which aggravates the accumulation of gate defect states, making it more likely to produce device failures caused by gate instability compared to ordinary gate voltage control devices. In the context of immature GaN growth technology, GaN devices will produce particularly serious device threshold voltage drift, output current reduction and other phenomena, resulting in unstable device working state and reduced reliability, which limits the application of devices. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a double-layer passivation depletion-mode MIS-HEMT device and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0007] A method for preparing a double-layer passivated depletion-mode MIS-HEMT device, comprising:

[0008] Step 1: sequentially growing an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer on a substrate;

[0009] Step 2: forming device isolation regions on both sides of the sample obtained in step 1;

[0010] Step 3: growing a Si passivation layer on the upper surface of the AlGaN barrier layer, and forming a layer of SiO on the surface of the Si passivation layer by a thermal oxidation process. 2 oxide layer, thus forming Si-SiO 2 Double-layer passivation structure;

[0011] Step 4: Define the gate region by photolithography and etch away the SiO2 on both sides of the gate region. 2 Oxide layer and Si passivation layer;

[0012] Step 5: Deposit SiO on the entire sample surface 2 Passivation layer;

[0013] Step 6: Fabricate the source, drain and gate of the device to form a double-layer passivated depletion-mode MIS-HEMT device.

[0014] In one embodiment of the present invention, step 1 comprises:

[0015] Using metal organic compound chemical vapor deposition process, a 50-500nm thick AlN nucleation layer, a 200-8000nm thick AlGaN buffer layer, a 50-500nm thick GaN channel layer, and a 10-30nm thick AlGaN layer are grown on the substrate in sequence. x Ga 1-x N barrier layers, wherein x=0.1-0.5.

[0016] In one embodiment of the present invention, step 3 comprises:

[0017] 31) growing 2 to 5 atomic layers of Si on the AlGaN barrier layer using an atomic layer deposition process to form a Si passivation layer on the surface of the AlGaN barrier layer; wherein the thickness of the Si passivation layer is 2 to 5 nm;

[0018] 32) forming a layer of SiO on the surface of the Si passivation layer by a thermal oxidation process 2 Oxide layer; wherein the SiO 2 The thickness of the oxide layer is 1 to 2 nm.

[0019] In one embodiment of the present invention, step 5 comprises:

[0020] Plasma enhanced chemical vapor deposition was used to deposit SiO on the entire sample surface. 2 Materials to form SiO with a thickness of 5 to 100 nm 2 Passivation layer.

[0021] In one embodiment of the present invention, step 6 comprises:

[0022] 61) Define the source and drain regions by photolithography, and etch away the SiO2 under the source and drain regions. 2 Passivation layer and AlGaN barrier layer;

[0023] 62) depositing metal in the source and drain regions to form source and drain electrodes of the device;

[0024] 63) In the SiO 2 A gate metal is deposited in the gate region on the passivation layer to form a MIS structure, thereby completing device preparation.

[0025] In one embodiment of the present invention, the step 62) comprises:

[0026] A physical vapor deposition method or an electron beam evaporation process is used to deposit metal in the source and drain regions, and after high-temperature annealing, an ohmic contact between the source and the drain is formed.

[0027] Another embodiment of the present invention provides a double-layer passivation depletion-mode MIS-HEMT device, comprising a substrate, an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer, an AlGaN barrier layer, an isolation region, a Si passivation layer, a SiO 2 Oxide layer, SiO 2 Passivation layer, source, drain, gate;

[0028] The substrate, AlN nucleation layer, AlGaN buffer layer, GaN channel layer, and AlGaN barrier layer are arranged in sequence from bottom to top;

[0029] The isolation region is arranged in the AlGaN barrier layer and the GaN channel layer on both sides of the device;

[0030] The source electrode and the drain electrode are respectively arranged on the GaN channel layer on both sides of the device;

[0031] The Si passivation layer is disposed on the AlGaN barrier layer between the source and the drain;

[0032] The SiO 2 The oxide layer is located on the upper surface of the Si passivation layer;

[0033] The SiO 2 The passivation layer is disposed on the AlGaN barrier layer and covers the Si passivation layer and the SiO 2 Oxide layer;

[0034] The gate is located on the SiO 2 The SiO 2 On the passivation layer, a MIS device structure is formed.

[0035] In one embodiment of the present invention, the SiO 2 The oxide layer is formed on the upper surface of the Si passivation layer by a thermal oxidation process.

[0036] In one embodiment of the present invention, the thickness of the Si passivation layer is 2-5 nm; 2 The thickness of the oxide layer is 1 to 2 nm; the SiO 2 The thickness of the passivation layer is 5 to 100 nm.

[0037] Beneficial effects of the present invention:

[0038] 1. The present invention grows a dense Si passivation layer between the gate oxide and the semiconductor of the MIS structure and forms a Si-SiO 2 The double-layer passivation structure can be used as both the gate insulating layer and the surface passivation layer, avoiding direct contact between the original gate dielectric and the AlGaN barrier layer, effectively reducing the interface state between the gate oxide and the barrier layer, reducing the negative drift of the device threshold voltage, stabilizing the off-state leakage current unique to the depletion-type MIS device, improving the device reliability, and reducing the power consumption of the device in the off state;

[0039] 2. The preparation method of the double-layer passivated depletion-mode MIS-HEMT device provided by the present invention avoids the immature growth process of GaN materials by using mature Si passivation process, avoids the large number of interface states generated by GaN materials during the growth process, and realizes a depletion-mode MIS-HEMT device with high breakdown voltage, small gate leakage current, stable threshold voltage and excellent reliability, effectively reducing the failure problem of existing GaN MIS-HEMT devices caused by gate instability, so that GaN devices can play a greater role in their unique high-voltage and high-power application fields;

[0040] 3. The preparation method provided by the present invention simplifies the process steps, reduces the consumption of resources and energy in device manufacturing and use, and reduces the process cost and the complexity of the device structure.

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic flow chart of a method for preparing a double-layer passivated depletion-mode MIS-HEMT device provided by an embodiment of the present invention;

[0043] Figure 2 It is a schematic structural diagram of a double-layer passivated depletion-mode MIS-HEMT device provided by an embodiment of the present invention;

[0044] Figure 3a-3i is a process diagram for preparing a double-layer passivated depletion-mode MIS-HEMT device provided by an embodiment of the present invention;

[0045] Description of reference numerals:

[0046] 1-substrate; 2-AlN nucleation layer; 3-AlGaN buffer layer; 4-GaN channel layer; 5-AlGaN barrier layer; 6-isolation region; 7-Si passivation layer; 8-SiO 2 Oxide layer: 9-SiO 2 Passivation layer; 10-source; 11-drain; 12-gate. DETAILED DESCRIPTION

[0047] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0048] Embodiment 1

[0049] See also Figure 1 , Figure 1 1 is a flow chart of a method for preparing a double-layer passivated depletion-mode MIS-HEMT device provided by an embodiment of the present invention, which specifically includes the following steps:

[0050] Step 1: sequentially growing an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer on a substrate.

[0051] Specifically, in this embodiment, a metal organic chemical vapor deposition (MOCVD) technique is used to sequentially grow an AlN nucleation layer with a thickness of 50 to 500 nm, a GaN buffer layer with a thickness of 200 to 8000 nm, a GaN channel layer with a thickness of 50 to 500 nm, and an AlN layer with a thickness of 10 to 30 nm. x Ga 1-x N barrier layers, wherein x=0.1-0.5.

[0052] Among them, the heterojunction formed between the GaN channel layer and the AlGaN barrier layer generates a two-dimensional electron gas channel with high electron mobility due to the polarization reaction.

[0053] Step 2: Form device isolation regions on both sides of the sample obtained in step 1.

[0054] Optionally, this embodiment mainly forms an isolation region of the device by performing ion implantation on both side surfaces of the sample obtained in step 1; wherein the isolation region extends downward from the upper surface of the AlGaN barrier layer to the upper surface of the AlGaN buffer layer.

[0055] Specifically, this embodiment uses ion implantation technology to implant N ions into the AlGaN barrier layer and the GaN channel layer on the upper surface of the AlGaN barrier layer to form a high resistance region to achieve device isolation.

[0056] Step 3: Grow a Si passivation layer on the upper surface of the AlGaN barrier layer, and form a layer of SiO on the surface of the Si passivation layer by thermal oxidation process. 2 oxide layer, thus forming Si-SiO 2 Double-layer passivation structure.

[0057] First, 2 to 5 atomic layers of Si are grown on the AlGaN barrier layer using an atomic layer deposition (ALD) process, and in-situ Si is deposited at low temperature. 2 H 6 Passivation is performed to form a high-quality Si passivation layer on the surface of the AlGaN barrier layer; wherein the thickness of the Si passivation layer is 2 to 5 nm.

[0058] Then, a thin SiO layer is formed on the surface of the Si passivation layer by thermal oxidation process. 2 oxide layer, thus forming Si-SiO 2 Double-layer passivation structure.

[0059] In this embodiment, SiO is formed by high temperature natural thermal oxidation. 2 The thickness of the oxide layer is 1 to 2 nm.

[0060] Step 4: Define the gate region by photolithography and etch away the Si passivation layer and SiO2 on both sides of the gate region. 2 Oxide layer.

[0061] Specifically, this embodiment uses reactive ion etching (RIE) technology to etch away the Si passivation layer and the thin SiO2 outside the gate region. 2 Oxide layer.

[0062] Step 5: Deposit SiO on the entire sample surface 2 Passivation layer.

[0063] Specifically, this embodiment uses plasma enhanced chemical vapor deposition (PECVD) to deposit SiO on the entire surface of the sample obtained in step 4. 2 Materials, forming SiO with a thickness of 5 to 100 nm 2 Passivation layer.

[0064] Step 6: Fabricate the source, drain and gate of the device to form a double-layer passivated depletion-mode MIS-HEMT device.

[0065] In this embodiment, step 6 includes:

[0066] 61) Define the source and drain regions by photolithography and etch away the SiO2 under the source and drain regions. 2 passivation layer and AlGaN barrier layer.

[0067] Specifically, this embodiment uses inductively coupled plasma etching technology (ICP) to define the source and drain regions, and then etches away the SiO 2 Passivation layer and AlGaN barrier layer 5.

[0068] 62) Deposit metal in the source and drain regions to form source and drain electrodes of the device.

[0069] Specifically, a physical vapor deposition (PVD) method is used to deposit metal in the source and drain regions, and after high-temperature annealing, an ohmic contact between the source and the drain is formed.

[0070] 63) In SiO 2 A gate metal is deposited in the gate region on the passivation layer to form a MIS structure, thereby completing device preparation.

[0071] It should be noted that the MOCVD technology, ALD technology, RIE technology, PECVD technology, ICP technology and PVD technology used in this embodiment are all existing mature technologies. Their specific process parameters and process can be implemented by referring to the existing technology, and this embodiment will not be described in detail here.

[0072] In addition, for the selection of source, drain and gate metals, commonly used metals or metal combinations, such as Ti / Al, Ti / Al / Ni / Au or Ti / Al / Mo / Au, etc., may also be used, and this embodiment does not make any specific limitations on this.

[0073] In this embodiment, a dense Si passivation layer is grown between the gate oxide and the semiconductor of the MIS structure, and a Si-SiO 2The double-layer passivation structure can serve as both the gate insulating layer and the surface passivation layer, avoiding direct contact between the original gate oxide and the AlGaN barrier layer, effectively reducing the interface state between the gate dielectric and the barrier layer, reducing the negative drift of the device threshold voltage, stabilizing the off-state leakage current unique to the depletion-type MIS device, improving device reliability, and reducing the power consumption of the device in the off state.

[0074] Furthermore, the present invention avoids the immature growth process of GaN materials by using mature Si passivation process, avoids the large number of interface states generated by GaN materials during the growth process, realizes a depletion-type MIS-HEMT device with high breakdown voltage, small gate leakage current, stable threshold voltage, and excellent reliability, effectively reduces the failure problem of existing GaN MIS-HEMT devices caused by gate instability, and enables GaN devices to play a greater role in their unique high-voltage and high-power application fields. In addition, the preparation method provided by the present invention also simplifies the process steps, reduces the consumption of resources and energy in device manufacturing and use, and reduces the process cost and the complexity of the device structure.

[0075] Embodiment 2

[0076] Based on the above-mentioned embodiment 1, this embodiment provides a double-layer passivation depletion-mode MIS-HEMT device. Figure 2 , Figure 2 1 is a schematic diagram of the structure of a double-layer passivated depletion-mode MIS-HEMT device provided by an embodiment of the present invention, which includes:

[0077] Substrate 1, AlN nucleation layer 2, AlGaN buffer layer 3, GaN channel layer 4, AlGaN barrier layer 5, isolation region 6, Si passivation layer 7, SiO 2 Oxide layer 8, SiO 2 Passivation layer 9, source electrode 10, drain electrode 11, gate electrode 12;

[0078] Wherein, a substrate 1, an AlN nucleation layer 2, an AlGaN buffer layer 3, a GaN channel layer 4, and an AlGaN barrier layer 5 are arranged in sequence from bottom to top;

[0079] The isolation region 7 is arranged in the AlGaN barrier layer 5 and the GaN channel layer 4 on both sides of the device;

[0080] The source electrode 10 and the drain electrode 11 are respectively arranged on the GaN channel layer 4 on both sides of the device;

[0081] The Si passivation layer 7 is disposed on the AlGaN barrier layer 5 between the source 10 and the drain 11;

[0082] SiO 2 The oxide layer 8 is located on the upper surface of the Si passivation layer 7;

[0083] SiO 2 The passivation layer 9 is disposed on the AlGaN barrier layer 5 and covers the Si passivation layer 7 and the SiO 2 Oxide layer 8;

[0084] The gate is located on SiO 2 SiO above oxide layer 8 2 On the passivation layer 9, a MIS device structure is formed.

[0085] In this embodiment, the thickness of the Si passivation layer 7 is 2-5 nm; 2 The thickness of the oxide layer 8 is 1-2 nm; SiO 2 The thickness of the passivation layer 9 is 5 to 100 nm.

[0086] Furthermore, SiO 2 The oxide layer 8 is formed on the upper surface of the Si passivation layer 7 by a thermal oxidation process.

[0087] The double-layer passivated depletion-mode MIS-HEMT device provided in this embodiment can be prepared by the method provided in the above embodiment 1. Therefore, the device also has the advantages of high breakdown voltage, small gate leakage current, stable threshold voltage, stable working state, and high reliability, so that it can play a greater advantage in the unique high-voltage and high-power application fields.

[0088] Embodiment 3

[0089] Combine the following Figure 3a-3i The preparation process of the double-layer passivated depletion-mode MIS-HEMT device provided by the present invention is described in detail. Figure 3a-3i 1 is a process diagram for preparing a double-layer passivated depletion-mode MIS-HEMT device provided by an embodiment of the present invention, which specifically includes:

[0090] Step a: growing AlN nucleation layer 2, AlGaN buffer layer 3, GaN channel layer 4, AlGaN barrier layer 5 on substrate 1 in sequence

[0091] Specifically, a metal organic compound chemical vapor deposition technique is used to sequentially grow an AlN nucleation layer 2 with a thickness of 50 to 500 nm, a GaN buffer layer 3 with a thickness of 200 to 8000 nm, a GaN channel layer 4 with a thickness of 50 to 500 nm, and an AlN layer with a thickness of 10 to 30 nm. x Ga 1-x N barrier layer 5, where x = 0.1 to 0.5. The heterojunction formed between the GaN channel layer and the AlGaN barrier layer generates a two-dimensional electron gas channel with high electron mobility due to the polarization reaction, such as Figure 3a shown.

[0092] Step b: Making device isolation area 6

[0093] Specifically, N ion implantation technology is used to implant N ions into the isolation region 6 on the upper surface of the AlGaN barrier layer 5 to achieve device isolation. Figure 3b shown.

[0094] Step c: growing a Si passivation layer 7 on the upper surface of the AlGaN barrier layer 5

[0095] Specifically, atomic layer deposition (ALD) technology is used to perform in-situ Si 2 H 6 Passivation, forming a high-quality Si passivation layer 7 with a thickness of 2 to 5 nm, such as Figure 3c shown.

[0096] Step d: Thermal oxidation to form SiO 2 Oxide layer 8

[0097] Specifically, the Si passivation layer 7 is subjected to high temperature natural thermal oxidation to form a thin layer of SiO 2 Oxide layer 8, such as Figure 3d As shown, SiO 2 The thickness of the oxide layer 8 is 1 to 2 nm.

[0098] Step e: Etch away the Si passivation layer and SiO2 on both sides of the gate area 2 Oxide layer

[0099] Specifically, the gate region is defined by photolithography, and the Si passivation layer 7 and the thin SiO2 layer outside the gate region are etched away by reactive ion etching (RIE) technology. 2 Oxide layer 8, such as Figure 3e shown.

[0100] Step f: Deposition of SiO on the entire sample surface 2 Passivation layer 9

[0101] Specifically, a plasma enhanced chemical vapor deposition method is used to deposit SiO2 with a thickness of 5 to 100 nm on the entire sample at low temperature. 2 Passivation layer 9, such as Figure 3f shown.

[0102] Step g: Photolithography of source and drain areas

[0103] Specifically, the inductively coupled plasma etching technology (ICP) is used to define the source and drain regions, and then the SiO 2 The passivation layer 9 and the AlGaN barrier layer 5 are formed to form the source and drain regions of the device. Figure 3g shown.

[0104] Step h: Preparation of source and drain electrodes

[0105] Specifically, physical vapor deposition (PVD) is used to deposit source metal and drain metal, and then high temperature annealing is performed to form the source 10 and drain 11 of the device, such as Figure 3h shown.

[0106] Step i: Making the gate

[0107] Specifically, in SiO 2 A gate metal is deposited in the gate region on the passivation layer to form a MIS structure, thereby obtaining a device gate 12. Figure 3i shown.

[0108] At this point, the preparation of the double-layer passivated depletion-mode MIS-HEMT device is completed.

[0109] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0110] In addition, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes the first feature being directly below and obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0111] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a double-layer passivated depletion-mode MIS-HEMT device, characterized in that: include: Step 1: sequentially growing an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer on a substrate; Step 2: forming device isolation regions on both sides of the sample obtained in step 1; Step 3: growing a Si passivation layer on the upper surface of the AlGaN barrier layer, and forming a SiO2 oxide layer on the surface of the Si passivation layer by a thermal oxidation process, thereby forming a Si-SiO2 double-layer passivation structure; Step 4: defining the gate region by photolithography, and etching away the SiO2 oxide layer and the Si passivation layer on both sides of the gate region; Step 5: Deposit a SiO2 passivation layer on the entire sample surface; Step 6: Fabricate the source, drain and gate of the device to form a double-layer passivated depletion-mode MIS-HEMT device.

2. The method for preparing a double-layer passivated depletion-mode MIS-HEMT device according to claim 1, characterized in that: Step 1 includes: Using metal organic compound chemical vapor deposition process, a 50-500nm thick AlN nucleation layer, a 200-8000nm thick AlGaN buffer layer, a 50-500nm thick GaN channel layer, and a 10-30nm thick AlGaN layer are grown on the substrate in sequence. x Ga 1-x N barrier layers, wherein x=0.1-0.

5.

3. The method for preparing a double-layer passivated depletion-mode MIS-HEMT device according to claim 1, characterized in that: Step 3 includes: 31) growing 2 to 5 atomic layers of Si on the AlGaN barrier layer using an atomic layer deposition process to form a Si passivation layer on the surface of the AlGaN barrier layer; wherein the thickness of the Si passivation layer is 2 to 5 nm; 32) Forming a SiO2 oxide layer on the surface of the Si passivation layer by a thermal oxidation process; wherein the thickness of the SiO2 oxide layer is 1 to 2 nm.

4. The method for preparing a double-layer passivated depletion-mode MIS-HEMT device according to claim 1, characterized in that: Step 5 includes: The SiO2 material is deposited on the entire sample surface by plasma enhanced chemical vapor deposition to form a SiO2 passivation layer with a thickness of 5 to 100 nm.

5. The method for preparing a double-layer passivated depletion-mode MIS-HEMT device according to claim 1, characterized in that: The step 6 comprises: 61) defining the source and drain regions by photolithography, and etching away the SiO2 passivation layer and the AlGaN barrier layer under the source and drain regions; 62) depositing metal in the source and drain regions to form source and drain electrodes of the device; 63) Depositing gate metal in the gate region on the SiO2 passivation layer to form a MIS structure, thereby completing device preparation.

6. The method for preparing a double-layer passivated depletion-mode MIS-HEMT device according to claim 5, characterized in that: The step 62) comprises: A physical vapor deposition method or an electron beam evaporation process is used to deposit metal in the source and drain regions, and after high-temperature annealing, an ohmic contact between the source and the drain is formed.

7. A double-layer passivated depletion-mode MIS-HEMT device, characterized in that: It comprises a substrate (1), an AlN nucleation layer (2), an AlGaN buffer layer (3), a GaN channel layer (4), an AlGaN barrier layer (5), an isolation region (6), a Si passivation layer (7), a SiO2 oxide layer (8), a SiO2 passivation layer (9), a source electrode (10), a drain electrode (11), and a gate electrode (12); The substrate (1), the AlN nucleation layer (2), the AlGaN buffer layer (3), the GaN channel layer (4), and the AlGaN barrier layer (5) are arranged in sequence from bottom to top; The isolation region (6) is arranged in the AlGaN barrier layer (5) and the GaN channel layer (4) on both sides of the device; The source electrode (10) and the drain electrode (11) are respectively arranged on the GaN channel layer (4) at two sides of the device; The Si passivation layer (7) is arranged on the AlGaN barrier layer (5) between the source electrode (10) and the drain electrode (11); The SiO2 oxide layer (8) is located on the upper surface of the Si passivation layer (7); The SiO2 passivation layer (9) is arranged on the AlGaN barrier layer (5) and covers the Si passivation layer (7) and the SiO2 oxide layer (8); The gate is located on the SiO2 passivation layer (9) above the SiO2 oxide layer (8) to form a MIS device structure.

8. The double-layer passivated depletion-mode MIS-HEMT device according to claim 7, characterized in that: The SiO2 oxide layer (8) is formed on the upper surface of the Si passivation layer (7) through a thermal oxidation process.

9. The double-layer passivated depletion-mode MIS-HEMT device according to claim 7, characterized in that: The thickness of the Si passivation layer (7) is 2 to 5 nm; the thickness of the SiO2 oxide layer (8) is 1 to 2 nm; and the thickness of the SiO2 passivation layer (9) is 5 to 100 nm.

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