Semiconductor device, memory, print head and consumable cartridge

Abstract

This application discloses a semiconductor device, a memory, a printhead, and a consumable cartridge. The semiconductor device includes a semiconductor substrate and a transistor, an antifuse element, a resistor element, a first terminal, and a second terminal disposed on the semiconductor substrate. The transistor is connected to the first terminal. The antifuse element is connected between the transistor and the second terminal via a first wiring and a third wiring. The resistor element is connected in parallel with the antifuse element between the transistor and the second terminal via a second wiring and a fourth wiring. The first and third wirings are both referred to as antifuse wirings, and the second and fourth wirings are both referred to as resistor wirings. At least one antifuse wiring is arranged in a first stacked structure, and / or, at least one resistor wiring and its corresponding antifuse wiring are arranged in a second stacked structure. This application enables a larger wiring space for the resistor wirings, thereby increasing the resistance of the resistor wirings and improving data reading accuracy.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device, as well as a memory, printhead, and consumable cartridge containing the semiconductor device. Background Technology

[0002] Antifuse elements are widely used as one-time programmable memory. However, in semiconductor manufacturing processes, many factors can reduce the accuracy of data writing to and from the antifuse element. Currently, the commonly used antifuse element connection structure is as follows: the antifuse element and the resistor element are connected in parallel, and then the parallel antifuse element and the resistor element are connected in series between the power signal terminal and the ground terminal, and the antifuse element and the resistor element are connected to the ground terminal through a transistor.

[0003] In existing technologies, the wiring resistance between transistors and resistors is generally increased by increasing the wiring length from transistors to resistors, thereby increasing the voltage value before and after data reading and writing, and thus improving data reading accuracy. However, the existing layout method has a limited effect on increasing the wiring resistance and does not significantly improve data reading accuracy. To achieve a significant effect, the chip area needs to be large, which increases the chip cost. Summary of the Invention

[0004] In order to overcome the problems existing in the prior art, the main objective of this application is to provide a semiconductor device that can improve data reading accuracy and has low cost.

[0005] To achieve the above objectives, this application specifically adopts the following technical solution:

[0006] A semiconductor substrate is provided with a first terminal and a second terminal;

[0007] A transistor is disposed on the semiconductor substrate and connected to the first terminal;

[0008] An antifuse element is disposed on the semiconductor substrate and connected between the transistor and the second terminal;

[0009] A resistor element is disposed on the semiconductor substrate and connected in parallel with the antifuse element between the transistor and the second terminal;

[0010] Wherein, the transistor is connected to one end of the antifuse element via a first wiring and to one end of the resistor element via a second wiring; the other end of the antifuse element is connected to the second terminal via a third wiring and the other end of the resistor element is connected to the second terminal via a fourth wiring.

[0011] The first wiring and the third wiring are both referred to as antifuse wiring, and the second wiring and the fourth wiring are referred to as resistor wiring;

[0012] At least one of the antifuse wires is arranged in a first stacked structure, and / or at least one of the resistor wires is arranged in a second stacked structure with the corresponding antifuse wire, wherein the sum of the resistances of the resistor wires is greater than the sum of the resistances of the antifuse wires.

[0013] Compared to existing technologies, the semiconductor device of this application includes a semiconductor substrate and a transistor, an antifuse element, and a resistor element disposed on the semiconductor substrate. The semiconductor substrate has a first terminal and a second terminal. The transistor is connected to the first terminal, the antifuse element is connected between the transistor and the second terminal, and the resistor element is connected in parallel with the antifuse element between the transistor and the second terminal. The transistor is connected to one end of the antifuse element via a first wiring and to one end of the resistor element via a second wiring. The other end of the antifuse element is connected to the second terminal via a third wiring, and the other end of the resistor element is connected to the second terminal via a fourth wiring. The first and third wirings are both referred to as antifuse wirings, and the second and fourth wirings are both referred to as resistor wirings. At least one antifuse wiring is arranged in a first stacked structure, and / or, at least one of the aforementioned wirings... The resistor wiring and the corresponding antifuse wiring are arranged in a second stacked structure. The sum of the resistances of the resistor wirings is greater than the individual resistances of the antifuse wirings, thereby increasing the wiring space in the second and / or fourth wirings. This allows for an increase in the wiring distance in the second and / or fourth wirings, increasing the wiring resistance in the second and / or fourth wirings, and / or decreasing the wiring resistance of the first and / or third wirings. This increases the difference between the wiring resistance in the first and second wirings and / or the difference between the wiring resistance in the second and fourth wirings, thereby increasing the overall difference between the antifuse wiring resistance and the resistor wiring resistance. This improves data reading accuracy. At the same time, the design structure of this application allows for more compact devices, higher integration, smaller chip area, more chips per wafer, and lower cost. Attached Figure Description

[0014] Figure 1 The circuit schematic of the semiconductor device provided in the embodiments of this application is shown.

[0015] Figure 2 This is a top view of a semiconductor device provided in an embodiment of this application.

[0016] Figure 3 A cross-sectional view of a semiconductor device provided in an embodiment of this application.

[0017] Figure 4Another cross-sectional view of the semiconductor device provided in the embodiments of this application.

[0018] Figure 5 A top view of a semiconductor device provided in another embodiment of this application.

[0019] Figure 6 for Figure 5 A cross-sectional view of a semiconductor device.

[0020] Figure 7 A perspective view of the printhead provided in an embodiment of this application.

[0021] Attached image labels:

[0022] 1. Semiconductor substrate; 101. First terminal; 102. Second terminal; 103. First terminal wiring; 104. Second terminal wiring; 2. Transistor; 21. Source; 22. Drain; 23. Gate; 3. Antifuse element; 4. Resistor element; 5. First wiring; 51. First wiring sublayer; 6. Second wiring; 7. Third wiring; 71. Second wiring sublayer; 8. Fourth wiring; 9. First insulating layer; 10. Connector; 100. Printhead; 200. Substrate; 300. Nozzle plate; 301. Nozzle; 400. Filter; 500. Printing element; 201. Ink chamber; 202. Liquid channel. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0024] In the description of this application, unless otherwise expressly specified and limited, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; unless otherwise specified or explained, the term "multiple" refers to two or more, and the term "various types" refers to two or more; the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0025] In the description of this specification, it should be understood that the directional terms such as "upper" and "lower" used in the embodiments of this application are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. Furthermore, in the context, it should also be understood that when it is mentioned that an element is connected "upper" or "lower" to another element, it can be directly connected to the other element "upper" or "lower," or indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0026] Reference Figure 1 and Figure 2 As shown, Figure 1 The circuit schematic of the semiconductor device provided in the embodiments of this application is as follows. Figure 2 This is a top view of a semiconductor device provided in an embodiment of this application. The semiconductor device includes a semiconductor substrate 1 and a transistor 2, an antifuse element 3, and a resistor element 4 disposed on the semiconductor substrate 1. A first terminal 101 and a second terminal 102 are provided on the surface of the semiconductor substrate 1. The first terminal 101 has a first potential, and the second terminal 102 has a second potential. The magnitudes of the first potential and the second potential are different; for example, the first potential is less than the second potential. For example, the first potential is a ground potential, and the second potential is a power supply potential. The transistor 2 is connected to the first terminal 101, the antifuse element 3 is connected between the transistor 2 and the second terminal 102, and the resistor element 4 is connected in parallel with the antifuse element 3 between the transistor 2 and the second terminal 102.

[0027] Specifically, the surface of the semiconductor substrate 1 is further provided with a first terminal wiring 103 and a second terminal wiring 104. The first terminal wiring 103 is connected to the first terminal 101, and the second terminal wiring 104 is connected to the second terminal 102. The transistor 2 is connected to the first terminal wiring 103, and the antifuse element 3 and the resistor element 4 are respectively connected to the second terminal wiring 104.

[0028] Data read and write working principle

[0029] Before data is written: A high voltage is applied to the gate of transistor 2 to make it conduct. Since the data is not written to the antifuse element 3, when a read current I (e.g., 1mA) is applied to the second terminal 102, if the resistance of resistor element 4 is R1, the voltage of the second terminal 102 is V1 = I*R1 (at this time, the on-resistance of transistor 2 is ignored. If it is considered, it can be added, but the overall impact is not significant).

[0030] Writing data: Apply a high voltage to the gate of transistor 2 to turn it on. Apply a high voltage (e.g., 32V) through the second terminal 102, and the anti-fuse element 3 will melt and turn on, with a low resistance R2.

[0031] After the data is written: apply a high voltage to the gate of transistor 2 to turn it on, and apply a read current I (e.g., 1mA) to the second terminal 102. Then the voltage V2 of the second terminal 102 is V2 = I*[(R1*R2) / (R1+R2)]. Since R2 is much smaller than R1, the voltage after the data is written will be reduced by a lot.

[0032] Inaccurate data can be caused by factors such as temperature and manufacturing process. Data reading accuracy can be improved by changing the wiring resistance to increase the voltage difference before and after data writing. However, existing methods of changing the wiring resistance occupy a large chip area, and the change in the wiring resistance difference is not significant, resulting in poor performance in improving data reading accuracy.

[0033] Reference Figure 3 and Figure 4 As shown, Figure 3 A cross-sectional view of the semiconductor device provided in the embodiments of this application. Figure 4 This is another cross-sectional view of the semiconductor device provided in the embodiments of this application. Specifically, Figure 3 for Figure 2 Sectional view of AA, Figure 4 for Figure 2 A cross-sectional view of BB. Transistor 2 includes a source 21, a drain 22, and a gate 23. The source 21 of transistor 2 is connected to the first terminal wiring 103. The drain 22 of transistor 2 is connected to one end of antifuse element 3 via the first wiring 5, and the drain 22 of transistor 2 is also connected to one end of resistor element 4 via the second wiring 6. The other end of antifuse element 3 is connected to the second terminal wiring 104 via the third wiring 7, and the other end of resistor element 4 is connected to the second terminal wiring 104 via the fourth wiring 8. Each wiring is connected to a terminal or device via a connecting portion 10.

[0034] Furthermore, the first wiring 5 and the third wiring 7 are both referred to as antifuse wirings, and the second wiring 6 and the fourth wiring 8 are both referred to as resistor wirings. At least one antifuse wiring is arranged in a first stacked structure, and / or, at least one resistor wiring and its corresponding antifuse wiring are arranged in a second stacked structure, and the sum of the resistances of the resistor wirings is greater than the sum of the resistances of the antifuse wirings. Specifically, the second wiring 6 corresponds to the first wiring 5, and the fourth wiring 8 corresponds to the third wiring 7.

[0035] In this embodiment, the resistor wiring and the corresponding antifuse wiring are arranged in a second stacked structure. This second stacked structure places the antifuse wiring and resistor wiring on different wiring layers, allowing the resistor wiring to have a larger area and be longer, thus increasing resistance. Specifically, the first wiring 5 and the second wiring 6 are stacked, and the wiring resistance of the second wiring 6 is greater than that of the first wiring 5. And / or, the third wiring 7 and the fourth wiring 8 are stacked, with the third wiring 7 and the first wiring 5 located on the same wiring layer, and the fourth wiring 8 and the second wiring 6 located on different wiring layers, with the wiring resistance of the fourth wiring 8 greater than that of the third wiring 7. Preferably, the wiring resistance of both resistor wirings is greater than the antifuse wiring resistance, thus significantly increasing the resistance difference.

[0036] In this embodiment, the first wiring 5 and the second wiring 6 are arranged in a vertical spatial distribution, as are the third wiring 7 and the fourth wiring 8. This allows for a larger wiring space for the second wiring 6 and the fourth wiring 8, increasing their wiring distance and thus improving their wiring resistance. Consequently, it increases the difference between the wiring resistance in the first wiring 5 and the second wiring 6, as well as the difference between the wiring resistance in the fourth wiring 8 and the third wiring 7, thereby improving data reading accuracy. Furthermore, the design structure of this embodiment allows for a more compact device structure, higher integration, smaller chip area, and a greater number of chips per wafer, resulting in lower costs.

[0037] In addition, in this embodiment, the first wiring 5 and the third wiring 7 are placed on the same wiring layer, so the same material can be used to make the first wiring 5 and the third wiring 7 at the same time, which simplifies the manufacturing process and makes the structure simpler and the wiring distance shortest. In this embodiment, the second wiring 6 and the fourth wiring 8 are placed on different wiring layers, so that the two resistor wirings have sufficient wiring area to increase the wiring length.

[0038] To prevent short circuits between the antifuse wiring and the resistor wiring, the semiconductor device also includes a second insulating layer. The second insulating layer is disposed between the antifuse wiring and the resistor wiring. By setting the second insulating layer, the antifuse wiring and the resistor wiring are isolated, thereby preventing short circuits between the antifuse wiring and the resistor wiring and ensuring the normal operation of the semiconductor device.

[0039] Specifically, the semiconductor substrate 1 has a first surface and a second surface disposed opposite to each other. The semiconductor device further includes a first insulating layer 9, which is disposed on the first surface of the semiconductor substrate 1. A first wiring 5 and a third wiring 7 are disposed on the side of the first insulating layer 9 facing away from the semiconductor substrate 1. A second insulating layer is disposed on the side of the first wiring 5 and the third wiring 7 facing away from the first insulating layer 9. A second wiring 6 and a fourth wiring 8 are disposed on the side of the second insulating layer facing away from the first wiring 5 and the third wiring 7. Thus, along the direction from the second surface of the semiconductor substrate 1 to the first surface, the device (transistor, antifuse element, resistor element), the first insulating layer 9, the antifuse wiring, the second insulating layer, and the resistor wiring are arranged sequentially. Because the higher the position of the semiconductor device, the longer the trace needs to be, this embodiment places the resistor wiring at the top, thereby increasing the resistance of the resistor wiring.

[0040] The first insulating layer 9 and the second insulating layer can be single-layer insulating layers made of one material or multiple insulating layers stacked together. Each insulating layer is made of a different material, and other wiring layers can be provided between each insulating layer.

[0041] In the scheme of increasing the difference between the wiring resistance in the first wiring 5 and the wiring resistance in the second wiring 6, the wiring resistance in the second wiring 6 can be increased not only by increasing the wiring length, but also by using different conductive materials, or by reducing the width and thickness of the wiring in the second wiring 6. In this embodiment, the wiring utilizes spatial area without occupying planar area, allowing for a more compact arrangement of devices, higher integration, smaller chip area, more chips per wafer, and lower cost. Gold has a conductivity of approximately 2.4 × 10⁻⁶. -8 μS / cm, the electrical conductivity of aluminum is approximately 2.83 × 10 μS / cm. -8 μS / cm, the conductivity of copper is approximately 1.75 × 10 μS / cm. -8 μS / cm, the conductivity of polycrystalline silicon is approximately 2×10 μS / cm. -2 μS / cm, a difference of 6 orders of magnitude. R=ρ×L / S, where R is the resistance value, ρ is the resistivity of the conductor, L is the length of the conductor, S is the cross-sectional area of ​​the conductor, and S is the product of the conduction width and thickness.

[0042] Furthermore, in the thickness extension direction of the semiconductor device, the projection of the second wiring 6 at least partially overlaps with the projection of the antifuse element 3, thereby allowing at least a portion of the wiring in the second wiring 6 to be located above the antifuse element 3. This increases the wiring distance while saving chip area, thus reducing the area occupied by the semiconductor substrate 1. In other words, long-distance wiring does not increase the chip area. Alternatively, the projection of the second wiring 6 can at least partially overlap with the projection of the resistor element 4 in the thickness extension direction of the semiconductor device, thereby allowing at least a portion of the wiring in the second wiring 6 to be located above the resistor element 4, similarly saving chip area. Or, in the thickness extension direction of the semiconductor device, the projection of the fourth wiring 8 at least partially overlaps with the projection of the antifuse element 3, thereby allowing at least a portion of the wiring in the fourth wiring 8 to be located above the antifuse element 3, thus saving the area occupied by the semiconductor substrate 1. Alternatively, the projection of the fourth wiring 8 can at least partially overlap with the projection of the resistor element 4, thereby allowing at least a portion of the wiring in the fourth wiring 8 to be located above the resistor element 4, similarly saving the area occupied by the semiconductor substrate 1.

[0043] In some embodiments, to increase the wiring resistance of the second wiring 6 and the fourth wiring 8, both the second wiring 6 and the fourth wiring 8 have a meandering wiring structure. The meandering wiring structure can be, for example, a sinusoidal, serpentine, square, triangular, or sawtooth waveform, or other wiring configurations with meandering lines. This embodiment, by setting the second wiring 6 and the fourth wiring 8 to a meandering wiring structure, can significantly increase the wiring distance of the second wiring 6 and the fourth wiring 8 while effectively utilizing space, thereby increasing the wiring resistance of the second wiring 6 and the fourth wiring 8.

[0044] In this embodiment, both the second wiring 6 and the fourth wiring 8 have a circuitous wiring structure. It can be understood that in other embodiments, only the second wiring 6 may have a circuitous wiring structure, or only the fourth wiring 8 may have a circuitous wiring structure.

[0045] To further reduce the area occupied by the semiconductor substrate 1, the antifuse element 3 and the resistor element 4 are arranged side by side on the surface of the semiconductor substrate 1, with the distance between the resistor element 4 and the antifuse element 3 being relatively close, rather than using an interleaved arrangement. This is because increasing the wiring resistance of the second wiring 6 does not require increasing the distance between the resistor element 4 and the transistor 2; rather, the resistance of the second wiring 6 can be increased by adjusting the material, length, and thickness of the wiring. Note that the side-by-side arrangement does not mean that the antifuse element 3 and the resistor element 4 are of equal length; it only means that their center distance can be relatively close.

[0046] Based on the above embodiments, this application also discloses another specific implementation method, referring to... Figure 5 and Figure 6 As shown, Figure 5 This is a top view of a semiconductor device provided in another embodiment of this application. Figure 6 A cross-sectional view of a semiconductor device provided in another embodiment of this application, specifically, Figure 6 for Figure 5 A cross-sectional view of CC. The difference between this embodiment and the previous embodiment is that in this embodiment, the first layered structure includes multiple interconnected wiring sub-layers, and adjacent wiring sub-layers are separated by a third insulating layer. This embodiment reduces the resistance of the antifuse wiring by making the antifuse wiring consist of multiple interconnected wiring sub-layers.

[0047] Specifically, the first wiring 5 includes multiple layers of first wiring sub-layers 51 connected in parallel, with a third insulating layer between adjacent layers of first wiring sub-layers 51. The third wiring 7 includes multiple layers of second wiring sub-layers 71 connected in parallel, with a third insulating layer between adjacent layers of second wiring sub-layers 71.

[0048] In this embodiment, by configuring the first wiring 5 as a first wiring sub-layer 51 comprising multiple interconnected layers, compared to using only a single wire, the wiring resistance of the first wiring 5 can be reduced by using multiple interconnected wires, thereby increasing the difference between the wiring resistance in the first wiring 5 and the wiring resistance in the second wiring 6, and further improving data reading accuracy. Similarly, by configuring the third wiring 7 as a second wiring sub-layer 71 comprising multiple interconnected layers, compared to using only a single wire, the wiring resistance of the third wiring 7 can be reduced by using multiple interconnected wires, thereby increasing the difference between the wiring resistance in the third wiring 7 and the wiring resistance in the fourth wiring 8, and further improving data reading accuracy.

[0049] This embodiment increases the number of wirings in the first wiring 5 and the third wiring 7 spatially without occupying additional area of ​​the semiconductor substrate 1. Moreover, it achieves the goal of increasing the difference between the wiring resistance of the first wiring 5 and the second wiring 6, as well as the difference between the wiring resistance of the third wiring 7 and the fourth wiring 8, without extending the wiring length of the second wiring 6 and the fourth wiring 8. This allows for more compact devices, higher integration, smaller chip area, more chips per wafer, and lower cost. In specific implementations, the number of first wiring sub-layers 51 and second wiring sub-layers 71 can be selected according to the actual application scenario, thereby reducing the total parallel resistance of multiple parallel wirings. For example, two, three, or more layers of first wiring sub-layers 51 or second wiring sub-layers 71 can be set.

[0050] To further reduce the wiring resistance of multiple parallel-connected first wiring sublayers 51 or second wiring sublayers 71, multiple connection portions 10 are provided between each layer of first wiring sublayers 51 or second wiring sublayers 71. These connection portions 10 are used to connect adjacent first wiring sublayers 51 or adjacent second wiring sublayers 71, thereby reducing the wiring resistance of the first wiring 5 or second wiring 6. Specifically, through-holes can be provided on each third insulating layer, with conductive material placed within the through-holes to connect the wiring in adjacent first wiring sublayers 51 or adjacent second wiring sublayers 71 in parallel. Different through-hole sizes can be selected for different first wiring sublayers 51 or second wiring sublayers 71, preferably larger through-hole sizes, to reduce the connection resistance of the wiring in the first wiring sublayers 51 or second wiring sublayers 71, thereby further reducing the wiring resistance of the first wiring 5 or second wiring sublayer 71 and improving data reading accuracy. It is possible to set only the first wiring 5 as the first stacked structure, or only the third wiring 7 as the first stacked structure. Preferably, both the first wiring 5 and the third wiring 7 are set as the first stacked structure, so that the sum of the resistance of the first wiring 5 and the resistance of the third wiring 7 is smaller, thereby increasing the sum of the antifuse wiring resistance and the resistor wiring resistance, and thus improving the data reading accuracy.

[0051] Furthermore, the multiple first wiring sub-layers 51 are stacked only in the space between the transistor 2 and the antifuse element 3, and the multiple second wiring sub-layers 71 are stacked only in the space between the antifuse element 3 and the second terminal, thereby effectively reducing or not increasing the wiring length in the first wiring 5 and the third wiring 7, minimizing the wiring resistance in the first wiring 5 and the third wiring 7, and reducing the additional occupation of chip area.

[0052] In this embodiment, the plurality of first wiring sublayers 51 are stacked only in the space between the transistor 2 and the antifuse element 3, and the plurality of second wiring sublayers 71 are stacked only in the space between the antifuse element 3 and the second terminal. It can be understood that in other embodiments, only the plurality of first wiring sublayers 51 may be stacked in the space between the transistor 2 and the antifuse element 3, or only the plurality of second wiring sublayers 71 may be stacked in the space between the antifuse element 3 and the second terminal.

[0053] In this embodiment, the number of wiring sub-layers included in the first wiring 5 is the same as the number of wiring sub-layers included in the third wiring 7. That is, the number of layers of the first wiring sub-layer 51 is the same as the number of layers of the second wiring sub-layer 71, and the positions of each first wiring sub-layer 51 and each second wiring sub-layer 71 are respectively set, so that the first wiring 5 and the third wiring 7 can be made of the same material at the same time, simplifying the manufacturing process. At the same time, the second wiring 6 is not on the same layer as any of the first wiring sub-layers 51 in the first wiring 5, and the fourth wiring 8 is not on the same layer as any of the second wiring sub-layers 71 in the third wiring 7. This allows the wiring in the second wiring 6 and the fourth wiring 8 to have more space, extend the wiring length in the second wiring 6 and the fourth wiring 8, and further improve the wiring resistance difference between the first wiring 5 and the second wiring 6, and between the third wiring 7 and the fourth wiring 8, without increasing the chip area. Of course, the second wiring 6 and the fourth wiring 8 can also be set on the same layer as any of the wiring sub-layers.

[0054] In another embodiment, the first and second stacked structures can be combined. For example, the first wiring 5 can use a first stacked structure and the second wiring 6 can use a second stacked structure; the third wiring 7 can use a first stacked structure and the fourth wiring 8 can use a second stacked structure; the first wiring 5 can use a first stacked structure and the fourth wiring 8 can use a second stacked structure; the third wiring 7 can use a first stacked structure and the second wiring 6 can use a second stacked structure; the first wiring 5 and the third wiring 7 can use a first stacked structure and the second wiring 6 and the fourth wiring 8 can use a second stacked structure, etc. Various combinations are possible, or only one structure of one wire can be selected. That is, at least one antifuse wiring uses a first stacked structure, or at least one resistor wiring uses a second stacked structure, or at least one antifuse element uses a first stacked structure and at least one resistor wiring uses a second stacked structure.

[0055] Additionally, it should be noted that the wiring layers in this specification and the corresponding figures are only examples and may be located at other layers. For example, the first terminal wiring 103 and the second terminal wiring 104 may be located at other layers, and each insulation layer may be one, two, three or more layers, etc.

[0056] Based on the above embodiments, this application also discloses a memory, which includes the semiconductor device described in any of the above embodiments.

[0057] Based on the above embodiments, referring to Figure 7As shown, this application also discloses a printhead 100, which includes a substrate 200 (e.g., a semiconductor substrate), an nozzle plate 300 (flow path layer and nozzle layer), a filter 400, a printing element 500, and a semiconductor device as described in any of the above embodiments. The nozzle plate 300 is connected to the substrate 200 and forms an ink chamber 201 and a liquid channel 202. The ink chamber 201 is connected to the ink supply port of the ink cartridge via the liquid channel 202, and the nozzle plate 300 is provided with nozzles 301. The filter 400 is disposed in the liquid channel 202, and the printing element 500 is disposed in the ink chamber 201, through which ink in the ink chamber 201 is ejected from the nozzles 301. The semiconductor device is used to store information related to the consumable cartridge.

[0058] During operation, the ink in the ink cartridge flows through the ink supply tank to the ink supply port, and then through the filter 400 and the liquid channel 202 to the ink chamber 201. When the printing element 500 (such as a heating resistor, piezoelectric element, etc.) is actuated under the control of a signal, the ink in the ink chamber 201 will be ejected from the nozzle 301 to form an image or text.

[0059] Based on the above embodiments, this application also discloses a consumable box, which includes a storage tank and a print head as described in the above embodiments. The storage tank is used to contain the liquid to be printed, and the print head is installed on a side wall (such as the bottom wall) of the storage tank. The inside of the storage tank is connected to the print head, so that the liquid stored in the storage tank can be supplied to the print head and then flow out through the ink supply channel on the print head.

[0060] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, include: A semiconductor substrate is provided with a first terminal and a second terminal; A transistor is disposed on the semiconductor substrate and connected to the first terminal; An antifuse element is disposed on the semiconductor substrate and connected between the transistor and the second terminal; A resistor element is disposed on the semiconductor substrate and connected in parallel with the antifuse element between the transistor and the second terminal; Wherein, the transistor is connected to one end of the antifuse element via a first wiring and to one end of the resistor element via a second wiring; the other end of the antifuse element is connected to the second terminal via a third wiring and the other end of the resistor element is connected to the second terminal via a fourth wiring. The first wiring and the third wiring are both referred to as antifuse wiring, and the second wiring and the fourth wiring are referred to as resistor wiring; At least one of the antifuse wires is arranged in a first stacked structure, and / or at least one of the resistor wires is arranged in a second stacked structure with the corresponding antifuse wire, wherein the sum of the resistances of the resistor wires is greater than the sum of the resistances of the antifuse wires.

2. The semiconductor device according to claim 1, wherein The first layered structure includes multiple wiring sub-layers connected in parallel, and adjacent wiring sub-layers are separated by an insulating layer.

3. The semiconductor device according to claim 2, wherein The wiring sublayer is stacked in the space between the transistor and the antifuse element, and / or the wiring sublayer is stacked in the space between the antifuse element and the second terminal.

4. The semiconductor device of claim 2, wherein Multiple connection points are provided between two adjacent wiring sub-layers.

5. The semiconductor device of claim 1, wherein The second layered structure is such that the antifuse wiring and the resistor wiring are on different wiring layers.

6. The semiconductor device of claim 5, wherein, At least one of the resistor wires has a meandering wiring structure.

7. The semiconductor device of claim 6, wherein In the thickness extension direction of the semiconductor substrate, the projection of at least one of the resistor wirings at least partially overlaps with the projection of the antifuse element, and / or, the projection of at least one of the resistor wirings at least partially overlaps with the projection of the resistor element.

8. The semiconductor device according to any one of claims 1 to 7, wherein The semiconductor substrate has a first surface and a second surface opposite to the first surface. A device, the antifuse wiring, and the resistor wiring are sequentially disposed along the direction from the second surface to the first surface. The device includes the transistor, the antifuse element, and the resistor element.

9. The semiconductor device according to any one of claims 1-7, characterized in that, The first wiring and the third wiring are on the same wiring layer, while the second wiring and the fourth wiring are on different wiring layers.

10. A memory, characterized in that, The memory includes the semiconductor device as described in any one of claims 1 to 9.

11. A printhead, characterized in that, The printhead includes a nozzle, an ink chamber, and a printing element, wherein the printing element is used to eject ink from the ink chamber from the nozzle, and the printhead further includes a semiconductor device as described in any one of claims 1 to 9.

12. A consumable box, characterized in that, The consumable box includes a semiconductor device as described in any one of claims 1 to 9.

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