Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and specifically discloses a display panel comprising: a plurality of signal lines, at least part of the plurality of signal lines, two signal lines extending side by side to form a signal line group; the minimum distance between adjacent signal line groups is greater than the maximum distance between two signal lines in the same signal line group, and / or at least one signal line group comprises a bending segment. The application reduces the capacitive interference between adjacent signal line groups, reduces the capacitive difference between signal lines, thereby ensuring the display effect of the display panel, and the use of the bending segment can also shorten the extension length of the signal line group and save wiring space.

Description

Technical Field

[0001] This invention belongs to the field of electronic product technology, and particularly relates to a display panel and display device. Background Technology

[0002] Currently, small-to-medium-sized panels in the LTPS (Low Temperature Poly-Silicon) field generally use 7T1C pixel circuits for internal threshold voltage compensation, which involves a large number of thin-film transistors, hindering the development towards higher PPI. Furthermore, for under-display applications, cameras with high light transmittance are required. Traditional 7T1C circuits have poor light transmittance, preventing the main and secondary screens from achieving homogeneous display. However, using external compensation methods can reduce the number of thin-film transistors within the panel, enabling high PPI and under-display applications.

[0003] However, due to the limitations of the existing external compensation circuit wiring method, the detected threshold voltage is inaccurate, causing problems with the display screen.

[0004] Therefore, there is an urgent need for a new display panel and display device. Summary of the Invention

[0005] This invention provides a display panel and display device that reduces capacitive interference between adjacent signal trace groups and decreases the capacitance difference between signal traces, thereby ensuring the display effect of the display panel.

[0006] In one aspect, the present invention provides multiple signal traces, wherein at least some of the multiple signal traces extend side by side to form a signal trace group; the minimum distance between adjacent signal trace groups is greater than the maximum distance between two signal traces within the same signal trace group; and / or, at least one group of signal traces includes a bend.

[0007] According to one aspect of the invention, the distance between two signal traces within the same signal trace group is equal everywhere.

[0008] According to one aspect of the invention, at least one group of said signal traces includes adjacent bends and straight sections, wherein the sum of the trace lengths of the bends and straight sections of each of the said signal traces is equal.

[0009] According to one aspect of the invention, at least one group of said signal traces has a serpentine routing configuration in which the bends are arranged.

[0010] According to one aspect of the invention, the minimum distance between the straight segments of two adjacent groups of signal traces is greater than the minimum distance between the bent segments of two adjacent groups of signal traces.

[0011] According to one aspect of the invention, the minimum distance between the straight segments of two adjacent groups of signal traces is greater than or equal to twice the width of a single straight segment; preferably, the minimum distance between the straight segments of two adjacent groups of signal traces is equal to three times the width of a single straight segment; preferably, the width of a single straight segment is 2 μm to 3 μm; preferably, the minimum distance between the straight segments of two adjacent groups of signal traces is 6 μm to 9 μm.

[0012] According to one aspect of the present invention, the display panel includes a fan-out area, the fan-out area including a central routing area and an edge routing area, the edge routing area being located on both sides of the central routing area perpendicular to the routing extension direction; in the central routing area, the routing length of the bent segment of each signal routing group is greater than the routing length of the straight segment; in the edge routing area, the routing length of the bent segment of each signal routing group is less than the routing length of the straight segment.

[0013] According to one aspect of the present invention, the panel further includes a substrate, a first metal layer, and a second metal layer stacked along the thickness direction of the display panel. The second metal layer includes a plurality of conductive blocks, and the signal traces are disposed in the same layer as the first metal layer. Along the thickness direction of the display panel, the orthographic projections of the conductive blocks on the substrate and the orthographic projections of the signal traces on the substrate at least partially overlap. In the overlapping area of ​​the orthographic projections of a single conductive block and the signal traces on the substrate, the trace lengths of each group of signal traces are equal.

[0014] According to one aspect of the invention, it further includes an external circuit and a pixel driving circuit, the external circuit and the pixel driving circuit being electrically connected; each of the signal traces is electrically connected to a different external circuit.

[0015] Another aspect of the present invention provides a display device, including: the display panel in any of the above embodiments.

[0016] Compared with the prior art, the display panel provided in this embodiment of the invention includes multiple signal traces. At least some of these signal traces have two signal traces extending side-by-side to form a signal trace group. Since all signal traces use the same material, i.e., have the same impedance, according to the capacitance calculation rules, the greater the distance, the smaller the capacitance. When the minimum distance between adjacent signal trace groups is set to be greater than the maximum distance between two signal traces within the same signal trace group, the capacitance between adjacent signal trace groups can be made smaller than the capacitance between two signal traces within the same signal trace group. This reduces capacitance interference between adjacent signal trace groups, minimizes capacitance differences between signal traces, and thus ensures the display effect of the display panel. Furthermore, when at least one signal trace group includes a bend, the overlap area between the two signal traces in the signal trace group can be increased. The capacitance generated by the bend is relatively increased, and the capacitance difference between each signal trace group can be adjusted by adjusting the trace length of the bend. Using a bend can also shorten the extension length of the signal trace group, saving wiring space. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 It is a circuit diagram of an external circuit;

[0019] Figure 2 This is a schematic diagram of the structure of a display panel provided in one embodiment of the present invention;

[0020] Figure 3 yes Figure 2 A partial enlarged view of one embodiment at point B;

[0021] Figure 4 This is a schematic diagram of the structure of the bent segment provided in one embodiment of the present invention;

[0022] Figure 5 yes Figure 2 A partial enlarged view of one embodiment at point C;

[0023] Figure 6 yes Figure 2 A partial enlarged view of another embodiment at point C;

[0024] Figure 7 yes Figure 6 A diagram of the membrane structure of one embodiment at DD.

[0025] In the attached image:

[0026] 1-Control chip; 2-Signal trace; 21-Bend section; 22-Straight section; 3-Conductive block; M1-First metal layer; M2-Second metal layer; A1-Middle trace area; A2-Edge trace area; Y-First direction; X-Second direction. Detailed Implementation

[0027] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the invention.

[0028] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0029] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0030] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0031] In related technologies, transistors made of low-temperature polycrystalline silicon or oxide will experience threshold voltage Vth drift during use. Factors such as illumination in oxide semiconductors and source / drain electrode voltage stress can cause threshold voltage drift, resulting in the current passing through the light-emitting element being inconsistent with the required current, and the display uniformity of the display panel cannot be met.

[0032] To solve the above problem, an external circuit can be used to compensate the threshold voltage of the driving transistor in the pixel driving circuit, such as... Figure 1 As shown, Figure 1 This is a circuit diagram of an external circuit. Each external circuit is connected to a different signal line (Date / Sense). During compensation, capacitor Cdata is first charged through the signal line Date / Sense to reach a voltage of VDD+Vth. Since VDD is constant, Vth can be measured. Finally, voltage compensation is applied to the driving transistors of the pixel driving circuit based on the measured Vth. The inventors discovered that, due to limitations in the wiring configuration of existing signal lines Date / Sense and the control chip, the capacitance differences between the various signal lines Date / Sense in the prior art are significant. This leads to variations in the VDD+Vth voltage reached by Cdata in different external circuits within the same charging time, resulting in inaccurate measured Vth values. Consequently, the voltage compensation values ​​for the driving transistors of each pixel driving circuit also differ significantly, causing display problems.

[0033] This invention provides a display panel and a display device, which will be described below in conjunction with the accompanying drawings. Figures 2 to 7 Various embodiments of the display panel and display device will be described.

[0034] Please see Figures 2 to 5 , Figure 2 This is a schematic diagram of the structure of a display panel provided in one embodiment of the present invention; Figure 3 yes Figure 2 A partial enlarged view of one embodiment at point B; Figure 4 This is a schematic diagram of the structure of the bent segment provided in one embodiment of the present invention; Figure 5 yes Figure 2 A partial enlarged view of one embodiment at point C.

[0035] An embodiment of the present invention provides a display panel including multiple signal traces 2. In at least some of the multiple signal traces 2, two signal traces 2 extend side by side to form a signal trace group; the minimum distance a between adjacent signal trace groups is greater than the maximum distance b between two signal traces 2 in the same signal trace group; and / or, at least one group of signal traces includes a bend 21.

[0036] The display panel provided in this embodiment of the invention includes signal traces 2. Two signal traces 2 extend side by side to form a signal trace group. Since all signal traces 2 use the same material, i.e., have the same impedance, according to the capacitance calculation rules, the greater the distance, the smaller the capacitance. When the minimum distance 'a' between adjacent signal trace groups is set to be greater than the maximum distance 'b' between two signal traces 2 within the same signal trace group, the capacitance between adjacent signal trace groups can be made smaller than the capacitance between two signal traces 2 within the same signal trace group, reducing capacitance interference between adjacent signal trace groups and decreasing capacitance differences between signal traces 2, thereby ensuring the display effect of the display panel. When at least one signal trace group includes a bend segment 21, the bend segment 21 can increase the overlap area between the two signal traces 2 in the signal trace group. The capacitance generated by the bend segment 21 is relatively increased. The capacitance difference between each signal trace group can be adjusted by adjusting the trace length of the bend segment 21. Furthermore, using the bend segment 21 can also shorten the extension length of the signal trace group, saving wiring space.

[0037] It should be noted that, in at least some of the multiple signal traces 2, two signal traces 2 extend side by side to form a signal trace group. That is, some signal traces 2 may not form a signal trace group, while others may form one. The signal trace group may or may not have bends.

[0038] In some embodiments of this application, the display panel includes a fan-out area, which includes a central routing area A1 and an edge routing area A2. The edge routing area A2 is located on both sides of the central routing area A1 perpendicular to the routing extension direction. The signal traces 2 located in the edge routing area A2 can all form signal trace groups or partially form signal trace groups. The minimum distance a between adjacent signal trace groups is made greater than the maximum distance b between two signal traces 2 in the same signal trace group to reduce capacitive interference between adjacent signal trace groups. Specifically, the selection can be based on the capacitance difference of the signal traces 2 located in the edge routing area A2.

[0039] The signal traces located in the middle routing area A1 can extend side by side to form signal trace groups, and at least one signal trace group includes a bend section 21. The bend section 21 can increase the capacitance between signal traces. The capacitance difference between each signal trace group can be adjusted by adjusting the length of the bend section 21. It can also shorten the extension length of the signal trace group in the middle routing area A1, saving wiring space.

[0040] In this embodiment, the setting method of the minimum distance 'a' between adjacent signal trace groups being greater than the maximum distance 'b' between two signal traces 2 within the same signal trace group, and the setting method of at least one signal trace group including a bend segment 21, can both be applied to the signal trace 2 simultaneously or individually. For example, signal traces 2 located at different positions can be used as long as the capacitance difference between the signal traces 2 can be reduced to ensure the display effect of the display panel. There are no special limitations.

[0041] Optionally, the display panel also includes a control chip 1, and each signal trace 2 is electrically connected to the control chip 1. The control chip 1 can provide signals to external circuits through the signal traces 2. The signal traces 2 can be fan-out lines of the control chip 1 corresponding to the external circuit. The control chip 1 can also provide signal control for the internal compensation circuit or pixel driving circuit of the display panel. That is, the signal traces 2 can also be fan-out lines of the internal compensation circuit or pixel driving circuit or other traces. The embodiments of this application are improvements on the wiring method of the signal traces 2, and there are no special limitations on the application scenarios of the signal traces 2.

[0042] In some optional embodiments, the distance between two signal traces 2 in the same signal trace group is equal everywhere. Since each signal trace 2 uses the same material, that is, the impedance is the same, by making the distance equal everywhere, the capacitance between two signal traces 2 in the same signal trace group can be equal everywhere, thereby improving the capacitance consistency of two signal traces 2 in the same signal trace group.

[0043] Please see Figure 3 and Figure 5 In some optional embodiments, the signal trace group includes connected bends 21 and straight sections 22, and the sum of the trace lengths of the bends 21 and straight sections 22 of each signal trace group is equal.

[0044] It is understandable that the sum of the lengths of the bends 21 and straight sections 22 in each signal trace group is equal, so as to ensure that each signal trace 2 in each signal trace group has the same impedance, and that the impedance will not be different due to the different proportions of the lengths of the bends 21 and straight sections 22 in each signal trace group. This makes it easier to adjust the capacitance of each signal trace group under the condition of the same impedance.

[0045] Specifically, the rules for calculating capacitance are as follows:

[0046] Capacitance C = k × S / d; where k is the dielectric constant of the medium between the traces, S is the area of ​​the two traces facing each other, and d is the distance between the two traces.

[0047] By bending the two signal traces 2 within the same signal trace group at least twice through the bend segment 21, the facing area S between the two signal traces 2 can be effectively increased, thereby increasing the capacitance C.

[0048] Optionally, the bends 21 of each signal trace group can be arranged in a serpentine pattern. The bends 21 formed by the bends are arranged relative to each other, which increases the facing area S between the two signal traces 2, thereby generating additional capacitance and increasing the capacitance generated by the bends 21.

[0049] In some alternative embodiments, the bent segment 21 extends along the first direction Y, such as... Figure 3 As shown, this allows for better utilization of the wiring space. Optionally, the bending segment 21 extends along the second direction X, where the second direction X intersects the first direction Y, as shown. Figure 4 As shown, the second direction X can be perpendicular to the first direction Y without any special restrictions.

[0050] A serpentine path can be formed by straight lines, where each straight line bends at a right angle, such as... Figure 2 As shown, the serpentine path can also be a curved segment, that is, the bending segment 21 can be formed by a curve that bends multiple times, without any special limitation.

[0051] In addition to the serpentine routing form mentioned above, the bending segment 21 of each signal routing group can also be a broken line segment formed by bending multiple straight lines, similar to a "Z" shaped routing or other irregular broken line segments. The number of bends and the bending angle of the broken line segment can be selected according to the required routing length of the bending segment 21.

[0052] In some optional embodiments, the minimum distance between the straight segments 22 of two adjacent signal trace groups is greater than the minimum distance between the bent segments 21 of two adjacent signal trace groups. That is, by increasing the distance d between the two traces, the capacitance of the signal trace group in the straight segment 22 is reduced, which facilitates the adjustment of the capacitance difference between each signal trace group. In this embodiment, optionally, the angle between the extension direction of the straight segment 22 and the first direction Y is an acute angle, that is, each straight segment 22 is distributed as an inclined line, so that each straight segment 22 converges towards the location of the control chip 1 and is electrically connected to the control chip 1.

[0053] In some optional embodiments, the display panel includes a fan-out area, which includes a central routing area A1 and an edge routing area A2. The edge routing area A2 is located on both sides of the central routing area A1 perpendicular to the routing extension direction. In the central routing area A1, the routing length of the bent section 21 of each signal routing group is greater than the routing length of the straight section 22. In the edge routing area A2, the routing length of the bent section 21 of each signal routing group is less than the routing length of the straight section 22.

[0054] It should be noted that, due to the limitation of the location of the control chip 1, the signal traces in the edge trace area A2 need to extend from both sides towards the middle to facilitate connection with the control chip 1. The signal traces in the middle trace area A1 have a relatively small tilt angle or extend vertically along the first direction Y. This is to ensure that the trace length of the signal traces in the middle trace area A1 is equal to the trace length of the signal traces in the edge trace area A2. In this embodiment, in the middle trace area A1, the trace length of the bent section 21 of each signal trace group is greater than or equal to the trace length of the straight section 22; this reduces the impedance difference caused by the trace lengths of the middle trace area A1 and the edge trace area A2, thereby reducing the capacitance difference between the middle trace area A1 and the edge trace area A2. Furthermore, the signal traces in the edge trace area A2 include bent sections 21, and the trace length of the bent section 21 of each signal trace group is less than the trace length of the straight section 22, to reduce the capacitance difference between the middle trace area A1 and the edge trace area A2.

[0055] Furthermore, typically in the middle routing area A1, the length of the bent section 21 of each signal routing group is greater than the length of the straight section 22; in the edge routing area A2, the length of the bent section 21 of each signal routing group is less than the length of the straight section 22. That is, in the middle routing area A1, the capacitance of the bent section 21 has a major influence, while in the edge routing area A2, the capacitance of the straight section 22 has a major influence. In the prior art, since the middle routing area A1 uses a single trace to form a serpentine trace to reduce the length of the trace in its extension direction, this structure does not generate additional capacitance in the bent section 21, resulting in the capacitance of the traces in the middle routing area A1 being less than the capacitance of the traces in the edge routing area A2, causing a capacitance difference.

[0056] To reduce the capacitance difference between the middle routing area A1 and the edge routing area A2, this embodiment of the invention extends two signal traces 2 side-by-side to form a signal trace group. The signal trace group includes a bend section 21 to generate additional capacitance, thereby increasing the capacitance of the middle routing area A1. Specifically, since all signal traces 2 use the same material, i.e., all signal traces 2 have the same unit impedance, and the sum of the routing lengths of the bend section 21 and the straight section 22 of each signal trace 2 is equal, according to the capacitance calculation rule: capacitance C = k × S / d, by setting the bend section 21 as a serpentine routing pattern, the overlap area between the two signal traces 2 in the bend section 21 can be increased, thereby increasing the capacitance of the bend section 21 and saving routing space.

[0057] At the same time, the capacitance of the signal trace group in the straight segment 22 can be reduced by increasing the minimum distance between the straight segments 22 of two adjacent signal trace groups, that is, by increasing the distance d between the two traces. By combining the method of increasing the capacitance of the bending segment 21 and the method of reducing the capacitance of the straight segment 22, the capacitance difference between the signal trace groups in the middle trace area A1 and the edge trace area A2 can be reduced.

[0058] Optionally, the display panel also includes external circuitry and pixel driving circuitry, which are electrically connected; each signal trace 2 is electrically connected to a different external circuitry.

[0059] When the above wiring method is applied to the external circuit, the capacitance difference between each signal trace 2 is reduced. When capacitor Cdata is charged through each signal trace 2, the difference in the VDD+Vth voltage value reached by capacitor Cdata in different external circuits is reduced within the same charging time, which improves the accuracy of the measured Vth value. The difference in the voltage compensation value of each external circuit for the driving transistor of each pixel driving circuit is also reduced, thereby improving the display effect of the display panel.

[0060] According to the inventor's experiments, when using the existing signal trace 2 wiring method, the capacitance range between each signal trace 2 is 25pF to 35pF. When the charging time is 1ms, the voltage range of Cdata is 1.709V to 1.870V, and the measured difference of Vth is -100mV to 100mV. When the charging time is 18ms, the voltage range of Cdata is 2.764V to 2.846V, and the measured difference of Vth is -50mV to 50mV.

[0061] In this embodiment of the invention, the capacitance range between each signal trace 2 is 28.5pf to 31.5pf. When the charging time is 1ms, the voltage range of Cdata is 1.762V to 1.810V, and the measured difference of Vth is -25mV to 25mV. When the charging time is 18ms, the voltage range of Cdata is 2.788V to 2.813V, and the measured difference of Vth is -15mV to 15mV.

[0062] By comparing the above data, it can be seen that the signal trace 2 in the embodiment of the present invention can effectively reduce the capacitance range between each signal trace 2. Moreover, whether the charging time is 1ms or 18ms, compared with the prior art, the voltage range of Cdata and the measured difference range of Vth in the embodiment of the present invention are significantly reduced, which improves the accuracy of the voltage compensation value of each external circuit to the driving transistor of each pixel driving circuit, thereby improving the display effect of the display panel.

[0063] Optionally, the minimum distance between the straight segments 22 of two adjacent signal trace groups is greater than or equal to twice the width of a single straight segment 22, to ensure that the capacitance value between the straight segments 22 of two adjacent signal trace groups is significantly reduced, thus meeting the requirement of balancing the capacitance difference between signal trace groups located in the middle trace area A1 and the edge trace area A2. In this embodiment, specifically, when the minimum distance between two signal traces 2 in the same signal trace group is equal to the width of a single signal trace 2, the minimum distance between the straight segments 22 of two adjacent signal trace groups can be equal to three times the width of a single straight segment 22, that is, reserving space for one signal trace 2 between the straight segments 22 of two adjacent signal trace groups for easy configuration.

[0064] Optionally, the width of a single straight segment 22 is 2μm to 3μm, and the minimum distance between straight segments 22 of two adjacent signal trace groups is 6μm to 9μm. The capacitance can be adjusted by changing the minimum distance between straight segments 22 of two adjacent signal trace groups. Of course, the width of a single straight segment 22 and the minimum distance between straight segments 22 of two adjacent signal trace groups are not limited to the above values ​​and can be selected according to the need to reduce the capacitance difference of the signal traces 2.

[0065] It should be noted that, in addition to the capacitance that can be generated between each signal trace 2, capacitance can also be generated between signal trace 2 and other conductive layers of the adjacent display panel.

[0066] Please see Figure 6 and Figure 7 , Figure 6 yes Figure 2 A partial enlarged view of another embodiment at point C; Figure 7 yes Figure 6 The diagram shows a film layer structure of one embodiment. The display panel also includes a substrate, a first metal layer M1, and a second metal layer M2 stacked along the thickness direction of the display panel. The second metal layer M2 includes a plurality of conductive blocks 3. The signal traces 2 are disposed in the same layer as the first metal layer M1. Along the thickness direction of the display panel, the orthographic projections of the conductive blocks 3 on the substrate and the orthographic projections of the signal traces 2 on the substrate at least partially overlap. In the overlapping area of ​​the orthographic projections of a single conductive block 3 and the signal trace 2 on the substrate, the trace lengths of each signal trace group are equal.

[0067] It should be noted that since each signal trace 2 and the first metal layer M1 are disposed on the same layer; that is, the vertical distance between each signal trace 2 and the second metal layer M2 is equal, and the trace width and unit impedance between each signal trace 2 are equal, the parameter affecting the capacitance between each signal trace 2 and the conductive block 3 of the second metal layer M2 is only the length of the overlapping portion of the signal trace 2 and the individual conductive block 3. In this embodiment, by limiting the trace length of each signal trace group to be equal in the overlapping area of ​​the orthographic projection of the individual conductive block 3 and the signal trace 2 on the substrate along the thickness direction of the display panel, the front-facing capacitance of each signal trace group and the conductive block 3 is ensured to be equal, thereby reducing the capacitance difference between each signal trace group and the conductive block 3 along the thickness direction of the display panel. Optionally, the shape of each conductive block 3 can be a triangle, trapezoid, or other polygonal shape, or an ellipse, circle, or other shape including curved edges. The second metal layer M2 can specifically be a trace layer for VDD positive voltage traces and VSS negative voltage traces.

[0068] This invention also provides a display device, including: the display panel in any of the above embodiments.

[0069] The display device provided in this embodiment of the invention can be applied to mobile phones or any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This embodiment of the invention does not impose any special limitations on these.

[0070] The above are merely specific embodiments of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

[0071] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

Claims

1. A display panel, characterized in that, include: Multiple signal traces, at least some of which include two signal traces extending side by side to form a signal trace group; The minimum distance between adjacent signal trace groups is greater than the maximum distance between two signal traces within the same signal trace group; at least one signal trace group includes adjacent bends and straight sections, the sum of the trace lengths of the bends and straight sections of each signal trace group is equal, the bends of two signal traces within the same signal trace group are bent at least twice, and the different bends formed by the bends of different signal traces within the same signal trace group are arranged relative to each other.

2. The display panel according to claim 1, characterized in that, The distance between two signal traces within the same signal trace group is always equal.

3. The display panel according to claim 1, characterized in that, At least one group of the signal traces has a serpentine routing configuration for its bends.

4. The display panel according to claim 1, characterized in that, The minimum distance between the straight segments of two adjacent signal trace groups is greater than the minimum distance between the bent segments of two adjacent signal trace groups.

5. The display panel according to claim 1, characterized in that, The minimum distance between the straight segments of two adjacent signal trace groups is greater than or equal to twice the width of a single straight segment.

6. The display panel according to claim 5, characterized in that, The minimum distance between the straight segments of two adjacent signal trace groups is equal to three times the width of a single straight segment.

7. The display panel according to claim 1, characterized in that, The width of a single straight line segment is 2μm to 3μm.

8. The display panel according to claim 1, characterized in that, The minimum distance between the straight segments of the two adjacent signal trace groups is 6μm to 9μm.

9. The display panel according to claim 3, characterized in that, The display panel includes a fan-out area, which includes a central trace area and an edge trace area. The edge trace area is located on both sides of the central trace area perpendicular to the trace extension direction. In the intermediate routing area, the routing length of the bent section of each signal routing group is greater than or equal to the routing length of the straight section; In the edge routing area, the routing length of the bent segment of each signal routing group is less than the routing length of the straight segment.

10. The display panel according to claim 1, characterized in that, It also includes a substrate, a first metal layer and a second metal layer stacked along the thickness direction of the display panel, the second metal layer including a plurality of conductive blocks, and the signal traces and the first metal layer being disposed on the same layer; Along the thickness direction of the display panel, the orthographic projection of the conductive block on the substrate and the orthographic projection of the signal trace on the substrate at least partially overlap, and in the overlapping area of ​​the orthographic projections of a single conductive block and the signal trace on the substrate, the trace lengths of each signal trace group are equal.

11. The display panel according to claim 1, characterized in that, It also includes an external circuit and a pixel driving circuit, wherein the external circuit and the pixel driving circuit are electrically connected; Each of the aforementioned signal traces is electrically connected to a different external circuit.

12. A display device, characterized in that, include: The display panel according to any one of claims 1 to 11.

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