Compound drain power transistor

Abstract

The present invention discloses a composite drain power transistor and its manufacturing method, which mainly solves the problems of high turn-on voltage drop and limited bidirectional blocking capability of traditional devices. The composite drain power transistor comprises: a substrate, a transition layer, a barrier layer, and a passivation layer. The left and right sides of the passivation layer are respectively a source and an ohmic electrode. The left side of the ohmic electrode is provided with M anode blocks, N Schottky electrodes, and K P-type array blocks from right to left. The upper sides of the ohmic electrodes, P-type array blocks, Schottky electrodes, and anode blocks are interconnected metal. A window is opened in the passivation layer between the source and the P-type array block. A P-type block, an i-GaN block, and a gate are provided in sequence inside the passivation layer. The source, gate, ohmic electrode, Schottky electrode, and anode block form a HEMT structure. The barrier layer and passivation layer in contact with the Schottky electrode and anode block form a diode structure. The present invention reduces the turn-on voltage drop and reverse leakage current, improves the bidirectional blocking capability, and can be used in power electronic systems.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to a power transistor which can be used as a basic device of a power electronic system. Technical Background

[0002] In applications such as wireless charging, aerospace, and radio frequency, devices are often required to have bidirectional blocking properties to maintain high power conversion efficiency and improve device reliability. Thanks to the superior material properties of GaN, such as high breakdown field strength, good thermal properties, and high electron mobility, GaN-based enhancement-mode high electron mobility transistors have attracted great attention from researchers in high-power and high-frequency applications. However, traditional GaN-based enhancement-mode high electron mobility transistors can often only achieve unidirectional blocking, that is, the drain voltage can only be higher than the source voltage, and forward blocking is achieved by turning off the gate, which severely limits the application of such devices.

[0003] The main part of the traditional gallium nitride-based power switching device is a gallium nitride-based heterojunction structure, which includes: a substrate, a transition layer, a channel layer, a barrier layer, a P-GaN block, a drain, a source, and a gate; a drain is deposited on the left side of the upper barrier layer, a source is deposited on the right side of the upper barrier layer, a P-GaN block is deposited in the middle part of the upper barrier layer, and a gate is deposited on the upper part of the P-GaN block. Using the traditional structure to form a bidirectional blocking device, only an external Schottky diode can be connected in series, which will bring about a large parasitic effect, increase power consumption, and occupy a large area, making it difficult to achieve monolithic integration. In order to improve the problems existing in the above-mentioned traditional structure, the Ferdinand Braun Institute in Germany first proposed a groove SBD drain structure in 2009. The groove SBD drain structure is embedded in the traditional enhancement-mode high electron mobility transistor, that is, Figure 1 The existing gallium nitride-based power switching device shown in the figure consists of a substrate, a transition layer, a barrier layer, and a gate. An ohmic contact is located on the left side of the upper barrier layer, with a source electrode located above it. A Schottky contact is located on the right side of the barrier layer and the transition layer, with a drain electrode located above it. The entire upper portion of the device, except for the source, gate, and drain, is covered with a passivation layer. This device's fabrication process is compatible with conventional GaN-based HEMT device processes and can achieve bidirectional blocking. However, this device structure suffers from high forward turn-on voltage drop, low forward output current, high reverse leakage current, and limited bidirectional blocking capability. Summary of the Invention

[0004] The purpose of the present invention is to provide a composite drain power transistor to solve the problems of high forward turn-on voltage drop, low forward output current, large reverse leakage current and limited bidirectional blocking capability in the prior art, thereby reducing power consumption and improving monolithic integration.

[0005] To achieve the above object, the technical solution of the present invention is implemented as follows:

[0006] 1. Device Structure

[0007] A composite drain power transistor comprises, from bottom to top, a substrate 1, a transition layer 2, a barrier layer 3, and a passivation layer 4, characterized in that:

[0008] A source groove 5 is provided on the left side of the passivation layer 4 on the barrier layer 3, and a source electrode 7 is provided inside the source groove;

[0009] An ohmic groove 6 is provided on the rightmost side of the passivation layer 4, and an ohmic electrode 8 is provided inside the groove, the bottom of which contacts the upper surface of the barrier layer 3;

[0010] On the left side of the ohmic electrode 8, M anode blocks 14, N Schottky electrodes 13, and K P-type array blocks 10 are sequentially provided from right to left. The lower parts of the anode blocks 14 and the Schottky electrodes 13 are located in the transition layer 2, and the lower surface of the P-type array block 10 contacts the upper surface of the barrier layer 3.

[0011] The upper surfaces of the ohmic electrode 8, the P-type array block 10, the Schottky electrode 13 and the anode block 14 are provided with an interconnection metal 15 for connecting the ohmic electrode 8, the P-type array block 10, the Schottky electrode 13 and the anode block 14 to maintain the equipotential of these parts;

[0012] A window 16 is opened inside the passivation layer 4 between the source 7 and the P-type array block 10, and inside the window 16 are arranged a P-type block 17, an i-GaN block 18, and a gate 19 in order from bottom to top;

[0013] The source electrode 7, the gate electrode 19, the ohmic electrode 8, the Schottky electrode 13 and the anode block 14 on the right side form a HEMT structure. A diode structure is formed between the Schottky electrode 13 and the anode block 14 and the barrier layer 3 and the passivation layer 4 in contact with them. The HEMT and the diode are combined to form a power switching device.

[0014] Furthermore, the thickness a of the barrier layer 3 is 3-100 nm.

[0015] Furthermore, the passivation layer 4 is made of any one of SiO2, SiN, Al2O3, Sc2O3, HfO2, and TiO2, and its thickness b is 20 nm to 1000 nm.

[0016] Furthermore, the source electrode 7 and the ohmic electrode 8 both form ohmic contacts with the barrier layer 3 , and the Schottky electrode 13 and the anode block 14 both form Schottky contacts with the barrier layer 3 .

[0017] Furthermore, the K P-type array blocks 10 are distributed at equal intervals front and back, and the distance g between two adjacent array blocks is greater than 0; the lateral distance d between each P-type array block 10 and the Schottky electrode 13 is greater than 0.

[0018] Furthermore, the N Schottky electrodes 13 are distributed at equal intervals front and back, and the spacing h between two adjacent electrodes is greater than 0. These Schottky electrodes 13 and the K P-type array blocks 10 are staggered, N≥1, K≥2; the lateral spacing e between the Schottky electrode 13 and the anode block 14 is greater than 0.

[0019] Furthermore, the M anode blocks 14 are distributed at equal intervals front and back, and the longitudinal spacing i between two adjacent anode blocks is greater than 0. When the device is in a balanced state, a depletion region is generated between the anode blocks 14, and the current path is pinched off by the depletion region, M≥2; the lateral spacing f between each anode block 14 and the ohmic electrode 8 is greater than 0; the height c of each anode block 14 is the same as that of each Schottky electrode 13, c>a+b, where a is the thickness of the barrier layer 3, and b is the thickness of the passivation layer 4.

[0020] 2. Production Method

[0021] A method for manufacturing a composite drain power transistor of the present invention is characterized by comprising the following steps:

[0022] A) epitaxially growing GaN semiconductor material on substrate 1 to form a transition layer 2;

[0023] B) epitaxially growing a GaN-based wide bandgap semiconductor material on the transition layer 2 to form a barrier layer 3;

[0024] C) depositing a dielectric on the barrier layer 3 to form a passivation layer 4;

[0025] D) forming a mask on the passivation layer 4 for the first time, and using the mask to simultaneously etch the left and right sides of the passivation layer 4 until the upper surface of the barrier layer 3 is reached, thereby forming the source trench 5 and the ohmic recess 6;

[0026] E) forming a mask for the second time on the passivation layer 4, the source trench 5, and the ohmic groove 6, using the mask to deposit metal above the source trench 5 and the ohmic groove 6, and performing rapid thermal annealing to form the source electrode 7 and the ohmic electrode 8;

[0027] F) A mask is formed on the passivation layer 4, the source electrode 7, and the ohmic electrode 8 for the third time, and the mask is used to etch the passivation layer 4 at a position slightly to the right of the middle, until the upper surface of the barrier layer 3 is reached, forming K P-type array block grooves 9 arranged in a front and back manner with equal spacing;

[0028] G) forming a mask for the fourth time on the passivation layer 4, the source electrode 7, the ohmic electrode 8, and the P-type array block groove 9, and using the mask to deposit a P-type material inside the P-type array block groove 9 to form K P-type array blocks 10;

[0029] H) forming a mask for the fifth time on the passivation layer 4, the source electrode 7, the ohmic electrode 8, and the P-type array block 10, and using the mask to etch on the right side of the P-type array block 10 until it reaches the interior of the transition layer 2, thereby forming N Schottky grooves 11 and M anode grooves 12;

[0030] 1) forming a mask for the sixth time on the passivation layer 4, the source electrode 7, the ohmic electrode 8, the P-type array block 10, the Schottky groove 11, and the anode groove 12, and using the mask to deposit metal over the ohmic electrode 8, the Schottky groove 11, the anode groove 12, and the P-type array block 10 to form N Schottky electrodes 13, M anode blocks 14, and interconnect metal 15;

[0031] J) forming a mask for the seventh time on the passivation layer 4, the source electrode 7, and the interconnect metal 15, and using the mask to etch the passivation layer 4 between the source electrode 7 and the P-type array block 10 until the upper surface of the barrier layer 3 is reached, thereby forming a window 16;

[0032] K) A mask is formed for the eighth time on the passivation layer 4, the source electrode 7, the interconnect metal 15 and the window 16. The mask is used to deposit a 10 nm to 500 nm thick dopant with a doping concentration of 5×10 15 cm -3 ~1×10 22 cm -3 P-type block 17;

[0033] L) using the eighth mask, epitaxially growing an i-GaN block 18 with a thickness of 10 nm to 500 nm on the upper portion of the P-type block 17;

[0034] M) A ninth mask is made on the passivation layer 4, source electrode 7, interconnect metal 15 and i-GaN block 18. The mask is used to deposit metal on the upper portion of the i-GaN block 18 to form a gate 19, completing the fabrication of the entire device.

[0035] Compared with existing gallium nitride-based power switching devices, the device of the present invention has the following advantages:

[0036] First, the device has strong bidirectional blocking capability and good reliability.

[0037] The present invention can achieve excellent forward and reverse blocking characteristics due to the introduction of the P-type array block 10, Schottky electrode 13 and anode block 14 at the right end of the device. Specifically:

[0038] When a low level is applied to the source 7 and a high level is applied to the Schottky electrode 13 and the anode block 14, the diode on the right is in a forward biased state. At this time, the gate applies zero potential, thereby preventing the connection of the two-dimensional electron gas between the transition layer and the barrier layer, that is, no channel for the HEMT to conduct is formed, so that the device cannot be turned on, achieving forward blocking. Moreover, when the depletion region formed by the semiconductor layer below the gate adheres to the P-type array block 10, the depletion region formed by the semiconductor layer below the P-type array block 10 will continue to expand toward the Schottky electrode 13 and the anode block 14. Therefore, a higher voltage can be applied to the Schottky electrode 13 and the anode block 14, and the forward blocking capability of the device is significantly enhanced.

[0039] When a high level is applied to the source 7 and a low level is applied to the Schottky electrode 13 and the anode block 14, regardless of whether the gate is at zero potential, the entire device is in the off state because the diode on the right cannot conduct forward, thereby achieving reverse blocking. Moreover, since the depletion region of the semiconductor layer at the bottom of the P-type array block 10 is adhered to the depletion region of the semiconductor layer around the Schottky electrode 13 and the anode block 14 at this time, a higher voltage can be applied to the source 7, and the reverse blocking capability of the device is significantly enhanced.

[0040] Second, reduce the turn-on voltage and increase the output current.

[0041] Since the device of the present invention adopts the Schottky electrode 13 and the anode block 14, when the device is in the on state, carriers can flow in from the edges of the Schottky electrode 13 and the anode block 14, thereby increasing the contact area between the anode and the current of the Schottky barrier diode, thereby significantly reducing the turn-on voltage and increasing the conduction current; in addition, since the ohmic electrode 8 is provided on the right side of the passivation layer and is connected to the Schottky electrode 13 and the anode block 14 through the interconnection metal 15, the ultra-low voltage turn-on of the ohmic contact reduces the voltage drop at the anode end of the Schottky diode device in the on state, so that the turn-on voltage of the device is greatly reduced.

[0042] Third, reduce reverse leakage current.

[0043] Since the device of the present invention adopts the P-type array block 10, when the device is in the reverse off state, the depletion region generated by the P-type array block 10 can pinch off the channel and reduce the reverse leakage current of the device.

[0044] Fourth, increase the threshold voltage and enhance device reliability.

[0045] Since the present invention adds an i-GaN block 18 to the P-type block 17, the threshold voltage of the device is regulated. The original high threshold voltage no longer requires a higher P-type block 17 concentration and a lower work function contact metal. Since the i-GaN block 18 is added, the gate 19 can directly contact the i-GaN block 18, increasing the contact barrier height and width, thereby increasing the gate voltage shared by the barrier region and reducing the requirements for the gate metal work function. That is, the gate only needs ordinary metal, thereby improving the threshold voltage of the device and enhancing the reliability of the device.

[0046] Fifth, achieve monolithic integration and reduce system size.

[0047] In the device of the present invention, the Schottky electrode 13, anode block 14, and ohmic electrode are connected to the same potential via metal interconnect 15. These three components serve as both the drain of the HEMT structure and the anode of the diode structure, achieving interconnection through reuse. Compared to traditional external metal interconnects, this invention saves chip area and improves integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a structural diagram of an existing device;

[0049] Figure 2 is a top view of a composite drain power transistor of the present invention;

[0050] Figure 3 yes Figure 2 Sectional view along line AB;

[0051] Figure 4 yes Figure 2 Cross-sectional view along line CD;

[0052] Figure 5 It is a flowchart of the overall process of preparing the composite drain power transistor of the present invention;

[0053] Figure 6 It is a result diagram of the output characteristic and blocking characteristic simulation of the present invention. DETAILED DESCRIPTION

[0054] The embodiments and effects of the present invention are further described in detail below with reference to the accompanying drawings.

[0055] Reference Figure 2 、 Figure 3 、 Figure 4The composite drain power transistor provided in this embodiment includes: a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a source groove 5, an ohmic groove 6, a source electrode 7, an ohmic electrode 8, a P-type array block groove 9, a P-type array block 10, a Schottky groove 11, an anode groove 12, a Schottky electrode 13, an anode block 14, an interconnect metal 15, a window 16, a P-type block 17, an i-GaN block 18, and a gate 19. Among them:

[0056] The substrate 1 is made of silicon carbide, silicon or sapphire;

[0057] The transition layer 2 is located on the upper part of the substrate 1 and has a doping concentration of 1×10 15 ~1×10 18 cm -3 , thickness of 5 to 100 μm;

[0058] The barrier layer 3 is located on the upper part of the transition layer 2 and is composed of several layers of the same or different GaN-based wide bandgap semiconductor materials, with a thickness a of 3nm to 100nm and an Al composition of 0.1 to 0.4;

[0059] The passivation layer 4 is located on the upper portion of the barrier layer 3 and is made of any one of SiO2, SiN, Al2O3, Sc2O3, HfO2, TiO2 or other insulating dielectric materials, with a thickness b of 20nm to 1000nm;

[0060] The source trench 5 is located on the left side of the passivation layer 4, and its lower surface is in contact with the barrier layer 3;

[0061] The ohmic groove 6 is located on the right side of the passivation layer 4, and its lower surface is in contact with the barrier layer 3;

[0062] The source electrode 7 is located inside the source groove 5, and the source electrode 7 forms an ohmic contact with the barrier layer 3;

[0063] The ohmic electrode 8 is located inside the ohmic groove 6 , and the ohmic electrode 8 forms an ohmic contact with the barrier layer 3 ;

[0064] The P-type array block groove 9 is located in the middle and right side of the passivation layer 4, and its lower surface is in contact with the barrier layer 3;

[0065] There are K P-type array blocks 10, which are evenly spaced front and back and all located inside the P-type array block groove 9. The lower surface of the P-type array block 10 contacts the upper surface of the barrier layer 3. The distance g between two adjacent array blocks is greater than 0, and K ≥ 2.

[0066] The Schottky groove 11 is located inside the passivation layer 4, the barrier layer 3 and the transition layer 2 on the right side of the P-type array block groove 9, and its depth is c;

[0067] The anode groove 12 is located inside the passivation layer 4, the barrier layer 3 and the transition layer 2 on the right side of the Schottky groove 11, and its depth is c;

[0068] There are N Schottky electrodes 13, which are distributed frontally and rearwardly at equal intervals and are all located inside the Schottky groove 11. The N Schottky electrodes 13 and the K P-type array blocks 10 are staggered, and the lateral spacing d between the P-type array block 10 and the Schottky electrode 13 is greater than 0; the spacing h between two adjacent electrodes is greater than 0, and the height c of each Schottky electrode 13 is the same, c>a+b, where a is the thickness of the barrier layer 3, b is the thickness of the passivation layer 4, and a Schottky contact is formed between the Schottky electrode 13 and the barrier layer 3 in contact, and N≥1;

[0069] There are M anode blocks 14, which are evenly spaced front and back and located inside the anode tank 12. The height of each anode block 14 is c, and the longitudinal spacing i between two adjacent anode blocks is greater than 0. When the device is in equilibrium, a depletion region is generated between the anode blocks 14, and the current path is pinched off by the depletion region. The lateral spacing e between the anode block 14 and the Schottky electrode 13 is greater than 0, and the lateral spacing f between the anode block 14 and the ohmic electrode 8 is greater than 0. A Schottky contact is formed between the anode block 14 and the contacted barrier layer 3, wherein M ≥ 2;

[0070] The interconnection metal 15 is located on the upper surfaces of the ohmic electrode 8, the P-type array block 10, the Schottky electrode 13 and the anode block 14;

[0071] The window 16 is located inside the passivation layer 4 between the source 7 and the P-type array block 10, and its lower surface is in contact with the barrier layer 3;

[0072] The P-type block 17 is located inside the window 16 and is made of P-GaN, CuO or NiO material with a thickness of 10 nm to 500 nm and a doping concentration of 5×10 15 cm -3 ~1×10 22 cm -3 ;

[0073] The i-GaN block 18 is located inside the window 16 and on top of the P-type block 17, and has a thickness of 10 nm to 500 nm;

[0074] The gate 19 is located on the upper portion of the i-GaN block 18 , has a length smaller than that of the i-GaN block 18 , and forms a Schottky contact with the i-GaN block 18 ;

[0075] The source 7, gate 19, ohmic electrode 8, Schottky electrode 13 and anode block 14 on the right side form a HEMT structure. A diode structure is formed between the barrier layer 3 and passivation layer 4 in contact with the Schottky electrode 13 and anode block 14. The HEMT and diode are combined to form a power switching device.

[0076] Reference Figure 5 The present invention provides a method for preparing a composite drain power transistor, and provides the following three embodiments.

[0077] Example 1: A barrier layer 3 with a thickness a of 60 nm is fabricated on a silicon substrate. The passivation layer 4 is made of Al2O3 material with a thickness b of 320 nm. K=6, N=5, M=6, the Schottky electrode 13 and the anode block 14 have a height c of 480 nm, and the P-type array block 10 and the P-type block 17 are both made of CuO material to form a composite drain power transistor.

[0078] Step A: forming a transition layer 2 on the silicon substrate 1 by epitaxial growth.

[0079] The process conditions are set to 960℃, 45Torr, SiH4 as doping source, 4200sccm hydrogen flow rate, 4200sccm ammonia flow rate, and 110μmol / min gallium source flow rate. On silicon substrate 1, a metal organic chemical vapor deposition technique is used to deposit an epitaxial layer with a thickness of 5.2μm and a doping concentration of 8×10 19 cm -3 n - Type GaN transition layer 2.

[0080] Step B. Epitaxial Al growth on transition layer 2 0.25 Ga 0.75 N, forming barrier layer 3.

[0081] Set the vacuum degree to be less than or equal to 1.0×10 -10 mbar, RF power of 420W, the reactants used N2, high-purity Ga source, high-purity Al source process conditions, using molecular beam epitaxy technology, epitaxial thickness of 60nm Al on the GaN transition layer 2 0.25 Ga 0.75 N material, forming the barrier layer 3.

[0082] Step C: Al2O3 material is deposited on the barrier layer 3 to form a passivation layer 4.

[0083] The reaction temperature is set to 300°C, the reaction sources are trimethylaluminum (TMA) and deionized water, the reaction chamber pressure is 5 Torr, and a single reaction cycle includes 1.5 s of trimethylaluminum gas introduction, 3 s of nitrogen purge, 1 s of deionized water vapor introduction, and 3 s of nitrogen purge. Using atomic layer deposition technology, Al2O3 material with a thickness of 320 nm is deposited on top of the barrier layer 3 to form a passivation layer 4.

[0084] Step D: Fabricate the source trench 5 and the ohmic groove 6 .

[0085] The process conditions are set to 20 sccm for CF4 flow, 2 sccm for O2 flow, 20 mT for pressure, and 100 V for bias voltage. A mask is first made on the upper part of the passivation layer 4. Reactive ion etching technology is used with the mask to simultaneously etch the left and right sides of the passivation layer 4 until the upper surface of the barrier layer 3 is reached, thereby forming a source groove 5 and an ohmic groove 6.

[0086] Step E: Deposit metal inside the source groove 5 and the ohmic groove 6 to form the source 7 and the ohmic electrode 8 respectively.

[0087] Set the vacuum degree to less than 1.8×10 -3 Pa, the power is 400W, and the evaporation rate is Under the process conditions of , a mask is made on the passivation layer 4, the source groove 5 and the ohmic groove 6 for the second time, and the metal combination Ti / Al / Mo / Au is deposited on the source groove 5 and the ohmic groove 6 using the mask using electron beam evaporation technology, with thicknesses of 0.112μm, 0.123μm, 0.075μm and 0.084μm respectively; then, rapid thermal annealing is performed under the process conditions of a temperature of 850℃ and a time of 35s to form the source 7 and the ohmic electrode 8.

[0088] Step F: Making a P-type array block groove 9.

[0089] The process conditions are set to 28 sccm for CF4 flow, 3 sccm for O2 flow, 25 mT for pressure, and 110 V for bias voltage. A mask is made on the passivation layer 4, the source electrode 7, and the ohmic electrode 8 for the third time. The mask is used to etch the middle right portion of the passivation layer 4 until the upper surface of the barrier layer 3 is reached, forming six P-type array block grooves 9 arranged at equal intervals in front and back.

[0090] Step G: Fabricate a P-type array block 10 .

[0091] The target material is copper with a purity of 99.999%, the sputtering gas is high-purity argon, and the high-purity oxygen with the same purity is used as the reaction gas. The vacuum degree of the reaction chamber before sputtering is 2.0×10 -4Pa, the argon flow rate is maintained at 20 sccm, the oxygen flow rate is 10 sccm, the pressure of the deposition chamber is 0.5 Pa, the RF power is 35 W, and the substrate temperature is 200 ° C. The fourth mask is made on the passivation layer 4, the source 7, the ohmic electrode 8 and the six P-type array block grooves 9. Using the mask and magnetron sputtering technology, the six P-type array block grooves 9 are sputtered with a thickness of 320 nm and a doping concentration of 7×10 20 cm -3 CuO, forming six P-type array blocks 10.

[0092] Step H: Etching to form the Schottky groove 11 and the anode groove 12.

[0093] The process conditions are set to 25 sccm CF4 flow, 4 sccm O2 flow, 25 mT pressure, and 110 V bias voltage. A mask is made for the fifth time on the passivation layer 4, source 7, ohmic electrode 8, and P-type array block 10. The mask is used to etch the right side of the P-type array block 10 with an etching depth of 480 nm, forming five Schottky grooves 11 and six anode grooves 12.

[0094] Step I: Deposit metal to form Schottky electrode 13, anode block 14 and interconnection metal 15.

[0095] The vacuum degree was set to 1.6×10 -3 Pa, the power is 350W, and the evaporation rate is Under the process conditions, a mask is made for the sixth time on the passivation layer 4, source 7, ohmic electrode 8, P-type array block 10, Schottky groove 11 and anode groove 12. The mask is used to adopt electron beam evaporation technology to deposit metal Mo on the ohmic electrode 8, Schottky groove 11, anode groove 12 and P-type array block 10 to make Schottky contacts, forming five Schottky electrodes 13, six anode blocks 14 and interconnection metal 15; a diode structure is formed between the Schottky electrodes 13 and the anode blocks 14 and the barrier layer 3 and the passivation layer 4 in contact with them.

[0096] Step J: Etching the passivation layer 4 to form a window 16 .

[0097] The process conditions are set to 28 sccm for CF4 flow, 3 sccm for O2 flow, 25 mT for pressure, and 100 V for bias voltage. A mask is made on the passivation layer 4, the source 7, and the interconnect metal 15 for the seventh time. The passivation layer 4 between the source 7 and the P-type array block 10 is etched using reactive ion etching technology using the mask until the upper surface of the barrier layer 3 is reached, forming a window 16.

[0098] Step K: sputtering P-type material in the window 16 to form a P-type block 17 .

[0099] The target material is copper with a purity of 99.999%, the sputtering gas is high-purity argon, and the high-purity oxygen with the same purity is used as the reaction gas. The vacuum degree of the reaction chamber before sputtering is set to 2.0×10 -4 Pa, the argon flow rate is maintained at 20 sccm, the oxygen flow rate is 10 sccm, the pressure of the deposition chamber is 0.5 Pa, the RF power is 35 W, and the substrate temperature is 200 ° C. The eighth mask is made on the passivation layer 4, the source 7, the interconnection metal 15 and the window 16. The mask is used to deposit a 300 nm thick and doping concentration of 7×10 20 cm -3 CuO forms a P-type block 17.

[0100] Step L. Set the process conditions to 500°C, 46 Torr, 4300 sccm hydrogen flow rate, 4300 sccm ammonia flow rate, and 21 μmol / min gallium source flow rate. Using the eighth mask, use metal organic chemical vapor deposition technology on the upper part of the P-type block 17 to deposit undoped GaN material with a thickness of 240 nm to form an i-GaN block 18.

[0101] Step M: depositing metal on the top of the i-GaN block 18 to form a gate 19.

[0102] Set the vacuum degree to less than 1.8×10 -3 Pa, power is 500W, evaporation rate is less than Under the process conditions of step 1, a mask is formed for the ninth time on the passivation layer 4, the source electrode 7, the interconnect metal 15 and the i-GaN block 18. The mask is used to deposit a metal combination of Ni and Au with thicknesses of 0.020 μm and 0.32 μm, respectively, on the upper portion of the i-GaN block 18 using electron beam evaporation technology to form a gate 19. The source electrode 7, the gate 19, the ohmic electrode 8, the Schottky electrode 13 and the anode block 14 on the right side form a HEMT structure. The HEMT device is combined with the diode formed in step I to form a power switching device, completing the fabrication of the entire device.

[0103] Example 2: A barrier layer 3 with a thickness a of 100 nm is manufactured on a sapphire substrate, a passivation layer 4 is made of HfO2 material with a thickness b of 1000 nm, K=3, N=4, M=4, the height c of the Schottky electrode 13 and the anode block 14 is 1520 nm, and a composite drain power transistor is made of NiO material for both the P-type array block 10 and the P-type block 17.

[0104] Step 1. Fabricate a transition layer 2 on a sapphire substrate.

[0105] Using metal organic chemical vapor deposition technology, an epitaxial layer with a thickness of 6.3 μm and a doping concentration of 1×1016 cm -3 n - Type GaN transition layer 2;

[0106] The deposition process conditions are: temperature of 950°C, pressure of 40 Torr, SiH4 as the doping source, hydrogen flow rate of 4000 sccm, ammonia flow rate of 4000 sccm, and gallium source flow rate of 100 μmol / min.

[0107] Step 2. Epitaxial Al 0.1 Ga 0.9 N, forming barrier layer 3.

[0108] Using molecular beam epitaxy technology, Al with a thickness of 100 nm is grown on the GaN transition layer 2. 0.1 Ga 0.9 N material, forming barrier layer 3;

[0109] The process conditions of molecular beam epitaxy technology are: vacuum degree is less than or equal to 1.0×10 -10 mbar, the RF power is 400W, and the reactants are N2, high-purity Ga source, and high-purity Al source.

[0110] Step 3: Deposit HfO2 material to form a passivation layer 4.

[0111] Using radio frequency magnetron reactive sputtering technology, HfO2 material with a thickness of 1000 nm is deposited on the barrier layer 3 to form a passivation layer 4;

[0112] The process conditions of RF magnetron reactive sputtering technology are: the sputtering gas pressure in the reaction chamber is maintained at about 0.1 Pa, the flow rates of O2 and Ar are 1 sccm and 8 sccm respectively, the substrate temperature is fixed at 200°C, and the Hf target RF power is 150W.

[0113] Step 4: Form the source trench 5 and the ohmic groove 6.

[0114] A mask is first made on the upper portion of the passivation layer 4. Reactive ion etching technology is used with the mask to simultaneously etch the left and right sides of the passivation layer 4 until the upper surface of the barrier layer 3 is reached, thereby forming a source trench 5 and an ohmic recess 6.

[0115] The process conditions for reactive ion etching technology are: CF4 flow rate of 44 sccm, O2 flow rate of 6 sccm, pressure of 16 mT, and power of 270 W;

[0116] Step 5. Deposit metal in the source trench 5 and the ohmic groove 6 to form a source 7 and an ohmic electrode 8.

[0117] A second mask is formed on the passivation layer 4, the source groove 5, and the ohmic groove 6. Using this mask, a Ti / Au / Ta / Au metal combination is deposited inside the source groove 5 and the ohmic groove 6 using electron beam evaporation technology, with thicknesses of 0.257 μm, 0.168 μm, 0.308 μm, and 0.377 μm, respectively. Rapid thermal annealing is then performed to complete the formation of the source electrode 7 and the ohmic electrode 8.

[0118] The process conditions of electron beam evaporation technology are: vacuum degree less than 1.9×10 -3 Pa, the power is 410W, and the evaporation rate is

[0119] The process conditions of rapid thermal annealing are: temperature of 870°C and time of 35s.

[0120] Step 6. Make the P-type array block groove 9.

[0121] A mask is formed on the passivation layer 4, the source electrode 7 and the ohmic electrode 8 for the third time. Reactive ion etching is performed using the mask to etch the passivation layer 4 from the middle right to the upper surface of the barrier layer 3, forming three P-type array block grooves 9 arranged in front and back with equal spacing.

[0122] The etching process conditions are: CF4 flow rate of 50 sccm, O2 flow rate of 8 sccm, pressure of 18 mT, and power of 270 W.

[0123] Step 7. Deposit P-type material to form a P-type array block 10.

[0124] A mask is made on the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the P-type array block groove 9 for the fourth time. The mask is used to sputter a 1000 nm thick and 5×10-3 doping concentration of 10-30 nm in the P-type array block groove 9 using magnetron sputtering technology. 15 cm -3 P-type NiO, forming three P-type array blocks 10;

[0125] The process conditions of magnetron sputtering technology are: sputtering power of 120W, temperature of 300℃, Ar flow rate of 22sccm, and O2 flow rate of 33sccm.

[0126] Step 8: Etching to form the Schottky groove 11 and the anode groove 12.

[0127] A fifth mask is formed on the passivation layer 4, the source electrode 7, the ohmic electrode 8, and the P-type array block 10. Reactive ion etching is performed using the mask to etch the right side of the P-type array block 10 to a depth of 70 nm, forming four Schottky grooves 11 and four anode grooves 12.

[0128] The etching process conditions are: CF4 flow rate is 48 sccm, O2 flow rate is 6 sccm, pressure is 18 mT, and power is 270 W.

[0129] Step 9: Deposit metal to form Schottky electrode 13, anode block 14 and interconnection metal 15.

[0130] A sixth mask is formed on the passivation layer 4, source electrode 7, ohmic electrode 8, P-type array block 10, Schottky groove 11, and anode groove 12. Using this mask, electron beam evaporation is used to deposit Ni metal to a thickness of 1520 nm on the ohmic electrode 8, Schottky groove 11, anode groove 12, and P-type array block 10, forming four Schottky electrodes 13, four anode blocks 14, and interconnecting metal 15. A diode structure is formed between the barrier layer 3 and passivation layer 4 with which the Schottky electrodes 13 and anode blocks 14 contact.

[0131] The process conditions of electron beam evaporation technology are: vacuum degree is less than or equal to 1.6×10 -3 Pa, the power is set to 350W, and the evaporation rate is

[0132] Step 10: Etch the passivation layer 4 to form a window 16.

[0133] A seventh mask is made on the passivation layer 4, the source electrode 7, and the interconnect metal 15. The passivation layer 4 between the source electrode 7 and the P-type array block 10 is etched using the mask using reactive ion etching technology until the upper surface of the barrier layer 3 is reached, forming a window 16.

[0134] The etching process conditions are: CF4 flow rate is 48 sccm, O2 flow rate is 6 sccm, pressure is 18 mT, and power is 270 W.

[0135] Step 11. Sputter P-type material in the window 16 to form a P-type block 17.

[0136] The eighth mask is made on the passivation layer 4, the source 7, the interconnection metal 15 and the window 16. The mask is used to sputter a 500 nm thick and 5×10 15 cm -3 P-type NiO forms a P-type block 17;

[0137] The process conditions of magnetron sputtering technology are: sputtering power of 110W, temperature of 300℃, Ar flow rate of 20sccm, and O2 flow rate of 30sccm.

[0138] Step 12. Deposit undoped GaN material on the top of the P-type block 17 to form an i-GaN block 18.

[0139] The eighth mask is used again to deposit a 500 nm thick undoped GaN material on the upper portion of the P-type block 17 using metal organic chemical vapor deposition technology to form an i-GaN block 18 .

[0140] The deposition process conditions are: temperature of 520° C., pressure of 48 Torr, hydrogen flow rate of 4400 sccm, ammonia flow rate of 4400 sccm, and gallium source flow rate of 22 μmol / min.

[0141] Step 13: Deposit metal on the i-GaN block 18 to form a gate 19.

[0142] A ninth mask is formed on the passivation layer 4, source electrode 7, interconnect metal 15, and i-GaN block 18. Using this mask, a metal combination of Ta and Au is deposited on the top of the i-GaN block 18 using electron beam evaporation to a thickness of 0.034 μm / 0.127 μm, forming a gate 19. The source electrode 7, gate 19, ohmic electrode 8, Schottky electrode 13, and anode block 14 on the right side form a HEMT structure. This HEMT device is combined with the diode formed in step 9 to form a power switching device, completing the fabrication of the entire device.

[0143] The process conditions of electron beam evaporation are: vacuum degree less than 1.8×10 -3 Pa, power is 500W, evaporation rate is less than

[0144] Example 3: A barrier layer 3 with a thickness a of 3 nm is fabricated on a silicon carbide substrate. The passivation layer 4 is made of SiO2 material with a thickness b of 20 nm. K=3, N=1, M=3. The height c of the Schottky electrode 13 and the anode block 14 is 44 nm. Both the P-type array block 10 and the P-type block 17 are made of GaN material for a composite drain power transistor.

[0145] Step 1: Fabricate a transition layer 2 on a silicon carbide substrate 1.

[0146] Using metal organic chemical vapor deposition technology under the process conditions of temperature of 1050°C, pressure of 43 Torr, hydrogen flow rate of 4400 sccm, ammonia flow rate of 4400 sccm, and gallium source flow rate of 110 μmol / min, GaN material with a thickness of 7.7 μm was epitaxially grown on the silicon carbide substrate 1 to complete the production of the transition layer 2.

[0147] Step 2. Epitaxial Al 0.4 Ga 0.6 N, forming barrier layer 3.

[0148] Using molecular beam epitaxy technology, in a vacuum degree of less than or equal to 1.0×10 -11mbar, RF power 420W, reactants using N2, high-purity Ga source, high-purity Al source process conditions, epitaxial thickness of 3nm Al on the GaN transition layer 2 0.4 Ga 0.6 N material, forming the barrier layer 3.

[0149] Step 3. Deposit SiO2 to form a passivation layer 4.

[0150] Using plasma enhanced chemical vapor deposition technology, under the process conditions of temperature of 240°C, pressure of 1050mTorr, RF power of 25W, N2O flow rate of 840sccm, and SiH4 flow rate of 200sccm, a 20nm thick SiO2 is deposited on the barrier layer 3 to form the passivation layer 4.

[0151] Step 4: Etching to form the source trench 5 and the ohmic groove 6.

[0152] A mask is first made on the upper part of the passivation layer 4, and reactive ion etching technology is used with the mask. Under the process conditions of CF4 flow rate of 20 sccm, O2 flow rate of 2 sccm, pressure of 20 mT, and bias voltage of 100 V, etching is performed simultaneously on the left and right sides of the passivation layer 4 until the upper surface of the barrier layer 3 is reached, thereby forming a source groove 5 and an ohmic groove 6.

[0153] Step 5. Deposit metal inside the source groove 5 and the ohmic groove 6 to form a source electrode 7 and an ohmic electrode 8.

[0154] A second mask is made on the passivation layer 4, the source groove 5 and the ohmic groove 6. The mask is used to evaporate the ohmic groove 6 using electron beam evaporation technology in a vacuum of less than 1.8×10 -3 Pa, power is 380W, evaporation rate is Under the process conditions, a metal combination Ti / Al / Mo / Au is deposited on the source groove 5 and the ohmic groove 6, with thicknesses of 0.05μm, 0.014μm, 0.005μm, and 0.008μm, respectively; then, rapid thermal annealing is performed under the process conditions of a temperature of 860°C and a time of 30s to form the source 7 and the ohmic electrode 8.

[0155] Step 6. Etching to form a P-type array block groove 9.

[0156] A mask is made for the third time on the passivation layer 4 and the source electrode 6. Reactive ion etching technology is used. Under the process conditions of Cl2 flow rate of 15 sccm, pressure of 10 mTorr, and power of 130 W, the mask is used to etch at the right middle part of the passivation layer 4 until the upper surface of the barrier layer 3 is reached, forming three P-type array block grooves 9 arranged in front and back.

[0157] Step 7. Deposit P-type material to form a P-type array block 10.

[0158] A fourth mask was made on the passivation layer 4, source 7, ohmic electrode 8, and P-type array block groove 9. Using this mask, metal organic chemical vapor deposition technology was used. Under the process conditions of temperature of 950°C, pressure of 42 Torr, hydrogen flow rate of 4100 sccm, high-purity Mg source as dopant, ammonia flow rate of 4100 sccm, and gallium source flow rate of 100 μmol / min, a 20 nm thick and 1×10-40 doping concentration was deposited in the two P-type array block grooves 9. 22 cm -3 P-type GaN is used to form three P-type array blocks 10.

[0159] Step 8. Etching to form the Schottky groove 11 and the anode groove 12.

[0160] A mask is made for the fifth time on the passivation layer 4, source 7, ohmic electrode 8 and P-type array block 10. Reactive ion etching technology is used. Under the process conditions of Cl2 flow rate of 15 sccm, pressure of 10 mTorr and power of 130 W, the mask is used to etch on the right side of the P-type array block 10 with an etching depth of 44 nm, forming a Schottky groove 11 and three anode grooves 12.

[0161] Step 9. Deposit metal to form Schottky electrode 13, anode block 14 and interconnect metal 15.

[0162] A sixth mask was made on the passivation layer 4, source 7, ohmic electrode 8, P-type array block 10, Schottky groove 11 and anode groove 12. The mask was used to form a film by electron beam evaporation technology at a vacuum degree of 1.6×10 -3 Pa, the power is 350W, and the evaporation rate is Under the process conditions, metal W is deposited on the ohmic electrode 8, the Schottky groove 11, the anode groove 12 and the P-type array block 10 to make a Schottky contact, forming a Schottky electrode 13, three anode blocks 14 and an interconnection metal 15; a diode structure is formed between the Schottky electrode 13 and the anode block 14 and the barrier layer 3 and the passivation layer 4 in contact with them.

[0163] Step 10: Etch the passivation layer 4 to form a window 16.

[0164] A seventh mask is formed on the passivation layer 4, the source electrode 7, and the interconnect metal 15. Using this mask, reactive ion etching is performed on the passivation layer 4 between the source electrode 7 and the P-type array block 10 under process conditions of a Cl2 flow rate of 18 sccm, a pressure of 14 mTorr, and a power of 120 W. The etching is continued until the upper surface of the barrier layer 3 is reached, thereby forming a window 16.

[0165] Step 11. Sputtering P-type material in the window 16 to form a P-type block 17.

[0166] The eighth mask was made on the passivation layer 4, source 7, interconnect metal 15 and window 16. The mask was used to deposit a 15 nm thick and 1×10-4 doping concentration of 10-6 in the window 16 using metal organic chemical vapor deposition technology at a temperature of 950°C, a pressure of 42 Torr, a hydrogen flow rate of 4100 sccm, a high-purity Mg source as a dopant, an ammonia flow rate of 4100 sccm, and a gallium source flow rate of 100 μmol / min. 22 cm -3 P-type GaN is formed to form a P-type block 17.

[0167] Step 12. Fabricate an i-GaN block 18 on top of the P-type block 17 .

[0168] Using the eighth mask made, metal organic chemical vapor deposition technology is used on the upper part of the P-type block 17. Under the process conditions of temperature of 500°C, pressure of 46 Torr, hydrogen flow rate of 4300 sccm, ammonia flow rate of 4300 sccm, and gallium source flow rate of 21 μmol / min, undoped GaN material with a thickness of 17 nm is deposited to form an i-GaN block 18.

[0169] Step 13: Deposit multiple layers of metal to form a gate 19.

[0170] A ninth mask was formed on the passivation layer 4, source electrode 7, interconnect metal 15, and i-GaN block 18. Using this mask, a metal combination Gd / Au with a thickness of 0.28 μm / 0.39 μm, respectively, was sputtered on the top of the i-GaN block 18 under process conditions of a sputtering gas pressure of 0.1 Pa, an Ar flow rate of 8 sccm, a substrate temperature fixed at 200°C, and a target RF power of 150 W to form a gate 19. The source electrode 7, gate 19, ohmic electrode 8, Schottky electrode 13, and anode block 14 on the right side formed a HEMT structure. This HEMT device was combined with the diode formed in step nine to form a power switching device, completing the fabrication of the entire device.

[0171] In order to verify the effect of the present invention, the output characteristics and blocking characteristics of the device of the third embodiment of the present invention are simulated respectively. The results are as follows: Figure 6 ,in: Figure 6 (a) is the output characteristic curve, Figure 6 (b) is a bidirectional blocking characteristic diagram.

[0172] Depend on Figure 6It can be seen that the turn-on voltage of the device of the present invention is about 0.29V, the forward blocking voltage is 1836V, and the reverse blocking voltage is -1802V, indicating that the device of the present invention can achieve a low turn-on voltage and has good bidirectional blocking characteristics.

Claims

1. A composite drain power transistor comprising, from bottom to top: A substrate (1), a transition layer (2), a barrier layer (3), and a passivation layer (4), characterized in that: A source groove (5) is provided on the left side of the passivation layer (4) above the barrier layer (3), and a source electrode (7) is provided inside the source groove; An ohmic groove (6) is provided on the rightmost side of the passivation layer (4), an ohmic electrode (8) is provided inside the groove, and the bottom of the ohmic electrode is in contact with the upper surface of the barrier layer (3); The left side of the ohmic electrode (8) is provided with M anode blocks (14), N Schottky electrodes (13), and K P-type array blocks (10) in sequence from right to left, the lower parts of the anode blocks (14) and the Schottky electrodes (13) are located in the transition layer (2), and the lower surface of the P-type array block (10) is in contact with the upper surface of the barrier layer (3); The upper surfaces of the ohmic electrode (8), the P-type array block (10), the Schottky electrode (13), and the anode block (14) are provided with interconnecting metal (15) for connecting the ohmic electrode (8), the P-type array block (10), the Schottky electrode (13), and the anode block (14) to maintain the equipotential of these parts; A window (16) is provided inside the passivation layer (4) between the source electrode (7) and the P-type array block (10), and a P-type block (17), an i-GaN block (18), and a gate (19) are provided inside the passivation layer (4) in order from bottom to top; The source electrode (7), the gate electrode (19), the ohmic electrode (8), the Schottky electrode (13) and the anode block (14) on the right side form a HEMT structure. A diode structure is formed between the Schottky electrode (13) and the anode block (14) and the barrier layer (3) and the passivation layer (4) in contact therewith. The HEMT and the diode are combined to form a power switching device.

2. The composite drain power transistor according to claim 1, wherein: The thickness a of the barrier layer (3) is 3 nm to 100 nm; The passivation layer (4) is made of any one of SiO2, SiN, Al2O3, Sc2O3, HfO2, and TiO2, and its thickness b is 20nm~1000nm.

3. The device according to claim 1, wherein: The source electrode (7) and the ohmic electrode (8) both form ohmic contact with the barrier layer (3); The Schottky electrode (13) and the anode block (14) both form Schottky contacts with the contacting barrier layer (3).

4. The composite drain power transistor according to claim 1, wherein: The K P-type array blocks (10) are distributed frontally and rearwardly at equal intervals, and the distance g between two adjacent array blocks is greater than 0; and the lateral spacing d between each P-type array block (10) and the Schottky electrode (13) is greater than 0.

5. The composite drain power transistor according to claim 1, wherein: The N Schottky electrodes (13) are distributed at equal intervals in front and back, and the spacing h between two adjacent electrodes is greater than 0. These Schottky electrodes (13) and the K P-type array blocks (10) are staggered, with N≥1 and K≥2. The lateral spacing e between the Schottky electrode (13) and the anode block (14) is greater than 0.

6. The composite drain power transistor according to claim 1, wherein: The M anode blocks (14) are distributed at equal intervals in front and back, and the longitudinal spacing i between two adjacent anode blocks is greater than 0. When the device is in a balanced state, a depletion region is generated between the anode blocks (14), and the current path is pinched off by the depletion region, M≥2; the lateral spacing f between each anode block (14) and the ohmic electrode (8) is greater than 0; the height c of each anode block (14) and each Schottky electrode (13) is the same, c>a+b, where a is the thickness of the barrier layer (3) and b is the thickness of the passivation layer (4).

7. A method for manufacturing a composite drain power transistor, characterized in that: The steps include: A) epitaxially growing GaN semiconductor material on a substrate (1) to form a transition layer (2); B) epitaxially growing a GaN-based wide bandgap semiconductor material on the transition layer (2) to form a barrier layer (3); C) depositing a dielectric on the barrier layer (3) to form a passivation layer (4); D) making a mask on the passivation layer (4) for the first time, and using the mask to etch simultaneously on the left and right sides of the passivation layer (4) until the upper surface of the barrier layer (3) is reached, thereby forming a source trench (5) and an ohmic groove (6); E) forming a mask for the second time on the passivation layer (4), the source groove (5) and the ohmic groove (6), depositing metal on the source groove (5) and the ohmic groove (6) using the mask, and performing rapid thermal annealing to form a source electrode (7) and an ohmic electrode (8); F) making a mask for the third time on the passivation layer (4), the source electrode (7) and the ohmic electrode (8), and using the mask to etch at a position slightly to the right of the middle of the passivation layer (4) until the upper surface of the barrier layer (3) is reached, thereby forming K P-type array block grooves (9) arranged in front and back with equal spacing; G) forming a mask for the fourth time on the passivation layer (4), the source electrode (7), the ohmic electrode (8) and the P-type array block groove (9), and using the mask to deposit a P-type material inside the P-type array block groove (9) to form K P-type array blocks (10); H) forming a mask for the fifth time on the passivation layer (4), the source electrode (7), the ohmic electrode (8) and the P-type array block (10), and using the mask to etch on the right side of the P-type array block (10) until the inside of the transition layer (2), thereby forming N Schottky grooves (11) and M anode grooves (12); I) forming a mask for the sixth time on the passivation layer (4), the source (7), the ohmic electrode (8), the P-type array block (10), the Schottky groove (11) and the anode groove (12), and using the mask to deposit metal on the ohmic electrode (8), the Schottky groove (11), the anode groove (12) and the P-type array block (10) to form N Schottky electrodes (13), M anode blocks (14) and interconnecting metal (15); J) making a mask for the seventh time on the passivation layer (4), the source electrode (7), and the interconnection metal (15), and using the mask to etch the passivation layer (4) between the source electrode (7) and the P-type array block (10) until the upper surface of the barrier layer (3) is reached, thereby forming a window (16); K) Make a mask for the eighth time on the passivation layer (4), source (7), interconnect metal (15) and window (16), and use the mask to deposit a thickness of 10nm to 500nm in the window (16) with a doping concentration of 5´10 15 cm -3 ~1´10 22 cm -3 P-type block (17); L) using the eighth mask, epitaxially growing an i-GaN block (18) with a thickness of 10 nm to 500 nm on the upper portion of the P-type block (17); M) A mask is formed for the ninth time on the passivation layer (4), the source electrode (7), the interconnect metal (15) and the i-GaN block (18), and a metal is deposited on the upper portion of the i-GaN block (18) using the mask to form a gate (19), thereby completing the fabrication of the entire device.

8. The method for manufacturing a composite drain power transistor according to claim 7, wherein: The epitaxial processes in steps A), B), G), K), and L) include: metal organic chemical vapor deposition technology, plasma enhanced chemical vapor deposition technology, atomic layer deposition technology, and molecular beam epitaxy technology.

9. The method for manufacturing a composite drain power transistor according to claim 7, wherein: The technology for making the passivation layer (4) in step C) includes: chemical vapor deposition technology, atomic layer deposition technology, and radio frequency magnetron reactive sputtering technology.

10. The method for manufacturing a composite drain power transistor according to claim 7, wherein: The etching processes described in steps D), F), H), and J) have the following process conditions: CF4 flow rate of 20-50 sccm, O2 flow rate of 2-10 sccm, pressure of 15-25 mT, power of 180-270 W or Cl2 flow rate of 12-20 sccm, pressure of 7-15 mT, power of 80-130 W.

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