Array substrate, manufacturing method thereof, and display panel

Abstract

The present invention provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes an oxide semiconductor layer, a gate insulating layer, a gate, an interlayer insulating layer, and a source-drain metal layer located on a substrate. Among them, the oxide semiconductor layer includes a channel region and conductor regions on both sides of the channel region. The gate insulating layer overlaps with the conductor regions on both sides of the channel region respectively, and the orthographic projection of the part of the gate corresponding to the oxide semiconductor layer on the substrate falls within the range of the orthographic projection of the channel region on the substrate. Based on the fact that carriers will diffuse under the gate insulating layer due to the influence of high-temperature film formation, the manufacturing of the interlayer insulating layer is divided into two times. After the first interlayer insulating layer is manufactured, an etching process is used to form a gate with a smaller size. When the second interlayer insulating layer is manufactured, as the carriers diffuse, the conductor regions of the oxide semiconductor layer become longer and the channel region becomes narrower, which is beneficial to improving the aperture ratio and resolution of the array substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and particularly relates to an array substrate, a manufacturing method thereof, and a display panel. Background Art

[0002] Currently, in an oxide semiconductor array substrate manufactured by a top-gate self-alignment process, carriers in the conductorized region of the oxide semiconductor are likely to diffuse to the non-conductorized region under the influence of subsequent thermal processes and diffuse under the gate insulating layer, resulting in parasitic capacitance and short-channel effect. Specifically, as Figure 1 shown, it is a schematic structural diagram of an existing array substrate. The array substrate 100 includes a glass substrate 101, a light-shielding layer 102, a buffer layer 103, an oxide semiconductor layer 104, a gate insulating layer 105, a gate metal layer 106, an interlayer insulating layer 107, a source-drain metal layer 108, and a passivation layer 109, which are sequentially stacked from bottom to top. Among them, the gate insulating layer 105 and the gate metal layer 106 are formed simultaneously. The conductorization process is performed on the oxide semiconductor layer 104 by a top-gate self-alignment process, and the part not covered by the gate insulating layer 105 is conductorized. However, the carrier concentration in the conductorized region 1041 of the oxide semiconductor layer 104 is relatively high, and diffusion is likely to occur during subsequent thermal processes, forming a carrier diffusion region L1 under the gate insulating layer 105. As a result, a parasitic capacitance is formed between the carrier diffusion region L1 and the upper gate metal layer 106, and the length of the effective channel region 1042 formed under the gate insulating layer 105 becomes shorter, resulting in device instability. In addition, the size of the gate metal layer 106 is relatively large, requiring a large design space, resulting in a low aperture ratio and resolution of the array substrate.

[0003] Therefore, it is necessary to provide a technical solution to solve the above problems. Summary of the Invention

[0004] The present invention provides an array substrate, a manufacturing method thereof, and a display panel, which can solve the technical problems of instability of TFT devices in existing array substrates and low aperture ratio and resolution of array substrates.

[0005] To solve the above problems, the technical solutions provided by the present invention are as follows:

[0006] An embodiment of the present invention provides an array substrate, including:

[0007] A substrate;

[0008] An oxide semiconductor layer, disposed on the substrate, including a channel region and conductor regions located on both sides of the channel region;

[0009] A gate insulating layer, disposed on a side of the oxide semiconductor layer away from the substrate;

[0010] A gate, disposed on a side of the gate insulating layer away from the substrate;

[0011] An interlayer insulating layer, disposed on a side of the gate away from the substrate;

[0012] A source-drain metal layer, disposed on a side of the interlayer insulating layer away from the substrate, and electrically connected to the conductor region through a via hole penetrating the interlayer insulating layer;

[0013] Wherein, edges of the gate insulating layer respectively overlap with the conductor regions on both sides of the channel region, and a projection of a portion of the gate corresponding to the oxide semiconductor layer on the substrate falls within a projection range of the channel region on the substrate.

[0014] Optionally, in some embodiments of the present invention, a projection of a portion of the gate corresponding to the oxide semiconductor layer on the substrate coincides with a projection of the channel region on the substrate.

[0015] Optionally, in some embodiments of the present invention, the interlayer insulating layer includes a first interlayer insulating layer and a second interlayer insulating layer, the first interlayer insulating layer is located on a side of the second interlayer insulating layer close to the substrate, and the first interlayer insulating layer exposes the gate and the gate insulating layer.

[0016] Optionally, in some embodiments of the present invention, the first interlayer insulating layer covers a portion of the conductor region not covered by the gate insulating layer, and the source-drain metal layer is electrically connected to the conductor region through the via hole penetrating the first interlayer insulating layer and the second interlayer insulating layer.

[0017] Optionally, in some embodiments of the present invention, a metal light-shielding layer and a buffer layer are further disposed between the substrate and the oxide semiconductor layer, and the metal light-shielding layer is located on a side of the buffer layer away from the oxide semiconductor layer;

[0018] The source-drain metal layer includes a source and a drain, wherein the drain is electrically connected to the metal light-shielding layer through a contact hole penetrating the interlayer insulating layer and the buffer layer.

[0019] An embodiment of the present invention further provides a method for manufacturing an array substrate, including the following steps:

[0020] S1, providing a substrate, and fabricating an oxide semiconductor layer on the substrate;

[0021] S2, fabricating a gate insulating layer, a gate, and an interlayer insulating layer on the oxide semiconductor layer, and forming a channel region of the oxide semiconductor layer and conductor regions on both sides of the channel region;

[0022] S3. Form a via hole penetrating through the interlayer insulating layer and exposing the conductor region.

[0023] S4. Fabricate a source-drain metal layer on the interlayer insulating layer, and the source-drain metal layer is electrically connected to the conductor region through the via hole.

[0024] Wherein, the edges of the gate insulating layer respectively overlap with the conductor regions on both sides of the channel region, and the projection of the part of the gate corresponding to the oxide semiconductor layer on the substrate falls within the projection range of the channel region on the substrate.

[0025] Optionally, in some embodiments of the present invention, S2 includes the following steps:

[0026] S21. Fabricate a stacked gate insulating layer and a gate transition layer on the oxide semiconductor layer, and form a first conductor region on the part of the oxide semiconductor layer not covered by the gate insulating layer.

[0027] S22. Fabricate the first interlayer insulating layer, the interlayer insulating layer covers the first conductor region, and at the same time, the carriers of the first conductor region diffuse to the part of the oxide semiconductor layer corresponding to the gate insulating layer to form a second conductor region adjacent to the first conductor region.

[0028] S23. Etch the gate transition layer to form a gate.

[0029] S24. Fabricate the second interlayer insulating layer to form an interlayer insulating layer covering the gate, the gate insulating layer, and the oxide semiconductor layer. At the same time, the carriers of the first conductor region and the second conductor region diffuse towards the part of the oxide semiconductor layer corresponding to the gate to form a third conductor region between the part of the oxide semiconductor layer corresponding to the gate and the second conductor region.

[0030] Wherein, the first conductor region, the second conductor region, and the third conductor region constitute the conductor region.

[0031] Optionally, in some embodiments of the present invention, S21 includes the following steps:

[0032] S211. Sequentially fabricate a gate insulating film, a gate metal film, and a photoresist on the oxide semiconductor layer. The photoresist includes a reserved area, and the part of the photoresist other than the reserved area is removed through a yellow light process.

[0033] S212, etch the gate insulating film and the gate metal film to remove the portions of the gate insulating film and the gate metal film outside the retention area, so as to form the gate insulating layer and the gate transition layer;

[0034] S213, conductify the portion of the oxide semiconductor layer not covered by the gate insulating layer to form the first conductor region.

[0035] Optionally, in some embodiments of the present invention, S22 includes the following steps:

[0036] Fabricate the first interlayer insulating layer on the retention area of the oxide semiconductor layer and the photoresist, to form the first interlayer insulating layer covering the first conductor region. At the same time, carriers in the first conductor region diffuse to the portion of the oxide semiconductor layer corresponding to the gate insulating layer, so as to form a second conductor region adjacent to the first conductor region and overlapping with the gate insulating layer;

[0037] After S23 and before S24, the manufacturing method further includes the following steps:

[0038] Remove the retention area of the photoresist and the portion of the interlayer insulating layer covering the retention area.

[0039] Optionally, in some embodiments of the present invention, the portion of the oxide semiconductor layer corresponding to the gate constitutes the channel region, and the orthographic projection of the portion of the gate corresponding to the oxide semiconductor layer on the substrate coincides with the orthographic projection of the channel region on the substrate.

[0040] An embodiment of the present invention further provides a display panel, including the array substrate and the counter substrate as described above, and the array substrate and the counter substrate are disposed opposite to each other.

[0041] The beneficial effects of the present invention are as follows: For the array substrate, its manufacturing method, and the display panel provided by the present invention, by dividing the fabrication of the interlayer insulating layer into two times, after completing the fabrication of the first interlayer insulating layer, an etch process is used to form a gate with a smaller size. When the second interlayer insulating layer is fabricated, as the carriers diffuse, the conductor region of the oxide semiconductor layer becomes longer and the channel region becomes narrower. Compared with the conventional structure where the carriers of the oxide semiconductor layer diffuse below the gate, the gate of the present invention does not overlap with the diffused carrier portion of the oxide semiconductor layer due to its reduced size. Therefore, it is beneficial to improve the aperture ratio and resolution of the array substrate, and at the same time, it avoids the parasitic capacitance and short-channel effect caused by the diffused carriers, improving the stability of the TFT device. Description of the Drawings

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0043] Figure 1 is a schematic structural diagram of an existing array substrate;

[0044] Figure 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0045] Figure 3 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present invention;

[0046] Figure 4 is a flowchart of step S2 in the manufacturing method of an array substrate provided by an embodiment of the present invention;

[0047] Figure 5 is a flowchart of step S21 in the manufacturing method of an array substrate provided by an embodiment of the present invention;

[0048] Figures 6A - 6M is a schematic diagram of the manufacturing process of an array substrate provided by an embodiment of the present invention. Detailed Embodiments

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention. In addition, it should be understood that the specific embodiments described herein are only for explaining and understanding the present invention, and are not used to limit the present invention. In the present invention, unless otherwise stated, the orientation terms such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the drawings; and "inner" and "outer" refer to the outline of the device.

[0050] Please refer to Figure 2 , Figure 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention. An embodiment of the present invention provides an array substrate 200, which sequentially includes from bottom to top: a substrate 20, a metal light-shielding layer 21, a buffer layer 22, an oxide semiconductor layer 23, a gate insulating layer 24, a gate 25, an interlayer insulating layer 26, a source-drain metal layer 27, and a passivation layer 28.

[0051] Among them, the metal light-shielding layer 21 is located on the substrate 20 and is used to block the light emitted from one side of the substrate 20 towards the oxide semiconductor layer 23. The buffer layer 22 covers the metal light-shielding layer 21. The oxide semiconductor layer 23 is disposed on the side of the buffer layer 22 away from the substrate 20, and includes a channel region 232 and conductor regions 231 located on both sides of the channel region 232. The gate insulating layer 24 is disposed on the side of the oxide semiconductor layer 23 away from the substrate 20, the gate 25 is disposed on the side of the gate insulating layer 24 away from the substrate 20, and the interlayer insulating layer 26 is disposed on the side of the gate 25 away from the substrate 20. The source-drain metal layer 27 is disposed on the side of the interlayer insulating layer 26 away from the substrate 20 and is electrically connected to the conductor region 231 through a via hole penetrating the interlayer insulating layer 26. The passivation layer 28 is disposed on the side of the source-drain metal layer 27 away from the substrate 20.

[0052] Among them, the edges of the gate insulating layer 24 overlap with the conductor regions 231 on both sides of the channel region 232 respectively, and the orthographic projection of the portion of the gate 25 corresponding to the oxide semiconductor layer 23 on the substrate 20 falls within the range of the orthographic projection of the channel region 232 on the substrate 20.

[0053] Further, the conductor region 231 includes a first conductor region 2311, a second conductor region 2312, and a third conductor region 2313; the second conductor region 2312 is located between the first conductor region 2311 and the third conductor region 2313 and is in contact with the first conductor region 2311 and the third conductor region 2313.

[0054] Further, the gate insulating layer 24 overlaps with the second conductor region 2312 and the third conductor region 2313, and the orthographic projection of the portion of the gate 25 corresponding to the oxide semiconductor layer 23 on the substrate 20 coincides with the orthographic projection of the channel region 232 on the substrate 20.

[0055] It should be noted that the first conductor region 2311 is formed during the process of making the oxide semiconductor layer 23 conductive, and the second conductor region 2312 and the third conductor region 2313 are formed after the carriers of the first conductor region 2311 diffuse towards the direction close to the channel region 232 due to heat during subsequent thermal process. Since the gate 25 does not overlap with the conductor region 231 in the direction perpendicular to the substrate 20, after the carriers of the first conductor region 2311 diffuse below the gate insulating layer 24 under the influence of the subsequent thermal process, they will not form a parasitic capacitance with the gate 25, thereby improving the stability of the device.

[0056] Further, the interlayer insulating layer 26 includes a first interlayer insulating layer 261 and a second interlayer insulating layer 262. The first interlayer insulating layer 261 is located on the side of the second interlayer insulating layer 262 close to the substrate 20, and the first interlayer insulating layer 261 exposes the gate 25 and the gate insulating layer 24. Among them, the first interlayer insulating layer 261 covers the part of the conductor region 231 not covered by the gate insulating layer 24, and the source-drain metal layer 27 is electrically connected to the conductor region 231 through a via hole penetrating through the first interlayer insulating layer 261 and the second interlayer insulating layer 262.

[0057] Among them, the source-drain metal layer 27 includes a source 271 and a drain 272, and the drain 272 is electrically connected to the metal light-shielding layer 21 through a contact hole penetrating through the interlayer insulating layer 26 and the buffer layer 22.

[0058] Please refer to Figure 1 , in the process of manufacturing a conventional array substrate, it is necessary to conductify the part of the oxide semiconductor layer 104 not covered by the gate insulating layer 105. However, in subsequent thermal processes (such as manufacturing the interlayer insulating layer 107), due to the diffusion of carriers in the conductified part of the oxide semiconductor layer 104, the channel length of the oxide semiconductor layer 104 is shortened from the original L to L', and then the threshold voltage of the thin-film transistor decreases as the channel length shortens, resulting in the short-channel effect.

[0059] Please refer to Figure 2 , in the process of manufacturing the array substrate of the present invention, as the carriers of the first conductor region 2311 diffuse, the size of the gate 25 is reduced to a smaller size, so that the part of the gate 25 corresponding to the oxide semiconductor layer 23 corresponds to the channel region 232 formed after the carrier diffusion. Thus, the diffusion of carriers in the thermal process does not affect the length of the channel region 232, and further avoids the short-channel effect, further improving the stability of the device. In addition, due to the reduction of the size of the gate 25, the wiring space is reduced, which is beneficial to improving the aperture ratio and resolution of the array substrate.

[0060] Please refer to Figures 3 - 5 and Figures 6A - 6M , the embodiment of the present invention also provides a method for manufacturing an array substrate, including the following steps:

[0061] S1, provide a substrate, and manufacture an oxide semiconductor layer on the substrate.

[0062] Specifically, please refer to Figures 6A - 6B, before fabricating the oxide semiconductor layer in the step S1, the fabrication method further includes: fabricating a metal light-shielding layer 21 on a substrate 20, and then fabricating a buffer layer 22 covering the metal light-shielding layer 21 on the metal light-shielding layer 21.

[0063] Wherein, the thickness of the metal light-shielding layer 21 is The material of the metal light-shielding layer 21 can be at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The thickness of the buffer layer 22 is And the material of the buffer layer 22 can be at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ).

[0064] Please refer to Figure 6C , fabricate an oxide semiconductor layer 23 on the buffer layer 22, and the orthographic projection of the oxide semiconductor layer 23 on the substrate 20 is within the orthographic projection of the metal light-shielding layer 21 on the substrate 20. Wherein, the thickness of the oxide semiconductor layer 23 is The material of the oxide semiconductor layer 23 can be one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), or indium gallium zinc tin oxide (IGZTO).

[0065] S2, fabricate a gate insulating layer, a gate, and an interlayer insulating layer on the oxide semiconductor layer, and form a channel region of the oxide semiconductor layer and conductor regions on both sides of the channel region.

[0066] Specifically, the S2 includes the following steps:

[0067] S21, fabricate a stacked gate insulating layer and a gate transition layer on the oxide semiconductor layer, and form a first conductor region on a portion of the oxide semiconductor layer not covered by the gate insulating layer.

[0068] Furthermore, please refer to Figure 5 and Figures 6D - 6F , the step S21 specifically includes the following steps:

[0069] S211, sequentially fabricate a gate insulating film, a gate metal film, and a photoresist on the oxide semiconductor layer, the photoresist includes a reserved area, and remove a portion of the photoresist except the reserved area through a yellow light process.

[0070] As Figure 6D shown, sequentially fabricate a gate insulating film 24', a gate metal film 25', and a photoresist 30' on the oxide semiconductor layer 23.

[0071] Among them, the thickness of the gate insulating film 24' is and the material of the gate insulating film 24' can be at least one of silicon oxide and silicon nitride. The thickness of the gate metal film 25' is and the material of the gate metal film 25' can be at least one of molybdenum, aluminum, copper, and titanium.

[0072] As Figure 6E shown, the photoresist 30' includes a retention area 30, and the part of the photoresist 30' other than the retention area 30 is removed through a yellow light process.

[0073] S212, etch the gate insulating film and the gate metal film, and remove the parts of the gate insulating film and the gate metal film corresponding to the area outside the retention area to form the gate insulating layer and the gate transition layer.

[0074] As Figure 6F shown, first etch the gate metal film 25' to remove the part of the gate metal film 25' corresponding to the area outside the retention area 30 to form a gate transition layer 25a. Then, using the gate transition layer 25a as self-alignment, etch the gate insulating film 24' to remove the part corresponding to the area outside the gate transition layer 25a to form a gate insulating layer 24.

[0075] Among them, the etching of the gate metal film 25' is over-etching, and the orthographic projection of the gate transition layer 25a on the substrate 20 is within the orthographic projection of the gate insulating layer 24 on the substrate 20.

[0076] S213, conductivize the part of the oxide semiconductor layer not covered by the gate insulating layer to form the first conductor region.

[0077] Please continue to refer to Figure 6F , conductivize the part of the oxide semiconductor layer 23 not covered by the gate insulating layer 24 to form a first conductor region 2311. Among them, the part 23a of the oxide semiconductor layer 23 corresponding to the gate insulating layer 24 is not conductivized.

[0078] After the above step S21 is completed, S2 further includes the following steps:

[0079] S22, fabricate the first interlayer insulating layer. The interlayer insulating layer covers the first conductor region, and at the same time, the carriers of the first conductor region diffuse into the part of the oxide semiconductor layer corresponding to the gate insulating layer to form a second conductor region adjacent to the first conductor region.

[0080] In the present invention, the interlayer insulating layer 26 is fabricated in two steps. Please refer to Figure 6G, first, a first interlayer insulating layer is formed on the oxide semiconductor layer 23 and the reserved area 30 of the photoresist through a CVD process, forming a first interlayer insulating layer 261. The first interlayer insulating layer 261 is disconnected at the edge of the reserved area 30 and covers the first conductor area 2311. Since the CVD process is a thermal process, during the formation of the first interlayer insulating layer 261, the carriers of the first conductor area 2311 diffuse to the part 23a of the oxide semiconductor layer 23 corresponding to the gate insulating layer 24, forming a second conductor area 2312 adjacent to the first conductor area 2311.

[0081] Among them, the thickness of the first interlayer insulating layer 261 is and the material of the first interlayer insulating layer 261 can be at least one of silicon oxide and silicon nitride, or it can also be an organic material.

[0082] S23, please refer to Figure 6H , the gate transition layer 25a is etched to form a gate 25.

[0083] Please refer to Figure 6I , after the gate 25 is formed, the reserved area 30 of the photoresist and the part of the first interlayer insulating layer 261 covering the reserved area 30 are removed together.

[0084] S24, a second interlayer insulating layer is formed to form an interlayer insulating layer covering the gate, the gate insulating layer, and the oxide semiconductor layer. At the same time, the carriers of the first conductor area and the second conductor area diffuse towards the part of the oxide semiconductor layer corresponding to the gate, so as to form a third conductor area between the part of the oxide semiconductor layer corresponding to the gate and the second conductor area; among them, the first conductor area, the second conductor area, and the third conductor area constitute a conductor area.

[0085] Please refer to Figure 6J , a second interlayer insulating layer 262 is formed on the gate 25, the gate insulating layer 24, and the oxide semiconductor layer 23 through a CVD process. At the same time, affected by the high-temperature film formation, the carriers of the first conductor area 2311 and the second conductor area 2312 diffuse towards the part of the oxide semiconductor layer 23 corresponding to the gate 25, forming a third conductor area 2313 between the part of the oxide semiconductor layer 23 corresponding to the gate 25 and the second conductor area 2312.

[0086] Among them, the first conductor area 2311, the second conductor area 2312, and the third conductor area 2313 constitute a conductor area 231, and the part of the oxide semiconductor layer 23 corresponding to the gate 25 constitutes a channel area 232.

[0087] Among them, the positive projection of the part of the gate 25 corresponding to the oxide semiconductor layer 23 on the substrate 20 coincides with the positive projection of the channel region 232 on the substrate 20.

[0088] Among them, the thickness of the second interlayer insulating layer 262 is and the material of the second interlayer insulating layer 262 can be at least one of silicon oxide and silicon nitride, or it can also be an organic material.

[0089] After the above step S2 is completed, the manufacturing method of the array substrate further includes the following steps:

[0090] S3, forming a via hole that penetrates the interlayer insulating layer and exposes the conductor region.

[0091] Specifically, please refer to Figure 6K , through a yellow light etching process, an via hole 1 that penetrates the interlayer insulating layer 26 and exposes the conductor region 231, and a contact hole 2 that penetrates the interlayer insulating layer 26 and the buffer layer 22 and exposes the metal light-shielding layer 21 are etched.

[0092] S4, fabricating a source-drain metal layer on the interlayer insulating layer, and the source-drain metal layer is electrically connected to the conductor region through the via hole.

[0093] Specifically, please refer to Figure 6L , a source-drain metal layer 27 is fabricated on the interlayer insulating layer 26. The source-drain metal layer 27 includes a source electrode 271 and a drain electrode 272. The source electrode 271 and the drain electrode 272 are respectively electrically connected to the conductor region 231 through the corresponding via hole 1, and the drain electrode 272 is also electrically connected to the metal light-shielding layer 21 through the contact hole 2.

[0094] Among them, the thickness of the source-drain metal layer 27 is and the material of the source-drain metal layer 27 can be at least one of molybdenum, aluminum, copper, and titanium.

[0095] Please refer to Figure 6M , after the step S7, the manufacturing method may further include: fabricating a passivation layer 28 on the source-drain metal layer 27.

[0096] Among them, the passivation layer 28 is used to protect the thin film transistor from being invaded by external air and water vapor.

[0097] An embodiment of the present invention further provides a display panel, including the array substrate and the counter substrate as described above, and the array substrate and the counter substrate are disposed opposite to each other. Among them, the display panel may be a liquid crystal display panel, an organic light-emitting display panel, a quantum dot display panel, a Mini-LED display panel or a Micro-LED display panel, which is not limited here.

[0098] Based on the fact that carriers will diffuse under the gate insulating layer due to the influence of subsequent high-temperature film formation in the present invention, the fabrication of the interlayer insulating layer is divided into two times. After the fabrication of the first interlayer insulating layer is completed, an etching process is used to form a gate with a smaller size. When the second interlayer insulating layer is fabricated, as the carriers diffuse, the conductor region of the oxide semiconductor layer becomes longer, forming a channel region corresponding to the gate. Compared with the case where carriers in the oxide semiconductor layer diffuse under the gate in the traditional structure, the gate in the present invention does not overlap with the carrier diffusion part of the oxide semiconductor layer due to the reduced size, so the parasitic capacitance and short-channel effect caused by the diffused carriers are avoided, and the stability of the thin-film transistor device is improved. In addition, since the size of the gate is reduced, it is beneficial to improve the aperture ratio and resolution of the array substrate.

[0099] The embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A manufacturing method of an array substrate, characterized in that, it includes the following steps: S1, providing a substrate and fabricating an oxide semiconductor layer on the substrate; S2, fabricating a gate insulating layer, a gate, and an interlayer insulating layer on the oxide semiconductor layer, and forming a channel region of the oxide semiconductor layer and conductor regions on both sides of the channel region; S3, forming vias penetrating the interlayer insulating layer and exposing the conductor regions; S4, fabricating a source-drain metal layer on the interlayer insulating layer, and the source-drain metal layer is electrically connected to the conductor regions through the vias; wherein, the edges of the gate insulating layer respectively overlap with the conductor regions on both sides of the channel region, and the orthographic projection of the part of the gate corresponding to the oxide semiconductor layer on the substrate falls within the orthographic projection range of the channel region on the substrate; The S2 includes the following steps: S21, fabricating a stacked gate insulating layer and a gate transition layer on the oxide semiconductor layer, and forming a first conductor region on the part of the oxide semiconductor layer not covered by the gate insulating layer; S22, fabricating a first interlayer insulating layer, the interlayer insulating layer covering the first conductor region, and at the same time, carriers in the first conductor region diffuse to the part of the oxide semiconductor layer corresponding to the gate insulating layer to form a second conductor region adjacent to the first conductor region; S23, etching the gate transition layer to form a gate; S24, fabricating a second interlayer insulating layer to form an interlayer insulating layer covering the gate, the gate insulating layer, and the oxide semiconductor layer, and at the same time, carriers in the first conductor region and the second conductor region diffuse towards the part of the oxide semiconductor layer corresponding to the gate to form a third conductor region between the part of the oxide semiconductor layer corresponding to the gate and the second conductor region; wherein, the first conductor region, the second conductor region, and the third conductor region constitute the conductor region.

2. The manufacturing method of the array substrate according to claim 1, characterized in that, the S21 includes the following steps: S211, sequentially fabricating a gate insulating film, a gate metal film, and a photoresist on the oxide semiconductor layer, the photoresist including a reserved area, and removing the part of the photoresist except the reserved area through a yellow light process; S212, etching the gate insulating film and the gate metal film to remove the parts of the gate insulating film and the gate metal film corresponding to the area outside the reserved area to form the gate insulating layer and the gate transition layer; S213, conducting a conductorization process on the part of the oxide semiconductor layer not covered by the gate insulating layer to form the first conductor region.

3. The manufacturing method of the array substrate according to claim 2, characterized in that, the S22 includes the following steps: A first interlayer insulating layer is formed on the oxide semiconductor layer and the reserved area of the photoresist to form a first interlayer insulating layer covering the first conductor area. At the same time, carriers in the first conductor area diffuse to a portion of the oxide semiconductor layer corresponding to the gate insulating layer to form a second conductor area adjacent to the first conductor area and overlapping the gate insulating layer. After the step S23 and before the step S24, the manufacturing method further includes the following steps: Remove the reserved area of the photoresist and the portion of the interlayer insulating layer covering the reserved area.

4. The manufacturing method of the array substrate according to claim 1, characterized in that a portion of the oxide semiconductor layer corresponding to the gate constitutes a channel region, and a positive projection of the portion of the gate corresponding to the oxide semiconductor layer on the substrate coincides with a positive projection of the channel region on the substrate.

5. An array substrate, characterized in that it includes an array substrate manufactured by the manufacturing method of the array substrate according to any one of claims 1-4.

6. A display panel, characterized in that it includes the array substrate according to claim 5 and a counter substrate, and the array substrate and the counter substrate are disposed opposite to each other.

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