Light emitting diode and method of manufacturing the same

Abstract

Disclosed are a light emitting diode and a manufacturing method thereof, comprising: a substrate; an epitaxial layer on the substrate, the epitaxial layer comprising a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence from bottom to top, the first semiconductor layer and the second semiconductor layer having opposite doping types; a barrier layer between the first semiconductor layer and the multi-quantum well layer; a guide layer between the first semiconductor layer and the barrier layer; and a nano-pore array perpendicular to the surface of the first semiconductor layer and located in at least the guide layer and the first semiconductor layer. The light emitting diode and the manufacturing method thereof provided by the present application set the barrier layer and the guide layer between the first semiconductor layer and the multi-quantum well layer, form the nano-pore array penetrating through the guide layer and the first semiconductor layer and perpendicular to the surface of the first semiconductor layer, so as to adjust the light emission of the light emitting diode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a light emitting diode and a manufacturing method thereof. BACKGROUND

[0002] For GaN-based light emitting diodes, the internal quantum efficiency (IQE) has reached 70% to 80%, but the light extraction efficiency (LEE) has not reached a high level due to the limitation of the light emitting diode structure, resulting in that the electro-optical conversion efficiency is about 40% to 60%, which is still at a relatively low level. In addition, with the continuous increase of the working current of the light emitting diode, the problem of efficiency droop begins to appear and gradually intensifies.

[0003] For high-power light emitting diodes, the main scheme at present is flip-chip structure or vertical structure. For the vertical structure, better light extraction efficiency can be obtained by adding current blocking layer and reflective electrode, high reflector, light emitting surface patterning, patterned substrate epitaxy, or various schemes in combination, so the light extraction efficiency of the vertical structure light emitting diode is higher than that of the flip-chip structure. However, the process of the vertical structure light emitting diode is complex, and the process control requirement is more stringent. The flip-chip structure light emitting diode can also use reflective electrode, reflector and patterned substrate epitaxy scheme to improve the light extraction efficiency, but since the final light emitting surface is sapphire material, it is difficult to process the sapphire into a patterned surface to reduce the total reflection effect and thus improve the light extraction efficiency, so it is very important to further improve the light extraction efficiency of the flip-chip structure light emitting diode. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide a light emitting diode and a manufacturing method thereof, wherein the epitaxial layer includes a nano-pore array penetrating through the guide layer and the first semiconductor layer and being perpendicular to the surface of the first semiconductor layer, so as to adjust the light emission of the light emitting diode.

[0005] The first aspect of the present application provides a light emitting diode, comprising:

[0006] a substrate;

[0007] an epitaxial layer located on the substrate, the epitaxial layer comprising a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in order from bottom to top, the doping types of the first semiconductor layer and the second semiconductor layer being opposite to each other;

[0008] a barrier layer located between the first semiconductor layer and the multi-quantum well layer;

[0009] a guiding layer between the first semiconductor layer and the barrier layer; and

[0010] a nanopore array perpendicular to the surface of the first semiconductor layer and at least in the guiding layer and the first semiconductor layer.

[0011] Preferably, the barrier layer is a GaN material layer with the first doping type.

[0012] Preferably, the guiding layer is an AlxGa1-xN material layer with the first doping type, wherein x is 0.05-0.15. x Ga 1-x N material layer, wherein x is 0.05-0.15.

[0013] Preferably, the barrier layer is silicon-doped with a doping concentration of 5x1018cm-1-1x1020cm-1. 17 cm -3 -1x10 18 cm -3 .

[0014] Preferably, the guiding layer is silicon-doped with a doping concentration of 5x1018cm-1-9x1020cm-1. 19 cm -3 -9x10 19 cm -3 .

[0015] Preferably, the thickness of the barrier layer and the guiding layer ranges from 20nm to 100nm.

[0016] Preferably, the thickness of the guiding layer ranges from 5nm to 15nm.

[0017] Preferably, the barrier layer protects the multiple quantum well layer as a barrier layer for electrochemical etching; and the guiding layer guides the electrochemical etching to form the nanopore array at least in the guiding layer and the first semiconductor layer.

[0018] Preferably, the diameter of the nanopore in the nanopore array ranges from 10nm to 70nm.

[0019] Preferably, the epitaxial layer further comprises:

[0020] a buffer layer on the substrate;

[0021] an unintentionally doped layer on the buffer layer, and the first semiconductor layer is on the unintentionally doped layer;

[0022] an electron blocking layer on the multiple quantum well layer,

[0023] and the second semiconductor layer is on the electron blocking layer.

[0024] Preferably, the nano-pore array is also located in the non-intentionally doped layer, or in the non-intentionally doped layer and the buffer layer.

[0025] Preferably, the semiconductor structure further comprises:

[0026] a step located around the epitaxial layer, the step penetrating through the second semiconductor layer, the multi-quantum well layer, the barrier layer and the guide layer to expose a surface of the first semiconductor layer;

[0027] a first ohmic contact layer located on the surface of the first semiconductor layer of the lower step surface; and

[0028] a second ohmic contact layer located on the surface of the second semiconductor layer of the upper step surface.

[0029] Preferably, the semiconductor structure further comprises:

[0030] at least one via located in the epitaxial layer, the via penetrating through the second semiconductor layer, the multi-quantum well layer, the barrier layer and the guide layer to expose a surface of the first semiconductor layer;

[0031] a first ohmic contact layer located on the surface of the first semiconductor layer exposed by the via;

[0032] a second ohmic contact layer located on the surface of the second semiconductor layer;

[0033] a mirror layer located on the surface of the second ohmic contact layer.

[0034] Preferably, the semiconductor structure further comprises:

[0035] a dielectric layer covering the sidewall of the step, the sidewall and part of the surface of the first ohmic contact layer, the sidewall and part of the surface of the second ohmic contact layer, the dielectric layer having a first opening exposing part of the first ohmic contact layer and a second opening exposing part of the second ohmic contact layer;

[0036] a first electrode located on the dielectric layer and electrically connected with the first ohmic contact layer via the first opening; and

[0037] a second electrode located on the dielectric layer and electrically connected with the second ohmic contact layer via the second opening.

[0038] Preferably, the semiconductor structure further comprises:

[0039] a dielectric layer covering the sidewall and part of the surface of the mirror layer, the sidewall of the second ohmic contact layer, the sidewall of the via, the dielectric layer having a first opening exposing the first ohmic contact layer and a second opening exposing part of the mirror layer;

[0040] a first electrode on the dielectric layer and electrically connected with the first ohmic contact layer through the first opening; and

[0041] a second electrode on the dielectric layer and electrically connected with the mirror layer through the second opening.

[0042] Preferably, further comprising a mirror layer on the dielectric layer, the mirror layer having a first opening exposing part of the first ohmic contact layer and a second opening exposing part of the second ohmic contact layer, the first electrode and the second electrode being on the mirror layer.

[0043] The second aspect of the present application provides a method for manufacturing a light emitting diode, comprising:

[0044] forming an epitaxial layer on a substrate, the epitaxial layer comprising a first semiconductor layer, a guide layer, a barrier layer, a multiple quantum well layer and a second semiconductor layer stacked in order from bottom to top, the first semiconductor layer and the second semiconductor layer having opposite doping types;

[0045] electrochemically etching the epitaxial layer to form an array of nanopores perpendicular to the surface of the first semiconductor layer and at least in the guide layer and the first semiconductor layer.

[0046] Preferably, the barrier layer is a GaN material layer having the first doping type.

[0047] Preferably, the guide layer is an AlxGa1-xN material layer having the first doping type, wherein x is 0.05-0.15. x Ga 1-x N material layer having the first doping type.

[0048] Preferably, the barrier layer is silicon-doped, with a doping concentration of 5x10 17 cm -3 -1x10 18 cm -3 .

[0049] Preferably, characterized in that the guide layer is silicon-doped, with a doping concentration of 5x10 19 cm -3 -9x10 19 cm -3 .

[0050] Preferably, the thickness of the barrier layer ranges from 20nm to 100nm.

[0051] Preferably, the thickness of the guide layer ranges from 5nm to 15nm.

[0052] Preferably, the barrier layer protects the multi-quantum well layer as a barrier layer of electrochemical corrosion; and the guide layer forms the nano-pore array in at least the guide layer and the first semiconductor layer as a guide layer of electrochemical corrosion.

[0053] Preferably, the corrosion solution of the electrochemical corrosion is one of concentrated nitric acid, concentrated hydrofluoric acid, a mixed solution of concentrated nitric acid and ethanol, a mixed solution of concentrated hydrofluoric acid and ethanol, a mixed solution of concentrated nitric acid and isopropanol, and a mixed solution of concentrated hydrofluoric acid and isopropanol.

[0054] Preferably, the working voltage of the electrochemical corrosion is 10V-20V.

[0055] Preferably, the corrosion time of the electrochemical corrosion is 30s-180s.

[0056] Preferably, in the electrochemical corrosion process, the second semiconductor layer is used as an anode, and a platinum electrode is used as a cathode.

[0057] Preferably, the diameter of the nano-pore in the nano-pore array is 10nm-70nm.

[0058] Preferably, forming the epitaxial layer on the substrate further comprises:

[0059] forming a buffer layer and an unintentionally doped layer on the substrate in sequence, and the first semiconductor layer is located on the unintentionally doped layer; and

[0060] forming an electron barrier layer on the multi-quantum well layer, and the second semiconductor layer is located on the electron barrier layer.

[0061] Preferably, the nano-pore array is further located in the unintentionally doped layer, or the unintentionally doped layer and the buffer layer.

[0062] Preferably, the method further comprises: etching the second semiconductor layer, the multi-quantum well layer, the barrier layer and the guide layer in sequence to form a step around the epitaxial layer, and the step exposes the surface of the first semiconductor layer;

[0063] forming a first ohmic contact layer on the surface of the first semiconductor layer; and

[0064] forming a second ohmic contact layer on the surface of the second semiconductor layer.

[0065] Preferably, the method further comprises: etching the second semiconductor layer, the multi-quantum well layer, the barrier layer and the guide layer in sequence to form at least one through hole, and the through hole exposes the surface of the first semiconductor layer;

[0066] forming a first ohmic contact layer on the surface of the first semiconductor layer; and

[0067] a second ohmic contact layer and a mirror layer are sequentially formed on a surface of the second semiconductor layer.

[0068] Preferably, before forming the via hole, a protective layer is further formed on a surface of the second semiconductor layer, the protective layer covers an area where the via hole is formed, after forming the protective layer, electrochemical etching is performed, and after the electrochemical etching, the protective layer is removed.

[0069] Preferably, further comprising: forming a dielectric layer with a first opening and a second opening, the dielectric layer covers a sidewall of the step, a sidewall and a partial surface of the first ohmic contact layer, a sidewall of the second ohmic contact layer, and a sidewall of the via hole, the first opening exposes part of the first ohmic contact layer, and the second opening exposes part of the second ohmic contact layer;

[0070] a first electrode is formed on the dielectric layer, the first electrode is electrically connected to the first ohmic contact layer via the first opening; and

[0071] a second electrode is formed on the dielectric layer, the second electrode is electrically connected to the second ohmic contact layer via the second opening.

[0072] Preferably, further comprising: forming a dielectric layer with a first opening and a second opening, the dielectric layer covers a sidewall and a partial surface of the mirror layer, a sidewall of the second ohmic contact layer, and a sidewall of the via hole, the dielectric layer has a first opening exposing the first ohmic contact layer and a second opening exposing part of the mirror layer;

[0073] a first electrode is formed on the dielectric layer, the first electrode is electrically connected to the first ohmic contact layer via the first opening; and

[0074] a second electrode is formed on the dielectric layer, the second electrode is electrically connected to the mirror layer via the second opening.

[0075] Preferably, further comprising forming a mirror layer on the dielectric layer, the mirror layer has a first opening exposing part of the first ohmic contact layer and a second opening exposing part of the second ohmic contact layer, the first electrode and the second electrode are located on the mirror layer.

[0076] The application provides a light emitting diode and a manufacturing method thereof. A guide layer and a barrier layer are arranged between the first semiconductor layer and the multi-quantum well layer. The barrier layer serves as a barrier layer of electrochemical corrosion and protects the multi-quantum well layer from electrochemical corrosion. The guide layer serves as a guide layer of electrochemical corrosion, so that the guide layer and the first semiconductor layer form a nano-pore array perpendicular to the surface of the first semiconductor layer to adjust the light emission of the light emitting diode.

[0077] The nano-pore array is perpendicular to the surface of the first semiconductor layer and is arranged in the guide layer and the first semiconductor layer, so that the total reflection effect of the light emitting diode is significantly reduced, and the light extraction efficiency of the light emitting diode is improved.

[0078] Further, the nano-pore array can provide a relatively larger n-type ohmic contact area and reduce the voltage of the light emitting diode.

[0079] Further, the nano-pore array can reduce the compressive stress in the epitaxial layer, relieve the quantum confinement Stark effect (QCSE), further improve the internal quantum efficiency, and has great significance for realizing the industrialization of high-performance and high-power flip-chip light emitting diodes.

[0080] Further, the barrier layer has a lower doping concentration than the first semiconductor layer and the guide layer, so as to serve as a barrier layer of electrochemical corrosion and not corrode the multi-quantum well layer during the electrochemical corrosion process. The guide layer has a higher doping concentration, and the nano-pore array perpendicular to the surface of the guide layer and the first semiconductor layer is formed with the help of the guide layer. BRIEF DESCRIPTION OF DRAWINGS

[0081] The above and other objects, features and advantages of the application will be more clearly understood from the following description of embodiments of the application with reference to the drawings in which:

[0082] Figure 1 A cross-sectional schematic view of a light emitting diode provided by a first embodiment of the application is shown;

[0083] Figures 2a to 2g Cross-sectional views of the light emitting diode according to the first embodiment of the application at different stages in the manufacturing process are shown;

[0084] Figure 3 A cross-sectional schematic view of a light emitting diode provided by a second embodiment of the application is shown;

[0085] Figures 4a to 4g Cross-sectional views of the light emitting diode according to the second embodiment of the application at different stages in the manufacturing process are shown. DETAILED DESCRIPTION

[0086] The present application will be described in more detail with reference to the drawings. Like elements in the various figures are denoted by like reference numerals. For the sake of clarity, the various elements in the figures are not to scale. Furthermore, certain known elements have not been depicted so as to facilitate understanding of the present application.

[0087] The present application can take various forms, some of which will now be described.

[0088] Figure 1 A cross-sectional schematic diagram of a light emitting diode provided according to a first embodiment of the present application is shown. As shown, a GaN-based light emitting diode in a flip-chip structure is taken as an example for illustration, however the present application is not limited thereto. Figure 1

[0089] The light emitting diode comprises a substrate 110, an epitaxial layer 120, a barrier layer S0, a guide layer S, a first ohmic contact layer 131, a second ohmic contact layer 132, a dielectric layer 140, a mirror layer 150, a first electrode 161 and a second electrode 162.

[0090] The substrate 110 is a hetero-substrate, comprising a transparent single crystal substrate such as Ga2O3, SiC, sapphire, ZnO, LiGaO2, etc. The surface of the substrate 110 can also be pre-deposited with an AlN film, a BAlN film, a BN film, a graphene film, etc. Further, the surface of the substrate 110 has a patterned structure, the feature size of which ranges from hundreds of nanometers to several microns. The thickness of the substrate 110 is 300 microns to 2 millimeters.

[0091] In this embodiment, the substrate 110 is for example a sapphire substrate, which includes but is not limited to one of a mirror surface or a micron / nano patterned sapphire substrate, the preferred embodiment being a micron patterned sapphire.

[0092] The epitaxial layer 120 is located on the substrate 110, and can be a polycrystalline or single crystal structure, comprising one of a reciprocating continuous progressive epitaxial layer composed of a GaN / InGaN material system, the preferred embodiment being an InGaN structure containing different In components.

[0093] ​The epitaxial layer 120 comprises a buffer layer 121, an unintentionally doped layer 122, a first semiconductor layer 123, a multiple quantum well layer 124, an electron blocking layer 125 and a second semiconductor layer 126 which are sequentially stacked. In this embodiment, the buffer layer 121 is, for example, a gallium nitride (GaN) material layer, the unintentionally doped layer 122 is, for example, an unintentionally doped gallium nitride (GaN) material layer, the first semiconductor layer 123 is, for example, a gallium nitride (GaN) material layer of a first doping type (N type), the multiple quantum well (MQW) layer 124 comprises at least one period of quantum well, and the corresponding wavelength range is 360 nm to 600 nm; the electron blocking layer 125 is, for example, an aluminum gallium nitride (AlGaN) material layer of a second doping type (P type), and the second semiconductor layer 126 is, for example, a gallium nitride (GaN) material layer of the second doping type (P type). The multiple quantum well layer 124 is, for example, composed of aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), indium gallium nitride (InGaN) and the like. The total thickness of the epitaxial layer 120 is, for example, 5 microns to 10 microns.

[0094] The barrier layer S0 is located in the epitaxial layer 120, specifically between the first semiconductor layer 123 and the multiple quantum well layer 124, and the doping type of the barrier layer S0 is the same as that of the first semiconductor layer 123, for example, N type doping.

[0095] The guide layer S is located in the epitaxial layer 120, specifically between the first semiconductor layer 123 and the barrier layer S0, and the doping type of the guide layer S is the same as that of the first semiconductor layer 123, for example, N type doping.

[0096] The barrier layer S0 is a lightly doped gallium nitride (GaN) material layer, and specifically, the guide layer S is, for example, doped with silicon, and the doping concentration is 5x10 19 cm -3 ~ 9x10 19 cm -3 . The thickness of the barrier layer S0 is, for example, 20 nm to 100 nm. The guide layer S is a heavily doped, low Al component aluminum gallium nitride (Al x Ga 1-x N) material layer, and specifically, the guide layer S is, for example, doped with silicon, and the silicon doping concentration is in the range of 5x10 19 cm -3 ~ 9x10 19 cm -3 . The component content x of Al in the guide layer S is 0.05 to 0.15, for example, 0.1. The thickness of the guide layer S is 5 nm to 15 nm.

[0097] The epitaxial layer 120 has a nano-pore array which is perpendicular to the surface of the substrate 110, and the nano-pore array is located at least in the guide layer S and the first semiconductor layer 123, i.e. from the multi-quantum well layer 124 to the substrate 110, and the nano-pore array at least penetrates the guide layer S and stops at any one of the first semiconductor layer 123, the non-intentionally doped layer 122 and the buffer layer 121. The nano-pore in the nano-pore array has a feature size of several nanometers to tens of nanometers, and specifically, the diameter of the nano-pore in the nano-pore array is 10 nm to 70 nm.

[0098] The epitaxial layer 120 has a step around it, and the step penetrates the second semiconductor layer 126, the electron blocking layer 125, the multi-quantum well layer 124, the barrier layer S0 and the guide layer S in sequence and exposes the surface of the first semiconductor layer 123.

[0099] The first ohmic contact layer 131 is located on the surface of the first semiconductor layer 123 (the lower step surface of the step), and is in ohmic contact with the first semiconductor layer 123, and there is a gap between the first ohmic contact layer 131 and the step sidewall. The second ohmic contact layer 132 is located on the surface of the second semiconductor layer 126 layer (the upper step surface of the step), and is in ohmic contact with the second semiconductor layer 126.

[0100] The first ohmic contact layer 131, for example, includes at least one of chromium, aluminum, titanium and platinum, and the second ohmic contact layer 132, for example, adopts ITO material, but is not limited thereto.

[0101] The dielectric layer 140 covers part of the surface and the sidewall of the second ohmic contact layer 132, the sidewall of the step, the surface of the first semiconductor layer 123 of the lower step surface, and optionally, the dielectric layer 140 can also cover part of the surface of the first ohmic contact layer 131; the mirror layer 150 covers the dielectric layer 140.

[0102] In this embodiment, the dielectric layer 140 and the mirror layer 150 are provided, and in other embodiments, only one of the dielectric layer 140 and the mirror layer 150 can be provided.

[0103] The dielectric layer 140 and the mirror layer 150 have a first opening exposing the surface of the first ohmic contact layer 131 and a second opening exposing the surface of the second ohmic contact layer 132. The first electrode 161 is located on the surface of the mirror layer 150 and contacts the first ohmic contact layer 131 via the first opening, and the second electrode 162 is located on the surface of the mirror layer 150 and contacts the second ohmic contact layer 132 via the second opening, and the first electrode 161 and the second electrode 162 are separated from each other.

[0104] The dielectric layer 140 includes, but is not limited to, insulating dielectric materials such as silicon nitride, silicon oxide, and silicon oxynitride. The reflector layer 150 is, for example, a DBR reflector layer composed of SiO2 / TiO2, but is not limited thereto. The materials of the first electrode 161 and the second electrode 162 are at least one of titanium, gold, and tin.

[0105] In this embodiment, a nanopore array perpendicular to the surface of the first semiconductor layer 123 is formed in at least the guiding layer S and the first semiconductor layer 123 to significantly reduce the total internal reflection effect of the light-emitting diode (LED), thereby improving the light extraction efficiency of the LED. Furthermore, the nanopore array can provide a larger n-type ohmic contact area while reducing the LED voltage. The nanopore array can also reduce the compressive stress in the epitaxial layer, alleviate the quantum confinement Stark effect (QCSE), and further improve the internal quantum efficiency, which is of great significance for the industrialization of high-performance, high-power flip-chip LEDs.

[0106] Figures 2a to 2g The accompanying drawings show cross-sectional views of a light-emitting diode at different stages of its manufacturing process according to a first embodiment of the present invention. The manufacturing method provided in this embodiment operates on an entire wafer, and the drawings only show one chip unit.

[0107] like Figure 2a As shown, an epitaxial layer 120, a guiding layer S, and a barrier layer S0 are prepared on the surface of a substrate 110 by an epitaxial growth process.

[0108] In this step, for example, the epitaxial layer 120 is formed on the surface of the substrate 110 using a metal-organic chemical vapor deposition process. In alternative embodiments, the epitaxial layer 120 may also be formed using processes such as laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy.

[0109] The substrate 110 is a heterogeneous substrate, including transparent single-crystal substrates such as Ga2O3, SiC, sapphire, ZnO, and LiGaO2. The surface of the substrate 110 may also be pre-deposited with AlN thin films, BAlN thin films, BN thin films, graphene films, etc. The surface of the substrate 110 has a patterned structure, the characteristic dimensions of which range from hundreds of nanometers to several micrometers. The thickness of the substrate 110 is from 300 micrometers to 2 millimeters.

[0110] In this embodiment, the substrate 110 is, for example, a sapphire substrate, which includes, but is not limited to, a mirror-finished or micron / nano-scale patterned sapphire substrate, with micron-scale patterned sapphire being the preferred option.

[0111] The epitaxial layer 120 can be a polycrystalline or single-crystalline structure, and is composed of a reciprocating continuous progressive epitaxial layer composed of a GaN / InGaN material system. A preferred embodiment is an InGaN structure with different In components.

[0112] The epitaxial layer 120 includes a buffer layer 121, an unintentionally doped layer 122, a first semiconductor layer 123, a multiple quantum well layer 124, an electron blocking layer 125, and a second semiconductor layer 126, which are sequentially stacked. In this embodiment, the buffer layer 121 is, for example, a gallium nitride (GaN) material layer, the unintentionally doped layer 122 is, for example, an unintentionally doped gallium nitride (GaN) material layer, the first semiconductor layer 123 is, for example, a gallium nitride (GaN) material layer of a first doping type (N-type), the multiple quantum well (MQW) layer 124 includes at least one period of quantum wells, and corresponds to a wavelength range of 360 nm to 600 nm. The electron blocking layer 125 is, for example, an aluminum gallium nitride (AlGaN) material layer of a second doping type (P-type), and the second semiconductor layer 126 is, for example, a gallium nitride (GaN) material layer of the second doping type (P-type). The multiple quantum well layer 124 is composed of, for example, aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), indium gallium nitride (InGaN), or the like. The total thickness of the epitaxial layer 120 is, for example, 5 micrometers to 10 micrometers.

[0113] The barrier layer S0 is located in the epitaxial layer 120, specifically between the first semiconductor layer 123 and the multiple quantum well layer 124. The barrier layer S0 has the same doping type as the first semiconductor layer 123, for example, N-type doping.

[0114] The guide layer S is located in the epitaxial layer 120, specifically between the first semiconductor layer 123 and the barrier layer S0. The guide layer S has the same doping type as the first semiconductor layer 123, for example, N-type doping.

[0115] The barrier layer S0 is a lightly doped gallium nitride (GaN) material layer. Specifically, the guide layer S is, for example, silicon-doped, and the silicon doping concentration is 5x10 19 cm -3 ~ 9x10 19 cm -3 . The thickness of the barrier layer S0 is, for example, 20 nm to 100 nm. The guide layer S is a heavily doped, low Al component aluminum gallium nitride (Al x Ga 1-x N) material layer. Specifically, the guide layer S is, for example, silicon-doped, and the silicon doping concentration is 5x10 19 cm -3 ~ 9x1019 cm -3 The content of Al in the guiding layer S is x = 0.05-0.15, for example, x = 0.1. The thickness of the guiding layer S is 5-15 nm.

[0116] Further, the epitaxial layer 120 is etched by electrochemical etching to form a nanopore array in at least the guiding layer S and the first semiconductor layer 123.

[0117] In this step, the epitaxial layer 120 is immersed in an acid solution to electrochemically etch the epitaxial layer 120. The acid solution may, for example, be a mixed solution of concentrated nitric acid and ethanol, and in other embodiments, the acid solution may also be a mixed solution of concentrated nitric acid, concentrated hydrofluoric acid, concentrated hydrofluoric acid and ethanol, concentrated nitric acid and isopropanol, concentrated hydrofluoric acid and isopropanol, etc. In the electrochemical etching process, the epitaxial layer 120 (specifically, the second semiconductor layer 126 in the epitaxial layer 120) and the metal electrode in a network structure are connected together as an anode, and a platinum electrode is used as a cathode to electrochemically etch the epitaxial layer 120. The working voltage of the electrochemical etching is 10-20 V (for example, 15 V), and the etching time is 30-180 seconds (for example, 60 seconds).

[0118] Since the doping concentration of the barrier layer S0 is lower than that of the first semiconductor layer 123 and the guiding layer S, the barrier layer S0 acts as a barrier layer for electrochemical etching and does not etch the multi-quantum well layer 124 during the electrochemical etching process; the doping concentration of the guiding layer S is high, and the nanopore array perpendicular to the surface of the first semiconductor layer 123, for example, the (0001) plane, is formed in the guiding layer S and the first semiconductor layer 123 with the help of the guiding layer S to adjust the light emission of the light-emitting diode.

[0119] The nanopore array is perpendicular to the surface of the substrate 110, and the nanopore array is located at least in the guiding layer S and the first semiconductor layer 123, i.e., in the direction from the multi-quantum well layer 124 to the substrate 110, the nanopore array at least penetrates the guiding layer S and stops at any one of the first semiconductor layer 123, the unintentionally doped layer 122, and the buffer layer 121. The characteristic size of the nanopores in the nanopore array is several nanometers to several tens of nanometers, and specifically, the diameter of the nanopores in the nanopore array is 10-70 nm.

[0120] As shown in FIG. 1C, a step is formed around the epitaxial layer 120. Figure 2b

[0121] ​In this step, the step is formed around the epitaxial layer 120 by using photolithography and dry etching process. Specifically, a resist mask with an opening is formed on the surface of the epitaxial layer 120 (specifically, the second semiconductor layer 126), dry etching is performed on the second semiconductor layer 126, the electron blocking layer 125, the multi-quantum well layer 124, the barrier layer S0 and the guide layer S in sequence through the opening of the resist mask, and the surface of the first semiconductor layer 123 is exposed to form the step. The step is located at the four edges of the epitaxial layer 120.

[0122] As shown in Figure 2c , the second ohmic contact layer 132 is formed on the surface of the second semiconductor layer 126 (the upper step surface of the step), and the first ohmic contact layer 131 is formed on the surface of the first semiconductor layer 123 (the lower step surface of the step).

[0123] In this step, the second ohmic contact layer 132 is formed on the surface of the second semiconductor layer 126 (the upper step surface of the step) by using photolithography and dry etching, and high-temperature annealing is performed to form a good ohmic contact between the second ohmic contact layer 132 and the second semiconductor layer 126.

[0124] Further, the first ohmic contact layer 131 is formed on the surface of the first semiconductor layer 123 (the lower step surface of the step) by using physical vapor deposition, photolithography and etching process. The first ohmic contact layer 131 on the surface of the first semiconductor layer 123 forms a good ohmic contact with the first semiconductor layer 123. There is a gap between the first ohmic contact layer 131 and the sidewall of the step.

[0125] In this embodiment, the second ohmic contact layer 132 is made of ITO material, for example, and has a thickness of 100 nm, but is not limited thereto. The first ohmic contact layer 131 includes at least one of chromium, aluminum, titanium and platinum, for example.

[0126] As shown in Figure 2d , the dielectric layer 140 is formed on the lower step surface of the step, the sidewall of the step, the surface and sidewall of the first ohmic contact layer 131, and the surface and sidewall of the second ohmic contact layer 132.

[0127] In this step, a dielectric layer 140 with a thickness of 200 nanometers, for example, is deposited on the surface of the above semiconductor structure by using PECVD deposition process. The dielectric layer 140 covers the lower step surface of the step, the sidewall of the step, the surface and sidewall of the first ohmic contact layer 131, and the surface and sidewall of the second ohmic contact layer 132. The dielectric layer 140 includes but is not limited to silicon nitride, silicon oxide, silicon oxynitride and other insulating dielectrics.

[0128] As shown in Figure 2eAs shown in the figure, a mirror layer 150 is formed on the surface of the dielectric layer 140. The mirror layer 150 covers the dielectric layer 140, and is, for example, a DBR mirror layer composed of SiO2 / TiO2, but is not limited thereto.

[0129] As shown in the figure, the mirror layer 150 and the dielectric layer 140 are etched to form a first opening 141 and a second opening 142 penetrating through the mirror layer 150 and the dielectric layer 140. Figure 2f

[0130] In this step, the first opening 141 exposing part of the surface of the first ohmic contact layer 131 and the second opening 142 exposing part of the surface of the second ohmic contact layer 132 are formed in the mirror layer 150 and the dielectric layer 140. Further, for example, the first opening 141 and the second opening 142 are prepared in the mirror layer 150 and the dielectric layer 140 by using photolithography and dry etching process to communicate with part of the first ohmic contact layer 131 and part of the second ohmic contact layer 132.

[0131] As shown in the figure, the first electrode 161 and the second electrode 162 are formed. Figure 2g

[0132] In this step, a metal layer is prepared on the mirror layer 150 by using photolithography and physical vapor deposition process. The metal layer filling the first opening 141 and connecting with the first ohmic contact layer 131 is the first electrode 161, the metal layer filling the second opening 142 and connecting with the second ohmic contact layer 132 is the second electrode 162, and the first electrode 161 and the second electrode 162 on the surface of the mirror layer 150 are not in contact.

[0133] The material of the first electrode 161 and the second electrode 162 is at least one of titanium, gold and tin.

[0134] Figure 3 A cross-sectional schematic view of a light emitting diode according to a second embodiment of the present application is shown. As shown in the figure, a GaN-based light emitting diode in flip-chip structure is taken as an example for illustration, however, the present application is not limited thereto. Figure 3

[0135] The light emitting diode comprises a substrate 110, an epitaxial layer 120, a barrier layer S0, a guide layer S, a first ohmic contact layer 131, a second ohmic contact layer 132, a dielectric layer 140, a mirror layer 150, a first electrode 161 and a second electrode 162.

[0136] ​​​The substrate 110 is a heterogeneous substrate, including Ga2O3, SiC, sapphire, ZnO, LiGaO2, and other transparent single crystal substrates. The surface of the substrate 110 can also be pre-deposited with an AlN film, a BAlN film, a BN film, a graphene film, and the like. Further, the surface of the substrate 110 has a patterned structure with a feature size ranging from hundreds of nanometers to several microns. The thickness of the substrate 110 is 300 microns to 2 millimeters.

[0137] In this embodiment, the substrate 110 is, for example, a sapphire substrate, including but not limited to one of a mirror or a micron / nanometer patterned sapphire substrate, and the preferred option is a mirror sapphire.

[0138] The epitaxial layer 120 is located on the surface of the substrate 110, and can be a polycrystalline or single crystal structure, including one of a reciprocating continuous progressive epitaxial layer composed of a GaN / InGaN material system, and the preferred embodiment is an InGaN structure with different In components.

[0139] The epitaxial layer 120 includes a buffer layer 121, an unintentionally doped layer 122, a first semiconductor layer 123, a multiple quantum well layer 124, an electron blocking layer 125, and a second semiconductor layer 126 stacked in sequence. In this embodiment, the buffer layer 121 is, for example, a gallium nitride (GaN) material layer, the unintentionally doped layer 122 is, for example, an unintentionally doped gallium nitride (GaN) material layer, the first semiconductor layer 123 is, for example, a first doping type (N-type) gallium nitride (GaN) material layer, the multiple quantum well (MQW) layer 125 includes at least one period of quantum wells corresponding to a wavelength range of 360nm-600nm, the electron blocking layer 125 is, for example, a second doping type (P-type) aluminum gallium nitride (AlGaN) material layer, and the second semiconductor layer 126 is, for example, a second doping type (P-type) gallium nitride (GaN) material layer. The multiple quantum well layer 124 is, for example, composed of aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), indium gallium nitride (InGaN), and the like. The total thickness of the epitaxial layer 120 is, for example, 5 microns-10 microns.

[0140] The barrier layer S0 is located in the epitaxial layer 120, specifically between the first semiconductor layer 123 and the multiple quantum well layer 124, and has the same doping type as the first semiconductor layer 123, for example, N-type doping.

[0141] The guide layer S is located in the epitaxial layer 120, and specifically between the first semiconductor layer 123 and the barrier layer S0. The guide layer S has the same doping type as the first semiconductor layer 123, for example, N-type doping.

[0142] The barrier layer S0 is a lightly doped gallium nitride (GaN) material layer. Specifically, the guide layer S is doped with silicon, for example, and the doping concentration is 5x10 19 cm -3 ~ 9x10 19 cm -3 . The thickness of the barrier layer S0 is, for example, 20nm-100nm. The guide layer S is a heavily doped, low Al component aluminum gallium nitride (Al x Ga 1-x N) material layer. Specifically, the guide layer S is doped with silicon, for example, and the silicon doping concentration ranges from 5x10 19 cm -3 ~ 9x10 19 cm -3 . The component content x of Al in the guide layer S is 0.05-0.15, for example, 0.1. The thickness of the guide layer S is 5nm-15nm.

[0143] The epitaxial layer 120 has a nanohole array, which is perpendicular to the surface of the substrate 110. The nanohole array is located at least in the guide layer S and the first semiconductor layer 123, i.e. from the multi-quantum well layer 124 to the substrate 110, the nanohole array at least penetrates the guide layer S and stops at any one of the first semiconductor layer 123, the unintentionally doped layer 122, and the buffer layer 121. The characteristic size of the nanohole in the nanohole array is several nanometers to several tens of nanometers, and specifically, the diameter of the nanohole in the nanohole array is 10nm-70nm.

[0144] The epitaxial layer 120 has at least one through hole, which penetrates the second semiconductor layer 126, the electron barrier layer 125, the multi-quantum well layer 124, the barrier layer S0, and the guide layer S in turn, and exposes the surface of the first semiconductor layer 123.

[0145] The first ohmic contact layer 131 is located on the surface of the first semiconductor layer 123 exposed by the through hole, and is in ohmic contact with the first semiconductor layer 123. There is a gap between the first ohmic contact layer 131 and the sidewall of the through hole. The second ohmic contact layer 132 is located on the surface of the second semiconductor layer 126 layer, and is in ohmic contact with the second semiconductor layer 126.

[0146] The first ohmic contact layer 131 includes, for example, at least one material selected from chromium, aluminum, titanium, and platinum, and the second ohmic contact layer 132 is made of, for example, ITO material, but is not limited thereto.

[0147] The reflector layer 150 is located on the surface of the second ohmic contact layer 132. The reflector layer 150 is, for example, a metal reflector, and the material is, for example, at least one of Ag, Ti, and W. The reflector layer 150 can also be a DBR or ODR reflector layer, but is not limited thereto.

[0148] The dielectric layer 140 covers the surface and sidewalls of the mirror layer 150, the sidewalls of the second ohmic contact layer 132, and the sidewalls of the via. The dielectric layer 140 has a first opening and a second opening. The first opening exposes the first ohmic contact layer 131 at the bottom of the via 1201, and the second opening exposes a portion of the surface of the mirror layer 150. The dielectric layer 140 includes, but is not limited to, insulating dielectrics such as silicon nitride, silicon oxide, and silicon oxynitride.

[0149] The first electrode 161 is located on the surface of the dielectric layer 140 and contacts the first ohmic contact layer 131 via a first opening. The second electrode 162 is located on the surface of the dielectric layer 140 and contacts the reflector layer 150 via a second opening. The first electrode 161 and the second electrode 162 are separated from each other. The materials of the first electrode 161 and the second electrode 162 are at least one of titanium, gold, and tin.

[0150] Figures 4a to 4g The accompanying drawings show cross-sectional views of a light-emitting diode at different stages of its manufacturing process according to a second embodiment of the present invention. The manufacturing method provided in this embodiment operates on an entire wafer, and the drawings only show one chip unit.

[0151] like Figure 4a As shown, an epitaxial layer 120 and a barrier layer S0 are prepared on the surface of a substrate 110 by an epitaxial growth process.

[0152] In this step, for example, the epitaxial layer 120 is formed on the surface of the substrate 110 using a metal-organic chemical vapor deposition process. In alternative embodiments, the epitaxial layer 120 may also be formed using processes such as laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy.

[0153] The substrate 110 is a hetero-substrate, including Ga2O3, SiC, sapphire, ZnO, LiGaO2, and other transparent single crystal substrates. The surface of the substrate 110 can also be pre-deposited with an AlN film, a BAlN film, a BN film, a graphene film, and the like. Further, the surface of the substrate 110 has a patterned structure with a feature size ranging from hundreds of nanometers to several microns. The thickness of the substrate 110 is 300 microns to 2 millimeters. In the present embodiment, the substrate 110 is, for example, a sapphire substrate, including but not limited to one of a mirror surface or a micron / nanometer patterned sapphire substrate, with the preferred option being a mirror surface sapphire.

[0154] The epitaxial layer 120 can be a polycrystalline or single crystal structure, including one of a reciprocating continuous progression epitaxial layer composed of a GaN / InGaN material system, with the preferred embodiment being an InGaN structure containing different In components.

[0155] The epitaxial layer 120 includes, in order, a buffer layer 121, an unintentionally doped layer 122, a first semiconductor layer 123, a multiple quantum well layer 124, an electron blocking layer 125, and a second semiconductor layer 126. In the present embodiment, the buffer layer 121 is, for example, a gallium nitride (GaN) material layer, the unintentionally doped layer 122 is, for example, an unintentionally doped gallium nitride (GaN) material layer, the first semiconductor layer 123 is, for example, a first doping type (N-type) gallium nitride (GaN) material layer, the multiple quantum well (MQW) layer 125 includes at least one period of quantum wells corresponding to a wavelength range of 360nm-600nm, the electron blocking layer 125 is, for example, a second doping type (P-type) aluminum gallium nitride (AlGaN) material layer, and the second semiconductor layer 126 is, for example, a second doping type (P-type) gallium nitride (GaN) material layer. The MQW multiple quantum well structure is composed of, for example, aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), indium gallium nitride (InGaN), and the like. The total thickness of the epitaxial layer 120 is, for example, 5 microns-10 microns.

[0156] The barrier layer S0 is located in the epitaxial layer 120, specifically between the first semiconductor layer 123 and the multiple quantum well layer 124, and has the same doping type as the first semiconductor layer 123, for example, N-type doping.

[0157] The guide layer S is located in the epitaxial layer 120, specifically between the first semiconductor layer 123 and the barrier layer S0, and has the same doping type as the first semiconductor layer 123, for example, N-type doping.

[0158] The barrier layer S0 is a lightly doped gallium nitride (GaN) material layer. Specifically, the guiding layer S is, for example, silicon doped with a doping concentration of 5 x 10⁻⁶. 19 cm -3 ~9x10 19 cm -3 The thickness of the barrier layer S0 is, for example, 20 nm to 100 nm. The guiding layer S is heavily doped, low-Al content aluminum gallium nitride (Al₂O₃). x Ga 1-x N) Material layer, specifically, the guiding layer S is, for example, silicon doped with a silicon doping concentration in the range of 5 x 10⁻⁶. 19 cm -3 ~9x10 19 cm -3 The Al content x in the guiding layer S is 0.05 to 0.15, for example, 0.1. The thickness of the guiding layer S is 5 nm to 15 nm.

[0159] like Figure 4b As shown, a plurality of mutually separated protective layers 170 are formed on the surface of the second semiconductor layer 126. The area covered by the protective layers 170 is subsequently etched to form vias 1201. In this embodiment, the material of the protective layers 170 is, for example, silicon oxide (SiO2).

[0160] Furthermore, the epitaxial layer 120 is etched by electrochemical etching to form a nanopore array in at least the guiding layer S and the first semiconductor layer 123.

[0161] In this step, the epitaxial layer 120 is immersed in an acidic solution to perform electrochemical etching. The acidic solution is, for example, a mixture of concentrated hydrofluoric acid and ethanol. In other embodiments, the acidic solution may also be concentrated nitric acid, concentrated hydrofluoric acid, or a mixture of concentrated nitric acid and ethanol. During the electrochemical etching process, the epitaxial layer 120 (specifically, the second semiconductor layer 126 within the epitaxial layer 120) and a mesh-structured metal electrode are connected together as the anode, and a platinum electrode is used as the cathode to electrochemically etch the epitaxial layer 120. The operating voltage for electrochemical etching is 10V to 20V (e.g., 15V), and the etching time is 30 seconds to 180 seconds (e.g., 60 seconds). After electrochemical etching, the protective layer 170 is removed.

[0162] Since the doping concentration of the barrier layer S0 is lower than that of the first semiconductor layer 123 and the guide layer S, the barrier layer S0 acts as a barrier layer for electrochemical corrosion and will not corrode the multi-quantum well layer 124 during the electrochemical corrosion process. The guide layer S has a higher doping concentration. With the help of the guide layer S, a nanopore array perpendicular to the surface of the first semiconductor layer 123, such as the (0001) plane, is formed in the guide layer S and the first semiconductor layer 123 to adjust the light output of the light-emitting diode.

[0163] The nanopore array is perpendicular to the surface of the substrate 110. The nanopore array is located at least in the guiding layer S and the first semiconductor layer 123, i.e., in the direction from the multi-quantum well layer 124 to the substrate 110. The nanopore array penetrates at least the guiding layer S and terminates at any one of the first semiconductor layer 123, the unintentionally doped layer 122, and the buffer layer 121. The characteristic size of the nanopores in the nanopore array is from several nanometers to tens of nanometers; specifically, the diameter of the nanopores in the nanopore array is 10 nm to 70 nm.

[0164] like Figure 4c As shown, a through-hole 1201 is formed in the epitaxial layer 120.

[0165] In this step, for example, photolithography and dry etching processes are used to form at least one via 1201 in the epitaxial layer 120. Specifically, a resist mask with an opening is formed on the surface of the epitaxial layer 120 (specifically the second semiconductor layer 126). Dry etching is performed sequentially through the opening of the resist mask on the second semiconductor layer 126, the electron blocking layer 125, the multiple quantum well layer 124, the blocking layer S0, and the guiding layer S to expose the surface of the first semiconductor layer 123 to form the via 1201.

[0166] like Figure 4d As shown, a first ohmic contact layer 131 is formed on the surface of the first semiconductor layer 123 in the through hole 1201, and a second ohmic contact layer 132 and a mirror layer 150 are formed on the surface of the second semiconductor layer 126.

[0167] In this step, for example, photolithography and dry etching are used to form a second ohmic contact layer 132 on the surface of the second semiconductor layer 126, followed by high-temperature annealing to ensure good ohmic contact between the second ohmic contact layer 132 and the second semiconductor layer 126. The reflector layer 150 is then formed on the second ohmic contact layer 132.

[0168] Furthermore, a first ohmic contact layer 131 is formed on the surface of the first semiconductor layer 123 exposed by the through-hole 1201.

[0169] In this step, a first ohmic contact layer 131 is formed on the surface of the first semiconductor layer 123 exposed by the via hole 1201 by physical vapor deposition and photolithography and etching processes. The first ohmic contact layer 131 on the surface of the first semiconductor layer 123 forms a good ohmic contact with the first semiconductor layer 123. There is a gap between the first ohmic contact layer 131 and the sidewall of the via hole 1201.

[0170] In this embodiment, the second ohmic contact layer 132 is made of ITO material, for example, and has a thickness of 10 nm, for example, but is not limited thereto. The material of the mirror layer 150 is at least one of silver, titanium, and tungsten, for example, but is not limited thereto. The material of the first ohmic contact layer 131 includes at least one of chromium, aluminum, titanium, and platinum, for example.

[0171] As shown in FIG. 1C, a dielectric layer 140 is formed. Figure 4e

[0172] In this step, a dielectric layer 140 with a thickness of 1 micron, for example, is deposited on the surface of the semiconductor structure by a PECVD deposition process. The dielectric layer 140 is on the surface of the mirror layer 150 and fills the via hole 1201. The dielectric layer 140 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and other insulating dielectrics.

[0173] As shown in FIG. 1D, the dielectric layer 140 is etched to form a first opening 141 and a second opening 142 that pass through the dielectric layer 140. Figure 4f In this step, the first opening 141 that exposes part of the surface of the first ohmic contact layer 131 and the second opening 142 that exposes part of the surface of the mirror layer 150 are formed in the dielectric layer 140 by photolithography and dry etching processes.

[0174] As shown in FIG. 1E, a first electrode 161 and a second electrode 162 are formed.

[0175] Figure 4g In this step, a metal layer is prepared on the dielectric layer 140 by photolithography and physical vapor deposition processes. The metal layer that fills the first opening 141 and is connected to the first ohmic contact layer 131 serves as the first electrode 161, the metal layer that fills the second opening 142 and is connected to the mirror layer 150 serves as the second electrode 162, and the first electrode 161 and the second electrode 162 on the surface of the dielectric layer 140 do not contact each other.

[0176] The material of the first electrode 161 and the second electrode 162 is at least one of titanium, gold, and tin.

[0177] The material of the first electrode 161 and the second electrode 162 is at least one of titanium, gold, and tin.

[0178] ​​The application provides a light emitting diode and a manufacturing method thereof. A guide layer and a barrier layer are arranged between the first semiconductor layer and the multi-quantum well layer. The barrier layer serves as a barrier layer of electrochemical corrosion and protects the multi-quantum well layer from electrochemical corrosion. The guide layer serves as a guide layer of electrochemical corrosion, and a nano-pore array is formed in the guide layer and the first semiconductor layer to adjust the light emission of the light emitting diode.

[0179] The nano-pore array is perpendicular to the surface of the first semiconductor layer and is arranged in the guide layer and the first semiconductor layer, so as to significantly reduce the total reflection effect of the light emitting diode and improve the light extraction efficiency of the light emitting diode.

[0180] Further, the nano-pore array can provide a larger n-type ohmic contact area and reduce the voltage of the light emitting diode.

[0181] Further, the nano-pore array can reduce the compressive stress in the epitaxial layer, relieve the quantum confinement Stark effect (QCSE), further improve the internal quantum efficiency, and has great significance for realizing the industrialization of high-performance and high-power flip-chip light emitting diodes.

[0182] Further, the barrier layer has a lower doping concentration than the first semiconductor layer and the guide layer, so as to serve as a barrier layer of electrochemical corrosion and not corrode the multi-quantum well layer during the electrochemical corrosion process. The guide layer has a higher doping concentration, and the nano-pore array is formed in the guide layer and the first semiconductor layer perpendicular to the surface thereof with the help of the guide layer.

[0183] According to the embodiments of the application described above, the embodiments do not describe all the details and limit the application to the specific embodiments. It is obvious that many modifications and changes can be made according to the above description. The embodiments are selected and described in the specification in order to better explain the principles and practical applications of the application, so that those skilled in the art can well utilize the application and make modifications and uses on the basis of the application. The application is limited by the claims and their full scope and equivalents.

Claims

1. A light emitting diode, characterized by, The application relates to a substrate, an epitaxial layer on the substrate, the epitaxial layer comprising a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer stacked in sequence from bottom to top, the first semiconductor layer and the second semiconductor layer being of opposite doping types, a barrier layer between the first semiconductor layer and the multiple quantum well layer for protecting the multiple quantum well layer, a guide layer between the first semiconductor layer and the barrier layer, and a nanopore array perpendicular to the surface of the first semiconductor layer and located in at least the guide layer and the first semiconductor layer, the barrier layer having a lower doping concentration than the first semiconductor layer and the guide layer. The barrier layer is a GaN material layer with a first doping type. The thickness of the barrier layer and the guide layer ranges from 20nm to 100nm. The thickness of the guide layer ranges from 5nm to 15nm. The barrier layer serves as a barrier layer for electrochemical corrosion, and the guide layer serves as a guide layer for electrochemical corrosion to form a nanopore array in at least the guide layer and the first semiconductor layer. The diameter of the nanopores in the nanopore array ranges from 10nm to 70nm. The epitaxial layer further comprises a buffer layer on the substrate, an unintentionally doped layer on the buffer layer, the first semiconductor layer on the unintentionally doped layer, an electron barrier layer on the multiple quantum well layer, and the second semiconductor layer on the electron barrier layer. The nanopore array is also located in the unintentionally doped layer or in the unintentionally doped layer and the buffer layer.

2. The light emitting diode of claim 1, wherein, The application further comprises a step on the periphery of the epitaxial layer, the step penetrating through the second semiconductor layer, the multiple quantum well layer, the barrier layer and the guide layer to expose the surface of the first semiconductor layer, a first ohmic contact layer on the surface of the first semiconductor layer of the lower step face, and a second ohmic contact layer on the surface of the second semiconductor layer of the upper step face.

3. The light emitting diode of claim 1, wherein, The guiding layer is AlxGa1-xN, wherein x is 0.05-0.15 x Ga 1-x N material layer, wherein x is 0.05-0.

15.

4. The light emitting diode of claim 1, wherein, The barrier layer is doped with silicon at a concentration of 5 x 10 17 cm -3 1 x 10 18 cm -3 .

5. The light emitting diode of claim 1, wherein, The guiding layer is doped with silicon, with a doping concentration of 5 x 10 19 cm -3 9 x 10 19 cm -3 .

6. The light emitting diode of claim 1, wherein, The application further comprises at least one via in the epitaxial layer, the via penetrating through the second semiconductor layer, the multiple quantum well layer, the barrier layer and the guide layer to expose the surface of the first semiconductor layer, a first ohmic contact layer on the surface of the first semiconductor layer exposed by the via, a second ohmic contact layer on the surface of the second semiconductor layer, and a mirror layer on the surface of the second ohmic contact layer.

7. The light emitting diode of claim 1, wherein, The application further comprises a dielectric layer covering the sidewalls of the step, the sidewalls and part of the surface of the first ohmic contact layer, the sidewalls and part of the surface of the second ohmic contact layer, the dielectric layer having a first opening exposing part of the first ohmic contact layer and a second opening exposing part of the second ohmic contact layer, a first electrode on the dielectric layer and electrically connected to the first ohmic contact layer through the first opening, and a second electrode on the dielectric layer and electrically connected to the second ohmic contact layer through the second opening.

8. The light emitting diode of claim 1, wherein, The application further comprises 9. The light emitting diode of claim 1, wherein, ​ 10. The light emitting diode of claim 1, wherein, ​ ​ ​ ​ ​ 11. The light emitting diode of claim 10, wherein, ​ 12. The light emitting diode of claim 1, wherein, ​ ​ ​ ​ ​ 13. The light emitting diode of claim 1, wherein, ​ ​ ​ ​ ​ 14. The light emitting diode of claim 12, wherein, ​ ​ ​ ​ ​ 15. The light emitting diode of claim 13, wherein the first and second semiconductor layers are formed of a group III-V compound semiconductor. ​ A dielectric layer covers sidewalls and part of surfaces of the mirror layer, sidewalls of the second ohmic contact layer, and sidewalls of the via, the dielectric layer having a first opening exposing the first ohmic contact layer and a second opening exposing part of the mirror layer; A first electrode is on the dielectric layer and is electrically connected with the first ohmic contact layer via the first opening; and A second electrode is on the dielectric layer and is electrically connected with the mirror layer via the second opening. Further comprising a mirror layer on the dielectric layer, the mirror layer having a first opening exposing part of the first ohmic contact layer and a second opening exposing part of the second ohmic contact layer, the first electrode and the second electrode being on the mirror layer.

16. The light emitting diode of claim 14, wherein, The method comprises:

17. A method of fabricating a light emitting diode, characterized by: forming an epitaxial layer on a substrate, the epitaxial layer comprising, from bottom to top, a first semiconductor layer, a guide layer, a barrier layer, a multiple quantum well layer, and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer having opposite doping types; electrochemically etching the epitaxial layer to form an array of nanopores perpendicular to a surface of the first semiconductor layer and located at least in the guide layer and the first semiconductor layer; the barrier layer has a lower doping concentration than the first semiconductor layer and the guide layer; the barrier layer protects the multiple quantum well layer from electrochemical etching; the guide layer guides the electrochemical etching to form the array of nanopores at least in the guide layer and the first semiconductor layer. The barrier layer is a GaN material layer having a first doping type.

18. The method of manufacturing a light emitting diode according to claim 17, wherein The thickness of the barrier layer ranges from 20 nm to 100 nm.

19. The method of claim 17, wherein The guiding layer is AlxGa1-xN, wherein x is 0.05-0.15 x Ga 1-x N material layer, wherein x is 0.05-0.

15.

20. The method of claim 17, wherein The barrier layer is doped with silicon at a concentration of 5 x 10 17 cm -3 ~1 x10 18 cm -3 .

21. The method of claim 17, wherein The guiding layer is doped with silicon, with a doping concentration of 5 x 10 19 cm -3 ~9 x10 19 cm -3 .

22. The method of claim 17, wherein the method further comprises: The thickness of the guide layer ranges from 5 nm to 15 nm.

23. The method of claim 17, wherein the method further comprises: The etching solution for the electrochemical etching is one of concentrated nitric acid, concentrated hydrofluoric acid, a mixture of concentrated nitric acid and ethanol, a mixture of concentrated hydrofluoric acid and ethanol, a mixture of concentrated nitric acid and isopropanol, and a mixture of concentrated hydrofluoric acid and isopropanol.

24. The method of claim 17, wherein the light emitting diode is formed on a substrate. The working voltage for the electrochemical etching ranges from 10 V to 20 V.

25. The method of claim 17, wherein the method further comprises: The etching time for the electrochemical etching ranges from 30 seconds to 180 seconds.

26. The method of claim 17, wherein During the electrochemical etching, the second semiconductor layer is used as an anode, and a platinum electrode is used as a cathode.

27. The method of claim 17, wherein the method further comprises forming a passivation layer on the light emitting diode. The diameter of the nanopores in the array of nanopores ranges from 10 nm to 70 nm.

28. The method of claim 17, wherein the method further comprises: The method further comprises:

29. The method of claim 17, wherein the method further comprises: forming, on the substrate, a buffer layer and an unintentionally doped layer in sequence, the first semiconductor layer being on the unintentionally doped layer; and forming an electron blocking layer on the multiple quantum well layer, the second semiconductor layer being on the electron blocking layer. The array of nanopores is also located in the unintentionally doped layer or in the unintentionally doped layer and the buffer layer.

30. The method of claim 29, wherein The method further comprises:

31. The method of claim 17, wherein: etching the second semiconductor layer, the multiple quantum well layer, the barrier layer, and the guide layer in sequence to form a step around the epitaxial layer, the step exposing a surface of the first semiconductor layer; forming a first ohmic contact layer on the surface of the first semiconductor layer; and forming a second ohmic contact layer on a surface of the second semiconductor layer. The method further comprises: ​ 32. The method of claim 17, wherein ​ sequentially etching the second semiconductor layer, the multiple quantum well layer, the barrier layer and the guide layer to form at least one via hole, the via hole exposing a surface of the first semiconductor layer; forming a first ohmic contact layer on the surface of the first semiconductor layer; and sequentially forming a second ohmic contact layer and a mirror layer on the surface of the second semiconductor layer.

33. The method of claim 32, wherein the method further comprises: Before forming the via hole, further comprising forming a protective layer on the surface of the second semiconductor layer, the protective layer covering the area where the via hole is formed, performing electrochemical etching after forming the protective layer, and removing the protective layer after the electrochemical etching.

34. The method of claim 31, wherein Further comprising: forming a dielectric layer having a first opening and a second opening, the dielectric layer covering the sidewall of the step, the sidewall and part of the surface of the first ohmic contact layer, the sidewall of the second ohmic contact layer, and the sidewall of the via hole, the first opening exposing part of the first ohmic contact layer, and the second opening exposing part of the second ohmic contact layer; forming a first electrode on the dielectric layer, the first electrode being electrically connected to the first ohmic contact layer via the first opening; and forming a second electrode on the dielectric layer, the second electrode being electrically connected to the second ohmic contact layer via the second opening.

35. The method of claim 32, wherein: Further comprising: forming a dielectric layer having a first opening and a second opening, the dielectric layer covering the sidewall and part of the surface of the mirror layer, the sidewall of the second ohmic contact layer, and the sidewall of the via hole, the dielectric layer having a first opening exposing the first ohmic contact layer and a second opening exposing part of the mirror layer; forming a first electrode on the dielectric layer, the first electrode being electrically connected to the first ohmic contact layer via the first opening; and forming a second electrode on the dielectric layer, the second electrode being electrically connected to the mirror layer via the second opening.

36. The method of claim 34, wherein the method further comprises: Further comprising forming a mirror layer on the dielectric layer, the mirror layer having a first opening exposing part of the first ohmic contact layer and a second opening exposing part of the second ohmic contact layer, the first electrode and the second electrode being located on the mirror layer.

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