A Micro LED Chip and Its Fabrication Method

Abstract

The application relates to a MicroLED chip and a manufacturing method thereof, and belongs to the technical field of semiconductors.The MicroLED chip comprises a DBR reflection layer, an epitaxial structure located above the DBR reflection layer, a current blocking layer located above the epitaxial structure, a transparent conductive layer located above the epitaxial structure and the current blocking layer, an extension electrode located above the transparent conductive layer, an insulating protective layer located above the DBR reflection layer, the epitaxial structure, the current blocking layer, the transparent conductive layer and the extension electrode, and a soldering electrode located above the epitaxial structure, the extension electrode and the insulating protective layer, so that a novel chip structure is provided, a positive chip structure is adopted, positive and negative soldering electrodes are in the same height, and the MicroLED chip structure is expanded.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a Micro LED chip and its fabrication method. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device that converts electric current into light within a specific wavelength range. Its light-emitting principle relies on the energy difference of electrons moving between n-type and p-type semiconductors, releasing energy in the form of light. Therefore, LEDs are called cold light sources. They possess advantages such as low power consumption, small size, high brightness, easy integration with integrated circuits, and high reliability, making them widely used as light sources. Furthermore, with the maturity of LED technology, LED displays or Micro LED (micro-LED) displays, which directly utilize LEDs as self-emissive display pixels, are gradually becoming more widely used.

[0003] Micro LED refers to LED chips with a size of <50μm. It is considered the most likely to replace OLED as the next-generation mainstream display technology. Due to its small size, its pixel pitch can be below P0.5, making it widely used in devices and applications requiring high brightness, ultra-high resolution, and high color saturation. Because the chip is small, the bonding area is limited. Therefore, it is required that the positive and negative bonding electrodes be as equal in height as possible. However, most current Micro LED chips use a flip-chip structure where the growth substrate is peeled off (the light emission direction is opposite to the electrode direction), making it impossible to achieve the requirement of the positive and negative bonding electrodes being as equal in height as possible. Summary of the Invention

[0004] The purpose of this invention is to provide a Micro LED chip and its manufacturing method, which adopts a positively mounted chip structure in which the light emission direction is the same as the electrode direction, and makes the positive and negative welding electrodes of the chip at the same height.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A Micro LED chip, the chip comprising a DBR reflective layer, an epitaxial structure, a first current blocking layer, a second current blocking layer, a transparent conductive layer, a first extended electrode, a second extended electrode, an insulating protective layer, a first welding electrode, and a second welding electrode;

[0007] The epitaxial structure is disposed on the DBR reflective layer;

[0008] The first current blocking layer and the second current blocking layer are disposed on the epitaxial structure and located at both ends of the epitaxial structure;

[0009] The transparent conductive layer is disposed on the first current blocking layer, the second current blocking layer, and the epitaxial structure located between the first current blocking layer and the second current blocking layer;

[0010] The first extended electrode and the second extended electrode are disposed at intervals on the transparent conductive layer;

[0011] The insulating protective layer covers the outer surface of the structure consisting of the epitaxial structure, the first current blocking layer, the second current blocking layer, the transparent conductive layer, the first extended electrode, and the second extended electrode, and is in contact with the upper surface of the DBR reflective layer that is not in contact with the epitaxial structure;

[0012] The insulating protective layer has a first opening and a second opening; the first welding electrode is disposed on the insulating protective layer and is electrically connected to the first extended electrode through the first opening; the second welding electrode is disposed on the insulating protective layer and is electrically connected to the epitaxial structure through the second opening.

[0013] In the projection direction of the DBR reflective layer, the first current blocking layer, the first extended electrode, and the first welding electrode correspond to each other, and the second current blocking layer, the second extended electrode, and the second welding electrode correspond to each other.

[0014] A method for fabricating a Micro LED chip, the method comprising:

[0015] An epitaxial wafer is provided; the epitaxial wafer includes a growth substrate and an epitaxial structure stacked sequentially from bottom to top;

[0016] A first current blocking layer and a second current blocking layer are fabricated on the epitaxial structure;

[0017] A transparent conductive layer is fabricated on the first current blocking layer, the second current blocking layer, and the epitaxial structure;

[0018] A first extended electrode and a second extended electrode are fabricated on the transparent conductive layer;

[0019] An insulating protective layer is formed on the growth substrate, the epitaxial structure, the first current blocking layer, the second current blocking layer, the transparent conductive layer, the first extended electrode, and the second extended electrode.

[0020] A portion of the insulating protective layer is etched to form a first opening and a second opening; the first opening is used to expose a portion of the first extended electrode; the second opening is used to expose a portion of the epitaxial structure.

[0021] A first welding electrode is fabricated on the insulating protective layer and the first extended electrode. The first welding electrode is electrically connected to the first extended electrode through the first opening. A second welding electrode is fabricated on the insulating protective layer and the epitaxial structure. The second welding electrode is electrically connected to the epitaxial structure through the second opening, thereby forming an initial chip.

[0022] The initial chip is bonded to a temporary substrate by bonding.

[0023] The growth substrate is removed by laser lift-off.

[0024] A DBR reflective layer is fabricated under the epitaxial structure and the insulating protective layer;

[0025] Remove the temporary substrate to form a Micro LED chip.

[0026] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0027] This invention provides a Micro LED chip and its fabrication method, comprising a DBR reflective layer, an epitaxial structure above the DBR reflective layer, a current blocking layer above the epitaxial structure, a transparent conductive layer above the epitaxial structure and the current blocking layer, an extended electrode above the transparent conductive layer, an insulating protective layer above the DBR reflective layer, the epitaxial structure, the current blocking layer, the transparent conductive layer and the extended electrode, and a welding electrode above the epitaxial structure, the extended electrode and the insulating protective layer. This provides a novel chip structure, employing a positive-mounted chip structure with equal height for both positive and negative welding electrodes, thus expanding the Micro LED chip structure. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a traditional Micro LED chip in the existing technology;

[0030] Figure 2 This is a schematic diagram of the Micro LED chip provided in Embodiment 1 of the present invention;

[0031] Figure 3 This is a flowchart of the method for fabricating a Micro LED chip provided in Embodiment 2 of the present invention;

[0032] Figure 4 This is a schematic diagram of the growth substrate provided in Embodiment 2 of the present invention;

[0033] Figure 5 This is a schematic diagram of the structure of the initial epitaxial wafer provided in Embodiment 2 of the present invention;

[0034] Figure 6 This is a schematic diagram of the structure of the intermediate epitaxial wafer provided in Embodiment 2 of the present invention;

[0035] Figure 7 This is a schematic diagram of the structure of the epitaxial wafer provided in Embodiment 2 of the present invention;

[0036] Figure 8 This is a schematic diagram of the structure obtained after fabricating the current blocking layer according to Embodiment 2 of the present invention;

[0037] Figure 9 This is a schematic diagram of the structure obtained after fabricating the transparent conductive layer according to Embodiment 2 of the present invention;

[0038] Figure 10 This is a schematic diagram of the structure obtained after fabricating the extended electrode according to Embodiment 2 of the present invention;

[0039] Figure 11 This is a schematic diagram of the structure obtained after fabricating the insulating protective layer according to Embodiment 2 of the present invention;

[0040] Figure 12 This is a schematic diagram of the structure obtained after etching the insulating protective layer according to Embodiment 2 of the present invention;

[0041] Figure 13 This is a schematic diagram of the structure obtained after fabricating the welding electrode according to Embodiment 2 of the present invention;

[0042] Figure 14 This is a schematic diagram of the structure obtained after bonding to a temporary substrate according to Embodiment 2 of the present invention;

[0043] Figure 15 This is a schematic diagram of the structure obtained after removing the growth substrate according to Embodiment 2 of the present invention;

[0044] Figure 16 This is a schematic diagram of the structure obtained after fabricating the DBR reflective layer according to Embodiment 2 of the present invention;

[0045] Figure 17 This is a schematic diagram of the structure obtained after removing the temporary substrate, as provided in Embodiment 2 of the present invention.

[0046] Symbol explanation:

[0047] 01-Traditional epitaxial layer; 02-Traditional transparent conductive layer; 03-Traditional DBR reflective layer; 04-Traditional extended electrode; 05-Traditional bonding electrode; 1-Growth substrate; 2-Epiaxial structure; 3-Current blocking layer; 4-Transparent conductive layer; 5-Extended electrode; 6-Insulating protective layer; 7-Insulating protective layer window; 8-Bonding electrode; 9-Temporary substrate; 10-Bonding material; 11-DBR reflective layer. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] The purpose of this invention is to provide a Micro LED chip and its manufacturing method, which adopts a positively mounted chip structure in which the light emission direction is the same as the electrode direction, and makes the positive and negative welding electrodes of the chip at the same height.

[0050] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Example 1:

[0052] Because Micro LED chips are relatively small and the bonding area is limited, it is required that the positive and negative bonding electrodes of the chip be as equal in height as possible. Figure 1 As shown, most current Micro LED chips employ a flip-chip structure where the growth substrate is peeled off, meaning the light emission direction is opposite to the electrode direction. However, this cannot meet the requirement that the positive and negative bonding electrodes of the chip be as equal in height as possible. Therefore, the purpose of this embodiment is to provide a novel Micro LED chip structure. The light-emitting layer is located in the middle region of the Micro LED chip. Unlike the traditional flip-chip structure where the light emission direction is opposite to the electrode direction, this embodiment uses a right-mounted chip structure where the light emission direction is the same as the electrode direction. Under this special chip structure, the positive and negative bonding electrodes are made to be at the same height, thereby expanding the structure of the Micro LED chip.

[0053] like Figure 2 As shown, this embodiment provides a Micro LED chip, which includes a DBR reflective layer 11, an epitaxial structure 2, a first current blocking layer, a second current blocking layer, a transparent conductive layer 4, a first extended electrode, a second extended electrode, an insulating protective layer 6, a first welding electrode, and a second welding electrode.

[0054] The DBR reflective layer 11, also known as the DBR insulating and isolating reflective layer, comprises multiple layers of films made of different materials. These films can be made of SiO2, SiN, TiO2, Ta2O5, or MgF; that is, the DBR reflective layer 11 is a DBR reflective film layer structure formed by any combination of materials from SiO2, SiN, TiO2, Ta2O5, and MgF. A thicker layer results in better reflection, but also higher cost. In this embodiment, the thickness of the DBR reflective layer 11 is 1.5-10 μm, preferably 2.5-8 μm, and more preferably 3.5-5 μm, achieving an optimal balance between reflection performance and cost. In the 350-700 nm wavelength range, the reflectivity of the DBR reflective layer 11 is greater than 95%. Reflectivity is directly related to brightness; higher reflectivity results in higher chip brightness.

[0055] The epitaxial structure 2 is disposed on the DBR reflective layer 11. The angle between the epitaxial structure 2 and the horizontal direction containing the upper surface of the DBR reflective layer 11 is an acute angle, with an angle of 85-20°, preferably 75-35°, and more preferably 60-40°. This angle setting can increase light output. The epitaxial structure 2 includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially from bottom to top. The first semiconductor layer and the second semiconductor layer have opposite electrical properties; that is, when the first semiconductor layer is an N-type semiconductor, the second semiconductor layer is a P-type semiconductor; when the first semiconductor layer is a P-type semiconductor, the second semiconductor layer is an N-type semiconductor. Typically, the first semiconductor layer is an N-type semiconductor and the second semiconductor layer is a P-type semiconductor.

[0056] The epitaxial structure 2 can be fabricated by etching an initial epitaxial structure consisting of a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially, exposing the sides of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, as well as the surface of the first semiconductor layer. Optionally, plasma etching can be used for etching.

[0057] In this embodiment, the current blocking layer 3 is located at both ends of the epitaxial structure 2, comprising two opposing parts: a first current blocking layer and a second current blocking layer. The first and second current blocking layers are disposed on the epitaxial structure 2 at its two ends. Both the first and second current blocking layers are made of insulating and transparent materials, including one or more of SiO2, SiN, TiO2, Ta2O5, MgF, HfO, and Al2O3. Specifically, the materials of the first and second current blocking layers are SiO2, SiN, TiO2, Ta2O5, MgF, HfO, and Al2O3, or any combination thereof. The thickness of the first and second current blocking layers is 50-20000 Å, preferably 200-5000 Å, and more preferably 700-2500 Å. This selection of thickness achieves better insulation. In the 350-700 nm wavelength range, the transmittance of both the first and second current blocking layers is greater than 90%, achieving light transmission.

[0058] A transparent conductive layer 4 is disposed on a first current blocking layer, a second current blocking layer, and an epitaxial structure 2 located between the first and second current blocking layers. The transparent conductive layer 4 can be made of ITO, GaO, or ZnO, with a thickness of 100-3000 Å, preferably 300-2000 Å, and more preferably 600-900 Å. This selection of thickness achieves better current spreading. In the 350-700 nm wavelength range, the transmittance of the transparent conductive layer 4 is greater than 92%, thus achieving light transmission.

[0059] Extended electrodes 5 are located at both ends of the transparent conductive layer 4, comprising two opposing parts: a first extended electrode and a second extended electrode, which are spaced apart on the transparent conductive layer 4. The first and second extended electrodes have identical structures, both employing a metal stacked structure. The first extended electrode includes, from bottom to top, a bonding ohmic contact layer, a reflective layer, a blocking layer, a current spreading layer, an anti-etching layer, and a bonding layer, stacked sequentially. The bonding ohmic contact layer is made of one or more of Cr, Ni, and Ti, i.e., Cr, Ni, Ti, or any combination thereof, with a thickness of 10-50 Å, and exhibits good adhesion to the transparent conductive layer 4. The reflective layer is made of one or more of Al and Ag, i.e., Al, Ag, or any combination thereof, with a thickness of 500-3000 Å, and a reflectivity greater than 88% in the 350-700 nm wavelength range to improve light output. The barrier layer is made of one or more of Ti, Pt, and Ni, meaning the barrier layer is made of Ti, Pt, Ni, or any combination thereof, with a thickness of 500-3000 Å. The current spreading layer is made of one or more of Pt and Au, meaning the current spreading layer is made of Pt, Au, or any combination thereof, with a thickness of 2000-30000 Å. The etching stop layer is made of one or more of Pt and Ni, meaning the etching stop layer is made of Pt, Ni, or any combination thereof, with a thickness of 500-3000 Å. The bonding layer is made of one or more of Ti and Ni, meaning the bonding layer is made of Ti, Ni, or any combination thereof, with a thickness of 500-3000 Å.

[0060] The insulating protective layer 6 covers the outer surface of the structure composed of the epitaxial structure 2, the first current blocking layer, the second current blocking layer, the transparent conductive layer 4, the first extended electrode, and the second extended electrode, and is in contact with the upper surface of the DBR reflective layer 11 that is not in contact with the epitaxial structure 2. The insulating protective layer 6 is made of an insulating transparent material, including one or more of SiO2, SiN, TiO2, Ta2O5, MgF, HfO, and Al2O3, i.e., the material of the insulating protective layer 6 is SiO2, SiN, TiO2, Ta2O5, MgF, HfO, and Al2O3, or any combination thereof. The thickness of the insulating protective layer 6 is 2000-20000 Å, preferably 5000-15000 Å, and more preferably 7000-10000 Å, with the thickness selected to achieve better insulation. In the 350-700 nm wavelength range, the transmittance is greater than 90%, resulting in better light transmission.

[0061] The insulating protective layer 6 has a first opening and a second opening. Welding electrodes 8 are located at both ends of the insulating protective layer 6, comprising two opposing parts: a first welding electrode and a second welding electrode. The first welding electrode is disposed on the insulating protective layer 6 and connected to the first extended electrode via the first opening. The second welding electrode is disposed on the insulating protective layer 6 and connected to the epitaxial structure 2 via the second opening. The first and second welding electrodes have identical structures, both employing a metal stacked structure. The first welding electrode includes, from bottom to top, a bonding ohmic contact layer, a reflective layer, a barrier layer, and a welding layer, stacked sequentially. The bonding ohmic contact layer is made of one or more of Cr, Ni, and Ti, i.e., the bonding ohmic contact layer is made of Cr, Ni, Ti, or any combination thereof, with a thickness of 10-50 Å, and exhibits good ohmic contact performance with the epitaxial structure 2. The reflective layer is made of one or more of Al and Ag, meaning it is composed of Al, Ag, or any combination thereof, with a thickness of 500-3000 Å and a reflectivity greater than 88% in the 350-700 nm wavelength range. The barrier layer is made of one or more of Ti, Pt, and Ni, meaning it is composed of Ti, Pt, Ni, or any combination thereof, with a thickness of 500-3000 Å. The welding layer is made of one or more of Au, Sn, In, Ag, and Cu, meaning it is composed of Au, Sn, In, Ag, Cu, or any combination thereof, with a thickness of 0.1-30 μm.

[0062] In the projection direction of the DBR reflective layer 11, the first current blocking layer, the first extended electrode, and the first welding electrode correspond to each other, and the second current blocking layer, the second extended electrode, and the second welding electrode correspond to each other, thereby ensuring that the first welding electrode and the second welding electrode are at the same height. This provides a Micro LED chip with equal height for the positive and negative welding electrodes 8 using a positive-mounted chip structure. The distance between the first current blocking layer and the first extended electrode in the projection direction of the DBR reflective layer 11 is 0-10 μm, preferably 1-7 μm, more preferably 2-4 μm. The distance between the second current blocking layer and the second extended electrode in the projection direction of the DBR reflective layer 11 is 0-10 μm, preferably 1-7 μm, more preferably 2-4 μm. The distance between the first current blocking layer and the first welding electrode in the projection direction of the DBR insulating reflective layer is 0-10 μm, preferably 1-7 μm, more preferably 2-4 μm. The distance between the second current blocking layer and the second welding electrode in the projection direction of the DBR insulating reflective layer is 0-10 μm, preferably 1-7 μm, more preferably 2-4 μm.

[0063] The spacing between the first current blocking layer and the second current blocking layer is 5-200 μm, preferably 10-100 μm, and more preferably 20-50 μm. The spacing between the first extended electrode and the second extended electrode is 5-200 μm, preferably 10-100 μm, and more preferably 20-50 μm. The spacing between the first welding electrode and the second welding electrode is 5-200 μm, preferably 10-100 μm, and more preferably 20-50 μm.

[0064] The Micro LED chip provided in this embodiment includes a DBR reflective layer 11, an epitaxial structure 2 located on the DBR reflective layer 11, a current blocking layer 3 located on the epitaxial structure 2, a transparent conductive layer 4 located on the epitaxial structure 2 and the current blocking layer 3, an extended electrode 5 located on the transparent conductive layer 4, an insulating protective layer 6 located on the DBR reflective layer 11, the epitaxial structure 2, the current blocking layer 3, the transparent conductive layer 4 and the extended electrode 5, and a welding electrode 8 located on the epitaxial structure 2, the extended electrode 5 and the insulating protective layer 6. This provides a novel chip structure, adopting a positive-mounted chip structure, and the positive and negative welding electrodes 8 are of equal height, thus extending the Micro LED chip structure.

[0065] Example 2:

[0066] This embodiment provides a method for fabricating a Micro LED chip, used to fabricate the Micro LED chip described in Embodiment 1. The fabrication method includes:

[0067] (1) An epitaxial wafer is provided, the epitaxial wafer comprising a growth substrate and an epitaxial structure stacked sequentially from bottom to top;

[0068] Specifically, providing an epitaxial wafer may include: providing an initial epitaxial wafer, which includes a growth substrate, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially from bottom to top. Etching the initial epitaxial wafer exposes the sides of the second semiconductor layer and the light-emitting layer, as well as the surface of the first semiconductor layer, to form an intermediate epitaxial wafer. Further etching the intermediate epitaxial wafer exposes the sides of the first semiconductor layer and the surface of the growth substrate, to form an epitaxial wafer.

[0069] (2) Fabricate a first current blocking layer and a second current blocking layer on the epitaxial structure (specifically, the second semiconductor layer);

[0070] (3) A transparent conductive layer is fabricated on the first current blocking layer, the second current blocking layer and the epitaxial structure (specifically the second semiconductor layer);

[0071] (4) Fabricate a first extended electrode and a second extended electrode on the transparent conductive layer;

[0072] (5) An insulating protective layer is fabricated on the growth substrate, the epitaxial structure (specifically the first semiconductor layer and the second semiconductor layer), the first current blocking layer, the second current blocking layer, the transparent conductive layer, the first extended electrode, and the second extended electrode.

[0073] (6) Etch a portion of the insulating protective layer to form a first opening and a second opening. The first opening is used to expose a portion of the first extended electrode, and the second opening is used to expose a portion of the epitaxial structure (specifically the first semiconductor layer) to form an insulating protective layer window.

[0074] (7) A first welding electrode is fabricated on the insulating protective layer and the first extended electrode. The first welding electrode is electrically connected to the first extended electrode through the first opening. A second welding electrode is fabricated on the insulating protective layer and the epitaxial structure (specifically the first semiconductor layer). The second welding electrode is electrically connected to the epitaxial structure through the second opening to form an initial chip. At this time, the first welding electrode and the second welding electrode have the same height.

[0075] (8) The initial chip is bonded to the temporary substrate by bonding;

[0076] (9) The growth substrate is removed by laser lift-off;

[0077] (10) A DBR reflective layer is fabricated under the epitaxial structure (first semiconductor layer) and the insulating protective layer;

[0078] (11) Remove the temporary substrate to form a Micro LED chip.

[0079] Specifically, such as Figure 3 As shown, the above manufacturing method may include:

[0080] S101: As Figure 4 and Figure 5 As shown, an initial epitaxial wafer is provided, comprising a growth substrate 1, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially. The growth substrate 1 can be a Si substrate, an Al2O3 substrate, or a SiC substrate. The first and second semiconductor layers have opposite electrical properties; typically, the first semiconductor layer is an N-type semiconductor, and the second semiconductor layer is a P-type semiconductor. Figure 4 (a) is a top view of the growth substrate. Figure 4 (b) is a front view of the growth substrate; Figure 5 (a) is a top view of the initial epitaxial wafer. Figure 5 (b) is the front view of the initial epitaxial wafer.

[0081] S102: As Figure 6 As shown, the initial epitaxial wafer is etched using photolithography, etching, and resist stripping processes commonly used in the semiconductor industry, exposing the sides of the second semiconductor layer and the light-emitting layer, as well as the surface of the first semiconductor layer, to obtain the intermediate epitaxial wafer. Figure 6 (a) is a top view of the intermediate epitaxial wafer. Figure 6 (b) is a front view of the intermediate epitaxial wafer. Typically, plasma etching is used.

[0082] S103: As Figure 7 As shown, the etching process continues on the intermediate epitaxial wafer until the growth substrate 1 is exposed, resulting in the epitaxial structure 2. The etching is performed using plasma etching, or wet etching can be used. Wet etching can employ sulfuric acid, phosphoric acid, or a mixture thereof. After etching, the epitaxial structure 2 forms an acute angle with respect to the horizontal direction of the growth substrate 1, with an angle of 85-20°, preferably 75-35°, and more preferably 60-40°. Figure 7 (a) is a top view of extension structure 2. Figure 7 (b) is the front view of extension structure 2. Figure 7 The arc in the image represents the shape created after etching.

[0083] S104: As Figure 8 As shown, a current blocking layer 3 is fabricated on the second semiconductor layer using deposition, photolithography, etching, and resist stripping processes. This layer is located at both ends of the chip and comprises two opposing portions with a spacing of 5-200 μm, preferably 10-100 μm, and more preferably 20-50 μm. The material used is an insulating and transparent material, specifically SiO2, SiN, TiO2, Ta2O5, MgF, HfO, Al2O3, or any combination thereof. Figure 8 (a) is a top view of the structure obtained after fabricating the current blocking layer 3. Figure 8 (b) is a front view of the structure obtained after fabricating the current blocking layer 3.

[0084] S105: As Figure 9 As shown, a transparent conductive layer 4 is fabricated on top of the second semiconductor layer and the current blocking layer 3 using processes such as deposition, alloying, photolithography, etching, and resist stripping. Figure 9 (a) is a top view of the structure obtained after fabricating the transparent conductive layer 4. Figure 9 (b) is a front view of the structure obtained after fabricating the transparent conductive layer 4.

[0085] S106: As Figure 10 As shown, extended electrodes 5 are fabricated on the transparent conductive layer 4 using photolithography, deposition, lift-off, and resist removal processes. These electrodes are located at both ends of the chip and consist of two opposing parts with a distance of 5-200 μm between them, preferably 10-100 μm, and more preferably 20-50 μm. They correspond to the current blocking layer 3 in the projection direction of the DBR reflective layer 11, with a distance of 0-10 μm between them in the projection direction of the DBR reflective layer 11, preferably 1-7 μm, and more preferably 2-4 μm. Figure 10 (a) is a top view of the structure obtained after fabricating the extended electrode 5. Figure 10 (b) is a front view of the structure obtained after fabricating the extended electrode 5.

[0086] It should be noted that during the production process, the cross-sectional area of ​​the transparent conductive layer 4 is smaller than that of the second semiconductor layer. Therefore, the extended electrode 5 can not only be located on the transparent conductive layer, but can also extend to be located on the second semiconductor layer. In this case, the extended electrode 5 is located on both the transparent conductive layer 4 and the second semiconductor layer.

[0087] S107: As Figure 11 As shown, an insulating protective layer 6 is fabricated on the growth substrate 1, the first semiconductor layer, the current blocking layer 3, the second semiconductor layer, the transparent conductive layer 4, and the extended electrode 5. This insulating protective layer is made of a transparent material, specifically SiO2, SiN, TiO2, Ta2O5, MgF, HfO, Al2O3, or any combination thereof. Figure 11 (a) is a top view of the structure obtained after fabricating the insulating protective layer 6. Figure 11 (b) is a front view of the structure obtained after the insulation protective layer 6 is made.

[0088] S108: As Figure 12 As shown, photolithography, etching, and resist stripping processes are used to etch a portion of the insulating protective layer 6, exposing the first semiconductor layer and the extended electrode 5, forming the insulating protective layer window 7. Typically, plasma etching is used for etching. Figure 12 (a) is a top view of the structure obtained after etching the insulating protective layer 6. Figure 12 (b) is a front view of the structure obtained after etching the insulating protective layer 6.

[0089] S109: As Figure 13 As shown, welding electrodes 8 are fabricated on the insulating protective layer 6, the insulating protective layer window 7, the first semiconductor layer, and the extended electrode 5 using processes such as deposition, photolithography, lift-off, and resist removal. These electrodes are located at both ends of the chip, comprising two opposing portions with a distance of 5-200 μm between them, preferably 10-100 μm, and more preferably 20-50 μm. They correspond to the current blocking layer 3 in the projection direction of the DBR reflective layer 11, with a distance of 0-10 μm between them in the projection direction of the DBR reflective layer 11, preferably 1-7 μm, and more preferably 2-4 μm. Figure 13 (a) is a top view of the structure obtained after fabricating welding electrode 8. Figure 13 (b) is a front view of the structure obtained after the welding electrode 8 is fabricated.

[0090] S110: As Figure 14As shown, the chip is bonded to the temporary substrate 9 using bonding material 10. This bonding typically employs thermoforming. The bonding material 10 can be organic materials such as BCB or PI. The temporary substrate 9 is required to be a transparent material with a certain degree of rigidity, such as Al2O3 or SiO2. Figure 14 (a) is a top view of the structure obtained after bonding to the temporary substrate 9. Figure 14 (b) is a front view of the structure obtained after bonding to the temporary substrate 9.

[0091] S111: As Figure 15 As shown, the growth substrate 1 is removed using laser lift-off. Figure 15 (a) is a top view of the structure obtained after removing the growth substrate 1. Figure 15 (b) is a front view of the structure obtained after removing the growth substrate 1.

[0092] S112: As Figure 16 As shown, a DBR reflective layer 11 is fabricated on top of the first semiconductor layer and the insulating protective layer 6 of the growth substrate 1. This layer is a DBR reflective film structure formed by any combination of SiO2, SiN, TiO2, Ta2O5, and MgF, with a thickness of 1.5-10 μm, preferably 2.5-8 μm, and more preferably 3.5-5 μm. The reflectivity is greater than 95% in the 350-700 nm wavelength range. Figure 16 (a) is a top view of the structure obtained after fabricating the DBR reflective layer 11. Figure 16 (b) is a front view of the structure obtained after fabricating the DBR reflective layer 11.

[0093] S113: As Figure 17 As shown, the temporary substrate 9 is removed by laser lift-off to form a Micro LED chip. Figure 17 (a) is a top view of the structure obtained after removing the temporary substrate 9. Figure 17 (b) is a front view of the structure obtained after removing the temporary substrate 9.

[0094] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0095] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A Micro LED chip, characterized in that, The chip includes a DBR reflective layer, an epitaxial structure, a first current blocking layer, a second current blocking layer, a transparent conductive layer, a first extended electrode, a second extended electrode, an insulating protective layer, a first welding electrode, and a second welding electrode. The epitaxial structure is disposed on the DBR reflective layer; the epitaxial structure forms an acute angle with respect to the horizontal direction where the upper surface of the DBR reflective layer is located, with an angle of 85-20°. The first current blocking layer and the second current blocking layer are disposed on the epitaxial structure and located at both ends of the epitaxial structure; The transparent conductive layer is disposed on the first current blocking layer, the second current blocking layer, and the epitaxial structure located between the first current blocking layer and the second current blocking layer; The first extended electrode and the second extended electrode are disposed at intervals on the transparent conductive layer; The insulating protective layer covers the outer surface of the structure consisting of the epitaxial structure, the first current blocking layer, the second current blocking layer, the transparent conductive layer, the first extended electrode, and the second extended electrode, and is in contact with the upper surface of the DBR reflective layer that is not in contact with the epitaxial structure; The insulating protective layer has a first opening and a second opening; the first welding electrode is disposed on the insulating protective layer and is electrically connected to the first extended electrode through the first opening; the second welding electrode is disposed on the insulating protective layer and is electrically connected to the epitaxial structure through the second opening. In the projection direction of the DBR reflective layer, the first current blocking layer, the first extended electrode, and the first welding electrode correspond to each other, and the second current blocking layer, the second extended electrode, and the second welding electrode correspond to each other.

2. The chip according to claim 1, characterized in that, The DBR reflective layer comprises multiple layers of films made of different materials; the materials of the films are SiO2, SiN, TiO2, Ta2O5 or MgF; the thickness of the DBR reflective layer is 1.5-10 μm.

3. The chip according to claim 1, characterized in that, The epitaxial structure includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially from bottom to top; the first semiconductor layer and the second semiconductor layer have opposite electrical properties.

4. The chip according to claim 1, characterized in that, The first current blocking layer, the second current blocking layer, and the insulating protective layer are all made of insulating transparent materials, including one or more of SiO2, SiN, TiO2, Ta2O5, MgF, HfO, and Al2O3. The thickness of the first current blocking layer and the second current blocking layer is 50-20000A; the thickness of the insulating protective layer is 2000-20000A.

5. The chip according to claim 1, characterized in that, The transparent conductive layer is made of ITO, GaO, or ZnO; the thickness of the transparent conductive layer is 100-3000 Å.

6. The chip according to claim 1, characterized in that, The first extended electrode and the second extended electrode have the same structure; the first extended electrode includes a bonding ohmic contact layer, a reflective layer, a blocking layer, a current spreading layer, an anti-etching layer and a bonding layer stacked from bottom to top; The bonding ohmic contact layer is made of one or more of Cr, Ni, and Ti, with a thickness of 10-50 Å; the reflective layer is made of one or more of Al and Ag, with a thickness of 500-3000 Å; the barrier layer is made of one or more of Ti, Pt, and Ni, with a thickness of 500-3000 Å; the current spreading layer is made of one or more of Pt and Au, with a thickness of 2000-30000 Å; the anti-etching layer is made of one or more of Pt and Ni, with a thickness of 500-3000 Å; and the bonding layer is made of one or more of Ti and Ni, with a thickness of 500-3000 Å.

7. The chip according to claim 1, characterized in that, The first welding electrode and the second welding electrode have the same structure; the first welding electrode includes an adhesive ohmic contact layer, a reflective layer, a barrier layer and a welding layer stacked sequentially from bottom to top; The bonding ohmic contact layer is made of one or more of Cr, Ni, and Ti, with a thickness of 10-50 Å; the reflective layer is made of one or more of Al and Ag, with a thickness of 500-3000 Å; the barrier layer is made of one or more of Ti, Pt, and Ni, with a thickness of 500-3000 Å; and the welding layer is made of one or more of Au, Sn, In, Ag, and Cu, with a thickness of 0.1-30 μm.

8. The chip according to claim 1, characterized in that, The spacing between the first current blocking layer and the second current blocking layer is 5-200 μm; the spacing between the first extended electrode and the second extended electrode is 5-200 μm; the spacing between the first welding electrode and the second welding electrode is 5-200 μm.

9. A method for fabricating a Micro LED chip, used to fabricate the Micro LED chip of claim 1, characterized in that, The manufacturing method includes: An epitaxial wafer is provided; the epitaxial wafer includes a growth substrate and an epitaxial structure stacked sequentially from bottom to top; A first current blocking layer and a second current blocking layer are fabricated on the epitaxial structure; A transparent conductive layer is fabricated on the first current blocking layer, the second current blocking layer, and the epitaxial structure; A first extended electrode and a second extended electrode are fabricated on the transparent conductive layer; An insulating protective layer is formed on the growth substrate, the epitaxial structure, the first current blocking layer, the second current blocking layer, the transparent conductive layer, the first extended electrode, and the second extended electrode. A portion of the insulating protective layer is etched to form a first opening and a second opening; the first opening is used to expose a portion of the first extended electrode; the second opening is used to expose a portion of the epitaxial structure. A first welding electrode is fabricated on the insulating protective layer and the first extended electrode. The first welding electrode is electrically connected to the first extended electrode through the first opening. A second welding electrode is fabricated on the insulating protective layer and the epitaxial structure. The second welding electrode is electrically connected to the epitaxial structure through the second opening, thereby forming an initial chip. The initial chip is bonded to a temporary substrate by bonding. The growth substrate is removed by laser lift-off. A DBR reflective layer is fabricated under the epitaxial structure and the insulating protective layer; Remove the temporary substrate to form a Micro LED chip.

10. The manufacturing method according to claim 9, characterized in that, The provision of an epitaxial wafer specifically includes: An initial epitaxial wafer is provided, the initial epitaxial wafer comprising a growth substrate, a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked sequentially from bottom to top; The initial epitaxial wafer is etched to expose the sides of the second semiconductor layer and the light-emitting layer, as well as the surface of the first semiconductor layer, to form an intermediate epitaxial wafer; Continue etching the intermediate epitaxial wafer to expose the side surface of the first semiconductor layer and the surface of the growth substrate, forming an epitaxial wafer.

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