Wiring substrate and electronic device

Abstract

The wiring substrate and electronic device provided by the present disclosure include a base substrate; a plurality of sub-pad groups arranged at intervals along the row direction and / or the column direction, at least two sub-pad groups arranged along the row direction and / or the column direction are interconnected to form a first pad group; a plurality of first signal lines, each of the plurality of first signal lines includes a first main body extending along the column direction and a first branch connected to the first main body, at least part of the first branches of the first signal lines include a slit structure; the first branch is located between two adjacent rows of sub-pad groups; an insulating layer, covering the plurality of first signal lines and exposing each first pad group.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a wiring substrate and an electronic device. Background Art

[0002] In recent years, backlight and display technologies based on ultra-fine-pitch light-emitting diodes (Mini LED and Micro LED) have developed rapidly. Compared with traditional LCD products, ultra-fine-pitch LED products can achieve local dimming within a smaller range, better brightness uniformity, higher color contrast, and a thinner and lighter product form factor. Their display performance is basically the same as that of organic light-emitting diodes, but at a lower cost and with a longer product lifespan. Due to these advantages, ultra-fine-pitch LEDs have seen rapid development in recent years and have a promising market prospect. Summary of the Invention

[0003] The present disclosure provides a wiring substrate and an electronic device, the specific solutions of which are as follows:

[0004] In one aspect, an embodiment of the present disclosure provides a wiring substrate, comprising:

[0005] substrate;

[0006] a plurality of sub-pad groups arranged at intervals along a row direction and / or a column direction, wherein at least two of the sub-pad groups arranged along the row direction and / or the column direction are connected to each other to form a first pad group;

[0007] a plurality of first signal lines, each of the plurality of first signal lines comprising a first main portion extending along the column direction and a first branch portion connected to the first main portion, at least some of the first branches of the first signal lines comprising a slit structure; the first branch portion being located between two adjacent rows of the sub-pad groups;

[0008] The insulating layer covers the plurality of first signal lines and exposes each of the first pad groups.

[0009] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the first main body portion is located between two adjacent columns of the sub-pad groups;

[0010] The multiple first signal lines include at least one selected first signal line, one end of the first branch of the selected first signal line is floating, the first branches of other first signal lines in the multiple first signal lines are electrically connected to the first main body of the adjacent first signal line, and the first branch of the selected first signal line includes the slit structure.

[0011] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the slit structure includes a plurality of first slits, and the first slits extend along the row direction.

[0012] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, the slit structure also includes a plurality of second slits, the second slits extend along the column direction, two adjacent first slits are connected by one second slit, and the two ends of the same first slit are respectively connected to two second slits.

[0013] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, in the column direction, the size of the area of ​​the first branch located between two adjacent first slits is greater than the width of the first slit.

[0014] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the same first signal line includes one first main portion and at least one first branch portion forming an integrated structure.

[0015] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the first branches of different first signal lines are arranged at intervals along the row direction.

[0016] In some embodiments, the wiring substrate provided in the embodiments of the present disclosure further includes a plurality of second signal lines, each of the plurality of second signal lines including a second main portion extending along the column direction and a second branch portion connected to the second main portion;

[0017] At least one second main body and one first main body are included between two adjacent columns of the first pad groups; the second branch is located between two adjacent rows of the sub-pad groups, and only one of the second branch and the first branch is provided between two adjacent rows of the sub-pad groups; the second main body of a second signal line is electrically connected to the second branch of an adjacent second signal line.

[0018] In some embodiments, the above-mentioned wiring substrate provided in the embodiments of the present disclosure further includes a plurality of second pad groups, the second pad groups are electrically connected to the first pad groups, any second pad group is located between two adjacent first pad groups, and the orthographic projection of the first signal line or the second signal line on the base substrate does not overlap with the orthographic projection of the second pad group on the base substrate.

[0019] In some embodiments, the wiring substrate provided in the embodiments of the present disclosure further includes a plurality of connecting lines located on a side of the insulating layer away from the base substrate, the plurality of connecting lines including a plurality of first connecting lines and a plurality of second connecting lines;

[0020] a first branch portion of one of at least two adjacent first signal lines among the plurality of first signal lines, electrically connected to a first main portion of another of the two adjacent first signal lines through the first connecting line;

[0021] The second main portion of one of at least two adjacent second signal lines among the plurality of second signal lines is electrically connected to the second branch portion of the other of the two adjacent second signal lines through the second connecting line.

[0022] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, the insulating layer includes a plurality of vias, the connecting line includes a jumper resistor and connection terminals located at both ends of the jumper resistor, the jumper resistor is arranged parallel to the base substrate, the connection terminals are located in the vias, and the jumper resistor is electrically connected to two adjacent first signal lines or two adjacent second signal lines through two of the connection terminals.

[0023] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the first signal line and the second signal line are respectively used to transmit constant voltage signals of different amplitudes.

[0024] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned wiring substrate provided by an embodiment of the present disclosure.

[0025] The beneficial effects of the present disclosure are as follows:

[0026] The wiring substrate and electronic device provided by the present disclosure include a substrate; a plurality of sub-pad groups arranged in a row direction and / or a column direction, at least two of the sub-pad groups arranged in the row direction and / or the column direction are interconnected to form a first pad group; a plurality of first signal lines, each of the plurality of first signal lines including a first main portion extending in the column direction and a first branch connected to the first main portion, at least some of the first branches of the first signal lines including a slit structure; the first branch being located between two adjacent rows of sub-pad groups; and an insulating layer covering the plurality of first signal lines and exposing each of the first pad groups. By providing the slit structure in the first branch, the contact area between the insulating layer and the first branch can be effectively increased. Combined with Fourier's law: the amount of heat passing through a given cross section per unit time is proportional to the rate of temperature change in a direction perpendicular to the cross section and the cross-sectional area, and the direction of heat transfer is opposite to the direction of temperature increase, it can be seen that the increased contact area between the insulating layer and the first branch in the present disclosure can transfer more heat from the first branch to the insulating layer for heat dissipation, thereby improving the heat dissipation capacity of the first signal lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A schematic structural diagram of a wiring substrate provided in an embodiment of the present disclosure;

[0028] Figure 2 for Figure 1 Enlarged schematic diagram of the middle M region;

[0029] Figure 3 For the Figure 2 The cross-sectional view of the middle I-I';

[0030] Figure 4 for Figure 1 Equivalent circuit diagram of the first signal line in ;

[0031] Figure 5 A schematic structural diagram of the first branch provided in an embodiment of the present disclosure;

[0032] Figure 6 For the Figure 1 Sectional view along line II-II';

[0033] Figure 7 A schematic diagram of area division of a wiring substrate provided in an embodiment of the present disclosure;

[0034] Figure 8 A schematic diagram of another structure of a wiring substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0036] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in this disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0037] Ultra-fine-pitch LED (Mini LED and Micro LED) products are currently evolving towards three key trends: increasing the number of panels, narrowing bezels, and reducing product costs. However, while these three changes improve product performance, optimize display quality, and attract more consumers, they also pose greater challenges to the design of the wiring substrate (BP) for ultra-fine-pitch LEDs. First, a greater number of panels means more signal lines on the BP for supplying power and control signals to the chips. This increased number of signal lines increases the space required for the wiring take-up area, but the shrinking product bezels further compress the available width for wiring in the take-up area. Furthermore, reducing the number of chip-on-film (COF) bonding pads, a key cost-cutting measure, further increases the wiring density in the take-up area. Given increasingly limited space, the denser the wiring bundles that need to be routed simultaneously, the narrower the width available for each line, resulting in higher resistance. To address this issue, a wiring substrate can be constructed by filling the lamp area with copper and bridging it with jumpers. This allows multiple signal lines to be connected in parallel before the wire-collection area, directly facing the bonding pins of the flip chip. This eliminates the need for wiring near the frame and significantly reduces resistance. However, this design often results in excessive current in the signal lines near the bonding side, leading to localized overheating.

[0038] In order to improve the above technical problems existing in the related art, the present disclosure provides a wiring substrate, such as Figures 1 to 3 As shown, including:

[0039] Base substrate 101;

[0040] A plurality of sub-pad groups 102 are arranged at intervals along the row direction X and / or the column direction Y, and at least two sub-pad groups 102 arranged along the row direction X and / or the column direction Y are connected to each other to form a first pad group 102'; optionally, Figure 1 The four sub-pad groups 102 arranged along the row direction X and the column direction Y are connected to each other to form a first pad group 102'. Optionally, the sub-pad group 102 includes first pads P electrically connected to the pins of two-pin electronic components (such as light-emitting diodes). pad and the second pad N pad ;

[0041] A plurality of first signal lines 103, each of the plurality of first signal lines 103 including a first main portion 31 extending along a column direction Y and a first branch portion 32 connected to the first main portion 31, wherein at least some of the first branches 32 of the first signal lines 103 include a slit structure S; the first branch portion 32 is located between two adjacent rows of sub-pad groups 102;

[0042] The insulating layer 104 covers the plurality of first signal lines 103 and exposes each first pad group 102 ′.

[0043] In the above-mentioned wiring substrate provided in the embodiment of the present disclosure, by setting a slit structure S in the first branch 32, the contact area between the insulating layer 104 and the first branch 32 can be effectively increased. Combined with Fourier's law of thermodynamics: the amount of heat passing through a specific cross-section per unit time is proportional to the temperature change rate and the cross-sectional area in the direction perpendicular to the cross-sectional direction, and the direction of heat transfer is opposite to the direction of temperature increase. It can be seen that the present disclosure increases the contact area between the insulating layer 104 and the first branch 32, so that more heat on the first branch 32 can be transferred to the insulating layer 104 for heat dissipation, thereby improving the heat dissipation capacity of the first signal line 103.

[0044] It should be understood that, when the cross-section of the slit structure S perpendicular to the base substrate 101 is rectangular, the contact area between the insulating layer 104 and the first branch 32 at the slit structure S is (2ac + 2bc). Before the slit structure S is provided, the contact area between the insulating layer 104 and the first branch 32 at the location where the slit structure S is to be provided is ab, where a is the length of the slit structure S in the extension direction, b is the width of the slit structure S in a direction perpendicular to its extension direction on a plane parallel to the base substrate 101, and c is the thickness of the first branch 32 in a direction perpendicular to the base substrate 101. Therefore, compared to before the slit structure S is provided, the change in the contact area between the insulating layer 104 and the first branch 32 after the slit structure S is provided is (2ac + 2bc - ab). When (2ac + 2bc - ab) is greater than 0, the effect of increasing the contact area between the insulating layer 104 and the first branch 32 is achieved. In some embodiments, the value of (2ac + 2bc - ab) can be flexibly set based on actual needs. Specifically, the more heat generated by the first branch 32, the larger the value of (2ac + 2bc - ab) that needs to be set. Optionally, in the present disclosure, the side contact area between the first branch 32 and the insulating layer 104 is 251.4% of the side contact area between the first branch 32 and the insulating layer 104 before the slit structure S is provided, and the total contact area between the first branch 32 and the insulating layer 104 is 135.3% of the total contact area between the first branch 32 and the insulating layer 104 before the slit structure S is provided.

[0045] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 1 and Figure 4As shown, the first main body 31 is located between two adjacent columns of sub-pad groups 102; the plurality of first signal lines 103 include at least one selected signal line 103', one end of the first branch 32 of the selected signal line 103' is floating, and the first branches 32 of the other first signal lines 103 in the plurality of first signal lines 103 are electrically connected to the first main body 31 of the adjacent first signal line 103, and the first branch 32 of the selected signal line 103' includes a slit structure. Figure 1 Among the four first signal lines (103-1, 103-2, 103-3, 103-4) shown, some of the first signal lines include at least two first main bodies spaced apart from each other and at least one first branch forming an integral structure with one first main body, such as the first signal line 103-2; some of the first signal lines include a main body and at least two first branches spaced apart from each other, wherein one first branch and the first main body form an integral structure, such as the first signal line 103-3. The equivalent circuit formed by the equivalent resistance of each first signal line is shown in FIG. Figure 4 As shown. Where A represents the equivalent resistance of the first branch 32 of the selected signal line 103', G represents the equivalent resistance of the first main body and / or the first branch in the first signal line 103, and J represents the equivalent resistance of the first connecting line 51 connecting the two first signal lines. Figure 4 As can be seen, while the first branch 32 of the selected signal line 103' is physically connected to the first main portion 31 of the selected signal line 103', one end of the branch 32 is not connected to any other electrical structure. Therefore, the first branch 32 of the selected signal line 103' can be considered to be floating. Therefore, a slit structure S can be provided in the first branch 32 of the selected signal line 103' to dissipate heat. This not only improves the heat dissipation capability of the first signal line 103 but also prevents any impact on the electrical characteristics of the first signal line 103.

[0046] In some embodiments, to ensure more uniform heat dissipation across the entire first signal line 103, four first signal lines 103 may be grouped together, with the first first signal line 103 in each group being a selected signal line 103' having a slit structure S. The first branch portion 32 of the (n+1)th first signal line 103 is electrically connected to the first main portion 31 of the nth first signal line 103, where n is greater than or equal to 1 and less than or equal to 3. Of course, in some embodiments, other numbers of first signal lines 103 may be grouped together, and this is not a limitation herein.

[0047] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 5As shown, the slit structure S may include a plurality of first slits S1, which extend along the row direction X. This is equivalent to the slit structure S being composed of a plurality of first slits S1 extending along the row direction X and arranged side by side along the column direction Y. This slit structure S is relatively simple, easy to manufacture, and can also facilitate heat dissipation. In some embodiments, in order to further increase the contact area between the insulating layer A and the first branch 32 at the slit structure S, thereby improving the heat dissipation capability of the first branch 32, as shown in FIG. Figure 3 As shown, multiple second slits S2 can also be set in the slit structure S. The second slits S2 extend along the column direction Y. Two adjacent first slits S1 are connected by one second slit S2. The two ends of the same first slit S1 are respectively connected to the two second slits S2. That is, the slit structure S is a curved and extended slit.

[0048] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 2 and Figure 5 As shown, in the column direction Y, the size of the area of ​​the first branch 32 located between two adjacent first slits S1 is larger than the width of the first slit S1, which can prevent the first branch 32 between two adjacent first slits S1 from being too thin and breaking, ensuring a stable connection between the first branch 32 and the first main body 31, and facilitating the heat on the first signal line 103 to be transferred from the first main body 31 to the first branch 32, and then further transferred to the insulating layer 104 through the slit structure A, thereby improving the overall heat dissipation capacity of the first signal line 103. In some embodiments, the width of the first slit S1 can be 15μm, which is the current process limit. Optionally, as Figure 3 As shown, a buffer layer BF may be provided on the entire surface of the base substrate 101 so that the surface of the first branch 32 and other signal lines facing the base substrate 101 contacts the buffer layer BF to further improve the heat dissipation capability of the signal lines.

[0049] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 1 、 Figure 2 and Figure 5 As shown, the same first signal line 103 may include multiple main bodies 31 and multiple first branches 32 , wherein at least one first main body 31 and at least one first branch 32 may form an integral structure.

[0050] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 1 As shown, to facilitate connection and simplify the design of the first signal line 103 , the first branches 32 of different first signal lines 103 can be arranged at intervals along the row direction X, that is, all the first branches 32 can be arranged side by side between two adjacent rows of sub-pad groups 102 .

[0051] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 1 As shown, it may also include multiple second signal lines 106, each of the multiple second signal lines 106 includes a second main body 61 extending along the column direction Y and a second branch 62 connected to the second main body 61; at least one second main body 61 and one first main body 31 are included between two adjacent columns of first pad groups 102'; the second branch 62 is located between two adjacent rows of sub-pad groups 102, and only one of the second branch 62 and the first branch 32 is provided between two adjacent rows of sub-pad groups 102; the second main body 61 of at least one second signal line 106 is electrically connected to the second branch 62 of the adjacent second signal line 106.

[0052] In some embodiments, the above-mentioned wiring substrate provided in the embodiments of the present disclosure further includes a plurality of second pad groups 107, the second pad groups 107 are electrically connected to the first pad groups 102', any second pad group 107 is located between two adjacent first pad groups 102', the orthographic projection of the first signal line 103 or the second signal line 106 on the base substrate 101 and the orthographic projection of the second pad group 107 on the base substrate 101 do not overlap with each other, optionally, between a certain number of adjacent two first pad groups 102', a second pad group 107 and a second main body 61 may be provided at the same time, and the second main body 61 is provided with a recess C for avoiding the second pad group 107.

[0053] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 1 and Figure 6 As shown, it also includes a plurality of connecting lines 105 located on the side of the insulating layer 104 away from the base substrate 101, and the plurality of connecting lines 105 include a plurality of first connecting lines 51 and a plurality of second connecting lines 52; the first branch 32 of one of the two adjacent first signal lines 103 is electrically connected to the first main body 31 of the other of the two adjacent first signal lines 103 through the first connecting line 51; the second main body 61 of one of the two adjacent second signal lines 106 is electrically connected to the second branch 62 of the other of the two adjacent second signal lines 106 through the second connecting line 52.

[0054] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 6As shown, the insulating layer 104 includes a plurality of vias V, and the connecting line 105 includes a jumper resistor 1051 and connection terminals 1052 located at both ends of the jumper resistor 1051. The jumper resistor 1051 is arranged parallel to the substrate 101, and the connection terminals 1052 are located within the vias V. The jumper resistor 1051 is electrically connected to two adjacent first signal lines 103 or two adjacent second signal lines 106 through the two connection terminals 1052. A jumper resistor, also known as a zero-ohm resistor, is a special-purpose resistor with a very small resistance value. An automatic placement machine or an automatic insertion machine can be used to place the jumper resistor between two points in the wiring substrate that cannot be directly connected by wiring, thereby achieving an electrical connection between the two points.

[0055] In some embodiments, the connection line 105 can be formed by conventional film forming and patterning processes.

[0056] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 1 As shown, first signal line 103 and second signal line 106 are respectively used to transmit constant voltage signals of different amplitudes. For example, first signal line 103 is used to transmit a first voltage signal, and second signal line 106 is used to transmit a second voltage signal. Optionally, the difference between the amplitude of the second voltage signal provided by the second signal line and the amplitude of the first voltage signal provided by the first signal line is equal to the sum of the rated voltages of the multiple electronic components coupled to first pad group 102', so that each electronic component can operate normally under the rated voltage.

[0057] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as Figure 7 As shown, the base substrate 101 includes a plurality of pad areas PA ( Figure 7 Only two pad areas PA are shown, and in the column direction Y, the base substrate 101 includes a binding area BA electrically connected to the flip chip film COF, a parallel area AA1 located on one side of the binding area BA, and a normal wiring area AA2 located on the side of the parallel area AA1 away from the binding area BA. The wiring method of the parallel area AA1 can be seen in FIG. Figure 1 , the wiring method of normal wiring area AA2 is as follows Figure 8 In some embodiments, as shown Figure 1 and Figure 8As shown, the second pad groups 107 in each pad area PA are cascaded with each other, the sub-pad groups 102 of the first pad group 102' are arranged in series, the first sub-pad group 102 in each first pad group 102' is connected to the second signal line 106, and the ground pads Gnd of all the cascaded first pad groups 102' in a pad area PA are connected to the same first signal line 103. The power line 108 is composed of a plurality of mutually spaced sub-segments 81, each sub-segment 81 is connected to the power supply pad Pwr of a second pad group 107 in a pad area PA. Optionally, two adjacent sub-segments 81 in a pad area PA can be connected to each other via a lead 109. Optionally, the lead 109 and the sub-segment 81 are integral structures. In each pad area PA, the address pads Di of the first-level second pad group 107 are connected to the address signal line 110, the output pads Out of the k-th (k is a positive integer)-level second pad group 107 and the address pads Di of the (k+1)-th-level second pad group 107 are connected via a cascade line 111, and the output pads Out of the last-level second pad group 107 are connected to the feedback signal line 112. Other essential components of the wiring substrate should be understood by those skilled in the art and will not be described in detail herein, nor should they be construed as limiting the present disclosure.

[0058] Optionally, in order to save the number of patterning times and reduce the number of film layers, in the present disclosure, the first signal line 103, the second signal line 106, the power line 108, the lead 109, the cascade line 111, and the feedback signal line 112 can be set in the same layer. Specifically, in the present disclosure, "the same layer" refers to the use of the same film-forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (mask, also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

[0059] Based on the same inventive concept, an embodiment of the present disclosure also provides an electronic device, including the above-mentioned wiring substrate provided in the embodiment of the present disclosure, an electronic component electrically connected to the sub-pad group 102, and a driver chip electrically connected to the second pad group 107, etc. Optionally, the electronic device can be: a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and any other product or component with a display function. The electronic device includes but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply and other components. In addition, it can be understood by those skilled in the art that the above-mentioned structure does not constitute a limitation on the above-mentioned electronic device provided in the embodiment of the present disclosure. In other words, the above-mentioned electronic device provided in the embodiment of the present disclosure may include more or fewer of the above-mentioned components, or a combination of certain components, or different component arrangements.

[0060] Although the present disclosure has described preferred embodiments, it should be understood that those skilled in the art may make various changes and modifications to the embodiments without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations.

Claims

1. A wiring substrate, characterized in that: include: substrate; a plurality of sub-pad groups arranged at intervals along a row direction and / or a column direction, wherein at least two of the sub-pad groups arranged along the row direction and / or the column direction are connected to each other to form a first pad group; a plurality of first signal lines, each of the plurality of first signal lines comprising a first main portion extending along the column direction and a first branch portion connected to the first main portion, and at least some of the first branches of the first signal lines comprising a slit structure; The first branch is located between two adjacent rows of sub-pad groups; an insulating layer covering the plurality of first signal lines and exposing each of the first pad groups; The first main body is located between two adjacent columns of the sub-pad groups; The plurality of first signal lines include at least one selected first signal line, one end of a first branch of the selected first signal line is floating, the first branches of other first signal lines in the plurality of first signal lines are electrically connected to the first main body of an adjacent first signal line, and the first branch of the selected first signal line includes the slit structure; The slit structure includes a plurality of first slits, wherein the first slits extend along the row direction; In the column direction, the size of the area of ​​the first branch between two adjacent first slits is greater than the width of the first slit; The same first signal line includes one first main portion and at least one first branch portion forming an integral structure.

2. The wiring substrate according to claim 1, wherein The slit structure further includes a plurality of second slits, wherein the second slits extend along the column direction, two adjacent first slits are connected through one second slit, and both ends of the same first slit are respectively connected to two second slits.

3. The wiring substrate according to claim 1, wherein The first branches of different first signal lines are arranged at intervals along the row direction.

4. The wiring substrate according to claim 1, wherein Also comprising a plurality of second signal lines, each of the plurality of second signal lines comprising a second main portion extending along the column direction and a second branch portion connected to the second main portion; At least one second main body and one first main body are included between two adjacent columns of the first pad groups; the second branch is located between two adjacent rows of the sub-pad groups, and only one of the second branch and the first branch is provided between two adjacent rows of the sub-pad groups; the second main body of a second signal line is electrically connected to the second branch of an adjacent second signal line.

5. The wiring substrate according to claim 4, wherein It also includes multiple second pad groups, which are electrically connected to the first pad group. Any second pad group is located between two adjacent first pad groups, and the orthographic projection of the first signal line or the second signal line on the base substrate does not overlap with the orthographic projection of the second pad group on the base substrate.

6. The wiring substrate according to claim 4, wherein It also includes a plurality of connecting lines located on a side of the insulating layer away from the base substrate, the plurality of connecting lines including a plurality of first connecting lines and a plurality of second connecting lines; a first branch portion of one of at least two adjacent first signal lines among the plurality of first signal lines, electrically connected to a first main portion of another of the two adjacent first signal lines through the first connecting line; The second main portion of one of at least two adjacent second signal lines among the plurality of second signal lines is electrically connected to the second branch portion of the other of the two adjacent second signal lines through the second connecting line.

7. The wiring substrate according to claim 6, wherein The insulating layer includes multiple vias, the connecting line includes a jumper resistor and wiring terminals located at both ends of the jumper resistor, the jumper resistor is arranged parallel to the substrate, the wiring terminals are located in the vias, and the jumper resistor is electrically connected to two adjacent first signal lines or two adjacent second signal lines through two wiring terminals.

8. The wiring substrate according to claim 4, wherein The first signal line and the second signal line are respectively used to transmit constant voltage signals of different amplitudes.

9. An electronic device, characterized in that: The invention comprises the wiring substrate according to any one of claims 1 to 8.

Images