Preparation method of three-terminal memristor neuron device, three-terminal memristor neuron device

Abstract

The application discloses a three-terminal memristor neuron device and a preparation method thereof. The preparation method comprises the following steps in sequence: preparing an input electrode on the upper surface of a substrate to obtain a first intermediate part, wherein the input electrode is a silver electrode; preparing an insulating layer on the upper surface of the first intermediate part, and opening a contact through hole on the insulating layer; preparing an active layer on the upper surface of the insulating layer, and forming an output electrode on the upper surface of the active layer to obtain a second intermediate part, wherein the region of the active layer located in the contact through hole is regarded as an active region, and the active region is respectively connected with the upper surface of the input electrode and the lower surface of the output electrode; preparing a current-limiting layer on the upper surface of the second intermediate part, and forming a grounding electrode on the upper surface of the current-limiting layer to obtain the three-terminal memristor neuron device. The three-terminal memristor neuron device provided by the application can output corresponding pulse signals based on the received input signals in real time without the help of an external circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a three-terminal memristor neuron device and its fabrication method. Background Technology

[0002] The rapid development of artificial intelligence and machine learning technologies has led to a continuous increase in the demand for computing power. As Moore's Law reaches its limits, improving chip computing power and reducing energy consumption are becoming increasingly difficult. The brain, a highly complex system, can effectively combine complex dynamics to perform "computation," while possessing the advantages of high performance and low power consumption. Brain-inspired neuromorphic computing was first proposed in the 1990s by Professor Carver Mead of Caltech. Its main idea is to simulate the function of the brain's nervous system through large-scale integration of electronic devices. Neuromorphic computing further simulates the human brain based on neural network computing architecture, expressing and transmitting information in the form of impulses, exhibiting asynchronous and event-driven characteristics. Compared with traditional computing systems based on the von Neumann architecture, brain-inspired neuromorphic computing architectures have advantages such as high parallelism, high energy efficiency, and high fault tolerance. The human brain contains approximately 10... 11 There are 10 neurons, and the neurons are connected by 10... 4 Neurons are connected by synapses. Neurons are the basic units of information processing and cognitive behavior in the nervous system; therefore, the development of artificial neuron devices is of great significance for neuromorphic chips.

[0003] Current neuron circuits are mainly built on traditional CMOS (complementary metal oxide semiconductor) circuits. The simulation of neuron function often relies on circuit modules composed of capacitors and hundreds of MOSFET (metal-oxide-semiconductor field-effect transistor) devices, which leads to problems such as high hardware cost, high circuit power consumption, and complex circuit design. This is not conducive to high-density, large-scale integration and makes it difficult to support the construction of neuromorphic computing chips that can rival the function and integration scale of the human brain. Summary of the Invention

[0004] This invention addresses the drawback of existing analog neuron devices based on CMOS transistors and capacitors having a large area by providing a three-terminal memristor neuron device that can directly accept input signals and generate outputs, eliminating the need for a power supply, as well as a method for fabricating this neuron device.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] A method for fabricating a three-terminal memristor neuron device includes the following steps performed sequentially:

[0007] S100. An input electrode is fabricated on the upper surface of a substrate to obtain a first intermediate component, wherein the input electrode is a silver electrode.

[0008] S200. An insulating layer is prepared on the upper surface of the first intermediate component, and a contact through hole is formed on the insulating layer;

[0009] S300. An active layer is prepared on the upper surface of the insulating layer, and an output electrode is formed on the upper surface of the active layer to obtain a second intermediate component. The region of the active layer located in the contact via is defined as the active region, and the active region is connected to the upper surface of the input electrode and the lower surface of the output electrode, respectively.

[0010] S400. A current-limiting layer is prepared on the upper surface of the second intermediate component, and a ground terminal electrode is formed on the upper surface of the current-limiting layer to obtain a three-terminal memristor neuron device.

[0011] As one possible implementation, step S100 includes:

[0012] A first patterned region is defined by photolithography on the substrate, and a 10-70 nm layer of silver is deposited based on the first patterned region to form an input electrode, thereby obtaining a first intermediate device.

[0013] As one possible implementation, step S200 includes:

[0014] A second patterned region is defined by photolithography on the first intermediate component. The second patterned region includes a portion of the input terminal electrode. An insulating material is deposited based on the second patterned region to form an insulating layer.

[0015] The insulating layer and the input terminal electrode partially overlap to form an overlapping region. The insulating layer is etched to form a contact via, which is located in the overlapping region.

[0016] Further, step S300 includes:

[0017] A third patterned region is defined by photolithography on the insulating layer. The third patterned region includes the area where the contact via is located. An active material and an inert metal material are sequentially deposited based on the third patterned region. The active material is deposited to form an active layer, and the inert metal material is deposited to form an output electrode.

[0018] Furthermore:

[0019] The active material is FeO. x MgO x SiO xor AlO x .

[0020] As one possible implementation, step S400 includes:

[0021] A fourth patterned region is defined by photolithography on the upper surface of the second intermediate component. The fourth patterned region includes a portion of the output electrode. An insulating material and an inert metal material are sequentially deposited based on the fourth patterned region. The insulating material is deposited to form a current-limiting layer, and the inert metal material is deposited to form a ground electrode.

[0022] As one possible implementation method:

[0023] The thickness of the output electrode and the ground electrode is 30–70 nm.

[0024] As one possible implementation method:

[0025] The thickness of the current-limiting layer is 10-30 nm.

[0026] As one possible implementation method:

[0027] The thickness of the active layer is 20-40 nm.

[0028] The present invention also proposes a three-terminal memristor neuron device prepared according to any one of the above methods, the three-terminal memristor neuron device comprising a substrate, and, stacked on the substrate from bottom to top:

[0029] The silver electrode serves as the input electrode;

[0030] An insulating layer with contact vias is provided. In this invention, the insulating layer partially overlaps with the input electrode, and the contact vias are located in the overlapping area between the insulating layer and the input electrode.

[0031] An active layer is connected to the upper surface of the output electrode through a contact via. That is, a portion of the active layer is located in the contact via and is in contact with the upper surface of the output electrode. In this invention, the area of ​​the active layer located in the contact via is referred to as the active area. In this invention, the active layer is located on the upper surface of the insulating layer.

[0032] The output electrode is located on the upper surface of the active region in this invention, which is in contact with the output electrode and the lower surface of the active region is in contact with the input electrode.

[0033] In this invention, the current limiting layer overlaps with the output electrode.

[0034] Grounding electrode: In this invention, the grounding electrode is located on the upper surface of the current-limiting layer.

[0035] This invention, by adopting the above technical solutions, has significant technical effects:

[0036] The three-terminal memristor neuron device prepared in this invention can output corresponding pulse signals in real time based on the received input signals without the need for external circuitry. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of the first intermediate component in this invention;

[0039] Figure 2 This is a schematic diagram of the structure of the second intermediate component in this invention;

[0040] Figure 3 This is a schematic diagram of the structure of the invented three-terminal memristor neuron device.

[0041] Figure 4 This is a top view schematic diagram of the invention of the three-terminal memristor neuron device (for the sake of neatness, the substrate 100 and the insulating layer 300 are not omitted in the figure);

[0042] Figure 5 yes Figure 4 Enlarged cross-sectional view of region A in the middle;

[0043] Figure 6 This is a graph showing the electrical performance of the three-terminal memristor neuron device in Example 1;

[0044] Figure 7 This is a waveform diagram of the input signal of the three-terminal memristor neuron device in Example 1;

[0045] Figure 8 This is a waveform diagram of the output signal of the three-terminal memristor neuron device in Example 1;

[0046] Figure 9 This is a graph showing the electrical performance of the three-terminal memristor neuron device in Example 2;

[0047] Figure 10 These are the waveforms of the input and output signals of the three-terminal memristor neuron device in Example 2.

[0048] Figure 11 This is a graph showing the electrical performance of the three-terminal memristor neuron device in Example 3;

[0049] Figure 12 These are the waveforms of the input and output signals of the three-terminal memristor neuron device in Example 3.

[0050] In the picture:

[0051] 100 is the substrate, 200 is the input electrode, 300 is the insulating layer, 400 is the active layer, 500 is the output electrode, 600 is the current limiting layer, and 700 is the ground electrode.

[0052] 210 is the first electrode body, and 220 is the first connecting part;

[0053] 410 is the active region;

[0054] 510 is the second electrode body, and 520 is the second connecting part. Detailed Implementation

[0055] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments.

[0056] Example 1: A method for fabricating a three-terminal memristor neuron device, comprising the following steps:

[0057] S100. An input terminal electrode 200 is fabricated on the upper surface of the substrate 100 to obtain a first intermediate component. A schematic diagram of the structure of the first intermediate component is shown below. Figure 1 As shown;

[0058] In this embodiment, the input electrode 200 is a silver electrode;

[0059] S200: An insulating layer 300 is prepared on the upper surface of the first intermediate component, and a contact through hole is formed on the insulating layer 300.

[0060] S300: An active layer 400 is prepared on the upper surface of the insulating layer 300, and an output terminal electrode 500 is formed on the upper surface of the active layer 400 to obtain a second intermediate component. The structural schematic diagram of the second intermediate component is shown below. Figure 2 As shown;

[0061] In this embodiment, the region of the active layer 400 located within the contact via is designated as the active region 410, and the active region 410 is connected to the upper surface of the input electrode 200 and the lower surface of the output electrode 500, respectively.

[0062] S400. A current-limiting layer 600 is prepared on the upper surface of the second intermediate component, and a grounding electrode 700 is formed on the upper surface of the current-limiting layer 600 to obtain a three-terminal memristor neuron device. A schematic diagram of the structure of the three-terminal memristor neuron device is shown below. Figure 3 As shown in the top view diagram Figure 4As shown.

[0063] The complex dynamics of biological neurons originate from the dynamic behavior of the nerve membrane potential, and the dynamic characteristics of the nerve membrane are controlled by ion channels on the membrane, mainly including potassium ion channels and sodium ion channels. The on / off state of these ion channels can affect the dynamic behavior of the nerve membrane potential, i.e., voltage-gated ion channels.

[0064] This embodiment designs the input electrode 200, the active region 410, and the output electrode 500 so that, during actual operation, silver conductive filaments are induced to grow from the input electrode 200 to the output electrode 500 in the active region 410. The dynamic growth and breakage process of the silver conductive filaments under voltage simulates the switching state of potassium and sodium ions, thereby simulating the basic function of biological neurons.

[0065] Traditional CMOS neurons require hundreds of transistors and large capacitors, occupying a large area. In contrast, the three-terminal memristor neuron device provided in this application is based on the dynamic growth and breakage mechanism of silver conductive filaments. The diameter of the silver conductive filaments can be miniaturized to 10nm, and the three-terminal memristor neuron device can occupy an area of ​​less than 10nm*10nm. Therefore, the three-terminal memristor neuron device provided in this application is advantageous not only because memristor devices themselves have excellent scalability (<10nm), but also because auxiliary circuitry is removed, eliminating the need for the large capacitors (occupying approximately 1-100μm) typically used for integration. 2 (area), while possessing excellent scalability and high integration.

[0066] Existing neurons based on two-terminal memristor devices require a comparator to convert the memristor device current into an output voltage. However, the comparator is an active device and needs to be connected to a power supply.

[0067] This embodiment achieves a passive neuron device through the design of the current limiting layer 600 and the grounding electrode 700. In this embodiment, the current limiting layer 600 is equivalent to a grounded resistor, thereby converting the current generated when the silver conductive filament connects the input electrode 200 and the output electrode 500 into a voltage pulse, so that the output electrode 500 directly outputs a voltage pulse without the need for auxiliary circuits composed of a power supply and a comparator, which can effectively reduce the complexity and area occupied by the neuron circuit.

[0068] Traditional artificial neuron circuits require an additional sensing clock signal, which causes read operations to conflict with the input signal. Since the three-terminal memristor neuron device provided in this application is a passive device, it eliminates the need for a sensing clock signal, allowing input signals to approach or even overlap each other, thereby achieving true asynchronous, event-driven communication.

[0069] The specific implementation of fabricating the input electrode 200 on the upper surface of the substrate 100 in step S100 to obtain the first intermediate is as follows:

[0070] A first patterned region is defined by photolithography on the substrate 100, and silver of 10-70 nm is deposited based on the first patterned region to form an input electrode 200, thereby obtaining a first intermediate device.

[0071] The specific preparation method of the input electrode 200 in this embodiment is as follows:

[0072] A layer of photoresist (S1805) is spin-coated onto the prepared substrate 100, and then exposed by ultraviolet lithography (365nm wavelength) to form the pattern of the input electrode 200. After soaking in the developer (MF319) for 1 minute, a clear area of ​​the input electrode 200, namely the first pattern area, will appear.

[0073] A 70nm metallic silver film is deposited on the substrate 100. Then, the substrate 100 with the deposited metallic silver film is immersed in an acetone solution for 30 minutes. The photoresist and the deposited material (silver) on the photoresist are stripped off, leaving only the deposited silver film corresponding to the first pattern area to form the input electrode 200.

[0074] Note that the input electrode 200 is prepared using magnetron sputtering or other coating techniques, such as thermal evaporation, pulsed laser deposition, atomic layer deposition, etc. In this embodiment, a magnetron sputtering deposition machine is used to deposit metallic silver because the magnetron sputtering temperature is low and the photoresist is easy to peel off.

[0075] Furthermore, the substrate 100 used in this embodiment is a SiO2 / Si substrate;

[0076] A p-type Si substrate (100 crystal plane) is obtained, and a 1 μm thick thermally oxidized silicon dioxide layer is grown on the surface of the p-type Si substrate to obtain a SiO2 / Si substrate.

[0077] The specific implementation method for preparing an insulating layer 300 on the upper surface of the first intermediate component and forming contact vias on the insulating layer 300 in step S200 is as follows:

[0078] A second patterned region is defined by photolithography on the first intermediate component. The second patterned region includes a portion of the input terminal electrode 200. An insulating material is deposited based on the second patterned region to form an insulating layer 300.

[0079] The insulating layer 300 and the input terminal electrode 200 partially overlap to form an overlapping region. The insulating layer 300 is etched to form a contact via, which is located in the overlapping region.

[0080] The insulating material can be, for example, silicon dioxide (SiO2), aluminum oxide (Al2O3), or silicon nitride (Si3N4). In this embodiment, silicon dioxide (SiO2) is used as the insulating material.

[0081] Note that photolithography defines the second patterned region. The specific steps for depositing and forming the insulating layer 300 based on the second patterned region can refer to the steps for preparing the input electrode 200 described above. This embodiment will not elaborate on these steps. Those skilled in the art can set the thickness of the insulating layer 300 according to actual needs, as long as the insulation requirements are met. There is no need to limit it in detail. In this embodiment, 60nm of insulating material is deposited to form the insulating layer 300.

[0082] The specific steps for creating contact vias in the insulating layer 300 are as follows:

[0083] Contact windows are defined by photolithography on the insulating layer 300. Using existing publicly available etching processes, the insulating material corresponding to the contact windows is etched away to form contact vias.

[0084] Those skilled in the art can also set the size of the contact window according to actual needs (photolithography process). This embodiment does not need to limit it in detail. In this embodiment, the contact window is a 2μm*2μm graphic area.

[0085] In step S200, an active layer 400 is prepared on the upper surface of the insulating layer 300, and an output electrode 500 is formed on the upper surface of the active layer 400 to obtain the second intermediate. The specific method is as follows:

[0086] A third patterned region is defined by photolithography on the insulating layer 300. The third patterned region includes the area where the contact via is located. Based on the third patterned region, an active material of 10-30 nm and an inert metal material of 30-70 nm are deposited sequentially. The active material is deposited to form an active layer 400, and the inert metal material is deposited to form an output electrode 500.

[0087] Active materials, for example, can be FeO x MgO x SiO x or AlO x ;

[0088] Inert metal materials can be, for example, platinum (Pt), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), tantalum (Ta), tungsten (W), tin (TiN), or alloys of the above metals;

[0089] In this embodiment, 33 nm FeO is deposited sequentially. x And 70nm platinum, i.e., the active layer 400 is FeO x The layer has a platinum electrode at the output end (electrode 500).

[0090] Note that the photolithography defines a third patterned region. The specific steps for depositing the active layer 400 and the output electrode 500 sequentially based on the third patterned region can refer to the steps for preparing the input electrode 200 described above. This embodiment will not repeat the steps.

[0091] The specific implementation of step S400, which involves fabricating a current-limiting layer 600 on the upper surface of the second intermediate component and forming a grounding electrode 700 on the upper surface of the current-limiting layer 600, is as follows:

[0092] A fourth patterned region is defined by photolithography on the upper surface of the second intermediate component. The fourth patterned region includes a portion of the output electrode 500. Based on the fourth patterned region, 10-30 nm of insulating material and 30-70 nm of inert metal material are deposited sequentially. The insulating material is deposited to form a current-limiting layer 600, and the inert metal material is deposited to form a ground electrode 700.

[0093] In practical use, the current limiting layer 600 will be equivalent to an internal resistor. The thicker the current limiting layer 600, the greater the internal resistance. If the thickness of the current limiting layer 600 is less than 10nm, it is difficult to play an insulating role, and the equivalent internal resistance is too small, resulting in an excessively large current limit, which affects the automatic reset function of the three-terminal memristor neuron device. If the thickness of the current limiting layer 600 exceeds 30nm, the equivalent internal resistance is too large, making it difficult to play a current limiting role. Those skilled in the art can set the thickness of the current limiting layer 600 in the range of 10-30nm according to actual needs.

[0094] In this embodiment, 10nm of silicon dioxide and 70nm of titanium tungsten are deposited sequentially, that is, the current limiting layer 600 is a silicon dioxide layer and the grounding electrode 700 is a titanium tungsten electrode.

[0095] Note that the photolithography defines a fourth patterned region. The specific steps for depositing and forming the current limiting layer 600 and the ground terminal electrode 700 sequentially based on the fourth patterned region can refer to the steps for preparing the input terminal electrode 200 described above. This embodiment will not repeat the steps.

[0096] Reference Figure 3 The three-terminal memristor neuron device prepared based on the preparation method disclosed in this embodiment includes a substrate 100, and the following components stacked on the substrate 100 from bottom to top:

[0097] The silver electrode 200, which serves as the output electrode 200, has a thickness of 70 nm.

[0098] The silicon dioxide layer, serving as the insulating layer 300, has a thickness of 60 nm.

[0099] FeO as active layer 400 x The layer has a thickness of 33nm;

[0100] The platinum electrode used as the output electrode 500 has a thickness of 70 nm.

[0101] The silicon dioxide layer used as the current limiting layer 600 has a thickness of 10 nm;

[0102] The 700 tungsten titanium electrode, used as the grounding electrode, has a thickness of 70 nm.

[0103] Reference Figure 4 ,in:

[0104] The input electrode 200 includes a first electrode body 210, which has a narrow portion and a wide portion, wherein the narrow portion is provided with a first connecting portion 220;

[0105] The output electrode 500 includes a second electrode body 510, which has a narrow portion and a wide portion, wherein the narrow portion is provided with a second connecting portion 520.

[0106] Reference Figure 5 The active region 410 is located between the first connecting portion 220 and the second connecting portion 520, and the first connecting portion 220 and the second connecting portion 520 are connected through the active region 410.

[0107] In this embodiment, the wide portion of the first electrode body 210 and the wide portion of the second electrode body 510 are far apart from each other.

[0108] Note that in this embodiment, the projected pattern of the insulating layer 300 (ignoring the through holes) completely covers the projected pattern of the output electrode 500, and the projected pattern of the current limiting layer 600 completely covers the projected pattern of the ground electrode 700, so as to achieve the effect of insulation.

[0109] The electrical performance of the three-terminal memristor neuron device prepared in this embodiment was tested. The testing process was as follows:

[0110] Grounding is applied to the ground terminal electrode 700 of the three-terminal memristor neuron device, and a DC voltage (from 0V to 0.8V and then back to 0V) is applied to the input terminal electrode 200. The current at the output terminal electrode 500 is monitored, and the resulting electrical characteristic diagram is shown below. Figure 6 The curve corresponding to CC = 100 μA is shown below;

[0111] Reference Figure 6 It can be known that:

[0112] During the process of DC voltage changing from 0V to 0.8V, when the DC voltage applied to the input electrode 200 does not exceed the threshold voltage (V th When this occurs, the current monitored from the output electrode 500 remains at an extremely low level (10pA) until the DC voltage exceeds the threshold voltage (V). thAt this point, the current jump will become very high;

[0113] During the process of the DC voltage decreasing from 0.8V to 0V, until the DC voltage is less than the holding voltage (V hold When the current returns to its initial low current state, the current will return to its initial low current state.

[0114] The electrical characteristics of the resulting three-terminal memristor neuron device are shown in the figure below, obtained by replacing the current-limiting layer 600 in this embodiment with a 20nm silicon dioxide layer. Figure 6 The curve corresponding to CC = 10 μA is shown below;

[0115] The electrical characteristics of the resulting three-terminal memristor neuron device are shown in the figure below, obtained by replacing the current-limiting layer 600 in this embodiment with a 30nm silicon dioxide layer. Figure 6 The curve corresponding to CC = 1 μA is shown below;

[0116] Depend on Figure 6 It can be seen that the speed at which the current recovers to the initial low current state is related to the compliance current (CC). When the CC current is smaller, the silver conductive filaments formed in the active region 410 are thinner and are more likely to spontaneously break under the influence of surface energy and concentration gradient, thus the recovery speed is faster. The CC current is related to the thickness of the current limiting layer 600. The thicker the current limiting layer 600, the larger the equivalent built-in resistance, which leads to a smaller CC current and makes the device recover to the off state faster.

[0117] Functional verification was performed on the three-terminal memristor neuron device prepared in this embodiment;

[0118] As can be seen from the above process of testing electrical performance, when an input voltage pulse signal is applied, the silver conductive filaments in the three-terminal memristor neuron device will be induced to grow slowly from the input electrode 200 to the output end in the active region 410. However, when the voltage is removed or the voltage is small, the conductive filaments will spontaneously break under the action of surface energy and concentration gradient. Therefore, in actual use, the leakage integrate-and-fire (LIF) neuron function can be realized based on the above electrical characteristics of the three-terminal memristor neuron device. The following verifies the realization of the neuron function of the three-terminal memristor neuron device prepared in this embodiment. The verification steps are as follows:

[0119] The input electrode 200 of the three-terminal memristor neuron device (current limiting layer 600 thickness is 10nm) prepared in this embodiment is connected to a pulse function generator, the output electrode 500 is connected to an oscilloscope, and the ground electrode 700 is grounded. The pulse function generator generates a continuous voltage pulse (3.3V, pulse width 1ms).

[0120] The waveform of the input signal of the three-terminal memristor neuron device is shown below. Figure 7As shown, the waveform of the output signal is as follows: Figure 8 As shown, its working process is as follows:

[0121] The continuous voltage pulse signal generated by the pulse function generator induces the growth of silver conductive filaments in the active region 410. This process is dominated by electron tunneling, resulting in extremely low current (10 pA) in the entire three-terminal memristor neuron device. Because of this extremely low current, the voltage at the output electrode 500 is 0 V. This process is equivalent to the accumulation of neurons. However, as the voltage pulse is removed, the silver conductive filaments spontaneously contract, resulting in leakage. Figure 8 This corresponds to the integration stage;

[0122] As the silver conductive filaments gradually grow until they connect the input electrode 200 and the output electrode 500, a huge current is generated. This current passes through the current-limiting layer 600 (equivalent to an internal resistor), which converts this current into a corresponding voltage pulse output, representing the neuron's firing behavior. Figure 8 Corresponding to the mid-fire stage;

[0123] Because the silver conductive filament connects the input electrode 200 and the output electrode 500, the resistance of the three-terminal memristor neuron device decreases. At this point, most of the voltage falls across the current-limiting layer 600. The reduced voltage across the input electrode 200 and the output electrode 500 causes the thin conductive filament to break spontaneously, restoring the three-terminal memristor neuron device to a high-resistance state. This achieves the automatic reset function of the memristor neuron. Figure 8 This corresponds to the Auto-reset stage.

[0124] During the accumulation process, the current of the three-terminal memristor neuron device is extremely low (10pA). During the entire process of the three-terminal memristor neuron device generating pulses, most of the power consumption is consumed in the emission process. The current in the emission process is limited by the output terminal and the current limiting layer 600. Therefore, the power consumption of the entire three-terminal memristor neuron device can be as low as 10fJ.

[0125] In summary, the three-terminal memristor neuron device proposed in this embodiment exhibits almost zero current during integration and automatically recovers to a static potential after excitation. Furthermore, the insulating layer 300 provides a limiting current, enabling the three-terminal memristor neuron device to achieve the basic functions of biological neurons, such as accumulation, leakage, emission, and depolarization, through a single neuron, while also achieving power consumption comparable to that of biological neurons (10 fJ).

[0126] Example 2: The inert metal material used for the output electrode 500 in Example 1 and the deposition thickness of each layer were adjusted, while everything else remained the same as in Example 1. The resulting three-terminal memristor neuron device consisted of the following components stacked sequentially from bottom to top on the substrate 100:

[0127] The silver electrode 200 used as the input electrode has a thickness of 40 nm.

[0128] The functional layer 300 comprises an insulating layer 300 and an active layer 400, wherein the insulating layer 300 is a silicon dioxide layer with a thickness of 60 nm, and the active layer 400 is FeO. x The layer is 30nm thick;

[0129] The tungsten electrode 500, which serves as the output electrode 500, has a thickness of 60 nm.

[0130] The silicon dioxide layer used as the current limiting layer 600 has a thickness of 20nm;

[0131] The 700 tungsten titanium electrode, used as the grounding electrode, has a thickness of 60 nm.

[0132] The electrical performance diagram of the above three-terminal memristor neuron device is shown in Figure 1. Figure 9 As shown, by Figure 9 It is understood that, provided that the thickness of each layer meets the requirements of this application, the output electrode 500 can be changed to other inert metal electrodes (tungsten electrodes), and the three-terminal memristor neuron device can still simulate the function of a neuron on a single device.

[0133] The input signal and output signal obtained for functional verification of the above three-terminal memristor neuron device are as follows: Figure 10 As shown.

[0134] Reference Figure 9 and Figure 10 It can be seen that the three-terminal memristor neuron device provided in this embodiment can also realize the accumulation, firing and automatic reset of biological neurons, but the current in the accumulation stage fluctuates to a certain extent, and the power consumption will be higher than that of the three-terminal memristor neuron device provided in Embodiment 1.

[0135] Example 3: The active material used in the active layer 400 and the deposition thickness of each layer in Example 2 were adjusted, while all other aspects remained the same as in Example 2. The resulting three-terminal memristor neuron device consisted of the following components stacked sequentially from bottom to top on the substrate 100:

[0136] The silver electrode 200 used as the input electrode has a thickness of 30 nm.

[0137] The functional layer 300 comprises an insulating layer 300 and an active layer 400, wherein the insulating layer 300 is a silicon dioxide layer with a thickness of 60 nm, and the active layer 400 is MgO.x The layer is 30nm thick;

[0138] The tungsten electrode 500, which serves as the output electrode 500, has a thickness of 60 nm.

[0139] The silicon dioxide layer used as the current limiting layer 600 has a thickness of 30nm;

[0140] The 700 tungsten titanium electrode, used as the grounding electrode, has a thickness of 60 nm.

[0141] The electrical performance diagram of the above three-terminal memristor neuron device is shown in Figure 1. Figure 11 As shown, by Figure 11 It can be seen that, provided that the thickness of each layer meets the requirements of this application, the active layer 400 can be made of other active materials (MgO). x Three-terminal memristor neuron devices can still simulate the function of neurons on a single device.

[0142] The input signal and output signal obtained for functional verification of the above three-terminal memristor neuron device are as follows: Figure 12 As shown.

[0143] Reference Figure 11 and Figure 12 It can be seen that the three-terminal memristor neuron device provided in this embodiment can also realize the accumulation, firing and automatic reset of biological neurons, but the current in the accumulation stage fluctuates to a certain extent, and the power consumption will be higher than that of the three-terminal memristor neuron device provided in Embodiment 1.

[0144] It should be noted that:

[0145] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0146] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0147] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0148] Furthermore, it should be noted that the shapes and names of the parts and components described in the specific embodiments described in this specification may differ. All equivalent or simple variations made to the structure, features, and principles described in this patent concept are included within the protection scope of this patent. Those skilled in the art to which this invention pertains may make various modifications or additions to the described specific embodiments or use similar methods to replace them, as long as they do not depart from the structure of this invention or exceed the scope defined in these claims, they should all fall within the protection scope of this invention.

Claims

1. A method for fabricating a three-terminal memristor neuron device, characterized in that, This includes the following steps performed sequentially: S100. An input electrode is fabricated on the upper surface of a substrate to obtain a first intermediate component, wherein the input electrode is a silver electrode. S200. An insulating layer is prepared on the upper surface of the first intermediate component, and a contact through hole is formed on the insulating layer; S300. An active layer is prepared on the upper surface of the insulating layer, and an output electrode is formed on the upper surface of the active layer to obtain a second intermediate device. The region of the active layer located in the contact via is defined as the active region. The active region is connected to the upper surface of the input electrode and the lower surface of the output electrode, respectively. During device operation, a silver conductive filament grows from the input electrode to the output electrode in the active region. The dynamic growth and breakage process of the silver conductive filament under voltage is used to simulate the switching state of potassium ions and sodium ions. S400. A current-limiting layer is prepared on the upper surface of the second intermediate component, and a ground terminal electrode is formed on the upper surface of the current-limiting layer to obtain a three-terminal memristor neuron device.

2. The method for fabricating a three-terminal memristor neuron device according to claim 1, characterized in that, Step S100 includes: A first patterned region is defined by photolithography on the substrate, and 10-70 nm of silver is deposited based on the first patterned region to form an input electrode, thereby obtaining a first intermediate device.

3. The method for fabricating a three-terminal memristor neuron device according to claim 1 or 2, characterized in that, Step S200 includes: A second patterned region is defined by photolithography on the first intermediate component. The second patterned region includes a portion of the input terminal electrode. An insulating material is deposited based on the second patterned region to form an insulating layer. The insulating layer and the input terminal electrode partially overlap to form an overlapping region. The insulating layer is etched to form a contact via, which is located in the overlapping region.

4. The method for fabricating a three-terminal memristor neuron device according to claim 3, characterized in that, Step S300 includes: A third patterned region is defined by photolithography on the insulating layer. The third patterned region includes the area where the contact via is located. An active material and an inert metal material are sequentially deposited based on the third patterned region. The active material is deposited to form an active layer, and the inert metal material is deposited to form an output electrode.

5. The method for fabricating a three-terminal memristor neuron device according to claim 4, characterized in that: The active material is FeO. x MgO x SiO x or AlO x .

6. The method for fabricating a three-terminal memristor neuron device according to claim 1 or 2, characterized in that, Step S400 includes: A fourth patterned region is defined by photolithography on the upper surface of the second intermediate component. The fourth patterned region includes a portion of the output electrode. An insulating material and an inert metal material are sequentially deposited based on the fourth patterned region. The insulating material is deposited to form a current-limiting layer, and the inert metal material is deposited to form a ground electrode.

7. The method for fabricating a three-terminal memristor neuron device according to claim 1 or 2, characterized in that: The thickness of the output electrode and the ground electrode is 30~70 nm.

8. The method for fabricating a three-terminal memristor neuron device according to claim 1 or 2, characterized in that: The thickness of the current-limiting layer is 10-30 nm.

9. The method for fabricating a three-terminal memristor neuron device according to claim 1 or 2, characterized in that: The thickness of the active layer is 20-40 nm.

10. A three-terminal memristor neuron device prepared according to any one of claims 1 to 9.

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