A method and device for implementing patches, an embedded system, and a storage medium

Abstract

The present application provides a patch implementation method, apparatus, embedded system, and storage medium. When a patch needs to be applied, a patch function corresponding to a target function with a jump operation instruction set at the function entry is obtained and stored, and then the address in the memory variable corresponding to the target function is modified to point to the address of the patch function. The entire process is automated and does not require manual participation. Additionally, by changing the address in the memory variable, it is possible to jump to the patch function without changing the function call semantics, which is more convenient for code optimization and static analysis.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and more specifically, to a patch implementation method, apparatus, embedded system, and storage medium. Background Art

[0002] With the rapid development of Internet technology, various software applications emerge in an endless stream. When software has BUGs or needs to be upgraded to add new functions, patches can be applied to the corresponding code of the software. In existing solutions, software developers need to manually modify the code and change the function call semantics. If there are many points where patches need to be applied, the workload of software developers is large and new BUGs are easily introduced. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide a patch implementation method, apparatus, embedded system, and storage medium to solve the problems in the prior art that when applying patches to software, it is necessary to manually change the function call semantics, resulting in a large workload and easily introducing new BUGs.

[0004] The embodiments of this application provide a patch implementation method, including:

[0005] Obtain and store a patch function corresponding to a target function; a jump operation instruction is set at the function entry of the target function; the jump operation instruction is used to jump to the address in the memory variable corresponding to the target function when receiving an execution instruction for the target function, so as to execute the function corresponding to the address;

[0006] Modify the address in the memory variable to point to the address of the patch function.

[0007] In the above implementation process, when a patch needs to be applied, obtain and store a patch function corresponding to a target function with a jump operation instruction set at the function entry, and then modify the address in the memory variable corresponding to the target function to point to the address of the patch function. The whole process is automated and does not require manual participation. In addition, by changing the address in the memory variable, it is possible to jump to the patch function without changing the function call semantics, which is more convenient for code optimization and static analysis.

[0008] Further, before obtaining and storing the patch function corresponding to the target function, the method further includes:

[0009] Obtain the source program;

[0010] Determine the function to be patched from the source program;

[0011] Generate a no-operation instruction at the function entry of the function to be patched;

[0012] Generate corresponding jump operation instructions for the function to be patched;

[0013] Replace the NOP instruction with the corresponding jump operation instruction to obtain the target function.

[0014] In the above implementation process, a NOP instruction is generated at the function entry of the function to be patched, reserving storage space for subsequent modification to a jump operation instruction.

[0015] Further, generating a NOP instruction at the function entry of the function to be patched includes:

[0016] During the compilation of the source program, a NOP instruction is generated at the function entry of the function to be patched through a compilation tool.

[0017] In the above implementation process, a NOP instruction is directly generated at the function entry of the function to be patched through a compilation tool, and the generation method is simple and convenient.

[0018] Further, the jump operation instruction is used to load the address in the memory variable corresponding to the target function into a temporary register when receiving an execution instruction for the target function, and jump to the address pointed to by the temporary register.

[0019] In the above implementation process, a jump operation is implemented based on a temporary register, and it can jump to the address pointed to by the temporary register, expanding the jump space range.

[0020] Further, the function of the jump operation instruction is implemented by an extended operation instruction; the extended operation instruction includes memory variable identification information, register identification information, and operation code information, and the extended operation instruction is used to: load the address from the memory variable corresponding to the memory variable address into the temporary register corresponding to the register identification information, and jump to the address pointed to by the temporary register; the memory variable address is an address calculated according to the corresponding offset address and the preset address in the base address register, and the offset address is an address calculated according to the memory variable identification information.

[0021] In the above implementation process, the function of the jump operation instruction is implemented by an extended operation instruction. Compared with implementing this function through multiple operation instructions, it can save the memory space occupied by the program and improve the execution efficiency of the processor.

[0022] Further, the target function is a function pre-set in the read-only memory.

[0023] In the above implementation process, since the target function is pre-set in the read-only memory, the system power consumption can be reduced and the cost can be reduced.

[0024] Further, the obtaining and storing the patch function corresponding to the target function includes:

[0025] Obtain the patch function corresponding to the target function, and store the patch function in a memory with modifiable data.

[0026] In the above implementation process, storing the patch function in a memory with modifiable data facilitates subsequent modification of the patch function.

[0027] Further, after modifying the address in the memory variable to point to the address of the patch function, the method further includes:

[0028] Obtain a new patch function corresponding to the target function;

[0029] Store the new patch function in the memory with modifiable data;

[0030] When the starting address of the new patch function in the memory with modifiable data is different from the starting address of the original patch function in the memory with modifiable data, modify the address in the memory variable to point to the address of the new patch function.

[0031] In the above implementation process, by modifying the address in the memory variable to point to the address of the new patch function, a new patch can be applied to the target function.

[0032] Further, the storing the new patch function in the memory with modifiable data includes:

[0033] When it is determined that the memory space size required by the new patch function is less than or equal to the memory space size occupied by the original patch function, delete the original patch function from the memory with modifiable data, and store the new patch function in the position of the original patch function; the starting address of the new patch function in the memory with modifiable data is the same as the starting address of the original patch function in the memory with modifiable data;

[0034] When it is determined that the memory space size required by the new patch function is greater than the memory space size occupied by the original patch function, store the new patch function in the free space that can accommodate the new patch function, and the free space is the free storage space in the memory with modifiable data.

[0035] In the above implementation process, on the one hand, when it is determined that the memory space size required by the new patch function is less than or equal to the memory space size occupied by the original patch function, the new patch function can be overwritten on the original patch function, which can save the memory resources occupied by the program. And since the starting address of the new patch function in the data-modifiable memory is the same as the starting address of the original patch function in the data-modifiable memory, there is no need to modify the address in the corresponding memory variable at this time, so the processing efficiency can be improved. On the other hand, when it is determined that the memory space size required by the new patch function is greater than the memory space size occupied by the original patch function, the new patch function can be stored in another free space that can accommodate the function, and then the address in the memory variable is modified to point to the address of the new patch function.

[0036] The embodiment of the present application also provides a patch implementation device, including:

[0037] An acquisition storage module, configured to acquire and store a patch function corresponding to a target function; the target function is a function to be patched with a jump operation instruction set at the function entry; the jump operation instruction is used to control a jump to an address in a memory variable corresponding to the target function when the target function receives an execution instruction, so as to execute a function corresponding to the address;

[0038] A modification module, configured to modify the address in the memory variable to the current storage address of the patch function.

[0039] The embodiment of the present application also provides an embedded system, including a processor and a memory, where a computer program is stored in the memory, and the processor executes the computer program to implement any one of the above methods.

[0040] The embodiment of the present application also provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by at least one processor, any one of the above methods is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 It is a schematic flowchart of a patch implementation method provided in Embodiment 1 of the present application;

[0043] Figure 2Schematic flow chart of generating an objective function provided in the first embodiment of the present application;

[0044] Figure 3 First function layout diagram provided in the first embodiment of the present application;

[0045] Figure 4 Second function layout diagram provided in the first embodiment of the present application;

[0046] Figure 5 Schematic diagram of the instruction structure of the extended operation instruction provided in the first embodiment of the present application;

[0047] Figure 6 Third function layout diagram provided in the first embodiment of the present application;

[0048] Figure 7 Schematic diagram of the structure of the patch implementation device provided in the second embodiment of the present application;

[0049] Figure 8 Schematic diagram of the structure of the embedded system provided in the third embodiment of the present application. Detailed implementation manners

[0050] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] It should be noted that the descriptions involving "first", "second", etc. in the embodiments of the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0052] In the description of the present invention, it should be understood that the numerical labels before the steps do not represent the sequence of executing the steps, but are only used to conveniently describe the present invention and distinguish each step, and thus cannot be understood as a limitation to the present invention.

[0053] Multiple embodiments will be provided below to specifically introduce the patch implementation method, device, embedded system and storage medium.

[0054] Embodiment 1:

[0055] To solve the problem in the prior art that when patching software, it is necessary to manually change the function call semantics, which is laborious and prone to introducing new BUGs, the embodiment of the present application provides a patch implementation method. Please refer to Figure 1 as shown. The method can be executed by an embedded system on which a target function is stored, and a jump operation instruction is set at the function entry of the target function; the jump operation instruction is used to jump to the address in the memory variable corresponding to the target function when receiving an execution instruction for the target function, so as to execute the function corresponding to the address.

[0056] The following elaborates on the specific process of the patch implementation method in detail. It should be noted that the method provided by the present invention is not limited by Figure 1 the specific order described below.

[0057] Step S11: Obtain and store a patch function corresponding to the target function, and a jump operation instruction is set at the function entry of the target function.

[0058] Step S12: Modify the address in the memory variable to point to the address of the patch function.

[0059] It should be noted that an embedded system generally has a CPU (Central Processing Unit), RAM (Random Access Memory), ROM (Read-Only Memory), Flash (Flash Memory), etc. The program code can be placed in the ROM, and the data can be placed in the on-chip RAM. The characteristic of placing the program code in the ROM is low cost, and it is produced together with the integrated circuit photomask. When the integrated circuit is manufactured, the program code cannot be modified. If there are manufacturing errors or logical errors in the program code, it can be repaired by patching.

[0060] In the embodiment of the present application, in order to reduce costs and save power consumption, when manufacturing an integrated circuit, the target function can be set in the read-only memory. The patch function is usually generated after the integrated circuit is manufactured, and the patch function may be modified again later. Therefore, in step S11, the obtained patch function can be stored in a memory with modifiable data, for example, stored in the RAM or Flash.

[0061] For easy understanding, first, the process of generating the target function is described.

[0062] Please refer to Figure 2 as shown. The target function in the embodiment of the present application can be generated through the following steps before step S11:

[0063] Step S111: Obtain the source program.

[0064] In the embodiments of the present application, the corresponding source program can be obtained for an application program, and the source program here refers to the source code of the application program.

[0065] Step S112: Determine the function to be patched from the source program.

[0066] In step S112, the function to be patched can be determined according to the actual application scenario. For example, there may be 100 or 200 functions to be patched in a source program.

[0067] Step S113: Generate a no-operation instruction at the function entry of the function to be patched.

[0068] In step S113, when compiling the source program, a no-operation instruction can be generated at the function entry of the function to be patched through a compilation tool. For example, through the compilation option patchable-function-entry in the open-source compiler GNU GCC, a NOP instruction can be generated at the function entry of the function to be patched. Here, the NOP instruction is also a no-operation instruction. For example, if fpatchable-function-entry = 3, the compiler will generate an additional and continuous series of 3 NOP instructions at the entry point of the function.

[0069] Step S114: Generate a corresponding jump operation instruction for the function to be patched.

[0070] Step S115: Replace the no-operation instruction with the corresponding jump operation instruction to obtain the target function.

[0071] After the linker completes the linking of the source program, the no-operation instruction can be replaced with the corresponding jump operation instruction to obtain the target function, and then the target function is stored in the read-only memory. Of course, the functions in the source program that do not need to be patched can also be stored in the read-only memory.

[0072] It can be understood that the jump operation instruction in the embodiments of the present application is essentially a function, and the function can be run by a processor in an embedded system to implement the corresponding function. The jump operation instruction in the embodiments of the present application can adopt the instructions in the existing instruction sets. For example, the standard instructions in the ARM instruction set, RISCV instruction set, MIPS instruction set, or x86 instruction set can be directly used to implement the jump function.

[0073] It can be understood that in actual applications, an appropriate number of NOP instructions can be reserved at the function entry of the function to be patched according to the characteristics of the instructions to be used. The appropriate number of NOP instructions here serves as a placeholder, and the space they occupy needs to accommodate the size of the jump operation instruction in step S114.

[0074] The jump operation instruction in the embodiment of the present application can implement the jump function based on a register. That is, the jump operation instruction is used to load the address of the memory variable corresponding to the target function into a temporary register when receiving an execution instruction for the target function, and then jump to the address pointed to by the temporary register. Of course, in other embodiments, the jump function can also be implemented based on a long jump or a short jump.

[0075] When the jump operation instruction implements the jump function based on the register, if the instructions in the existing RISCV instruction set are used, three NOP instructions need to be generated at the function entry of the function to be patched. For details, please refer to Figure 3 As shown, Figure 3 This is the function layout diagram after linking is completed but instruction replacement has not yet started. Figure 3 There are three functions to be patched, func1, func2, and func3, and any of these three functions can be patched as needed. It should be noted that the embodiment of the present application is not limited to three functions to be patched.

[0076] Figure 3 Entry1, Entry2, and Entry3 in the table represent the memory variables corresponding to the target function func1, the memory variables corresponding to the target function func2, and the memory variables corresponding to the target function func3, respectively. Figure 3 Entry1, Entry2, and Entry3 in the function store the starting addresses of the func1, func2, and func3 function bodies, respectively, rather than the starting addresses of the functions func1, func2, and func3. The starting address of each function body is equal to the starting address of each function minus a fixed offset. This fixed offset is the length occupied by consecutive NOP instructions. Assuming the fixed offset is N bytes, the starting address of the func(x) function body = the starting address of the func(x) function - N.

[0077] After replacing the no-operation instructions with the corresponding jump operation instructions to obtain the target function, the function layout diagram can be found in Figure 4 As shown, at this time, the jump operation instruction has replaced the NOP instruction sequence. It should be noted that in the embodiment of the present application, a corresponding memory variable needs to be preset for each function to be patched, and the memory variable is stored in a data-modifiable memory. The size of the memory variable can be flexibly selected according to the system's memory resources. In this way, each target function has a corresponding memory variable.

[0078] It is understandable that a continuous address space can be opened in the data modifiable memory to store the memory variables corresponding to each function to be patched. Each memory variable is stored continuously in the address space, that is, it can be stored in the order ofFigure 3 or Figure 4 store each memory variable in the manner shown.

[0079] The temporary register used to load the memory variable, that is Figure 3 and Figure 4 the Register in

[0080] It should be noted that the function of the jump operation instruction in the embodiments of the present application can be implemented by an extended operation instruction. Please refer to Figure 5 As shown, the extended operation instruction includes memory variable identification information, register identification information, and operation code information. In the embodiments of the present application, 10 bit positions can be allocated for the memory variable identification information. The extended operation instruction in the embodiments of the present application is used to: load the address from the memory variable corresponding to the memory variable address into the temporary register corresponding to the register identification information, and jump to the address pointed to by the temporary register; the memory variable address is the address calculated according to the corresponding offset address and the preset address in the base address register, and the offset address is the address calculated according to the memory variable identification information. Specifically, the offset address can be calculated according to the memory variable identification information, the memory size occupied by the memory variable, and the memory size occupied by the address stored in the memory variable.

[0081] If the standard instruction in the 32-bit RISCV instruction set architecture is used to implement "loading the address in the corresponding memory variable into the temporary register and jumping to the address pointed to by the temporary register", since the memory variable itself occupies 4 bytes, and the "loading" operation also requires a certain amount of byte space, and each instruction in the RISCV instruction set architecture corresponds to a maximum of 4 bytes of storage space, so if the function of the jump operation instruction is implemented by the standard instruction in the RISCV instruction set architecture, 3 RISCV instructions are required. Two 4-byte instructions are used to implement "loading the address in the memory variable into the temporary register", and one 2-byte instruction is used to implement "jumping to the address pointed to by the temporary register". Therefore, if the function of the jump operation instruction in the embodiments of the present application is implemented by the standard instruction in the existing instruction set architecture, this instruction requires a total of 10 bytes of storage space.

[0082] In the embodiments of the present application, a method for implementing the function of a jump operation instruction by extending an operation instruction is provided. When implementing "loading the address in the corresponding memory variable into a temporary register and jumping to the address pointed to by the temporary register" through the extended operation instruction provided in the embodiments of the present application, since the processor can calculate the memory variable address based on the memory variable identification information and the preset address in the base address register, and there is no need to carry the memory variable address in the extended instruction, therefore, the function of "loading the address in the corresponding memory variable into a temporary register and jumping to the address pointed to by the temporary register" can be implemented through a 4-byte instruction. On the one hand, this extended instruction saves storage space, and on the other hand, it realizes the jump of the entire address space.

[0083] It can be understood that the semantics of the extended instruction in the embodiments of the present application is: loading the value of L+P into the corresponding Register and jumping to the address indicated by Register, where L represents the preset address in the base address register JBRegister, and P represents the offset of the address of the patch function relative to the preset address. P can be calculated based on the memory variable identification information, the address space size occupied by the memory variable, and the address space size occupied by the address stored in the memory variable in the extended operation instruction. Generally speaking, the address space size occupied by the memory variable is equal to the address space size occupied by the address stored in the memory variable. Therefore, the offset address can be calculated through the formula P = Entry ID*M - M, where Entry ID is the memory variable identification, representing the first, second... nth memory variable, M represents the address space size occupied by a memory variable, and the address space size occupied by an address in the memory variable can also be M. For a 32-bit processor, M can be taken as 4 bytes, and for a 64-bit processor, M can be taken as 8 bytes. The specific value of M can be flexibly set according to the actual application scenario. In the embodiments of the present application, an example is given with M equal to 4 bytes. At this time, the semantics of the extended instruction is: loading the value of L+EntryID*4 - 4 into the corresponding Register and jumping to the address indicated by Register.

[0084] JBRegister in the embodiments of the present application is a register that can be written by a program. According to the planning of Flash or RAM in the embedded system, it can point to the address of the first memory variable, that is, the address of Entry 1. Of course, in other embodiments, JBRegister can also point to the addresses of other memory variables, such as Entry 2, Entry 3, etc. In the embodiments of the present application, JBRegister is configured to cooperate with the extended instruction to implement the function of "loading the address in the corresponding memory variable into a temporary register and jumping to the address pointed to by the temporary register".

[0085] It can be understood that, in order to improve the speed of reading memory variables, the memory variables in the embodiments of the present application can be stored in the RAM.

[0086] After generating the target functions in the above manner and completing the configuration of the memory variables corresponding to each target function, the target functions can be patched through the above steps S11 and S12.

[0087] Please refer to Figure 6 as shown. Suppose an application has Figure 6 the 3 target functions shown. These 3 target functions are stored in the ROM. Here, taking patching the target function func2 as an example for illustration.

[0088] First, the new func2 can be obtained and stored. Here, the new func2 is also the patch function of the target function func2, and the new func2 is a function that has undergone compilation and linking processing. In the embodiments of the present application, the obtained new func2 can be stored in the Flash. It should be noted that the new func2 here can be a normal function, that is, a function without a NOP instruction at the function entry.

[0089] Then, change the address stored in the memory variable Entry2 corresponding to the target function func2 to the starting address of the new func2 function. The effect of this is that when the original func2 in the ROM is called, that is, when the target function func2 is called, the program control flow will be transferred to the new func2 for execution via the pointer of the Register. That is, at this time, the function body of the old func2 will no longer be executed, achieving the purpose of replacing the old func2 with the new func2.

[0090] In practical applications, when patching an application, the patch functions corresponding to multiple target functions of the application can be obtained, and then each patch function can be stored in a memory with modifiable data, and the addresses in the memory variables corresponding to each target function can be modified to point to the addresses of their respective corresponding patch functions. It should be noted that each of these patch functions is a function that has undergone compilation and linking. It can be understood that after patching the target function in the above manner, a new patch can also be applied to the target function.

[0091] In one embodiment, when a new patch needs to be applied to a target function of the application, all patch functions corresponding to the application in the modifiable memory can be cleared first, and then all patch functions corresponding to the application in the modifiable memory are rewritten. That is, at this time, the new patch function corresponding to the target function needs to be obtained, and the original patch functions corresponding to other target functions also need to be obtained, and then the new patch function and the original patch functions are rewritten into the modifiable memory. Here, other target functions refer to those target functions that do not need to be patched this time but have been patched before. It can be understood that the new patch function and the original patch functions here are functions that have been compiled and linked. In this embodiment, packing and overall rewriting all patch functions corresponding to the target application can save storage space and improve patch reliability.

[0092] In another embodiment, when a new patch needs to be applied to a target function, it is not necessary to clear the patch functions corresponding to the application in the modifiable memory. Instead, only the new patch function corresponding to the target function can be rewritten into the modifiable memory, and the original patch functions corresponding to other target functions are retained in the modifiable memory. That is, in this embodiment, it is not necessary to rewrite the original patch functions corresponding to other target functions into the modifiable memory. This can reduce the amount of function rewriting and improve the rewriting efficiency.

[0093] Specifically, in the embodiments of the present application, after patching the target function, when applying a new patch to the patch function, that is, after step S12, the following steps may further be included:

[0094] Obtain the new patch function corresponding to the target function;

[0095] Store the new patch function in the modifiable memory;

[0096] When the starting address of the new patch function in the modifiable memory is different from the starting address of the original patch function in the modifiable memory, modify the address in the memory variable corresponding to the target function to point to the address of the new patch function.

[0097] When it is determined that the memory space size required by the new patch function is less than or equal to the memory space size occupied by the original patch function, delete the original patch function from the modifiable memory and store the new patch function in the position of the original patch function; the starting address of the new patch function in the modifiable memory is the same as the starting address of the original patch function in the modifiable memory;

[0098] When it is determined that the memory space required for the new patch function is larger than the memory space occupied by the original patch function, the new patch function is stored in the free space that can accommodate the new patch function, and the free space is the free storage space in the memory where data can be modified.

[0099] In the above implementation process, on the one hand, when it is determined that the memory space required for the new patch function is less than or equal to the memory space occupied by the original patch function, the new patch function can be overwritten on the original patch function, which can save the memory resources occupied by the program. And since the starting address of the new patch function in the memory where data can be modified is the same as the starting address of the original patch function in the memory where data can be modified, there is no need to modify the address in the corresponding memory variable at this time, so the processing efficiency can be improved. On the other hand, when it is determined that the memory space required for the new patch function is larger than the memory space occupied by the original patch function, the new patch function can be stored in another free space that can accommodate the function, and then the address in the memory variable is modified to point to the address of the new patch function.

[0100] Through the patch implementation method provided by the embodiments of the present application, when a patch needs to be applied, the patch function corresponding to the target function with a jump operation instruction set at the function entry is obtained and stored, and then the address in the memory variable corresponding to the target function is modified to point to the address of the patch function. The whole process is automated and does not require manual participation. In addition, by changing the address in the memory variable, it is possible to jump to the patch function without changing the function call semantics, which is more convenient for code optimization and static analysis.

[0101] Embodiment 2:

[0102] The embodiments of the present application provide a patch implementation device. Please refer to Figure 7 as shown, including:

[0103] An acquisition and storage module 701, configured to acquire and store a patch function corresponding to a target function; the target function is a function to be patched with a jump operation instruction set at the function entry; the jump operation instruction is used to control a jump to the address in the memory variable corresponding to the target function when the target function receives an execution instruction, so as to execute the function corresponding to the address;

[0104] A modification module 702, configured to modify the address in the memory variable to point to the address of the patch function.

[0105] In an exemplary embodiment, the apparatus further includes an objective function generation module, configured to obtain a source program; determine a function to be patched from the source program; generate a no-operation instruction at the function entry of the function to be patched; generate a corresponding jump operation instruction for the function to be patched; and replace the no-operation instruction with the corresponding jump operation instruction to obtain the objective function.

[0106] In an exemplary embodiment, the objective function generation module is configured to generate a no-operation instruction at the function entry of the function to be patched through a compilation tool during the compilation of the source program.

[0107] In an exemplary embodiment, the jump operation instruction is configured to, when receiving an execution instruction for the objective function, load an address in a memory variable corresponding to the objective function into a temporary register, and jump to the address pointed to by the temporary register.

[0108] In an exemplary embodiment, the function of the jump operation instruction is implemented by an extended operation instruction; the extended operation instruction includes memory variable identification information, register identification information, and operation code information, and the extended operation instruction is configured to: load an address from a memory variable corresponding to a memory variable address into a temporary register corresponding to the register identification information, and jump to the address pointed to by the temporary register; the memory variable address is an address calculated according to a corresponding offset address and a preset address in a base address register, and the offset address is an address calculated according to the memory variable identification information.

[0109] In an exemplary embodiment, the objective function is a function pre-set in a read-only memory.

[0110] In an exemplary embodiment, the acquisition and storage module 701 is configured to obtain a patch function corresponding to an objective function, and store the patch function in a memory with modifiable data.

[0111] In an exemplary embodiment, the acquisition and storage module 701 is configured to obtain a new patch function corresponding to an objective function, store the new patch function in a memory with modifiable data, and when a starting address of the new patch function in the memory with modifiable data is different from a starting address of the original patch function in the memory with modifiable data, modify the address in the memory variable to point to the new patch function.

[0112] In an exemplary embodiment, the acquisition storage module 701 is configured to delete the original patch function from the memory where data can be modified and store the new patch function at the position of the original patch function when it is determined that the memory space required by the new patch function is less than or equal to the memory space occupied by the original patch function; the starting address of the new patch function in the memory where data can be modified is the same as the starting address of the original patch function in the memory where data can be modified; when it is determined that the memory space required by the new patch function is greater than the memory space occupied by the original patch function, the new patch function is stored in the free space that can accommodate the new patch function, and the free space is the free storage space in the memory where data can be modified.

[0113] In an exemplary embodiment, the acquisition storage module 701 is used to store the new patch function, and the modification module 702 is used to modify the address in the memory variable to point to the address of the new patch function.

[0114] It should be understood that for the sake of concise description, some content described in Embodiment 1 will not be repeated in this embodiment.

[0115] Embodiment 3:

[0116] Based on the same inventive concept, an embodiment of the present application provides an embedded system. Please refer to Figure 8 As shown, it includes a processor 801 and a memory 802. A computer program is stored in the memory 802, and the processor 801 executes the computer program to implement the steps of the method in Embodiment 1 above, which will not be repeated here.

[0117] It can be understood that Figure 8 The structure shown is only for illustration. The embedded system may also include more or fewer components than those shown in Figure 8 or have a different configuration from that shown in Figure 8 shown.

[0118] The processor 801 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor 801 may be a general-purpose processor, including a CPU, an NP (network processor), etc.; it may also be a DSP (digital signal processor), an ASIC (application-specific integrated circuit), an FPGA (field-programmable gate array), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute various methods, steps, and logic block diagrams disclosed in the embodiments of the present application.

[0119] The memory 802 may include, but is not limited to, a RAM (random access memory), a ROM (read-only memory), a PROM (programmable read-only memory), an EPROM (erasable read-only memory), an EEPROM (electrically erasable read-only memory), etc.

[0120] This embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital) card, MMC (Multimedia) card, etc. One or more programs for implementing the above steps are stored in this computer-readable storage medium. These one or more programs can be executed by one or more processors to implement the steps of the methods in the above embodiments, which will not be elaborated here.

[0121] The serial numbers of the above embodiments of the present invention are only for description and do not represent the superiority or inferiority of the embodiments.

[0122] Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0123] The above is only the embodiments of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for implementing a patch, characterized in that, Including: Obtain and store a patch function corresponding to a target function; a jump operation instruction is set at the function entry of the target function; the jump operation instruction is used to jump to an address in a memory variable corresponding to the target function when receiving an execution instruction for the target function, so as to execute a function corresponding to the address; Modify the address in the memory variable to point to the address of the patch function; Wherein, the jump operation instruction is used to load the address in the memory variable corresponding to the target function into a temporary register when receiving an execution instruction for the target function, and jump to the address pointed to by the temporary register; the function of the jump operation instruction is implemented by an extended operation instruction; the extended operation instruction includes memory variable identification information, register identification information, and operation code information, and the extended operation instruction is used to: load the address from the memory variable corresponding to the memory variable address into the temporary register corresponding to the register identification information, and jump to the address pointed to by the temporary register; The memory variable address is an address calculated according to a corresponding offset address and a preset address in a base address register, and the offset address is an address calculated according to the memory variable identification information.

2. The patch implementation method according to claim 1, wherein Before the obtaining and storing the patch function corresponding to the target function, the method further includes: Obtain a source program; Determine a function to be patched from the source program; Generate a no-operation instruction at the function entry of the function to be patched; Generate a corresponding jump operation instruction for the function to be patched; Replace the no-operation instruction with the corresponding jump operation instruction to obtain the target function.

3. The patch implementation method according to claim 2, characterized in that The generating a no-operation instruction at the function entry of the function to be patched includes: During the compilation of the source program, generate a no-operation instruction at the function entry of the function to be patched through a compilation tool.

4. The patch implementation method according to claim 1, wherein The target function is a function preset in a read-only memory.

5. The patch implementation method according to any one of claims 1-4, characterized in that The obtaining and storing the patch function corresponding to the target function includes: Obtain a patch function corresponding to the target function, and store the patch function in a memory with modifiable data.

6. The patch implementation method according to claim 5, wherein, After modifying the address in the memory variable to point to the address of the patch function, the method further includes: Obtain a new patch function corresponding to the target function; Store the new patch function in the memory with modifiable data; When the starting address of the new patch function in the memory with modifiable data is different from the starting address of the original patch function in the memory with modifiable data, modify the address in the memory variable to point to the new patch function.

7. The patch implementation method according to claim 6, characterized in that, The storing the new patch function in the memory with modifiable data includes: When it is determined that the memory space required by the new patch function is less than or equal to the memory space occupied by the original patch function, delete the original patch function from the memory where data can be modified, and store the new patch function at the position of the original patch function; the starting address of the new patch function in the memory where data can be modified is the same as the starting address of the original patch function in the memory where data can be modified; When it is determined that the memory space required by the new patch function is greater than the memory space occupied by the original patch function, store the new patch function in the free space that can accommodate the new patch function, and the free space is the free storage space in the memory where data can be modified.

8. A patch implementation device, characterized in that, Comprising: An acquisition storage module, configured to acquire and store a patch function corresponding to a target function; the target function is a function to be patched with a jump operation instruction set at the function entry; the jump operation instruction is used to control a jump to an address in a memory variable corresponding to the target function when the target function receives an execution instruction, so as to execute a function corresponding to the address; A modification module, configured to modify the address in the memory variable to point to the address of the patch function; Wherein, the jump operation instruction is used to load the address in the memory variable corresponding to the target function into a temporary register when receiving an execution instruction for the target function, and jump to the address pointed to by the temporary register; the function of the jump operation instruction is implemented by an extended operation instruction; the extended operation instruction includes memory variable identification information, register identification information, and operation code information, and the extended operation instruction is used for: loading an address from a memory variable corresponding to the memory variable address into the temporary register corresponding to the register identification information, and jumping to the address pointed to by the temporary register; The memory variable address is an address calculated according to a corresponding offset address and a preset address in a base address register, and the offset address is an address calculated according to the memory variable identification information.

9. An embedded system, characterized in that, Comprising a processor and a memory, wherein a computer program is stored in the memory, and the processor executes the computer program to implement the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by at least one processor, the method according to any one of claims 1-7 is implemented.

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