Interrupt controller, chip, computer device, and interrupt control method and medium

Abstract

Embodiments of the present disclosure provide an interrupt controller, a chip, a computer device, an interrupt control method and a medium. The interrupt controller comprises a configuration unit, a first selection unit and a normalization processing unit. The normalization processing unit comprises a plurality of normalization sub-units. Each normalization sub-unit is connected to the first selection unit. Different normalization sub-units adopt different normalization processing modes. The configuration unit is configured to obtain first configuration information. The first configuration information is generated in advance based on the type of an interrupt request. Each type of interrupt request corresponds to a normalization processing mode. The first selection unit is configured to send the interrupt request to one of the plurality of normalization sub-units based on the first configuration information. Each normalization sub-unit of the plurality of normalization sub-units is configured to normalize the received interrupt request by using the normalization processing mode corresponding to the sub-unit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the chip technical field, and in particular to an interrupt controller, a chip, a computer device, an interrupt control method and a medium. BACKGROUND

[0002] There are a large number of interrupt sources in chip development, and the characteristics of these interrupt sources and the interrupt mechanisms adopted are often different. Generally, the interrupt requests sent by the interrupt sources are processed by an interrupt controller. However, the interrupt controller in the related art has poor adaptability and is difficult to adapt to interrupt sources with different characteristics and different interrupt mechanisms. SUMMARY

[0003] In a first aspect, an embodiment of the present disclosure provides an interrupt controller, which comprises a configuration unit, a first selection unit and a normalization processing unit, the normalization processing unit comprises a plurality of normalization sub-units, each normalization sub-unit is connected with the first selection unit, and different normalization sub-units adopt different normalization processing modes; the configuration unit is configured to obtain first configuration information, the first configuration information is generated in advance based on the type of an interrupt request, and each type of interrupt request corresponds to a normalization processing mode; the first selection unit is configured to send the interrupt request to one of the plurality of normalization sub-units based on the first configuration information; and each normalization sub-unit of the plurality of normalization sub-units is configured to perform normalization processing on the received interrupt request by using the normalization processing mode corresponding to the unit.

[0004] In some embodiments, the plurality of normalization sub-units comprises: a first normalization sub-unit configured to directly output a first level active type interrupt request; a second normalization sub-unit configured to output a second level active type interrupt request after level conversion; and a third normalization sub-unit configured to output a pulse type interrupt request after conversion into a first level active type interrupt request; one of the first level and the second level is a high level, and the other is a low level.

[0005] In some embodiments, the second normalization sub-unit comprises a polarity conversion circuit, and / or the third normalization sub-unit comprises an edge detection circuit.

[0006] In some embodiments, the interrupt controller further comprises an arbitration unit connected with each normalization sub-unit respectively, configured to determine the priority of a plurality of received interrupt requests, and output the plurality of interrupt requests in sequence according to the priority of the plurality of interrupt requests.

[0007] In some embodiments, the plurality of interrupt requests are pre-divided into a plurality of groups; the arbitration unit comprises: a group-in arbitration unit configured to determine the priority of the interrupt requests in the same group and output the interrupt requests in the same group in turn according to the priority of the interrupt requests in the same group; and a group-between arbitration unit configured to determine the priority of the interrupt requests between different groups and output the interrupt requests of each group in turn according to the priority of the interrupt requests between different groups.

[0008] In some embodiments, the number of groups is determined based on the maximum number of interrupt requests that can be processed by the interrupt controller.

[0009] In some embodiments, the configuration unit is further configured to obtain second configuration information pre-generated based on a priority policy of the interrupt requests; the arbitration unit comprises: a second selection unit and a plurality of arbitration sub-units, each of the arbitration sub-units is connected with a corresponding normalization sub-unit, and each of the arbitration sub-units corresponds to a priority policy; each of the arbitration sub-units is configured to determine the priority of the plurality of interrupt requests received based on the corresponding priority policy; and the second selection unit is configured to select one of the arbitration sub-units based on the second configuration information and output the interrupt requests in turn according to the priority determined by the selected arbitration sub-unit.

[0010] In some embodiments, the plurality of arbitration sub-units comprises an arbitration sub-unit adopting a round-robin scheduling priority policy and an arbitration sub-unit adopting a fixed priority policy.

[0011] In some embodiments, the interrupt controller further comprises: a query unit configured to query the information of the interrupt mechanism corresponding to the interrupt request; and a sending unit configured to send the information queried by the query unit and the information carried by the interrupt request after being packed into a data packet.

[0012] In some embodiments, the configuration unit is further configured to obtain third configuration information pre-generated based on the interrupt mechanism of the interrupt request; the query unit comprises: a third selection unit and a plurality of query sub-units, each of the query sub-units corresponds to an interrupt mechanism; each of the query sub-units is configured to query the information of the interrupt mechanism corresponding to the query sub-unit; and the third selection unit is configured to select one of the query sub-units based on the third configuration information.

[0013] In some embodiments, the interrupt controller further comprises: an interrupt mask register configured to mask the interrupt request.

[0014] In a second aspect, the chip is provided, which comprises: an IP unit configured to output an interrupt request; and the interrupt controller according to any one of the embodiments of the present disclosure, configured to normalize the interrupt request and output the normalized interrupt request to a host.

[0015] In a third aspect, the computer device is provided, which comprises: the chip according to any one of the embodiments of the present disclosure; and a host configured to communicate with the chip through a communication interface and perform data processing in response to the normalized interrupt request.

[0016] In a fourth aspect, the interrupt control method is provided, which is applied to the interrupt controller according to any one of the embodiments of the present disclosure, and the method comprises: obtaining, by a configuration unit, first configuration information, the first configuration information being generated in advance based on types of interrupt requests, each type of interrupt request corresponding to a normalization processing mode; sending, by a first selection unit, the interrupt request to one of a plurality of normalization sub-units based on the first configuration information; and performing, by the selected normalization sub-unit, normalization processing on the received interrupt request.

[0017] In a fifth aspect, the computer readable storage medium is provided, which stores computer readable instructions, and the instructions are executed to implement: the method performed by the configuration unit, the first selection unit or the normalization processing unit in the interrupt controller according to any one of the embodiments of the present disclosure; or the method performed by the arbitration unit in the interrupt controller comprising the arbitration unit according to any one of the embodiments of the present disclosure; or the method performed by the query unit or the sending unit in the interrupt controller comprising the query unit and the sending unit according to any one of the embodiments of the present disclosure; or the method performed by the interrupt mask register in the interrupt controller comprising the interrupt mask register according to any one of the embodiments of the present disclosure.

[0018] By adopting the above scheme, the embodiments of the present disclosure can normalize various types of interrupt requests into the same type, thereby realizing the unification of interrupt sources with different characteristics. Therefore, the interrupt controller according to the embodiments of the present disclosure can be used to process interrupt requests from interrupt sources with various characteristics, and has strong portability and adaptability.

[0019] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0021] Figure 1 is a schematic diagram of an interrupt controller of an embodiment of the present disclosure.

[0022] Figure 2A and Figure 2B are schematic diagrams of an arbitration unit of an embodiment of the present disclosure, respectively.

[0023] Figure 3 is a schematic diagram of a query unit of an embodiment of the present disclosure.

[0024] Figure 4A is a schematic diagram of an MSI arbitration mechanism of an embodiment of the present disclosure.

[0025] Figure 4B is a schematic diagram of an MSI-X arbitration mechanism of an embodiment of the present disclosure.

[0026] Figure 5 is a schematic diagram of the overall workflow of an interrupt controller of an embodiment of the present disclosure.

[0027] Figure 6 is a schematic diagram of a chip of an embodiment of the present disclosure.

[0028] Figure 7 is a schematic diagram of a computer device of an embodiment of the present disclosure.

[0029] Figure 8 is a flowchart of an interrupt control method of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to various alternative embodiments as well. The following description is not limited to the exemplary embodiments, but rather, is intended to apply to any embodiments within the scope of the present disclosure. The drawings referred to in this description should not be understood as being to scale with any one another. In other words, the dimensions of the various features in the drawings can have been exaggerated for the sake of explanation or clarity.

[0031] The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, it will be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0032] It should be understood that, although the terms first, second, third, etc. can be employed in this disclosure to describe various information, the information should not be limited to these terms. These terms are only used to differentiate one piece of information from another piece of information of the same type. For example, without departing from the scope of the disclosure, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining".

[0033] In order to better understand the technical solutions in the embodiments of the disclosure by those skilled in the art, and to make the above-mentioned purposes, features and advantages of the embodiments of the disclosure more apparent and easy to understand, the technical solutions in the embodiments of the disclosure will be further described in detail below with reference to the drawings.

[0034] There are a large number of interrupt sources in chip development, and different interrupt sources have different characteristics. For example, some interrupt sources output level type interrupt requests, and some interrupt sources output pulse type interrupt requests. Among them, the level type interrupt request further includes a high level effective type interrupt request and a low level effective type interrupt request. Among them, the high level effective type interrupt request means that the interrupt request is valid when the interrupt request is high, and the low level effective type interrupt request means that the interrupt request is valid when the interrupt request is low. In addition, these interrupt sources need to use a specific interrupt mechanism to communicate with the host, for example, some interrupt sources use MSI (Message Signaled Interrupt) mechanism, and some interrupt sources use MSI-X mechanism. Generally, the interrupt controller processes the interrupt request sent by the interrupt source. However, the adaptability of the interrupt controller in the related art is poor, and it is difficult to adapt to interrupt sources with different characteristics and different interrupt mechanisms.

[0035] Based on this, the disclosure provides an interrupt controller, as shown in Figure 1 and Figure 5 The interrupt controller comprises:

[0036] The configuration unit 101, the first selection unit 102, and the normalization processing unit 103, the normalization processing unit 103 comprises a plurality of normalization sub-units 1031, each normalization sub-unit 1031 is connected with the first selection unit 102 respectively, and different normalization sub-units 1031 adopt different normalization processing modes;

[0037] The configuration unit 101 is configured to obtain first configuration information, the first configuration information is generated in advance based on the type of interrupt request, and each type of interrupt request corresponds to a normalization processing mode;

[0038] The first selection unit 102 is configured to receive an interrupt request and send the received interrupt request to one of the plurality of normalization sub-units 1031 based on the first configuration information.

[0039] Each of the plurality of normalization sub-units 1031 is configured to normalize the received interrupt request in a normalization processing mode corresponding to the normalization sub-unit.

[0040] The configuration unit 101 can be a configuration interface connected to a configuration bus to obtain configuration information sent through the configuration bus. The configuration information includes first configuration information which determines the normalization mode of the interrupt request. Through normalization processing, the characteristics of each interrupt source can be unified, such as converting a pulse interrupt request sent by the interrupt source into a level interrupt request, converting a low-active interrupt request into a high-active interrupt request, etc. Therefore, the first configuration information can be generated in advance according to the characteristics of the interrupt source in the application scenario of the interrupt controller. In the above example, when the interrupt source sends a pulse interrupt request or a low-active interrupt request, the first configuration information corresponding to the interrupt request can be generated to convert the interrupt request into a high-active interrupt request.

[0041] Corresponding to a plurality of different types of interrupt requests, a plurality of normalization sub-units 1031 can be set. Different normalization sub-units 1031 adopt different normalization processing modes. For example, in some application scenarios, the interrupt request received by the interrupt controller is a high-active interrupt request, and therefore a first normalization sub-unit can be set to directly output the received interrupt request. In other application scenarios, the interrupt request received by the interrupt controller is a low-active interrupt request, and therefore a second normalization sub-unit can be set to convert the interrupt request to a high-active interrupt request. In other application scenarios, the interrupt request received by the interrupt controller is a pulse interrupt request, and therefore a third normalization sub-unit can be set to convert the pulse interrupt request to a high-active interrupt request.

[0042] The second normalization sub-unit can be implemented by a polarity conversion circuit. The polarity conversion circuit can convert the level of the input signal, for example, convert the high level to low level or convert the low level to high level. By directly outputting the high level effective interrupt request and converting the low level effective interrupt request to high level effective interrupt request by the polarity conversion circuit, the level type interrupt request can be unified to high level effective interrupt request. The third normalization sub-unit can be implemented by an edge detection circuit. The edge detection circuit can detect the edge (rising edge or falling edge) of the interrupt request and generate the corresponding level signal according to the detected level. Therefore, by using the edge detection circuit, the pulse type interrupt request can be unified to high level effective interrupt request.

[0043] The above examples show the embodiment of normalizing the interrupt requests with various characteristics to high level effective interrupt request. In actual application, the normalization mode is not limited to this. For example, the interrupt requests with various characteristics can also be normalized to low level effective interrupt request. In this case, if the received interrupt request is low level effective interrupt request, it is directly outputted; if the received interrupt request is high level effective interrupt request, it is converted to low level effective interrupt request by the polarity conversion circuit. If the received interrupt request is pulse type interrupt request, it is converted to high low level effective interrupt request by the edge detection circuit, and then converted to low level effective interrupt request by the polarity conversion circuit.

[0044] In different application scenarios, different normalization sub-units 1031 can be selected by the first selection unit 102, so as to adopt different normalization processing modes for the received interrupt request. Still taking the case of normalizing various interrupt requests to high level effective interrupt request as an example, in the current application scenario, if the interrupt request is high level effective interrupt request, the first selection unit 102 can select the first normalization sub-unit; if the interrupt request is low level effective interrupt request, the first selection unit 102 can select the second normalization sub-unit; if the interrupt request is pulse type interrupt request, the first selection unit 102 can select the third normalization sub-unit.

[0045] The first selection unit 102 can select different normalization sub-units 1031 by configuring different first configuration information. In some embodiments, the identification information of the normalization sub-units 1031 can be used as the first configuration information. For example, assume that "00", "01" and "11" represent the first normalization sub-unit, the second normalization sub-unit and the third normalization sub-unit respectively. Alternatively, the identification information corresponding to the type of the interrupt request can be used as the first configuration information, and the association between the identification information corresponding to the type of the interrupt request and the identification information of the normalization sub-units 1031 can be established in the first selection unit. For example, "00", "01" and "11" represent the high-level active type of interrupt request, the low-level active type of interrupt request and the pulse type of interrupt request respectively, and A, B and C represent the first normalization sub-unit, the second normalization sub-unit and the third normalization sub-unit respectively. The association shown in the following table can be established:

[0046]

[0047]

[0048] In this way, when the first normalization sub-unit needs to be used, the first configuration information can be configured as "00". When the first configuration information is configured as "00", the first selection unit 102 can determine the normalization sub-unit with the identification information A according to the above association, and select the normalization sub-unit to normalize the interrupt request. In addition to the above-mentioned manner, other manners can also be used to generate the first configuration information, as long as the first selection unit 102 can send the interrupt request to the corresponding normalization sub-unit for normalization based on the first configuration information. Here, it is not listed one by one.

[0049] The embodiments of the present disclosure set multiple normalization sub-units 1031 in the interrupt controller, and select one from them by the first selection unit 102 to normalize the interrupt request. The various types of interrupt requests can be normalized to the same type, so that the interrupt sources with different characteristics can be unified. When the characteristics of the interrupt source change, the hardware structure of the interrupt controller does not need to be changed, and the first configuration information only needs to be changed to adapt the new interrupt source. Therefore, the interrupt controller of the embodiments of the present disclosure can be used to process the interrupt requests from interrupt sources with various characteristics, and has strong portability and adaptability.

[0050] In some embodiments, the interrupt controller further comprises an arbitration unit 104 connected to each normalization subunit respectively, for determining the priority of the received multiple interrupt requests and outputting the multiple interrupt requests in order according to the priority of the multiple interrupt requests. By assigning priority to interrupt requests, urgent interrupt requests can be processed first. The multiple interrupt requests received by the arbitration unit 104 can be any interrupt request output by a normalization subunit. The arbitration unit 104 can use any priority policy to determine the priority of the multiple interrupt requests. For example, a round-robin priority policy or a fixed priority policy can be used. Assuming that the interrupt numbers of the multiple interrupt requests are 1, 2, …, n respectively. In the round-robin priority policy, a default interrupt number of the highest priority interrupt request can be set in advance, assuming that the interrupt number is i, then the priority of each interrupt request with an interrupt number of i, i+1, i+2, …, n, 1, 2, …, i-1 decreases in order. In the fixed priority policy, the priority of each interrupt request can be fixed according to the interrupt number of each interrupt request in ascending or descending order. Taking the case of fixing the priority of each interrupt request according to the interrupt number of each interrupt request in ascending order as an example, the priority of each interrupt request with an interrupt number of 1, 2, …, n decreases in order.

[0051] The priority policy used by the arbitration unit 104 can be determined based on second configuration information, which can also be obtained by the configuration unit 101. For example, when the second configuration information is “0”, the priority policy is determined to be a round-robin priority policy, and when the second configuration information is “1”, the priority policy is determined to be a fixed priority policy.

[0052] In some embodiments, the multiple interrupt requests can be divided into multiple groups in advance. For example, the number of groups can be determined based on the maximum number of interrupt requests that can be processed by the interrupt controller. Assuming that the maximum number of interrupt requests that can be processed by the interrupt controller is N, it can be divided into k groups, and each group can include at most N / k interrupt requests. In addition to the above average grouping method, the present disclosure can also use a non-average grouping method, i.e., the number of interrupt requests included in each group can be different. The specific grouping method can be determined according to actual needs, and the present disclosure does not limit this.

[0053] In the case of grouping interrupt requests, as Figure 2BAs shown, the arbitration unit 104 can be divided into an intra-group arbitration unit 1041 and an inter-group arbitration unit 1042. The intra-group arbitration unit 1041 is configured to determine the priority of the interrupt requests in the same group and output the interrupt requests in the same group in order of the priority of the interrupt requests in the same group. There can be one or more intra-group arbitration units 1041. The inter-group arbitration unit 1042 is configured to determine the priority of the interrupt requests between different groups and output the interrupt requests of each group in order of the priority of the interrupt requests between different groups. The inter-group arbitration unit 1042 can arbitrate the interrupt requests with the same priority in each group, for example, first arbitrate the interrupt requests with the highest priority in each group and then arbitrate the interrupt requests with the second highest priority in each group. For example, assuming that the maximum number of interrupt requests that can be processed by the interrupt controller is 30, which is divided into three groups, g1, g2 and g3, each group can include at most 10 interrupt requests, and the interrupt requests in each group are denoted as g1={s 1,1 , s 1,2 , ……, s 1,10}, g2={s 2,1 , s 2,2 , ……, s 2,10} and g3={s 3,1 , s 3,2 , ……, s 3,10}. The priority of the 10 interrupt requests in g1 is determined by the intra-group arbitration unit, and the interrupt request with the highest priority is assumed to be g 1,3 . Similarly, the interrupt requests with the highest priority in g2 and g3 are assumed to be g 2,1 and g 3,5 , respectively. Then, the priority of g 1,3 , g 2,1 and g 3,5 is determined by the inter-group arbitration unit, and the priority of g 1,3 , g 2,1 and g 3,5 is assumed to decrease in order, and the inter-group arbitration unit outputs g 1,3 , g 2,1 and g 3,5 in order.

[0054] In the same way, the output order of the interrupt requests with the second highest priority in g1, g2 and g3 can be determined, which are assumed to be g 2,2 , g 1,1 and g 3,2 . Thus, the output order of the interrupt requests is {g 1,3 , g 2,1 , g 3,5 , g 2,2 , g 1,1 , g3,2 By employing intra-group and inter-group arbitration units, the granularity of arbitration can be reduced, and the accuracy of arbitration results can be improved.

[0055] In some embodiments, such as Figure 2A As shown, the arbitration unit includes a second selection unit and multiple arbitration subunits. Each arbitration subunit is connected to each normalization subunit in the normalization processing unit 103, and each arbitration subunit corresponds to a priority strategy. Each of the multiple arbitration subunits is used to determine the priority of multiple received interrupt requests based on the corresponding priority strategy. The second selection unit is used to select one of the multiple arbitration subunits based on the second configuration information, and output each interrupt request in sequence according to the priority determined by the selected arbitration subunit.

[0056] For example, the plurality of arbitration subunits includes a first arbitration subunit (also known as a Round Robin arbitration subunit) employing a round-robin scheduling priority strategy, and a second arbitration subunit (also known as a fixed arbitration subunit) employing a fixed priority strategy. Normalized interrupt requests can be input into the first and second arbitration subunits respectively. The first and second arbitration subunits can use different priority strategies to prioritize the interrupt requests, resulting in different ranking results. The second selection unit can determine which arbitration subunit's ranking result to select based on the second configuration information. In some embodiments, the priority strategy identification information can be used as the second configuration information, and the priority strategy identification information can be associated with the arbitration subunit's identification information. Alternatively, the arbitration subunit's identification information can be directly used as the second configuration information. By setting multiple arbitration subunits employing different priority strategies, the interrupt controller can flexibly select the priority strategy in different application scenarios, further improving the interrupt controller's portability and adaptability.

[0057] Furthermore, when the arbitration unit includes an intra-group arbitration unit 1041 and an inter-group arbitration unit 1042, both the intra-group arbitration unit 1041 and the inter-group arbitration unit 1042 can include a second selection unit and multiple arbitration sub-units. For example... Figure 2BAs shown, the arbitration sub-units and the second selection units in the intra-group arbitration unit 1041 can be referred to as intra-group arbitration sub-units and intra-group selection units respectively, and the arbitration sub-units and the second selection units in the inter-group arbitration unit 1042 can be referred to as inter-group arbitration sub-units and inter-group selection units respectively. As can be seen, each of the interrupt requests output by the normalization processing unit 103 can be output to each of the intra-group arbitration sub-units, one of the intra-group arbitration sub-units can be selected by the intra-group arbitration selection unit, and each of the interrupt requests output by the selected intra-group arbitration sub-unit can be output to each of the inter-group arbitration sub-units in turn. Then, one of the inter-group arbitration sub-units can be selected by the inter-group arbitration selection unit, and each of the interrupt requests output by the selected inter-group arbitration sub-unit can be output to the lower-level processing unit in turn.

[0058] In some embodiments, as shown, the interrupt controller further comprises a query unit 105 configured to query information of an interrupt mechanism corresponding to the interrupt request, and a sending unit 106 configured to send the information queried by the query unit and the information carried in the interrupt request after the information is packed into a data packet. The interrupt mechanism can include but is not limited to MSI interrupt mechanism and MSI-X interrupt mechanism. By adopting the present embodiment, the interrupt controller can be adapted to multiple interrupt mechanisms, thereby further improving the portability and adaptability of the interrupt controller. Figure 3

[0059] In some embodiments, the configuration unit 101 is further configured to obtain third configuration information, which is generated in advance based on an interrupt mechanism of an interrupt request. The query unit 105 comprises a third selection unit (also referred to as a strategy selection unit) and a plurality of query sub-units, each of which corresponds to an interrupt mechanism; each of the plurality of query sub-units is configured to query information of the interrupt mechanism corresponding to the query sub-unit; and the third selection unit is configured to select one of the plurality of query sub-units based on the third configuration information.

[0060] Optionally, the category identification information of the interrupt mechanism can be taken as the third configuration information, and the category identification information of the interrupt mechanism can be associated with the identification information of the query sub-unit. Alternatively, the identification information of the query sub-unit can be taken as the third configuration information. Each of the plurality of query sub-units is connected with an arbitration unit, can receive an interrupt request sent by the arbitration unit 104, and query an interrupt mechanism for the interrupt request. However, only when one of the query sub-units is selected by the third selection unit, the information queried by the query sub-unit can be output to the sending unit for data packing.

[0061] In some embodiments, in the case of adopting MSI interrupt mechanism, the information queried by the query unit and the information carried in the interrupt request can be packed into an MSI packet. Figure 4A ​The data packet shown includes the following fields:

[0062] msi_vector, bits 0-4 in the data packet, indicates the message type of the MSI.

[0063] msi_vfunc_active (bit 5 in the data packet) and msi_vfunc_num (bits 6-8 in the data packet), wherein msi_vfunc_num can be configured to any value between 0 and 7. These two fields together indicate through which virtual function the interrupt request is sent. If msi_vfunc_active is 0, it indicates that the interrupt request is sent through the physical function, and msi_vfunc_num is invalid. If msi_vfunc_active is 1, it indicates that the interrupt request is sent through the virtual function indicated by msi_vfunc_num.

[0064] TC value, bits 9-11 in the data packet, indicates the value of the traffic class of the current interrupt in transmission, which can be configured to any value between 0 and 7.

[0065] inter_pri_num, bits 12-18 in the data packet, indicates the interrupt number of the interrupt request.

[0066] Wherein, the four fields of msi_vector, msi_vfunc_active, msi_vfunc_num and TC are queried by the query unit, and inter_pri_num is carried in the interrupt request.

[0067] In the case of using the MSI-X interrupt mechanism, the information queried by the query unit and the information carried in the interrupt request can be packaged into Figure 4B The data packet shown includes the following fields:

[0068] lower address field, bits 0-31 in the data packet.

[0069] upper address field, bits 32-63 in the data packet.

[0070] message data field, bits 64-95 in the data packet.

[0071] TC field, bits 96-98 in the data packet, has the same meaning as the TC field in the MSI interrupt mechanism.

[0072] intr_entry_map, 99th bit to 109th bit in the data packet.

[0073] inter_pri_num, 110th bit to 116th bit in the data packet, indicating the interrupt number of the interrupt request.

[0074] wherein the lower address, the upper address, the message data and the TC are obtained by the querying unit, the inter_pri_num is carried in the interrupt request, and the intr_entry_map is converted based on the inter_pri_num.

[0075] The sending unit 106 can pack the information obtained by the querying unit and the information carried in the interrupt request, and send the data packet obtained after the packing to the host through a peripheral interface (for example, a PCIe interface, a USB interface, etc.).

[0076] Optionally, the arbitration unit of the embodiment of the present disclosure can also be provided with a selection unit (referred to as a fourth selection unit) before each arbitration subunit. The fourth selection unit can select one arbitration subunit (referred to as a target arbitration subunit) based on the second configuration information, and directly send the normalized interrupt request to the target arbitration subunit. After the priority arbitration of the target arbitration subunit, the second selection unit selects the target arbitration subunit based on the second configuration information, and sequentially outputs each interrupt request sent by the target arbitration subunit to the lower-level processing unit.

[0077] Optionally, the querying unit of the embodiment of the present disclosure can also be provided with a selection unit (referred to as a fifth selection unit) before each querying subunit. The fifth selection unit can select one querying subunit (referred to as a target querying subunit) based on the third configuration information, and send the interrupt request output by the previous-stage processing unit to the target querying subunit. The target querying subunit can query the information of the interrupt mechanism corresponding to the unit, and send the information obtained by the third selection unit to the sending unit for data packing.

[0078] In some embodiments, the interrupt controller further comprises an interrupt mask register for masking the interrupt request. For example, the interrupt mask register can be an M-bit register, each bit corresponding to an interrupt source, and by setting the data bit corresponding to each interrupt source, the interrupt request sent by the interrupt source can be masked or developed. Assuming that the number of bits of the interrupt mask register is 8, the data bit is "1" indicating that the interrupt request sent by the corresponding interrupt source is masked, and "0" indicating that the interrupt request sent by the corresponding interrupt source is opened, then "11111110" indicates that the interrupt request sent by the interrupt source corresponding to the 0th data bit of the interrupt mask register is developed, and the interrupt requests sent by other interrupt sources are all developed. In this way, the interrupt request sent by the interrupt source corresponding to the 0th data bit of the interrupt mask register will not be reported out (for example, reported to the host), and the interrupt requests sent by other interrupt sources will be reported out. The interrupt mask register can be arranged in the configuration unit, and after receiving the interrupt request, it can be determined whether the interrupt request needs to be masked based on the information in the interrupt mask register. If it does not need to be masked, the interrupt request is normalized, priority arbitration, and finally sent to the host. If it needs to be masked, the interrupt request can be discarded directly.

[0079] Referring to Figure 5 The overall processing flow of the interrupt controller of the embodiments of the present disclosure is as follows:

[0080] First, the user can configure various strategies according to the needs, and the strategies include:

[0081] Request processing strategy (i.e., first configuration information), used to determine the normalization processing mode of the interrupt request;

[0082] Intra-group priority configuration information, in the case where the priority strategy includes RR strategy and fixed strategy, the interrupt number of the interrupt request with the highest default priority in the RR strategy can be configured;

[0083] Intra-group arbitration selection strategy (i.e., second configuration information), used to determine the intra-group arbitration unit selected by the intra-group arbitration selection unit. If the intra-group arbitration unit adopting the RR arbitration mode is selected, the interrupt priority of each interrupt source needs to be configured. If not configured, the priority of the interrupt request with the smallest interrupt number is the highest by default;

[0084] Inter-group priority configuration information, which has the same effect as the intra-group priority configuration information;

[0085] Inter-group arbitration selection strategy (i.e., second configuration information), used to determine the inter-group arbitration unit selected by the inter-group arbitration selection unit;

[0086] The interrupt mechanism selection strategy (i.e., the third configuration information) is used to determine the query subunit selected by the strategy selection unit.

[0087] After the configuration is completed, if the user needs to turn off some interrupts, the interrupt mask register can be configured. After the interrupt mask register is enabled, the corresponding interrupts will no longer be reported.

[0088] After the above operations are completed, the interrupt controller is in a working state. If a group of interrupt requests enter the interrupt controller, each interrupt request in the group of interrupt requests will be normalized, and then in-group arbitration is performed, which preferentially outputs high-priority interrupt requests to the next stage for inter-group arbitration.

[0089] During inter-group arbitration, each interrupt request is sequentially output to the next stage for strategy query of the interrupt mechanism according to the priority of the interrupt request.

[0090] After the strategy query unit (i.e., the aforementioned query unit 105) receives the result output by the previous stage, different query subunits query the information corresponding to the MSI interrupt mechanism or the MSI-X interrupt mechanism, and then select one of the interrupt mechanisms based on the third configuration information in the configuration unit. The information corresponding to the selected interrupt mechanism is output to the next stage for packaging and sending.

[0091] The sending unit receives the information output by the previous stage, packages the information with the information in the interrupt request in a specified manner, and sends it out in a certain timing and format.

[0092] Compared with the interrupt controller in the related art, the present disclosure implements a more general peripheral device interrupt controller design. Since the interrupt controller in the present disclosure can be compatible with multiple interrupt mechanisms and multiple interrupt source characteristics, the application scenario portability and adaptability of the interrupt controller are strong, and the interrupt controller can be flexibly applied to communication interfaces supporting various interrupt mechanisms and interrupt source characteristics. This scheme can be applied in scenarios that require flexible switching of communication interfaces, meets the interrupt communication needs between the host and the slave, and adapts to multiple needs.

[0093] As shown in Figure 6 The present disclosure also provides a chip, which includes:

[0094] an IP unit 601, configured to output an interrupt request; and

[0095] an interrupt controller 602, configured to normalize the interrupt request and output the normalized interrupt request to a host.

[0096] The IP unit 601 is an interrupt source, and the number of IP units can be greater than or equal to 1. In different application scenarios, the types of the IP unit 601 can be different, and different types of IP units have different interrupt characteristics, thereby being able to send interrupt requests of different types.

[0097] In some embodiments, the chip is an AI chip. The interrupt controller 602 can adopt the interrupt controller of any of the preceding embodiments. The interrupt controller can obtain configuration information sent through a configuration bus, and then process the interrupt request sent by the IP unit. For specific details, refer to the preceding embodiments, which will not be described here. The sending unit in the interrupt controller 602 can be connected to the host through a communication interface such as a PCIe interface or a USB interface, so as to send the processed interrupt request (including normalization processing, priority arbitration processing, and packaging processing, etc.) to the host. The host can perform data processing in response to the interrupt request.

[0098] Referring to Figure 7 The present disclosure also provides a computer device, which comprises:

[0099] a chip 701; and

[0100] a host 702, which communicates with the chip through a communication interface, and is configured to perform data processing in response to the normalized interrupt request.

[0101] The chip 701 can adopt the chip in the preceding embodiments. The host 702 can include a processor such as a central processing unit (CPU), a graphic processing unit (GPU), a neural processing unit (NPU), etc. The processor can perform data processing in response to the interrupt request.

[0102] Referring to Figure 8 The present disclosure also provides an interrupt control method, which is applied to the interrupt controller of any of the embodiments of the present disclosure, and the method comprises:

[0103] Step 801: obtaining first configuration information through a configuration unit, wherein the first configuration information is generated in advance based on the type of an interrupt request, and each type of interrupt request corresponds to a normalization processing mode;

[0104] Step 802: sending, through a first selection unit, the interrupt request to one of a plurality of normalization sub-units based on the first configuration information;

[0105] Step 803: normalizing the received interrupt request by the selected normalization subunit.

[0106] In some embodiments, the normalization subunit includes a plurality of normalization subunits, and the normalizing the received interrupt request by the selected normalization subunit includes:

[0107] directly outputting the interrupt request of the first level-sensitive type by a first normalization subunit of the plurality of normalization subunits;

[0108] outputting the interrupt request of the second level-sensitive type after level conversion by a second normalization subunit of the plurality of normalization subunits;

[0109] outputting the interrupt request of the pulse type after converting the interrupt request of the pulse type into the interrupt request of the first level-sensitive type by a third normalization subunit of the plurality of normalization subunits;

[0110] one of the first level and the second level is high, and the other is low.

[0111] In some embodiments, the second normalization subunit includes a polarity conversion circuit, and / or the third normalization subunit includes an edge detection circuit.

[0112] In some embodiments, the interrupt controller further includes an arbitration unit, and the method further includes:

[0113] determining priorities of the received plurality of interrupt requests by the arbitration unit, and outputting the plurality of interrupt requests in sequence according to the priorities of the plurality of interrupt requests.

[0114] In some embodiments, the plurality of interrupt requests are pre-divided into a plurality of groups, the arbitration unit includes an intra-group arbitration unit and an inter-group arbitration unit, and the determining priorities of the received plurality of interrupt requests by the arbitration unit, and outputting the plurality of interrupt requests in sequence according to the priorities of the plurality of interrupt requests includes:

[0115] determining priorities of interrupt requests in a same group by the intra-group arbitration unit, and outputting the interrupt requests in the same group in sequence according to the priorities of the interrupt requests in the same group;

[0116] determining priorities of interrupt requests between different groups by the inter-group arbitration unit, and outputting the interrupt requests of each group in sequence according to the priorities of the interrupt requests between the different groups.

[0117] In some embodiments, a number of the groups is determined based on a maximum number of interrupt requests processable by the interrupt controller.

[0118] In some embodiments, the configuration unit is further configured to obtain second configuration information, which is generated in advance based on a priority policy of the interrupt request; the arbitration unit comprises a second selection unit and a plurality of arbitration sub-units, each of the arbitration sub-units is connected with a respective normalization sub-unit, and each of the arbitration sub-units corresponds to a priority policy; the priority of the received plurality of interrupt requests is determined by each of the arbitration sub-units based on the corresponding priority policy, and the plurality of interrupt requests are output in sequence according to the priority of the plurality of interrupt requests, comprising:

[0119] the priority of the received plurality of interrupt requests is determined by each of the arbitration sub-units based on the corresponding priority policy;

[0120] one of the arbitration sub-units is selected by the second selection unit based on the second configuration information, and each interrupt request is output in sequence according to the priority determined by the selected arbitration sub-unit.

[0121] In some embodiments, the plurality of arbitration sub-units comprises an arbitration sub-unit adopting a round-robin scheduling priority policy and an arbitration sub-unit adopting a fixed priority policy.

[0122] In some embodiments, the interrupt controller further comprises a query unit and a sending unit, and the method further comprises:

[0123] the information of the interrupt mechanism corresponding to the interrupt request is queried by the query unit; and

[0124] the information queried by the query unit and the information carried by the interrupt request are packaged into a data packet by the sending unit and then sent.

[0125] In some embodiments, the configuration unit is further configured to obtain third configuration information, which is generated in advance based on the interrupt mechanism of the interrupt request; the query unit comprises a third selection unit and a plurality of query sub-units, each of the query sub-units corresponds to the information of an interrupt mechanism; the information of the interrupt mechanism corresponding to the interrupt request is queried by the query unit, comprising:

[0126] the information of the interrupt mechanism corresponding to the interrupt request is queried by each of the query sub-units;

[0127] one of the query sub-units is selected by the third selection unit based on the third configuration information.

[0128] In some embodiments, the method further comprises:

[0129] the interrupt request is shielded by an interrupt shield register.

[0130] The method of the embodiments of the present disclosure can be executed by the interrupt controller of any of the foregoing embodiments, and the specific details of the method executed by the interrupt controller are described in the foregoing embodiments of the function of the interrupt controller, which will not be described herein.

[0131] The embodiments of the present disclosure also provide a computer-readable storage medium having computer-readable instructions stored thereon, which, when executed, implement the method executed by the configuration unit, the first selection unit, or the normalization processing unit in the interrupt controller of any of the embodiments of the present disclosure; or the method executed by the arbitration unit in the interrupt controller comprising the arbitration unit according to any of the embodiments of the present disclosure; or the method executed by the query unit or the sending unit in the interrupt controller comprising the query unit and the sending unit according to any of the embodiments of the present disclosure; or the method executed by the interrupt mask register in the interrupt controller comprising the interrupt mask register according to any of the embodiments of the present disclosure.

[0132] Computer-readable media includes permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device. According to the definition herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carriers.

[0133] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by means of software plus necessary general hardware platforms. Based on such understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in the embodiments of the present disclosure or some parts of the embodiments.

[0134] The systems, apparatuses, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, and the specific forms of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0135] The various embodiments described in the specification are progressive, and the same or similar parts among the various embodiments can be mutually referred to. Each embodiment focuses on the differences from other embodiments. In particular, the device embodiments are described more simply because they are basically similar to the method embodiments, and the relevant parts can be referred to the part of the method embodiments. The device embodiments described above are merely illustrative, and the modules described as separate components can or can not be physically separated, and the functions of each module can be implemented in one or more software and / or hardware in the implementation of the embodiments of the specification. Some or all of the modules can be selected to achieve the purpose of the embodiments of the specification according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0136] The above is only a specific implementation of the embodiments of the specification, and it should be noted that those skilled in the art can make several improvements and refinements without departing from the principles of the embodiments of the specification, and these improvements and refinements should also be considered within the protection scope of the embodiments of the specification.

Claims

1. An interrupt controller, characterized by The interrupt controller comprises: The configuration unit, the first selection unit and the normalization processing unit, the normalization processing unit comprises a plurality of normalization sub-units, each normalization sub-unit is connected with the first selection unit respectively, and different normalization sub-units adopt different normalization processing modes; The configuration unit is used for obtaining first configuration information and second configuration information, the first configuration information is generated in advance based on the type of interrupt request, each type of interrupt request corresponds to a normalization processing mode, and the second configuration information is generated in advance based on the priority policy of interrupt request; The first selection unit is used for receiving an interrupt request, and sending the received interrupt request to one of the plurality of normalization sub-units based on the first configuration information; Each normalization sub-unit of the plurality of normalization sub-units is used for adopting the normalization processing mode corresponding to the unit to normalize the received interrupt request; The arbitration unit connected with each normalization sub-unit respectively is used for determining the priority of the received multiple interrupt requests, and outputting the multiple interrupt requests in turn according to the priority of the multiple interrupt requests, the arbitration unit comprises a second selection unit and a plurality of arbitration sub-units, each arbitration sub-unit is connected with each normalization sub-unit respectively, and each arbitration sub-unit corresponds to a priority policy; Each arbitration sub-unit of the plurality of arbitration sub-units is used for determining the priority of the received multiple interrupt requests based on the corresponding priority policy; The second selection unit is used for selecting one of the plurality of arbitration sub-units based on the second configuration information, and outputting each interrupt request in turn according to the priority determined by the selected arbitration sub-unit.

2. The interrupt controller of claim 1, wherein, The plurality of normalization sub-units comprises: The first normalization sub-unit is used for directly outputting the interrupt request of the first level active type; The second normalization sub-unit is used for outputting the interrupt request of the second level active type after level conversion; The third normalization sub-unit is used for outputting the interrupt request of the pulse type after converting into the interrupt request of the first level active type; One of the first level and the second level is high level, and the other is low level.

3. The interrupt controller of claim 2, wherein, The second normalization sub-unit comprises a polarity conversion circuit, and / or the third normalization sub-unit comprises an edge detection circuit.

4. The interrupt controller of claim 1, wherein, The plurality of interrupt requests are divided into a plurality of groups in advance; The arbitration unit comprises: The in-group arbitration unit is used for determining the priority of the interrupt requests in the same group, and outputting the interrupt requests in the same group in turn according to the priority of each interrupt request in the same group; The inter-group arbitration unit is used for determining the priority of the interrupt requests between different groups, and outputting the interrupt requests of each group in turn according to the priority of each interrupt request between different groups.

5. The interrupt controller of claim 4, wherein, The number of groups is determined based on the maximum number of interrupt requests that can be processed by the interrupt controller.

6. The interrupt controller of claim 1, wherein, The plurality of arbitration sub-units comprises an arbitration sub-unit adopting a round-robin scheduling priority policy and an arbitration sub-unit adopting a fixed priority policy.

7. The interrupt controller of claim 1, wherein, The interrupt controller further comprises: The query unit is configured to query information of an interrupt mechanism corresponding to the interrupt request. The sending unit is configured to send the information queried by the query unit and information carried by the interrupt request after the information is packed into a data packet.

8. The interrupt controller of claim 7, wherein, The configuration unit is further configured to obtain third configuration information, which is generated in advance based on the interrupt mechanism of the interrupt request. The query unit includes: The third selection unit and a plurality of query sub-units, each query sub-unit corresponding to an interrupt mechanism. Each query sub-unit of the plurality of query sub-units is configured to query information of an interrupt mechanism corresponding to the query sub-unit. The third selection unit is configured to select one query sub-unit of the plurality of query sub-units based on the third configuration information.

9. The interrupt controller according to any one of claims 1 to 8, wherein, The interrupt controller further includes: An interrupt mask register configured to mask the interrupt request.

10. A chip, characterized by The chip includes: An IP unit configured to output an interrupt request; and The interrupt controller of any one of claims 1 to 9, configured to perform normalization processing on the interrupt request and output the interrupt request after the normalization processing to a host.

11. A computer device, comprising: The computer device includes: The chip of claim 10; and A host configured to perform data processing in response to the interrupt request after the normalization processing by communicating with the chip through a communication interface.

12. An interrupt control method characterized by, The method applied to the interrupt controller of any one of claims 1 to 9 includes: Obtaining, by a configuration unit, first configuration information, which is generated in advance based on a type of interrupt request, each type of interrupt request corresponding to a normalization processing mode; Sending, by a first selection unit, the interrupt request to one normalization sub-unit of a plurality of normalization sub-units based on the first configuration information; Performing, by the selected normalization sub-unit, normalization processing on the received interrupt request.

13. A computer-readable storage medium having stored thereon computer-readable instructions, wherein, The instructions, when executed, implement the interrupt control method of claim 12. The instructions, when executed, implement the interrupt control method of claim 12.

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