A power consumption evaluation method, device, equipment, medium and product

Abstract

The present invention discloses a power consumption evaluation method, device, equipment, medium and product. The method includes: obtaining a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated; determining a target timing critical path, a capacitance flip rate, a total capacitance of the target circuit and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file; determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, a preset voltage value, a preset temperature value, a capacitance flip rate, a total capacitance of the target circuit and the operating voltage corresponding to the target process library file. The technical solution of the present invention can improve the accuracy of power consumption evaluation.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and in particular to a power consumption evaluation method, device, equipment, medium and product. Background Art

[0002] In order to better improve the performance of the processor, it is often necessary to evaluate the energy consumption of the processor in the early design stage. In terms of energy consumption evaluation, the structural level power consumption evaluation tool is a method that is more commonly used in the early design stage. In order to improve the performance of the processor, the processor usually needs to cope with different loads within a wide voltage range.

[0003] In past studies, the input of structural power consumption evaluation tools often requires clock-accurate simulation by performance simulators. This process is very time-consuming and often takes several days, more than ten days, or even longer, making it difficult to quickly explore the design space. In addition, traditional structural power consumption evaluation tools have poor evaluation effects under wide voltage conditions. They do not consider the changes in processor operating frequency under different voltages and always calculate processor power consumption at a fixed operating frequency. They cannot provide good help for the energy efficiency evaluation of new wide-voltage high-efficiency processors. Summary of the invention

[0004] Embodiments of the present invention provide a power consumption evaluation method, device, equipment, medium and product to improve the accuracy of power consumption evaluation.

[0005] According to one aspect of the present invention, there is provided a power consumption evaluation method, comprising:

[0006] Obtaining a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;

[0007] Determine a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file;

[0008] The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file.

[0009] Further, the target circuit includes: at least one circuit unit, and the target process library file includes: a power consumption value of the circuit unit under the target process condition and a delay value of the unit circuit under the target process condition;

[0010] Accordingly, determining a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file includes:

[0011] Determine the netlist information, timing constraint information and circuit top-level file of the target circuit according to the target circuit file;

[0012] Determine the target timing critical path, capacitance flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file of the target circuit based on the netlist information, timing constraint information, circuit top-level file, power consumption value of the circuit unit under the target process conditions and delay value of the circuit unit under the target process conditions of the target circuit.

[0013] Further, the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit, and the operating voltage corresponding to the target process library file, including:

[0014] Determine the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value;

[0015] The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined according to the delay value, capacitance flip rate, total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.

[0016] Further, the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined according to the delay value, the capacitance flip rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value, including:

[0017] The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is calculated based on the following formula:

[0018] P i,j =αCV 2 f i,j ;

[0019] Among them, P i,j is the power consumption of the processor to be evaluated when the voltage value is i and the temperature value is j, α is the capacitance flip rate, C is the total capacitance of the target circuit, V is the operating voltage corresponding to the target process library file, i is the voltage value, j is the temperature value, f i,jis the operating frequency of the processor to be evaluated when the voltage value is i and the temperature value is j, Delay i,j is the delay value of the processor to be evaluated when the voltage value is i and the temperature value is j.

[0020] Further, determining the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value includes:

[0021] Generate a spice file according to the target timing critical path, the preset voltage value and the preset temperature value;

[0022] Encapsulate the spice file to obtain the subcircuit file;

[0023] A SPICE simulation is performed based on the subcircuit file to obtain a delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.

[0024] Furthermore, i takes a value of 0.6V to 1.0V, and j takes a value of -25°C to 125°C.

[0025] According to another aspect of the present invention, there is provided a power consumption evaluation device, the power consumption evaluation device comprising:

[0026] An acquisition module, used to acquire a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;

[0027] A path determination module, used to determine a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file;

[0028] The power consumption value determination module is used to determine the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file.

[0029] According to another aspect of the present invention, there is provided an electronic device, the electronic device comprising:

[0030] at least one processor; and

[0031] a memory communicatively connected to the at least one processor; wherein,

[0032] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the power consumption evaluation method described in any embodiment of the present invention.

[0033] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the power consumption evaluation method described in any embodiment of the present invention when executed.

[0034] According to another aspect of the present invention, a computer program product is provided. When the computer program is executed by a processor, the computer program implements the power consumption evaluation method as described in any one of the embodiments of the present invention.

[0035] The embodiment of the present invention can improve the accuracy of power consumption evaluation by obtaining a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated; determining a target timing critical path, a capacitance flip rate, a total capacitance of the target circuit and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file; and determining a power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file.

[0036] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 is a flow chart of a power consumption evaluation method in an embodiment of the present invention;

[0039] Figure 2 is a structural schematic diagram of a power consumption evaluation device in an embodiment of the present invention;

[0040] Figure 3 It is a structural schematic diagram of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Embodiment 1

[0044] Figure 1 A flowchart of a power consumption evaluation method provided in an embodiment of the present invention is provided. This embodiment is applicable to power consumption evaluation. The method can be executed by a power consumption evaluation device in an embodiment of the present invention. The device can be implemented in software and / or hardware. Figure 1 As shown, the method specifically comprises the following steps:

[0045] S110, obtaining a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated.

[0046] It should be noted that the manufacturer provides process library files for different process conditions, pre-sets the research environment, that is, the target process conditions, and determines the process library files under the target process conditions as the target process library files.

[0047] The target circuit includes: at least one circuit unit, the target process library file includes: the power consumption value of the circuit unit under the target process conditions and the delay value of the unit circuit under the target process conditions, and the target process conditions can be process conditions determined according to the research environment. For example, it can be a process library file of 7nm1.1v and 40nm0.6v, where 7nm and 40nm are both processes, that is, the size of the processor transistor.

[0048] The target circuit file includes multiple sub-files, each of which is a file containing circuit sub-module information. The sub-files are input files for Design Compiler and Primetime, and Primetime is an EDA tool commonly used in timing analysis.

[0049] S120, determining a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file.

[0050] Specifically, the target timing critical path, capacitance flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file can be determined according to the target process library file and the target circuit file by: inputting the target process library file and the target circuit file into Primetime to obtain the target timing critical path, capacitance flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file. The target timing critical path, capacitance flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file can also be determined according to the target process library file and the target circuit file by: determining the netlist information, timing constraint information and circuit top-level file of the target circuit according to the target circuit file; determining the target timing critical path, capacitance flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file according to the netlist information, timing constraint information, circuit top-level file of the target circuit, power consumption value of the circuit unit under the target process conditions and delay value of the circuit unit under the target process conditions of the target circuit.

[0051] Optionally, the target circuit includes: at least one circuit unit, and the target process library file includes: a power consumption value of the circuit unit under target process conditions and a delay value of the unit circuit under target process conditions;

[0052] Accordingly, determining a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file includes:

[0053] Determine the netlist information, timing constraint information and circuit top-level file of the target circuit according to the target circuit file;

[0054] Determine the target timing critical path, capacitance flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file of the target circuit based on the netlist information, timing constraint information, circuit top-level file, power consumption value of the circuit unit under the target process conditions and delay value of the circuit unit under the target process conditions of the target circuit.

[0055] The netlist information of the target circuit includes: the logical relationship between circuit units and the attribute information of each circuit unit.

[0056] The timing constraint information includes: clock, input delay, output time, output load, etc.

[0057] The circuit top-level file is the sub-file that is executed first among the multiple sub-files contained in the target circuit file, that is, the circuit top-level file is executed first, and then other sub-files are called.

[0058] The netlist information and timing constraint information of the target circuit may be obtained by inputting the target circuit file into Design Compiler to obtain the netlist information and timing constraint information of the target circuit.

[0059] Specifically, the target timing critical path, capacitance flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file of the target circuit can be determined according to the netlist information, timing constraint information, circuit top-level file, power consumption value of the circuit unit under the target process conditions and delay value of the circuit unit under the target process conditions of the target circuit as follows: the netlist information, timing constraint information, circuit top-level file, power consumption value of the circuit unit under the target process conditions and delay value of the circuit unit under the target process conditions of the target circuit are input into Primetime to obtain the target timing critical path, capacitance flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file of the target circuit.

[0060] In a specific example, the target circuit file is input into Design Compiler to obtain the netlist information, timing constraint information and circuit top-level file of the target circuit, and the netlist information, timing constraint information, circuit top-level file, power consumption value of the circuit unit under the target process conditions and delay value of the circuit unit under the target process conditions of the target circuit are input into Primetime to obtain the target timing critical path and power consumption file of the target circuit, wherein the power consumption file includes W, Where α is the capacitance flip rate, C is the total capacitance of the target circuit, V is the operating voltage corresponding to the target process library file, K is the clock, and the value of AC is determined based on W, V, and K.

[0061] S130, determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file.

[0062] The preset voltage may range from 0.6V to 1.0V, and the preset temperature may range from -25°C to 125°C.

[0063] The power consumption values ​​of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value can be presented in the form of a list, which includes: voltage value, temperature value and power consumption value of the processor to be evaluated. For example, it can be power consumption value A of the processor to be evaluated when the voltage value is 0.6V and the temperature value is -25°C, power consumption value B of the processor to be evaluated when the voltage value is 0.7V and the temperature value is 40°C, power consumption value C of the processor to be evaluated when the voltage value is 0.6V and the temperature value is -10°C, etc., and the embodiment of the present invention does not limit this.

[0064] Specifically, the method for determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitor flip rate, the total capacitance of the target circuit, and the working voltage corresponding to the target process library file can be: determining the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, and the preset temperature value; determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value, the capacitor flip rate, the total capacitance of the target circuit, and the working voltage corresponding to the target process library file.

[0065] Optionally, determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit, and the operating voltage corresponding to the target process library file includes:

[0066] Determine the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value;

[0067] The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined according to the delay value, capacitance flip rate, total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.

[0068] Specifically, the method of determining the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value can be: generating a spice file according to the target timing critical path, the preset voltage value and the preset temperature value; encapsulating the spice file to obtain a subcircuit file; and performing spice simulation based on the subcircuit file to obtain the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.

[0069] In a specific example, after using Primetime to obtain a spice file containing a target timing critical path, the spice file is packaged to obtain a subcircuit file, and spice simulation is performed based on the subcircuit file. After completing the subcircuit packaging of the target timing critical path, spice simulation can be used to obtain the delay value of the processor to be evaluated under different voltage and temperature conditions.

[0070] Specifically, the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value may be determined according to the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit, and the working voltage corresponding to the target process library file. The method may be: determining the reciprocal of the delay value as the power consumption value. For example, the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value may be calculated based on the following formula:

[0071] The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is calculated based on the following formula:

[0072] P i,j =αCV 2 f i,j ;

[0073] Among them, P i,j is the power consumption of the processor to be evaluated when the voltage value is i and the temperature value is j, α is the capacitance flip rate, C is the total capacitance of the target circuit, V is the operating voltage corresponding to the process library file, i is the voltage value, j is the temperature value, f i,j is the operating frequency of the processor to be evaluated when the voltage value is i and the temperature value is j, Delay i,j is the delay value of the processor to be evaluated when the voltage value is i and the temperature value is j.

[0074] It should be noted that since the process library files provided by general chip foundries only contain the power consumption and delay values ​​of standard circuit units under several specific voltage and temperature environmental conditions, directly using these process library files can only obtain the delay information under these specific process conditions, and cannot obtain the circuit delay information within a wide voltage range. In order to realize the voltage scanning function, Primetime is first used to extract the timing critical path of the target circuit under one process library condition, and then these extracted timing critical paths are simulated by spice to generate the processor delay value to be evaluated under different voltage and temperature conditions for the target circuit.

[0075] Optionally, determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the delay value, the capacitance flip rate, the total capacitance of the target circuit, and the operating voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value includes:

[0076] The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is calculated based on the following formula:

[0077] P i,j =αCV 2 f i,j ;

[0078] Among them, P i,j is the power consumption of the processor to be evaluated when the voltage value is i and the temperature value is j, α is the capacitance flip rate, C is the total capacitance of the target circuit, V is the operating voltage corresponding to the target process library file, i is the voltage value, j is the temperature value, f i,j is the operating frequency of the processor to be evaluated when the voltage value is i and the temperature value is j, Delay i,j is the delay value of the processor to be evaluated when the voltage value is i and the temperature value is j.

[0079] Specifically, when modeling circuit delay information, the impact of voltage and temperature changes on target circuit delay is mainly considered, and simple regression of a single independent variable in the linear regression method is used to describe the relationship between voltage and temperature changes and circuit delay. Then, the processor's delay value can be used to represent the power consumption value of the processor under different voltage and temperature conditions.

[0080] Optionally, determining the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value includes:

[0081] Generate a spice file according to the target timing critical path, the preset voltage value and the preset temperature value;

[0082] Encapsulate the spice file to obtain the subcircuit file;

[0083] A SPICE simulation is performed based on the subcircuit file to obtain a delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.

[0084] It should be noted that since it is impossible to perform spice simulation directly based on spice files, it is necessary to first encapsulate the spice files to obtain subcircuit files, and then perform spice simulation on the subcircuit files.

[0085] Optionally, i takes a value of 0.6V to 1.0V, and j takes a value of -25°C to 125°C.

[0086] It should be noted that the actual frequency of the processor is not fixed under different operating voltages and temperatures. Generally speaking, when the processor performance requirements are met, the actual system frequency will also be reduced when the system power supply voltage is reduced. At this time, if the same system frequency is used to calculate the power consumption for different operating voltages as in the original structure-level power consumption assessment tool, it will produce errors that cannot be ignored.

[0087] The technical solution of this embodiment is to obtain a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated; determine the target timing critical path, capacitor flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file according to the target process library file and the target circuit file; determine the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitor flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file. The implementation of the present invention takes into account the influence of voltage and temperature changes on the operating frequency of the processor, so that more accurate power consumption evaluation can be performed, thereby improving the accuracy of power consumption evaluation.

[0088] Embodiment 2

[0089] Figure 2 This is a schematic diagram of the structure of a power consumption evaluation device provided by an embodiment of the present invention. This embodiment is applicable to power consumption evaluation. The device can be implemented in software and / or hardware. The power consumption evaluation device can be integrated in any device that provides power consumption evaluation function, such as Figure 2 As shown, the power consumption evaluation device specifically includes: an acquisition module 210 , a path determination module 220 and a power consumption value determination module 230 .

[0090] The acquisition module is used to acquire a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;

[0091] A path determination module, used to determine a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file;

[0092] The power consumption value determination module is used to determine the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file.

[0093] The above-mentioned product can execute the method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0094] The technical solution of this embodiment is to obtain a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated; determine the target timing critical path, capacitor flip rate, total capacitance of the target circuit and the operating voltage corresponding to the target process library file according to the target process library file and the target circuit file; determine the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitor flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file. The implementation of the present invention takes into account the influence of voltage and temperature changes on the operating frequency of the processor, so that more accurate power consumption evaluation can be performed, thereby improving the accuracy of power consumption evaluation.

[0095] Embodiment 3

[0096] Figure 3 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0097] like Figure 3As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0098] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0099] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the power consumption evaluation method.

[0100] In some embodiments, the power consumption evaluation method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the power consumption evaluation method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the power consumption evaluation method in any other appropriate manner (e.g., by means of firmware):

[0101] Obtaining a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;

[0102] Determine a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file;

[0103] The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file.

[0104] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0105] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0106] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0107] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0108] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0109] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0110] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0111] An embodiment of the present invention further provides a computer program product, including a computer program. When the computer program is executed by a processor, the power consumption evaluation method according to any embodiment of the present invention is implemented.

[0112] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A power consumption evaluation method, characterized in that: include: Obtaining a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated; Determine a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file; Determine the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit, and the operating voltage corresponding to the target process library file; The target circuit includes: at least one circuit unit, and the target process library file includes: a power consumption value of the circuit unit under the target process condition and a delay value of the circuit unit under the target process condition; Accordingly, determining a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file includes: Determine the netlist information, timing constraint information and circuit top-level file of the target circuit according to the target circuit file; Determine the target timing critical path, capacitance flip rate, total capacitance of the target circuit, and the operating voltage corresponding to the target process library file of the target circuit according to the netlist information, timing constraint information, circuit top-level file, power consumption value of the circuit unit under the target process conditions, and delay value of the circuit unit under the target process conditions of the target circuit; Determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit, and the operating voltage corresponding to the target process library file, including: Determine the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value; The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined according to the delay value, capacitance flip rate, total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.

2. The method according to claim 1, characterized in that: Determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the delay value, the capacitance flip rate, the total capacitance of the target circuit, and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value, including: The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is calculated based on the following formula: P i,j =αCV 2 f i,j ; Among them, P i,j is the power consumption of the processor to be evaluated when the voltage value is i and the temperature value is j, α is the capacitance flip rate, C is the total capacitance of the target circuit, V is the operating voltage corresponding to the target process library file, i is the voltage value, j is the temperature value, f i,j is the operating frequency of the processor to be evaluated when the voltage value is i and the temperature value is j, Delay i,j is the delay value of the processor to be evaluated when the voltage value is i and the temperature value is j.

3. The method according to claim 1, characterized in that Determining the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value, includes: Generate a spice file according to the target timing critical path, the preset voltage value and the preset temperature value; Encapsulate the spice file to obtain the subcircuit file; A SPICE simulation is performed based on the subcircuit file to obtain a delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.

4. The method according to claim 2, characterized in that The value of i is 0.6V~1.0V, and the value of j is -25℃~125℃.

5. A power consumption evaluation device, characterized in that: include: An acquisition module, used to acquire a target process library file corresponding to the processor to be evaluated and a target circuit file corresponding to the processor to be evaluated; A path determination module, used to determine a target timing critical path, a capacitance flip rate, a total capacitance of a target circuit, and an operating voltage corresponding to the target process library file according to the target process library file and the target circuit file; A power consumption value determination module, used to determine the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value, the preset temperature value, the capacitance flip rate, the total capacitance of the target circuit and the operating voltage corresponding to the target process library file; The target circuit includes: at least one circuit unit, and the target process library file includes: a power consumption value of the circuit unit under the target process condition and a delay value of the circuit unit under the target process condition; Accordingly, the path determination module is specifically used for: Determine the netlist information, timing constraint information and circuit top-level file of the target circuit according to the target circuit file; Determine the target timing critical path, capacitance flip rate, total capacitance of the target circuit, and the operating voltage corresponding to the target process library file of the target circuit according to the netlist information, timing constraint information, circuit top-level file, power consumption value of the circuit unit under the target process conditions, and delay value of the circuit unit under the target process conditions of the target circuit; The power consumption value determination module is specifically used for: Determine the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value; The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined according to the delay value, capacitance flip rate, total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.

6. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the power consumption evaluation method according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the power consumption evaluation method according to any one of claims 1 to 4 when executed.

8. A computer program product, characterized in that The computer program product comprises a computer program, which, when executed by a processor, implements the power consumption evaluation method according to any one of claims 1 to 4.

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