GOA circuit and array substrate

Abstract

The present application discloses a GOA circuit and an array substrate. The GOA circuit includes a plurality of cascaded gate driving units, wherein the Nth-stage gate driving unit includes an inverting module, and a portion of a clock signal can be output through the output end of the inverting module. Since the frequency of the clock signal is much higher than the frequency of the above-mentioned low-frequency control signal, the duration for which the output signal of the inverting module maintains the same potential is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a GOA circuit and an array substrate. Background Art

[0002] The gate drive circuit, also known as the GOA (Gate Driver On Array or Gate On Array, array substrate row drive) circuit, is a driving technology that utilizes the existing thin film transistor display device array process to manufacture the gate line (Gate) row scanning drive signal circuit on the array substrate to achieve row-by-row scanning of the gate line.

[0003] However, existing GOA circuits usually use a low-frequency control signal (LC1 or LC2) combined with an inverter to control the corresponding thin-film transistor to be in an on state or an off state, which not only increases the number of signal transmission lines (for transmitting LC1 and / or LC2) required for the GOA circuit, but also makes the gate potentials of these thin-film transistors in the same potential state for a long time, increases the stress on these thin-film transistors, and thus reduces the trustworthiness and reliability of the GOA circuit. Summary of the invention

[0004] The present application provides a GOA circuit and an array substrate to alleviate the technical problem that a large number of signal transmission lines and output signals of an inversion module are required to be in the same potential state for a long time.

[0005] In a first aspect, the present application provides a GOA circuit, which includes multiple cascaded gate drive units, wherein the Nth-stage gate drive unit includes an inverting module, a first control end of the inverting module is electrically connected to a pull-up node, a second control end of the inverting module, a first input end of the inverting module, and a second input end of the inverting module are all connected to a clock signal, a third input end of the inverting module is electrically connected to a low potential line, and an output end of the inverting module is used to output a control signal.

[0006] In some embodiments, the inverting module includes a first transistor, a second transistor, a third transistor and a fourth transistor, one of the source / drain of the first transistor and the gate of the first transistor are both connected to the clock signal; the gate of the second transistor is electrically connected to the other of the source / drain of the first transistor, and one of the source / drain of the second transistor is connected to the clock signal; one of the source / drain of the third transistor is electrically connected to the low potential line, and the other of the source / drain of the third transistor is electrically connected to the gate of the second transistor; the gate of the fourth transistor is electrically connected to the gate of the third transistor and a pull-up node, one of the source / drain of the fourth transistor is electrically connected to the low potential line, and the other of the source / drain of the fourth transistor is electrically connected to the other of the source / drain of the second transistor to output a control signal.

[0007] In some of the embodiments, a channel type of the first transistor is the same as a channel type of the second transistor, a channel type of the third transistor, and a channel type of the fourth transistor.

[0008] In some of the embodiments, the N-th stage gate driving unit further includes a first feedback submodule and a cascade module, the control end of the first feedback submodule is electrically connected to the output end of the inverting module, and one end of the first feedback submodule is electrically connected to the low potential line; the control end of the cascade module is electrically connected to the pull-up node, one end of the cascade module is connected to the clock signal, and the other end of the cascade module is electrically connected to the other end of the first feedback submodule.

[0009] In some of the embodiments, the first feedback sub-module includes a fifth transistor, one of the source / drain of the fifth transistor is electrically connected to the low potential line, the other of the source / drain of the fifth transistor is electrically connected to the other end of the cascade module, and the gate of the fifth transistor is electrically connected to the output end of the inversion module; the cascade module includes a sixth transistor, one of the source / drain of the sixth transistor is connected to the clock signal, the other of the source / drain of the sixth transistor is electrically connected to the other of the source / drain of the fifth transistor, and the gate of the sixth transistor is electrically connected to the pull-up node.

[0010] In some of the embodiments, the N-th level gate driving unit also includes a pull-up module and a second feedback sub-module, the control end of the pull-up module is electrically connected to the pull-up node, one end of the pull-up module is connected to the clock signal, and the other end of the pull-up module is electrically connected to the N-th level scan line; one end of the second feedback sub-module is electrically connected to the low potential line, the other end of the second feedback sub-module is electrically connected to the other end of the pull-up module, and the control end of the second feedback sub-module is electrically connected to the output end of the inverting module.

[0011] In some embodiments, the second feedback sub-module includes a seventh transistor, one of the source / drain of the seventh transistor is electrically connected to the low potential line, the other of the source / drain of the seventh transistor is electrically connected to the other end of the pull-up module, and the gate of the seventh transistor is electrically connected to the output end of the inverting module.

[0012] In some of the embodiments, the N-th stage gate driving unit also includes a third feedback sub-module, one end of the third feedback sub-module is electrically connected to the low potential line, the other end of the third feedback sub-module is electrically connected to the pull-up node, and the control end of the fourth feedback sub-module is electrically connected to the output end of the inverting module.

[0013] In some embodiments, the third feedback sub-module includes an eighth transistor, one of the source / drain of the eighth transistor is electrically connected to the low potential line, the other of the source / drain of the eighth transistor is electrically connected to the pull-up node, and the gate of the eighth transistor is electrically connected to the output end of the inverting module.

[0014] In some of the embodiments, the N-th level gate driving unit further includes a cascade module, a pull-up module, a second feedback submodule and a fourth feedback submodule, the control end of the cascade module is electrically connected to the pull-up node, and one end of the cascade module is connected to the clock signal; the control end of the pull-up module is electrically connected to the pull-up node, one end of the pull-up module is connected to the clock signal, and the other end of the pull-up module is electrically connected to the N-th level scan line; one end of the second feedback submodule is electrically connected to the low potential line, and the control end of the second feedback submodule is electrically connected to the output end of the inverting module; one end of the fourth feedback submodule is electrically connected to the other end of the second feedback submodule and the other end of the pull-up module, the other end of the fourth feedback submodule is electrically connected to the other end of the cascade module, and the control end of the fourth feedback submodule is connected to the clock signal.

[0015] In some embodiments, the second feedback sub-module includes a seventh transistor, one of the source / drain of the seventh transistor is electrically connected to the low potential line, and the gate of the seventh transistor is electrically connected to the output end of the inverting module; the fourth feedback sub-module includes a ninth transistor, one of the source / drain of the ninth transistor is electrically connected to the other end of the second feedback sub-module and the other end of the pull-up module, the other of the source / drain of the ninth transistor is electrically connected to the other end of the cascade module, and the gate of the ninth transistor is connected to the clock signal.

[0016] In some of the embodiments, the low potential line is used to transmit a low potential signal; the output end of the inverting module is used to output part of the clock signal during the pulse duration of the clock signal, and the output end of the inverting module is also used to output part of the low potential signal outside the pulse duration.

[0017] In some of the embodiments, the pull-up node is used to provide a corresponding pull-up control signal, and during a pulse duration of the clock signal, a potential of the pull-up control signal is opposite to a potential of the clock signal.

[0018] In a second aspect, the present application provides an array substrate, which includes a clock line and the GOA circuit in at least one of the above-mentioned embodiments, wherein the clock line is used to transmit a clock signal.

[0019] The GOA circuit and array substrate provided by the present application are configured such that the first input end of the inverting module, the second input end of the inverting module and the second control end of the inverting module are all connected to the clock signal. The output end of the inverting module can output a control signal including part of the clock signal. Since the frequency of the clock signal is much higher than the frequency of the above-mentioned low-frequency control signal, the potential of the output signal of the inverting module can be alternately switched between high potential and low potential at a faster speed, thereby reducing the duration for which the output signal of the inverting module maintains the same potential, thereby reducing the stress on the thin-film transistor connected to the output end of the inverting module, and improving the trustworthiness and reliability of the GOA circuit. At the same time, the inverting module shares the clock line commonly used by the GOA circuit, saving the signal transmission line for transmitting the above-mentioned low-frequency control signal, thereby reducing the frame space required for the GOA circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0021] Figure 1 It is a structural schematic diagram of a GOA circuit in the related technology.

[0022] Figure 2 FIG. 4 is another structural diagram of a GOA circuit in the related art.

[0023] Figure 3 for Figure 1 , Figure 2 Timing diagram of the GOA circuit shown.

[0024] Figure 4 This is a schematic diagram of the first structure of the GOA circuit provided in an embodiment of the present application.

[0025] Figure 5 A second structural diagram of the GOA circuit provided in an embodiment of the present application.

[0026] Figure 6 This is a third structural schematic diagram of the GOA circuit provided in an embodiment of the present application.

[0027] Figure 7 for Figure 4 , Figure 5 , Figure 6 Timing diagram of the GOA circuit shown. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0029] Figure 1: is a structural schematic diagram of a GOA circuit in the related art, the GOA circuit includes a plurality of cascaded gate driving units, wherein, in the N-th level gate driving unit, one of the source / drain of the thin film transistor T11 is electrically connected to the N-4-th level scanning line, the gate of the thin film transistor T11 is electrically connected to the N-4-th level cascade line, one of the source / drain of the thin film transistor T44 is electrically connected to the other of the source / drain of the thin film transistor T11, the gate of the thin film transistor T52, the gate of the thin film transistor T54, the gate of the thin film transistor T64, the gate of the thin film transistor T62, the gate of the thin film transistor T22, the gate of the thin film transistor T21, one end of the capacitor Cbt, one of the source / drain of the thin film transistor T42 The thin film transistor T41 is electrically connected to one of the sources / drains of the thin film transistor T43, and one of the sources / drains of the thin film transistor T41; the other of the sources / drains of the thin film transistor T44 is electrically connected to the low potential line, one of the sources / drains of the thin film transistor T52, one of the sources / drains of the thin film transistor T54, one of the sources / drains of the thin film transistor T32, the other of the sources / drains of the thin film transistor T42, the other of the sources / drains of the thin film transistor T43, one of the sources / drains of the thin film transistor T33, one of the sources / drains of the thin film transistor T64, one of the sources / drains of the thin film transistor T62, the other of the sources / drains of the thin film transistor T41, and the thin film transistor T54. The Nth clock line is electrically connected to one of the sources / drains of the thin film transistor T22 and one of the sources / drains of the thin film transistor T21. The other of the sources / drains of the thin film transistor T22 is electrically connected to the Nth-stage cascade line. The other of the sources / drains of the thin film transistor T21 is electrically connected to the other of the sources / drains of the thin film transistor T31 and the Nth-stage scan line. The gate of the thin film transistor T44 is electrically connected to the reset line. The first low-frequency control line is electrically connected to one of the sources / drains of the thin film transistor T51, the gate of the thin film transistor T51 and one of the sources / drains of the thin film transistor T53. The source / drain of the thin film transistor T51 is electrically connected to the gate of the thin film transistor T51 and the gate of the thin film transistor T53. The other one of the sources / drains is electrically connected to the gate of the thin film transistor T53 and the other one of the source / drain of the thin film transistor T52. The other one of the sources / drain of the thin film transistor T53 is electrically connected to the other one of the source / drain of the thin film transistor T54, the gate of the thin film transistor T32 and the gate of the thin film transistor T42. The other one of the sources / drain of the thin film transistor T32 is electrically connected to the other one of the source / drain of the thin film transistor T33, the other end of the capacitor Cbt and the other one of the source / drain of the thin film transistor T21. The second low-frequency control line is electrically connected to one of the source / drain of the thin film transistor T61, the gate of the thin film transistor T61 and one of the source / drain of the thin film transistor T63.The other of the source / drain of the thin film transistor T61 is electrically connected to the other of the source / drain of the thin film transistor T62 and the gate of the thin film transistor T63, the other of the source / drain of the thin film transistor T63 is electrically connected to the other of the source / drain of the thin film transistor T64, the gate of the thin film transistor T33 and the gate of the thin film transistor T43, and the N+4th level scanning line is electrically connected to the gate of the thin film transistor T31 and the gate of the thin film transistor T41.

[0030] The thin film transistors T51, T52, T53 and T54 are used to form a first inversion module, and the thin film transistors T61, T62, T63 and T64 are used to form a second inversion module.

[0031] Among them, the N-4th level scan line is used to transmit the N-4th level scan signal G(N-4). The N+4th level scan line is used to transmit the N+4th level scan signal G(N+4). The Nth level scan line is used to transmit the Nth level scan signal G(N). The reset line is used to transmit the reset signal Reset. The low potential line is used to transmit the low potential signal VSS. The first low-frequency control line is used to transmit the first low-frequency control signal LC1. The second low-frequency control line is used to transmit the second low-frequency control signal LC2. The N-4th level cascade line is used to transmit the N-4th level cascade signal ST(N-4). The Nth level cascade line is used to transmit the Nth level cascade signal ST(N). The Nth clock line is used to transmit the Nth clock signal CK(N).

[0032] It needs to be explained that Figure 1 The GOA circuit shown does not pull down the Nth stage cascade signal ST(N) outputted from the other source / drain of the thin film transistor T22, and the other source / drain of the thin film transistor T22 remains floating, which reduces the reliability of the cascade signal.

[0033] and Figure 1 compared to, Figure 2The GOA circuit shown in the figure adds a thin film transistor T72 and a thin film transistor T73. The first inversion module alternately pulls down the potential of the other one of the source / drain of the thin film transistor T22 through the thin film transistor T72, and the second inversion module alternately pulls down the potential of the other one of the source / drain of the thin film transistor T22 through the thin film transistor T73. Among them, one of the source / drain of the thin film transistor T72 is electrically connected to the low potential line, the other one of the source / drain of the thin film transistor T72 is electrically connected to the other one of the source / drain of the thin film transistor T22, and the gate of the thin film transistor T72 is electrically connected to the gate of the thin film transistor T42; one of the source / drain of the thin film transistor T73 is electrically connected to the low potential line, the other one of the source / drain of the thin film transistor T73 is electrically connected to the other one of the source / drain of the thin film transistor T22, and the gate of the thin film transistor T73 is electrically connected to the gate of the thin film transistor T43.

[0034] In addition, one of the source / drain of the thin film transistor T11 is changed to be electrically connected to the N-4th level scan line that transmits the N-4th level scan signal G(N-4), and the gate of the thin film transistor T11 is changed to be electrically connected to the N-4th level cascade line that transmits the N-4th level cascade signal ST(N-4). The gate of the thin film transistor T44 is changed to be electrically connected to the initial line that transmits the reset signal Reset. The gate of the thin film transistor T31 and the gate of the thin film transistor T41 are both changed to be electrically connected to the N+4th level scan line that transmits the N+4th level scan signal G(N+4).

[0035] It needs to be explained that Figure 2 Although the GOA circuit shown pulls down the Nth stage cascade signal ST(N) of another output in the source / drain of the thin film transistor T22, it requires the first inversion module to pull down alternately through the thin film transistor T72 and the second inversion module to pull down alternately through the thin film transistor T73, which not only increases the number of inversion modules, but also increases the number of thin film transistors used, which is not conducive to the realization of a narrow frame.

[0036] like Figure 3 As shown, the phases of the first clock signal CK1 to the sixth clock signal CK6 with the same frequency lag in sequence. One pulse duration of the first low-frequency control signal LC1 and the second low-frequency control signal LC2 may include multiple pulse durations of a clock signal (for example, any one of the first clock signal CK1 to the sixth clock signal CK6). It can be seen that in the GOA circuit, the frequency of the low-frequency control signal (the first low-frequency control signal LC1 or the second low-frequency control signal LC2) is much smaller than the frequency of the clock signal. Both the first low-frequency control line and the second low-frequency control line can be one of the signal transmission lines.

[0037] In view of the technical problem that the GOA circuit mentioned above requires a large number of signal transmission lines and the output signals of the first inversion module and / or the second inversion module are in the same potential state for a long time, this embodiment provides a GOA circuit, see Figures 4 to 7 ,like Figure 4 As shown, the GOA circuit includes a plurality of cascaded gate driving units, wherein the Nth-stage gate driving unit includes an inverting module 20, a first control end of the inverting module 20 is electrically connected to the pull-up node Q(N), a second control end of the inverting module 20, a first input end of the inverting module 20, and a second input end of the inverting module 20 are all connected to the clock signal CK, a third input end of the inverting module 20 is electrically connected to the low potential line, and an output end of the inverting module 20 is used to output a control signal, that is, part of the clock signal CK and part of the low potential signal VSS alternately constitute the control signal.

[0038] It can be understood that the GOA circuit provided in this embodiment is configured to connect the clock signal CK to the first input end of the inverting module 20, the second input end of the inverting module 20 and the second control end of the inverting module 20. The output end of the inverting module 20 can output a control signal. Since the frequency of the clock signal CK is much higher than the frequency of the above-mentioned low-frequency control signal, the potential of the output signal of the inverting module 20 can be alternately switched between high potential and low potential at a faster speed, thereby reducing the duration of the output signal of the inverting module 20 maintaining the same potential, thereby reducing the stress on the thin film transistor connected to the output end of the inverting module 20, and improving the trustworthiness and reliability of the GOA circuit; at the same time, the inverting module 20 shares the clock line commonly used by the GOA circuit, saving the signal transmission line for transmitting the above-mentioned low-frequency control signal, thereby reducing the wiring space required for the GOA circuit, which is conducive to achieving a narrow frame.

[0039] In one embodiment, the inverter module 20 includes a first transistor T51, a second transistor T53, a third transistor T52, and a fourth transistor T54. One of the source / drain of the first transistor T51 and the gate of the first transistor T51 are both connected to the clock signal CK; the gate of the second transistor T53 is electrically connected to the other of the source / drain of the first transistor T51, and one of the source / drain of the second transistor T53 is connected to the clock signal CK; one of the source / drain of the third transistor T52 is electrically connected to the low potential line, and the other of the source / drain of the third transistor T52 is electrically connected to the gate of the second transistor T53; the gate of the fourth transistor T54 is electrically connected to the gate of the third transistor T52 and the pull-up node Q(N), one of the source / drain of the fourth transistor T54 is electrically connected to the low potential line, and the other of the source / drain of the fourth transistor T54 is electrically connected to the other of the source / drain of the second transistor T53 to output the control signal.

[0040] It should be noted that the low potential line is used to transmit a low potential signal VSS or a constant voltage low potential signal. The above control signal may include a pulse portion between a rising edge and a falling edge of a clock signal CK.

[0041] In one embodiment, the channel type of the first transistor T51 is the same as the channel type of the second transistor T53, the channel type of the third transistor T52, and the channel type of the fourth transistor T54. For example, they can all be N-channels, in which case the inverting module 20 outputs a positive pulse signal; they can also all be P-channels, in which case the inverting module 20 can output a negative pulse signal.

[0042] In one embodiment, the N-th level gate driving unit further includes a pull-up control module 10, a pull-up module 70 and a feedback module 56, one end of the pull-up control module 10 is electrically connected to the first scan line, the control end of the pull-up control module 10 is electrically connected to the first cascade line, and the other end of the pull-up control module 10 is electrically connected to the pull-up node Q(N); the control end of the pull-up module 70 is electrically connected to the other end of the pull-up control module 10, one end of the pull-up module 70 is connected to the clock signal CK, and the other end of the pull-up module 70 is electrically connected to the N-th level scan line; one end of the feedback module 56 is electrically connected to the low potential line, the other end of the feedback module 56 is electrically connected to the corresponding node, and the control end of the feedback module 56 is electrically connected to the output end of the inversion module 20.

[0043] It should be noted that each gate driving unit usually needs to be electrically connected to at least one clock line to obtain the required clock signal, wherein one end of the pull-up module 70 is also usually electrically connected to the clock line so as to output the corresponding clock signal for use as a scanning signal. It can be understood that in this embodiment, the inversion module 20 can share the clock line commonly used by the GOA circuit, saving the signal transmission line for transmitting the above-mentioned low-frequency control signal, thereby reducing the wiring space required for the GOA circuit.

[0044] In one embodiment, the pull-up control module 10 includes a thin film transistor T11, one of the source / drain of the thin film transistor T11 is electrically connected to the first scan line, the gate of the thin film transistor T11 is electrically connected to the first cascade line, and the other of the source / drain of the thin film transistor T11 is electrically connected to the pull-up node Q(N).

[0045] The first scan line can be used to transmit a scan signal other than the N-th level scan signal G(N), for example, one of the N-1-th level scan signal, the N-2-th level scan signal, the N-3-th level scan signal G(N-3) or the N-4-th level scan signal, etc. The first cascade line can be used to transmit a cascade signal other than the N-th level cascade signal STN, for example, one of the N-1-th level cascade signal, the N-2-th level cascade signal, the N-3-th level cascade signal ST(N-3) or the N-4-th level cascade signal, etc.

[0046] In one embodiment, the pull-up module 70 may include a thin film transistor T21, one of the source / drain of the thin film transistor T21 is connected to the clock signal CK, the gate of the thin film transistor T21 is electrically connected to the pull-up node Q(N), and the other of the source / drain of the thin film transistor T21 is electrically connected to the Nth level scan line.

[0047] The Nth level scan line is used to transmit the Nth level scan signal G(N).

[0048] In one embodiment, the pull-up module 70 may further include a capacitor Cbt, one end of the capacitor Cbt is electrically connected to the gate of the thin film transistor T21 , and the other end of the capacitor Cbt is electrically connected to the other of the source / drain of the thin film transistor T21 .

[0049] In one embodiment, the N-th stage gate driving unit further includes a cascade module 40, one end of the cascade module 40 is connected to the clock signal CK, the control end of the cascade module 40 is electrically connected to the other end of the pull-up control module 10, and the other end of the cascade module 40 is electrically connected to the N-th stage cascade line.

[0050] The N-th stage cascade line is used to transmit the N-th stage cascade signal STN.

[0051] In one embodiment, the cascade module 40 may include a sixth transistor T22, one of the source / drain of the sixth transistor T22 is connected to the clock signal CK, the gate of the sixth transistor T22 is electrically connected to the other of the source / drain of the thin film transistor T11, and the other of the source / drain of the sixth transistor T22 is electrically connected to the above-mentioned Nth stage cascade line.

[0052] In one embodiment, if Figure 5 As shown, the feedback module 56 includes a control end of a first feedback submodule 100 electrically connected to the output end of the inverting module, one end of the first feedback submodule 100 electrically connected to the low potential line, and the other end of the first feedback submodule 100 electrically connected to the other end of the cascade module 40.

[0053] It should be noted that, since the frequency of the clock signal CK is much higher than the frequency of the above-mentioned low-frequency control signal, the potential of the output signal of the inverting module 20 can be alternately switched between high potential and low potential at a faster speed, thereby reducing the duration for which the control end of the first feedback submodule 100 maintains the same potential, thereby reducing the stress on the control end of the first feedback submodule 100 and improving the trustworthiness and reliability of the GOA circuit.

[0054] Furthermore, by electrically connecting one end of the first feedback submodule 100 with the low potential line and the other end of the cascade module 40 with the other end of the first feedback submodule 100, the first feedback submodule 100 can pull down the cascade signal output by the cascade module 40 under the control of the inverting module 20, thereby avoiding the suspended state of the cascade signal, improving the reliability of the cascade signal, and further improving the reliability of the GOA circuit.

[0055] Furthermore, the inverting module 20 and the cascade module 40 share the clock line commonly used by the GOA circuit, saving the signal transmission line for transmitting the above-mentioned low-frequency control signal, thereby reducing the wiring space required for the GOA circuit.

[0056] In one embodiment, the first feedback submodule 100 includes a fifth transistor T72, one of the source / drain of the fifth transistor T72 is electrically connected to the low potential line, the other of the source / drain of the fifth transistor T72 is electrically connected to the other end of the cascade module 40, and the gate of the fifth transistor T72 is electrically connected to the output end of the inverting module.

[0057] It should be noted that, in the present embodiment, the inverting module 20 can control the fifth transistor T72 to switch between the on state and the off state at a faster frequency, so as to reduce the gate potential of the fifth transistor T72 from being maintained at the same potential state for a long time, thereby reducing the electrical stress on the gate of the fifth transistor T72, improving the service life of the fifth transistor T72 and reducing the threshold voltage drift range of the fifth transistor T72, thereby improving the reliability and reliability of the GOA circuit.

[0058] In one embodiment, if Figure 4 , Figure 5 As shown, the feedback module 56 includes a second feedback submodule 50, one end of the second feedback submodule 50 is electrically connected to the low potential line, the other end of the second feedback submodule 50 is electrically connected to the other end of the pull-up module 70, and the control end of the second feedback submodule 50 is electrically connected to the output end of the inverting module 20.

[0059] It should be noted that, in the present embodiment, the inverting module 20 can control the second feedback submodule 50 to switch between the switching states at a faster frequency, so as to reduce the potential of the control end of the second feedback submodule 50 being maintained at the same potential state for a long time, thereby reducing the stress on the control end of the second feedback submodule 50 and improving the reliability of the GOA circuit.

[0060] In one embodiment, the second feedback submodule 50 includes a seventh transistor T32, one of the source / drain of the seventh transistor T32 is electrically connected to the low potential line, the other of the source / drain of the seventh transistor T32 is electrically connected to the other end of the pull-up module 70, and the gate of the seventh transistor T32 is electrically connected to the output end of the inversion module 20.

[0061] It should be noted that, in the present embodiment, the inverting module 20 can control the seventh transistor T32 to switch between the on state and the off state at a faster frequency, so as to reduce the gate potential of the seventh transistor T32 from being kept at the same potential state for a long time, thereby reducing the electrical stress on the gate of the seventh transistor T32, improving the service life of the seventh transistor T32 and reducing the threshold voltage drift range of the seventh transistor T32, thereby improving the reliability and reliability of the GOA circuit.

[0062] In one embodiment, the feedback module 56 further includes a third feedback submodule 60, one end of the third feedback submodule 60 is electrically connected to the low potential line, the other end of the third feedback submodule 60 is electrically connected to the other end of the pull-up control module 10, and the control end of the third feedback submodule 60 is electrically connected to the output end of the inverting module 20.

[0063] It should be noted that, in the present embodiment, the inverting module 20 can control the third feedback submodule 60 to switch between the switching states at a faster frequency, so as to reduce the potential of the control end of the third feedback submodule 60 remaining in the same potential state for a long time, thereby reducing the stress on the control end of the third feedback submodule 60 and improving the reliability of the GOA circuit.

[0064] In one embodiment, the third feedback submodule 60 includes an eighth transistor T42, one of the source / drain of the eighth transistor T42 is electrically connected to the low potential line, the other of the source / drain of the eighth transistor T42 is electrically connected to the other end of the pull-up control module 10, and the gate of the eighth transistor T42 is electrically connected to the output end of the inversion module 20.

[0065] It should be noted that, in the present embodiment, the inverting module 20 can control the eighth transistor T42 to switch between the on state and the off state at a faster frequency, so as to reduce the gate potential of the eighth transistor T42 from being maintained at the same potential state for a long time, thereby reducing the electrical stress on the gate of the eighth transistor T42, improving the service life of the eighth transistor T42 and reducing the threshold voltage drift range of the eighth transistor T42, thereby improving the reliability and reliability of the GOA circuit.

[0066] In one embodiment, if Figure 6 As shown, the feedback module 56 also includes a fourth feedback submodule 110, one end of the fourth feedback submodule 110 is electrically connected to the other end of the second feedback submodule 50, the other end of the fourth feedback submodule 110 is electrically connected to the other end of the cascade module 40, and the control end of the fourth feedback submodule 110 is connected to the clock signal CK.

[0067] It should be noted that, in the present embodiment, the inverting module 20 can control the second feedback submodule 50 to switch between the switch states at a faster frequency. On this basis, the fourth feedback submodule 110 can also switch between the switch states at a faster frequency under the control of the clock signal CK, which can not only reduce the long-term maintenance of the control terminal potential of the second feedback submodule 50 at the same potential state, but also reduce the long-term maintenance of the control terminal potential of the fourth feedback submodule 110 at the same potential state, thereby reducing the stress on the control end of the second feedback submodule 50 and the control end of the fourth feedback submodule 110, and can improve the reliability and reliability of the gate GOA circuit.

[0068] Moreover, compared with Figure 2 The thin film transistors T72 and T73 are used to directly pull down the potential of the other end of the cascade module 40, which requires more signal transmission lines, which requires a larger film thickness in the display panel. Figure 6 The GOA circuit shown can realize the pull-down of the cascade module 40 with the help of the second feedback sub-module 50 and the fourth feedback sub-module 110, thereby reducing the number of required signal transmission lines and the required film thickness, thereby providing more longitudinal (thickness direction) space for the thin film transistor T11, the thin film transistor T31, the thin film transistor T41, the thin film transistor T32, and the thin film transistor T42, thereby saving space for the display panel.

[0069] In addition, the control end of the fourth feedback submodule 110 is controlled by the drive of the clock signal, which can reduce the long-term maintenance of the control end potential of the fourth feedback submodule 110 at the same potential state, reduce the stress on the control end of the fourth feedback submodule 110, and help to extend the service life of the fourth feedback submodule 110, thereby further improving the trustworthiness and reliability of the GOA circuit.

[0070] In one embodiment, the fourth feedback submodule 110 includes a ninth transistor T71, one of the source / drain of the ninth transistor T71 is electrically connected to the other end of the second feedback submodule 50, the other of the source / drain of the ninth transistor T71 is electrically connected to the other end of the cascade module 40, and the gate of the ninth transistor T71 is connected to the clock signal CK.

[0071] It should be noted that, in the present embodiment, the inverting module 20 can control the second feedback submodule 50 to switch between the switch states at a faster frequency. On this basis, the ninth transistor T71 can also switch between the switch states at a faster frequency under the control of the clock signal CK, which can not only reduce the control terminal potential of the second feedback submodule 50 from being maintained at the same potential state for a long time, but also reduce the gate potential of the ninth transistor T71 from being maintained at the same potential state for a long time, thereby reducing the stress on the control terminal of the second feedback submodule 50 and the gate of the ninth transistor T71, and can improve the reliability and reliability of the GOA circuit.

[0072] Moreover, compared with Figure 2 The thin film transistors T72 and T73 are used to directly pull down the potential of the other end of the cascade module 40, which requires more signal transmission lines, which requires a larger film thickness in the display panel. Figure 6 The GOA circuit shown can realize the pull-down of the cascade module 40 with the help of the second feedback sub-module 50 and the ninth transistor T71, thereby reducing the number of required signal transmission lines and the required film thickness, thereby providing more longitudinal (thickness direction) space for the thin film transistor T11, the thin film transistor T31, the thin film transistor T41, the thin film transistor T32, and the thin film transistor T42, thereby saving space for the display panel.

[0073] In addition, the gate of the ninth transistor T71 is controlled by the drive of the clock signal, which can reduce the gate potential of the ninth transistor T71 from being maintained at the same potential state for a long time, reduce the stress on the gate of the ninth transistor T71, and help to extend the service life of the ninth transistor T71, thereby further improving the reliability of the GOA circuit.

[0074] In one embodiment, the low potential line is used to transmit the low potential signal VSS; the output end of the inverting module 20 is used to output part of the clock signal CK during the pulse duration of the clock signal CK, and the output end of the inverting module 20 is also used to output part of the low potential signal VSS outside the pulse duration.

[0075] It should be noted that the output end of the inverting module 20 can output a pulse signal, wherein the pulse signal is a voltage provided by the clock signal CK during its pulse duration, and the pulse signal is a voltage provided by the low potential signal VSS outside its pulse duration, that is, the pulse signal is synthesized by the clock signal CK and the low potential signal VSS.

[0076] In one embodiment, the pull-up node Q(N) is used to provide a corresponding pull-up control signal. During the pulse duration of the clock signal CK, the potential of the pull-up control signal is opposite to the potential of the clock signal CK.

[0077] It can be understood that when the potential of the pull-up control signal is at a high potential, the potential of the clock signal CK is at a low potential. At this time, the inversion module 20 outputs the low potential signal VSS; when the potential of the pull-up control signal is at a low potential, the potential of the clock signal CK is at a high potential. At this time, the inversion module 20 outputs the clock signal CK.

[0078] In one embodiment, the N-th stage gate driving unit further includes a reset module 30, one end of the reset module 30 is electrically connected to the other end of the pull-up control module 10, the control end of the reset module 30 is electrically connected to the initial line, and the other end of the reset module 30 is electrically connected to the low potential line.

[0079] The initial line can be used to transmit the initial signal STV or Figure 1 , Figure 2 The reset signal Reset shown in .

[0080] In one embodiment, the reset module 30 includes a thin film transistor T44, one of the source / drain of the thin film transistor T44 is electrically connected to the other of the source / drain of the thin film transistor T11, the gate of the thin film transistor T44 is electrically connected to the initial line, and the other of the source / drain of the thin film transistor T44 is electrically connected to the low potential line.

[0081] In one embodiment, the N-th stage gate driving unit further includes a first pull-down module 80, one end of the first pull-down module 80 is electrically connected to the other end of the pull-up module 70, a control end of the first pull-down module 80 is electrically connected to the second scan line, and the other end of the first pull-down module 80 is electrically connected to the low potential line.

[0082] Among them, the second scan line is used to transmit a scan signal other than the Nth level scan signal G(N), for example, it can be one of the N+1th level scan signal, the N+2th level scan signal, the N+3th level scan signal G(N+3) or the N+4th level scan signal, etc., which correspond in sequence to the scan signal transmitted by the first scan line.

[0083] In one embodiment, the first pull-down module 80 may include a thin film transistor T31, one of the source / drain of the thin film transistor T31 is electrically connected to the other of the source / drain of the thin film transistor T21, the gate of the thin film transistor T31 is electrically connected to the second scan line, and the other of the source / drain of the thin film transistor T31 is electrically connected to the low potential line.

[0084] In one embodiment, the N-th stage gate driving unit further includes a second pull-down module 90, one end of the second pull-down module 90 is electrically connected to the other end of the pull-up control module 10, the control end of the second pull-down module 90 is electrically connected to the second scan line, and the other end of the second pull-down module 90 is electrically connected to the low potential line.

[0085] In one embodiment, the second pull-down module 90 may include a thin film transistor T41, one of the source / drain of the thin film transistor T41 is electrically connected to the other of the source / drain of the thin film transistor T11, the gate of the thin film transistor T41 is electrically connected to the second scan line, and the other of the source / drain of the thin film transistor T41 is electrically connected to the low potential line.

[0086] It should be noted that the thin film transistor may be an N-channel thin film transistor or a P-channel thin film transistor, wherein the channel material of the thin film transistor is not specifically limited.

[0087] It needs to be explained that Figure 3 for Figure 1 , Figure 2 The timing diagram of the GOA circuit shown in Figure 1 is as follows: Figure 7 for Figures 4 to 6 The timing diagram of the GOA circuit shown in FIG. Figure 7 and Figure 3 The difference between the two is only that the names of the reset signal Reset and the initial signal STV are different, but the phase and frequency of the two are the same, so the two can be substantially the same. Figure 1 , Figure 2 The GOA circuit shown, Figures 4 to 6 The GOA circuit shown uses a smaller number of thin-film transistors and can achieve the same performance with less frame space. Figure 1 , Figure 2 The same output timing as the GOA circuit shown.

[0088] As Figure 3 , Figure 7 As shown, there is a vertical blank time period BT between two pulses of the reset signal Reset or the initial signal STV, and the end time of the vertical blank time period BT coincides with or is at the same time as a rising edge of a pulse of the reset signal Reset or the initial signal STV. Assuming that one cycle of the clock signal CK is 6H, the high level duration of the clock signal CK is 2.64H, the low level duration of the clock signal CK is 3.36H, the pulse duration of the reset signal Reset or the initial signal STV is 4H, the rising edge of a pulse corresponding to the reset signal Reset or the initial signal STV is 2H earlier than the rising edge of the pulse of the first clock signal CK1, and the rising edge interval of two adjacent clock signals can be 1H, the pulse duration of the Nth scanning signal G(N), that is, the gate line opening time of the corresponding row sub-pixel, is 2.64H, and the pulse duration of the corresponding data signal Data, that is, the charging time of the corresponding row sub-pixel, is 1H, wherein the gate line opening time of the corresponding row sub-pixel and the charging time of the corresponding row sub-pixel at least partially overlap. Among them, the potential of the low potential signal VSS can be but is not limited to -12V. H can be any time period, for example, it can be but not limited to any value between 0.1 microseconds and 5 microseconds, and can specifically be 0.2 microseconds, 0.3 microseconds...0.5 microseconds, 1.0 microseconds, etc., or can be customized according to the resolution of the display panel.

[0089] In one of the embodiments, the present embodiment provides an array substrate, which includes a clock line and the GOA circuit in at least one of the above embodiments, wherein the clock line is used to transmit a clock signal CK.

[0090] It can be understood that the display device provided in this embodiment is configured to connect the clock signal CK to the first input terminal of the inverting module 20, the second input terminal of the inverting module 20 and the second control terminal of the inverting module 20. The output terminal of the inverting module 20 can output a control signal. Since the frequency of the clock signal CK is much higher than the frequency of the above-mentioned low-frequency control signal, the potential of the output signal of the inverting module 20 can be alternately switched between high potential and low potential at a faster speed, thereby reducing the duration of the output signal of the inverting module 20 maintaining the same potential, thereby reducing the stress on the thin film transistor connected to the output terminal of the inverting module 20, and improving the trustworthiness and reliability of the GOA circuit; at the same time, the inverting module 20 shares the clock line commonly used by the GOA circuit, saving the signal transmission line for transmitting the above-mentioned low-frequency control signal, thereby reducing the frame space required for the GOA circuit.

[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0092] The GOA circuit and array substrate provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A GOA circuit, characterized in that: The invention comprises a plurality of cascaded gate driving units, wherein the Nth stage gate driving unit comprises: An inverting module, wherein a first control terminal of the inverting module is electrically connected to a pull-up node, a second control terminal of the inverting module, a first input terminal of the inverting module and a second input terminal of the inverting module are all connected to a clock signal, a third input terminal of the inverting module is electrically connected to a low potential line, and an output terminal of the inverting module is used to output a control signal; A cascade module, wherein a control end of the cascade module is electrically connected to the pull-up node, and one end of the cascade module is connected to the clock signal; A pull-up module, wherein a control end of the pull-up module is electrically connected to the pull-up node, one end of the pull-up module is connected to the clock signal, and the other end of the pull-up module is electrically connected to the Nth level scan line; a second feedback submodule, wherein one end of the second feedback submodule is electrically connected to the low potential line, and a control end of the second feedback submodule is electrically connected to the output end of the inverting module; and A fourth feedback submodule, one end of the fourth feedback submodule is electrically connected to the other end of the second feedback submodule and the other end of the pull-up module, the other end of the fourth feedback submodule is electrically connected to the other end of the cascade module, and the control end of the fourth feedback submodule is connected to the clock signal.

2. The GOA circuit according to claim 1, characterized in that: The inverting module comprises: A first transistor, wherein one of a source and a drain of the first transistor and a gate of the first transistor are both connected to the clock signal; a second transistor, wherein a gate of the second transistor is electrically connected to the other of the source / drain of the first transistor, and one of the source / drain of the second transistor is connected to the clock signal; a third transistor, one of a source and a drain of the third transistor being electrically connected to the low potential line, and the other of a source and a drain of the third transistor being electrically connected to the gate of the second transistor; and A fourth transistor, wherein a gate of the fourth transistor is electrically connected to a gate of the third transistor and the pull-up node, one of the source / drain of the fourth transistor is electrically connected to the low potential line, and the other of the source / drain of the fourth transistor is electrically connected to the other of the source / drain of the second transistor to output the control signal.

3. The GOA circuit according to claim 2, characterized in that: A channel type of the first transistor is the same as a channel type of the second transistor, a channel type of the third transistor, and a channel type of the fourth transistor.

4. The GOA circuit according to claim 1, characterized in that: The Nth-stage gate driving unit further includes: a first feedback submodule, wherein a control end of the first feedback submodule is electrically connected to the output end of the inverting module, and one end of the first feedback submodule is electrically connected to the low potential line; and A cascade module, wherein a control end of the cascade module is electrically connected to the pull-up node, one end of the cascade module is connected to the clock signal, and the other end of the cascade module is electrically connected to the other end of the first feedback submodule.

5. The GOA circuit according to claim 4, characterized in that: The first feedback submodule includes a fifth transistor, one of the source / drain of the fifth transistor is electrically connected to the low potential line, the other of the source / drain of the fifth transistor is electrically connected to the other end of the cascade module, and the gate of the fifth transistor is electrically connected to the output end of the inversion module; The cascade module includes a sixth transistor, one of the source / drain of the sixth transistor is connected to the clock signal, the other of the source / drain of the sixth transistor is electrically connected to the other of the source / drain of the fifth transistor, and the gate of the sixth transistor is electrically connected to the pull-up node.

6. The GOA circuit according to claim 4, characterized in that: The Nth-stage gate driving unit further includes: A pull-up module, wherein a control end of the pull-up module is electrically connected to the pull-up node, one end of the pull-up module is connected to the clock signal, and the other end of the pull-up module is electrically connected to the Nth level scan line; A second feedback submodule, one end of the second feedback submodule is electrically connected to the low potential line, the other end of the second feedback submodule is electrically connected to the other end of the pull-up module, and the control end of the second feedback submodule is electrically connected to the output end of the inverting module.

7. The GOA circuit according to claim 6, characterized in that: The second feedback submodule includes a seventh transistor, one of the source / drain of the seventh transistor is electrically connected to the low potential line, the other of the source / drain of the seventh transistor is electrically connected to the other end of the pull-up module, and the gate of the seventh transistor is electrically connected to the output end of the inversion module.

8. The GOA circuit according to claim 6, characterized in that: The N-th stage gate driving unit also includes a third feedback submodule, one end of the third feedback submodule is electrically connected to the low potential line, the other end of the third feedback submodule is electrically connected to the pull-up node, and the control end of the third feedback submodule is electrically connected to the output end of the inverting module.

9. The GOA circuit according to claim 8, characterized in that: The third feedback submodule includes an eighth transistor, one of the source / drain of the eighth transistor is electrically connected to the low potential line, the other of the source / drain of the eighth transistor is electrically connected to the pull-up node, and the gate of the eighth transistor is electrically connected to the output end of the inverting module.

10. The GOA circuit according to claim 1, characterized in that: The second feedback submodule comprises a seventh transistor, one of a source and a drain of the seventh transistor is electrically connected to the low potential line, and a gate of the seventh transistor is electrically connected to the output end of the inversion module; The fourth feedback submodule includes a ninth transistor, one of the source / drain of the ninth transistor is electrically connected to the other end of the second feedback submodule and the other end of the pull-up module, the other of the source / drain of the ninth transistor is electrically connected to the other end of the cascade module, and the gate of the ninth transistor is connected to the clock signal.

11. The GOA circuit according to any one of claims 1 to 10, characterized in that: The low potential line is used to transmit a low potential signal; the output end of the inverting module is used to output part of the clock signal during the pulse duration of the clock signal, and the output end of the inverting module is also used to output part of the low potential signal outside the pulse duration.

12. The GOA circuit according to claim 11, characterized in that: The pull-up node is used to provide a corresponding pull-up control signal. During the pulse duration of the clock signal, the potential of the pull-up control signal is opposite to the potential of the clock signal.

13. An array substrate, characterized in that: The method comprises a clock line and a GOA circuit as claimed in any one of claims 1 to 12, wherein the clock line is used to transmit the clock signal.

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