Method of driving a display screen and display driving circuit therefor

Abstract

A method for driving a display driving circuit of a display panel and the display driving circuit thereof are disclosed. The method includes the steps of determining whether a plurality of first data codes corresponding to first data voltages output to data lines of the display panel through a multiplexer during a first horizontal line period are equal; determining whether each first data code is equal to a corresponding second data code of a plurality of second data codes corresponding to second data voltages output to the data lines through the multiplexer during a second horizontal line period succeeding the first horizontal line period; and in response to the first data codes being all equal and each first data code being equal to the corresponding second data code, outputting a control signal to control a switcher of the multiplexer to maintain an open state after the switcher is opened to output a first data voltage.

Description

Technical Field

[0001] The present invention relates to a method for driving a display screen and a display driving circuit thereof, and in particular to a method for driving a display screen and a related display driving circuit thereof for reducing power consumption. Background Art

[0002] There is a one-to-many application between the display driver device and the data lines on the organic light-emitting diode (OLED) display. That is, each output channel in the display driver device can output voltage to multiple data lines on the OLED display in a time-sharing manner. Therefore, a multiplexer (MUX) can be set on the OLED display to switch the output of the display driver device to different data lines in a time-sharing manner. The multiplexer can be controlled to sequentially transmit the data voltage to the data lines during each horizontal line period to store the corresponding charge on the parasitic capacitance of the data lines. Then, the gate control switch (i.e., the scan switch) of the OLED display can be turned on, so that the data voltage on the data line is input into the pixel through charge sharing.

[0003] Traditionally, OLED displays can have a pre-charge operation configured or not, depending on the required display quality. Consequently, OLED displays employ two control timing schemes: pre-charge OFF and pre-charge ON. Pre-charge operation involves briefly turning on all switches in a multiplexer before the switches sequentially turn on to output the data voltage during a horizontal line period. This allows the data line voltage to be pre-charged to an appropriate level. This pre-charge operation enables optimized visual performance on OLED displays.

[0004] During each horizontal line period, when outputting and displaying the data voltage for each horizontal line, the display driver can control the multiplexer in a predetermined manner according to a predetermined control timing scheme for the organic light-emitting diode display screen, thereby transmitting the data voltage to the corresponding pixel by switching the switches in the multiplexer. However, regardless of the control timing scheme used, the data voltage transmission process requires multiple changes in the state of the multiplexer switches. Each switch state change (i.e., toggle, i.e., transitioning from an on state to an off state, or vice versa) consumes power. In this case, since a display screen typically has a large number of multiplexers, and the switches in each multiplexer are constantly switching, this inevitably results in significant power consumption. Summary of the Invention

[0005] Therefore, the main object of the present invention is to provide a method for driving a display screen and a related display driving circuit thereof, which can reduce power consumption by reducing the switching times of switches in a multiplexer (MUX), thereby solving the above-mentioned problem.

[0006] An embodiment of the present invention discloses a method for a display driver circuit for driving a display screen. The method includes the following steps: determining whether a plurality of first data codes corresponding to a plurality of first data voltages outputted to a group of data lines on the display screen via a multiplexer during a first horizontal line period are equal; determining whether each of the plurality of first data codes is equal to a corresponding second data code among a plurality of second data codes corresponding to a plurality of second data voltages outputted to the group of data lines via the multiplexer during a second horizontal line period subsequent to the first horizontal line period; and, in response to the plurality of first data codes being determined to be equal and each of the plurality of first data codes being determined to be equal to the corresponding second data code, outputting a control signal among a plurality of control signals to control the switch to remain in an open state after a switch of the multiplexer is turned on to output a first data voltage among the plurality of first data voltages.

[0007] Another embodiment of the present invention discloses a display driver circuit for driving a display screen. The display driver circuit includes an output buffer, a digital-to-analog converter (DAC), and a data controller. The output buffer is configured to output a plurality of first data voltages to a group of data lines on the display screen via a multiplexer during a first horizontal line period, and to output a plurality of second data voltages to the group of data lines via the multiplexer during a second horizontal line period following the first horizontal line period. The DAC is coupled to the output buffer and is configured to generate the plurality of first data voltages based on a plurality of first data codes and to generate the plurality of second data voltages based on a plurality of second data codes. The data controller is coupled to the digital-to-analog converter and is configured to determine whether the plurality of first data codes are equal; determine whether each first data code among the plurality of first data codes is equal to a corresponding second data code among the plurality of second data codes; and, in response to the plurality of first data codes being determined to be equal and each first data code among the plurality of first data codes being determined to be equal to the corresponding second data code, output a control signal among a plurality of control signals to control a switch of the multiplexer to maintain an open state after the switch is turned on to output a first data voltage among the plurality of first data voltages.

[0008] Another embodiment of the present invention discloses a display driver circuit for driving a display screen. The display driver circuit includes an output buffer, a digital-to-analog converter, and a data controller. The output buffer is configured to output a plurality of first output voltages to a group of data lines on the display screen via a multiplexer during a first horizontal line period, and to output a plurality of second output voltages to the group of data lines via the multiplexer during a second horizontal line period following the first horizontal line period. The digital-to-analog converter is coupled to the output buffer and is configured to receive a plurality of first data codes and a plurality of second data codes, generate a plurality of first data voltages based on a first portion of the plurality of first data codes, and generate a plurality of second data voltages based on a first portion of the plurality of second data codes. The data controller is coupled to the digital-to-analog converter and is configured to determine whether the plurality of first data codes are equal; determine whether each of the plurality of first data codes is equal to a corresponding second data code of the plurality of second data codes; and, in response to the plurality of first data codes being determined to be equal and each of the plurality of first data codes being determined to be equal to the corresponding second data code, output a control signal from a plurality of control signals to control a switch of the multiplexer to remain in an open state after the switch is turned on to output a first output voltage of the plurality of first output voltages. The output buffer further generates the plurality of first output voltages by interpolation based on the plurality of first data voltages and a second portion of the plurality of first data codes, and generates the plurality of second output voltages by interpolation based on the plurality of second data voltages and a second portion of the plurality of second data codes. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a schematic diagram of a display system according to an embodiment of the present invention.

[0010] Figure 2 Timing diagram for the precharge shutdown scheme.

[0011] Figure 3 Timing diagram for the precharge start-up scheme.

[0012] Figure 4 and Figure 5 A schematic diagram of an equivalent circuit model of a display pixel.

[0013] Figure 6 The waveforms of the control signal and other related signals used for the multiplexer during the power saving period and the non-power saving period according to the embodiment of the present invention are shown.

[0014] Figure 7 FIG. 1 is a schematic diagram of a display driving circuit according to an embodiment of the present invention.

[0015] Figure 8The waveforms of the control signals and other related signals of the multiplexer during the power saving period and the non-power saving period according to another embodiment of the present invention are shown.

[0016] Figure 9 The waveforms of the control signals and other related signals of the multiplexer during the power saving period and the non-power saving period according to another embodiment of the present invention are shown.

[0017] Figure 10 Flowchart of a process of embodiment 1 of the present invention.

[0018] The description of the accompanying drawings is as follows:

[0019] 10 Display System

[0020] 100 host devices

[0021] 110, 70 display driver circuit

[0022] 112 Timing Control Circuit

[0023] 114 Gate drive circuit

[0024] 116 Data drive circuit

[0025] 118 registers

[0026] 120 display screen

[0027] GL1~GLn gate lines

[0028] DL1~DLN, DL data line

[0029] M1, M2 multiplexers

[0030] SW1~SWN switches

[0031] Hsync horizontal synchronization signal

[0032] Gate gate control signal

[0033] Vout, V1~V6 data voltage

[0034] Vpre pre-charge voltage

[0035] CS storage capacitor

[0036] DIO diode

[0037] GSW Gate Controlled Switch

[0038] NPX Node

[0039] Vinit initial signal

[0040] 702 Output Buffer

[0041] 704 Digital-to-Analog Converter

[0042] 706 Data Buffer

[0043] 708 Data Controller

[0044] V_OUT output voltage

[0045] V_DAT data voltage

[0046] C_DAT data code

[0047] CTRL control signal

[0048] 1000 Process

[0049] Steps 1002-1010 DETAILED DESCRIPTION

[0050] Figure 1 FIG. 1 is a schematic diagram of a display system 10 according to an embodiment of the present invention. Figure 1 As shown, the display system 10 includes a host device 100, a display driver circuit 110, and a display screen 120. The display system 10 can be implemented in an electronic device with a display function, such as a laptop computer, a mobile phone, or a wearable electronic device. The host device 100 can provide operating mode information regarding the electronic device to the display driver circuit 110. Upon receiving the operating mode information, the display driver circuit 110 can determine a control timing scheme for the display screen 120 based on the operating mode of the electronic device. The display driver circuit 110 then outputs various control signals to the display screen 120 according to the control timing scheme.

[0051] In an embodiment of the present invention, the host device 100 may be an application processor (AP), a central processing unit (CPU), a microprocessor, or a microcontroller unit (MCU), but is not limited thereto. The display driver circuit 110 may be implemented in a display driver integrated circuit (DDIC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device. Alternatively, the display driver circuit 110 may include multiple chips implemented on a circuit board that work together to control the display screen 120. The display screen 120 may be an organic light-emitting diode (OLED) display, which may have various sizes, such as a sub-millimeter organic light-emitting diode (mini-OLED) display or a micro-OLED display. In other embodiments, the display screen 120 may also be a sub-millimeter light-emitting diode (mini-LED) display or a micro-LED display, but is not limited thereto.

[0052] Specifically, the display driver circuit 110 includes a timing control circuit 112, a gate driver circuit 114, a data driver circuit 116, and a register 118. The timing control circuit 112 is used to control the operation of the gate driver circuit 114 and the data driver circuit 116. The gate driver circuit 114 is used to output gate control signals to the gate lines (e.g., GL1-GLn) on the display screen 120. In some embodiments, the data driver circuit 116 includes a gate driver control circuit, which can be implemented in a semiconductor chip (e.g., the display driver circuit 110) and a gate on array (GOA) circuit in the display screen 120. The gate driver control circuit generates clock signals and synchronization signals and outputs them to the gate array circuit for use by the gate array circuit, causing the gate array circuit to generate gate control signals. The data driver circuit 116 (also known as a source driver circuit) is used to output display data voltages to the data lines (e.g., DL1-DL6) on the display screen 120. Display data may be provided by the host device 100. More specifically, the timing control circuit 112 may receive source display data from the host device 100 and store the display data in a register 118. The register 118 may be implemented by a latch circuit, which may be integrated with or independent of the timing control circuit 112. The timing control circuit 112 may perform necessary image processing on the display data before transmitting the display data to the data driver circuit 116. Subsequently, depending on the operating mode, the timing control circuit 112 may control the data driver circuit 116 to output data voltages corresponding to the display data using a predetermined control timing scheme, and may also control the gate driver circuit 114 to output gate control signals.

[0053] Display screen 120 includes an array of display pixels, each of which is controlled by a gate driver circuit 114 via one of gate lines GL1-GLn and by a data driver circuit 116 via one of data lines (e.g., DL1-DL6). Gate driver circuit 114 sequentially activates gate control switches (i.e., scan switches) in the pixels using gate control signals, allowing data voltages to be input from data driver circuit 116 to the pixels via data lines DL1-DL6.

[0054] like Figure 1As shown, there is a one-to-many relationship between each data output of the data driving circuit 116 and the data lines of the display panel 120 driven by the display driving circuit 110, i.e. one data output of the data driving circuit 116 can output data voltages to multiple data lines of the display panel 120 in time division. In this example, each data output of the data driving circuit 116 is used to output display data voltages to multiple data lines DL1-DL6 and multiple columns of pixels. The transmission of the data voltages can be controlled by a multiplexer (MUX) M1 on the display panel 120. In this example, the multiplexer M1 is a 1-to-6 structure, such that each data output can output data voltages to six data lines DL1-DL6 in time division. The multiplexer M1 includes six switches SW1-SW6, which are respectively coupled to the data lines DL1-DL6. The switches SW1-SW6 can be well controlled, such that the data driving circuit 116 can output data voltages to the pixels on the display panel 120 in time division. In an embodiment, the timing control circuit 112 can output control signals to control the operation of the switches SW1-SW6, and correspondingly control the data driving of the data driving circuit 116, as shown in the following. Figure 1

[0055] It is noted that the embodiment of the multiplexer M1 in Figure 1 is only one of the many embodiments of the present application. In another embodiment, the multiplexer M1 can include different number of switches, such that one data output of the data driving circuit 116 can output data voltages to eight, ten or any number of data lines. In addition, Figure 1 Only a portion of the pixels on the display panel 120 is shown. In practice, the pixel array on the display panel 120 can include hundreds or thousands of rows and hundreds or thousands of columns of display pixels, and the display panel 120 can be provided with multiple sets of multiplexers having the same structure as the multiplexer M1.

[0056] The control timing scheme adopted by the display panel 120 includes a pre-charge OFF scheme and a pre-charge ON scheme. In the pre-charge OFF scheme, a line period (i.e. a period during which one row of pixels (which can also be regarded as one horizontal line or display line) is turned on to receive display data voltages) includes a data output period, during which the data driving circuit 116 outputs data voltages in time division. However, according to the pre-charge OFF scheme, the line period does not include a pre-charge period. Please refer to Figure 2 Figure 2 ​​This is a timing diagram of the precharge shutdown scheme, which shows the horizontal synchronization signal (Hsync), the gate control signal (Gate) transmitted to a gate line to turn on / off the scan switch in the pixel (or pixel circuit) on the current horizontal line, the control signal used to turn on / off the switches SW1 to SW6, and the waveform of the data voltage Vout output by the data driving circuit 116. Figure 2 As shown, a signal at a logic low state or a low potential can turn on (or conduct) a target switch or transistor, and a signal at a logic high state or a high potential can turn off (or disconnect) the target switch or transistor.

[0057] Please refer to Figure 2 Matching Figure 1 As shown, a pulse of the horizontal synchronization signal Hsync represents the beginning of each horizontal line period. During the data output period, the data driver circuit 116 can output data voltages V1-V6 in a time-sharing manner. Simultaneously, the switches SW1-SW6 of the multiplexer M1 are sequentially turned on to transmit the data voltages V1-V6 to the data lines DL1-DL6, respectively. The charge corresponding to the data voltages V1-V6 is stored in the parasitic capacitances of the data lines DL1-DL6. Next, when the switches SW1-SW6 are turned off, the gate control signal Gate can turn on the gate control switch in the pixel (which can be implemented, for example, by a thin-film transistor (TFT)). In this example, the drive transistor is a P-type transistor, which is turned on when the potential of the control signal is low. At this time, the data voltages V1-V6 stored on the data lines DL1-DL6 can be transmitted to the corresponding pixels through charge sharing.

[0058] Please refer to Figure 3 , Figure 3 This is the timing diagram of the pre-charge start-up scheme. Figure 3 As shown, during the entire data output period when the data driver circuit 116 time-shares the data voltages V1-V6, the gate-controlled switches in the pixels on the current horizontal line are simultaneously turned on by the gate control signal Gate, and the gate-controlled switches in the pixels remain turned on. Therefore, the data voltages V1-V6 can be directly input into the corresponding pixels instead of being temporarily stored in the parasitic capacitance of the data lines DL1-DL6. However, as described above, when the gate-controlled switches in the pixels are turned on but the corresponding switches in the multiplexer M1 have not yet turned on, the residual charge on the corresponding data line (corresponding to the previous data voltage) is first input into the pixel, causing the voltage in the pixel to reach a higher level. In this case, due to the diode-connected structure in the pixel, if the current data voltage level is lower than the voltage in the pixel, the current data voltage will not be input into the pixel.

[0059] Therefore, the precharge start-up scheme also includes a precharge period located before the data output period. More specifically, within a horizontal line period indicated by the horizontal synchronization signal Hsync, a precharge period can be arranged before the data output period. During the precharge period, the gate control signal Gate can maintain the scan switch on a horizontal line in a closed state, the switches SW1 to SW6 in the multiplexer M1 can be in an open state at the same time, and the data driving circuit 116 applies a precharge voltage Vpre to each data line DL1 to DL6 to clear the residual charge on the data lines DL1 to DL6. In a preferred embodiment, the switches SW1 to SW6 can receive the same control signal to be turned on and off simultaneously during the precharge period. This control signal can be received from the timing control circuit 112, such as Figure 1 shown.

[0060] Please refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit model of a display pixel, which is an equivalent circuit model of a pixel in the data writing stage, and takes a light-emitting diode pixel with a P-type driving transistor as an example. Figure 4 As shown, the equivalent circuit of the pixel includes a storage capacitor CS, a diode DIO and a gate control switch GSW. The pixel is connected to a data line DL for receiving a display data voltage, wherein the data line DL can be as follows: Figure 1 Any of the data lines DL1-DL6 on the display screen 120 is shown. The gate control switch GSW receives a gate control signal Gate from the gate driver circuit 114 to turn the pixel on or off. Diode DIO represents the diode-connected structure formed by the driver transistor and the compensation transistor within the pixel. Storage capacitor CS is used to store charge corresponding to the data voltage, which is used to drive the driver transistor within the pixel to output current to the light-emitting diode for light emission.

[0061] Please refer to Figure 4 Matching Figure 3 As shown in the waveform, when the previous data voltage is transmitted, the voltages of the data line DL and the node NPX in the pixel both reach the previous data voltage. Then, before outputting the current data voltage, the charge stored in the storage capacitor CS must be cleared in the initial stage. For example, an initial signal Vinit can be used to control the potential of the node NPX to drop to a lower voltage (such as zero voltage). After the initial stage ends and the data writing stage begins, the gate control signal Gate turns on the gate control switch GSW (such as SW1) before the switches SW1 to SW6 in the multiplexer M1 are turned on. Figure 3As shown in Figure 2 ). With the gate control switch GSW turned on, the remaining charge on the data line DL and node NPX share charge, reaching the same potential. Since the parasitic capacitance of the data line DL is often much larger than the capacitance of the storage capacitor CS within the pixel (because the length of the data line DL must span an entire column of pixels), this charge sharing causes node NPX to reach a potential close to that of the data line DL. If a precharge operation is not performed before the drive transistor is turned on, if the previous display data voltage is higher, the voltage at node NPX will increase during the charge sharing process, preventing the next lower display data voltage from being input to the pixel through the diode connection circuit.

[0062] Therefore, it is necessary to set a pre-charge period and use a pre-charge voltage to avoid the above situation. Figure 3 As shown, during the precharge period before the gate control signal Gate turns on the pixel, switches SW1-SW6 are simultaneously turned on, and the data driver circuit 116 outputs a precharge voltage Vpre to the data lines DL1-DL6, causing the potentials of the data lines DL1-DL6 to reach the precharge voltage Vpre. This precharge voltage Vpre must be low enough to allow the subsequent data voltages V1-V6 output during the next data output period to be successfully written into the pixel. More specifically, the precharge voltage Vpre can have any suitable voltage value that is lower than the minimum of the data voltages V1-V6 and has a margin. This margin must be equal to or greater than the threshold voltage of the drive transistor in the diode-connected circuit.

[0063] The pre-charge operation can be widely used in organic light emitting diode displays. Figure 4 An embodiment of using a P-type driving transistor to drive a light-emitting diode (such as an organic light-emitting diode) is shown. Therefore, the pre-charge voltage Vpre needs to be lower than the data voltages V1 to V6. In another embodiment, the control timing of the pre-charge start scheme can also be applied to display pixels where the light-emitting diode is driven by an N-type transistor. Its equivalent circuit model is as follows: Figure 5 As shown. It should be noted that the pre-charge voltage Vpre for N-type drive pixels needs to be a relatively high voltage. More specifically, the pre-charge voltage Vpre can have any suitable voltage value that is higher than the maximum of the data voltages V1-V6 and has a margin that is equal to or greater than the threshold voltage of the drive transistor. The higher pre-charge voltage Vpre can push the data line DL to a higher level during the pre-charge period, thereby maintaining the node NPX at a higher potential after charge sharing, thereby preventing the subsequent data voltages V1-V6 from being able to activate the diode connection structure within the pixel.

[0064] It can be seen that the pre-charging operation can actually be pre-charging or pre-discharging, depending on the pixel circuit design. The pre-charging operation can be regarded as a reset operation for the voltage of the data line.

[0065] Figure 2 and Figure 3 The control timings for the precharge-off scheme and the precharge-on scheme are shown, respectively. The main difference between them is that in the precharge-off scheme, when the gate control switch GSW is turned on, the switches SW1-SW6 in the multiplexer M1 are turned off. Therefore, the pixels are charged by the charge on the data lines DL1-DL6, and the light emission is determined by the amount of charge transferred to the pixels. In the precharge-on scheme, the switches SW1-SW6 in the multiplexer M1 and the gate control switch GSW are both turned on. Therefore, the pixels are directly charged by the data driver circuit 116 via the data voltages V1-V6. During the precharge period before the data voltages V1-V6 are charged, the precharge voltage Vpre is used to clear or reset the residual charge on the data lines DL1-DL6.

[0066] like Figure 2 and Figure 3 As shown, in the pre-charge-on scheme, each switch needs to switch (including opening and closing) four times during each horizontal line period; in the pre-charge-off scheme, each switch needs to switch (including opening and closing) twice during each horizontal line period. To reduce the number of switch switching times, the present invention proposes a multiplexer control method that can adjust the multiplexer switching according to the image content to reduce the overall switch switching number, thereby reducing the power consumption generated by the switch switching.

[0067] In one embodiment, when the display driver circuit 110 determines that all data voltages output by the same multiplexer (e.g., M1) are equal during two or more consecutive horizontal line periods, the display driver circuit 110 may control the multiplexer M1 to enter a power-saving mode. In power-saving mode, switches SW1-SW6 within the multiplexer M1 are controlled to remain in an open state. In other words, the display driver circuit 110 provides control signals to continuously turn on the switches SW1-SW6. Because all data voltages output by the data driver circuit 116 through the switches SW1-SW6 within the multiplexer M1 during these horizontal line periods are equal, the timing of writing the data voltages to the pixels is not affected, and the display of the image is not affected. Thus, by continuously turning on the switches SW1-SW6 for more than two horizontal line periods, the number of switch switching operations can be reduced. When the display driving circuit 110 determines that the data voltages output by the same multiplexer on consecutive horizontal lines are no longer the same, the display driving circuit 110 can control the control timing of the multiplexer M1 to return to the original non-power saving mode, such as the control timing of the pre-charge on or pre-charge off scheme described above.

[0068] Figure 6 The waveforms of the control signals and other related signals (i.e., the horizontal synchronization signal Hsync and the gate control signal Gate) used for the multiplexer according to an embodiment of the present invention during the power saving period and the non-power saving period are shown. The power saving period is the period when the multiplexer operates in the power saving mode, and the non-power saving period is the period when the multiplexer operates in the non-power saving mode. In this example, the multiplexer has N switches SW1 to SWN, where N can be any positive integer. Figure 6 As shown, during the non-power saving period, the switches SW1 to SWN are switched according to a predetermined timing scheme (eg Figure 2 、 3 The display driver circuit sequentially transmits data voltages to the corresponding data lines and pixels. When the power-saving period begins, switches SW1-SWN turn on and remain on until the end of the power-saving period. No unnecessary switching occurs during this period. Figure 6 The control timing of the pre-charge on scheme and the pre-charge off scheme are shown. Both control timing schemes can reduce switch switching by extending the on time of the switch.

[0069] It is worth noting that all switches SW1-SWN being simultaneously turned on means that the data voltage is simultaneously transmitted to the data line and pixel corresponding to each switch. To avoid affecting the image display, the display driver circuit must detect the image content to be displayed. Moreover, the power saving mode can only be activated under specific image content, that is, image content that is not affected by the power saving operation used to reduce switching.

[0070] Please refer to Figure 7 , Figure 7 FIG. 1 is a schematic diagram of a display driving circuit 70 according to an embodiment of the present invention. Figure 7 As shown, the display driver circuit 70 includes an output buffer 702, a digital-to-analog converter (DAC) 704, a data buffer 706, and a data controller 708. Although a multiplexer M2 on the display screen is not included in the display driver circuit 70, it is shown in FIG. Figure 7 For ease of explanation.

[0071] Specifically, output buffer 702 transmits an output voltage V_OUT to a set of data lines DL1-DLN on the display screen via multiplexer M2 during each horizontal line period. Output buffer 702 may be an operational amplifier (OA) with sufficient driving capability to drive the data lines DL1-DLN on the display screen. A digital-to-analog converter 704 is coupled to output buffer 702 and generates a data voltage V_DAT based on a corresponding data code C_DAT. The data code C_DAT is stored in a data buffer 706 before being received and processed by the DAC 704. Data buffer 706 may be, for example, a data latch in a data driver circuit or a register in a timing control circuit, but is not limited thereto. A data controller 708 determines the data code C_DAT stored in data buffer 706 and, accordingly, outputs a control signal CTRL to control switches SW1-SWN in multiplexer M2. In one embodiment, data controller 708 may be a logic circuit module included in the timing control circuit.

[0072] In one embodiment, the digital-to-analog converter 704 may generate a data voltage V_DAT based on all of the data code C_DAT; accordingly, the output buffer 702 transmits the data voltage V_DAT to the display as the output voltage V_OUT. In another embodiment, the digital-to-analog converter 704 may receive the data code C_DAT and generate the data voltage V_DAT based on a first portion of the data code C_DAT. Upon receiving the data voltage V_DAT from the digital-to-analog converter 704, the output buffer 702 may interpolate the data voltage V_DAT and a second portion of the data code C_DAT to generate the output voltage V_OUT. For example, if the digital-to-analog converter 704 is a 6-bit digital-to-analog converter that is required to process a 10-bit data code C_DAT, the first six higher-order bits of the data code C_DAT may be provided to the digital-to-analog converter 704 to generate the data voltage V_DAT. The output buffer 702 receives the data voltage V_DAT and information about the last four lower bits of the data code C_DAT, and interpolates the lower bits of the data code C_DAT to generate an output voltage V_OUT to be output to the display.

[0073] In order to prevent the image display from being affected by the power saving operation, the data controller 708 can determine whether the data codes corresponding to the data voltages outputted by the same multiplexer (such as M2) during the same horizontal line period are equal. Figure 6 As shown, during the power-saving period, switches SW1-SWN are simultaneously turned on. Therefore, during the same horizontal line period, the output voltages V_OUT to be output to a row of pixels via multiplexer M2 should be equal. This prevents the displayed image from being affected. This is because the on-times of switches SW1-SWN are extended and overlap. In this case, the data codes C_DAT corresponding to the output voltages V_OUT should also be equal.

[0074] In addition, the data controller 708 can also determine whether the data codes corresponding to the data voltages output by the same multiplexer (e.g., M2) during multiple consecutive horizontal line periods are equal. For example, the output buffer 702 can output multiple first output voltages to the data lines DL1-DLN via the multiplexer M2 during a first horizontal line period. These first output voltages correspond to multiple first data codes (e.g., converted by the digital-to-analog converter 704 or converted by the output buffer 702 through interpolation). The output buffer 702 can also output multiple second output voltages to the data lines DL1-DLN via the multiplexer M2 during a second horizontal line period following the first horizontal line period. These second output voltages correspond to multiple second data codes (e.g., converted by the digital-to-analog converter 704 or converted by the output buffer 702 through interpolation). Therefore, the data controller 708 can determine whether any one or more of the first data codes are equal to the corresponding second data codes output by the same switch, thereby determining whether to extend the on-period of the switch to span multiple horizontal line periods.

[0075] In one embodiment, the data controller 708 may determine whether all first data codes corresponding to the first horizontal line period are equal, and also determine whether each of the first data codes is equal to a second data code corresponding to the first data code among the second data codes in the second horizontal line period following the first horizontal line period. If both determinations are "yes," after a switch in the multiplexer M2 (which may be any of the switches SW1-SWN) is turned on to output or transmit the first output voltage during the first horizontal line period, the data controller 708 may output a control signal CTRL to the switch to control the switch to remain in the on state. In other words, after the switch is turned on, it may remain in the on state until the end of the first horizontal line period.

[0076] When the data controller 708 determines that the first data codes corresponding to the first horizontal line period are all equal and that each first data code is equal to the corresponding second data code corresponding to the second horizontal line period (i.e., the next horizontal line period), the power saving period can begin from the first horizontal line period. In other words, the switch can be turned on during the first horizontal line period and its on time can be extended to at least the end of the second horizontal line period. In this way, based on the data controller 708 performing the above two data determinations on the data code to be displayed in each horizontal line period, the power saving period (i.e., maintaining the switch in the on state without switching between the on / off states) can be continued until the result of the determination in response to at least one of the above two data determination conditions is negative.

[0077] If the power saving period starts from another line period before the first line period, the switch has been turned on in the previous line period and remains on until the first line period. In this case, the data controller 708 can determine whether the first data codes corresponding to the first line period are all equal, and determine whether each first data code is equal to the corresponding second data code corresponding to the second line period, so as to determine whether to continue to extend the on period of the switch (i.e. remain in the power saving mode) or turn off the switch (i.e. leave the power saving mode and enter the non-power saving mode).

[0078] Therefore, the data controller 708 needs to decide the timing control scheme whether to control the switch to remain on or to return to the non-power saving mode. If the data controller 708 determines that the data codes corresponding to the output voltages outputted by the same multiplexer in the same line period are not equal, and / or determines that any data code is not equal to the corresponding data code in the next line period, the data controller 708 can output a control signal CTRL to turn off the switch. As shown in Figure 6 When the power saving period ends (i.e. the last line period in which the power saving operation is performed), the switches SW1-SWN are turned off and the switch switching according to the operation mode of the pre-charge on scheme or the pre-charge off scheme is restarted in the next line period.

[0079] In another embodiment, in order to determine whether the data codes are equal, the data controller 708 can determine whether the data codes corresponding to the output voltages outputted by the multiplexer in the same line period or a plurality of consecutive line periods have the same characteristics, such as corresponding to the same specific gray scale (i.e. specific data code). For example, the data controller 708 can determine whether the data codes are all the same as a specific data code, such as the corresponding data code of the minimum gray scale value, for causing the display screen to display a plurality of consecutive black lines.

[0080] In this way, the multiplexer M2 can enter the power saving mode when displaying a grayscale image, because the corresponding data codes of the three pixel colors (red, green and blue) in the grayscale image are all the same, so that there is no need to control the switch to be sequentially turned on / off when writing the data voltages on each line, and there is no need to perform the pre-charge operation in the pre-charge on scheme before writing the data voltages, so that the number of switch switching can be reduced.

[0081] Thus, in one embodiment, before outputting the data voltage for each horizontal display line, the data controller 708 detects whether the data code corresponding to the current horizontal display line is identical to the data code of the previous horizontal display line (or the next horizontal display line). Alternatively or additionally, in one embodiment, before outputting the data voltage for each horizontal display line, the data controller 708 detects whether the data codes corresponding to all switches SW1-SWN in the multiplexer M2 are identical. When two or more consecutive horizontal display lines have the same data code (and therefore the same data voltage), the aforementioned method of extending the switch on time can be used to reduce the number of switch switching cycles.

[0082] It is worth noting that the power saving operation can be performed under the same corresponding output voltage of the display data on a horizontal display line. This same data voltage may come from the same or different original display data grayscale. Generally speaking, the original display data grayscale may undergo various signal processing to improve the visual effect, such as overdriving, subpixel rendering, white balance calibration, etc. These signal processing may change the data code finally output to the digital-to-analog converter, thereby changing the corresponding data voltage. The image content detection of the present invention is mainly performed on the final output data code. In fact, the data controller in the display driving circuit does not judge the analog data voltage, but makes a judgment based on the digital data code corresponding to the final output data voltage, so as to enable the power saving mode multiplexer control method when the data voltages of a horizontal display line or several consecutive horizontal display lines are equal. Therefore, in one embodiment, in order to make a judgment on whether they are equal, the data controller can take out the data code from the data latch in the data driving circuit, or take out the data code that has completed various signal processing and is ready to be transmitted to the data driving circuit from the register of the timing control circuit. In other words, Figure 7 The data buffer 706 in may be as follows Figure 1 The data driver circuit 116 shown includes a data latch or register 118 .

[0083] It is worth noting that the purpose of the present invention is to extend the on-time of the switch in the multiplexer to span multiple horizontal line periods under specific images (for example, the data codes corresponding to the data voltages transmitted through the same multiplexer during a horizontal line period are all equal), thereby reducing the number of switch switching times. Those skilled in the art can make modifications or changes accordingly, without limitation. For example, Figure 6The power-saving operation described herein is only one of many embodiments of the present invention. During the power-saving period, all switches SW1-SWN are simultaneously turned on and off. In another embodiment, the switch on / off timings can be flexibly adjusted to similarly reduce the number of switch toggling cycles.

[0084] For example, Figure 8 FIG. 2 shows the waveforms of the control signals and other related signals used for the multiplexer during the power saving period and the non-power saving period according to another embodiment of the present invention. Figure 8 As shown, during the power-saving period, each switch SW1-SWN can still be sequentially turned on according to the predetermined timing of the pre-charge on / off scheme, and then remain in the on state until the last horizontal line of the power-saving period, when it is sequentially turned off. Regardless of whether the switches SW1-SWN are turned on / off simultaneously or sequentially, no additional switch state switching occurs during the power-saving period, thereby achieving the goal of reducing power consumption. In other embodiments, the switches can be controlled to turn on simultaneously and turn off sequentially, or to turn on sequentially and turn off simultaneously, or the order of turning on / off the switches can be arbitrarily adjusted according to system requirements. These variations in control methods are all within the scope of the present invention.

[0085] As long as the data codes corresponding to the output voltages to be output during a specific horizontal line period are determined to be equal, and those data codes are determined to be equal to the corresponding data codes during the next horizontal line period, the switch can be controlled to remain in the open state until at least the end of the specific horizontal line period. Furthermore, the switch can be closed if the data controller detects that any subsequent data codes have different values.

[0086] In the above Figure 6 and Figure 8 In the embodiment shown, all switches SW1-SWN are maintained in the on state and stop switching during the power saving period. In another embodiment, some switches can be selectively controlled to remain in the on state in the power saving mode, while the other switches continue to use the predetermined control timing of the pre-charge on or pre-charge off scheme. Therefore, during the power saving period, the data controller only controls one or more of the switches SW1-SWN to remain in the on state. Figure 9 As shown, during the power-saving period, switches SW3-SWN are kept on longer to reduce state switching, while switches SW1 and SW2 maintain the same control timing as during the non-power-saving period. As long as the on-time of any switch in the multiplexer is extended and spans multiple horizontal periods, the related operation falls within the scope of the present invention. In this case, switch state switching can still be reduced, achieving the effect of power saving.

[0087] The above operation of the display driving circuit can be summarized as a process 1000. Figure 10 The process 1000 can be implemented in a display driver circuit for driving a display screen, such as Figure 1 The display driving circuit 110 or Figure 7 The display driving circuit 70 in FIG. Figure 10 As shown, process 1000 includes the following steps:

[0088] Step 1002 : Turn on a switch of the multiplexer to output a first data voltage among a plurality of first data voltages.

[0089] Step 1004: Determine whether the first data codes corresponding to the first data voltages output to a group of data lines on the display screen by the multiplexer during a first horizontal line period are equal. If so, execute step 1006; if not, execute step 1010.

[0090] Step 1006: Determine whether each of the plurality of first data codes is equal to a corresponding second data code among the plurality of second data codes corresponding to the plurality of second data voltages output to the set of data lines by the multiplexer during a second horizontal line period following the first horizontal line period. If so, execute step 1008; if not, execute step 1010.

[0091] Step 1008: Control the switch to remain in the on state.

[0092] Step 1010: Turn off the switch.

[0093] It should be noted that the order of step 1004 and step 1006 can be interchanged, and step 1008 and step 1010 are executed based on the judgment results of step 1004 and step 1006. For other detailed operations and changes of process 1000, please refer to the description in the above paragraphs and will not be repeated here.

[0094] In summary, the present invention provides a control method for controlling the switches of a multiplexer configured on a display screen with a one-to-many structure. The control timing for both the precharge-on scheme and the precharge-off scheme requires that the multiplexer's switches continuously switch during each horizontal line period. In the present invention, when the display driver circuit determines that the corresponding data codes of the data voltages output by the multiplexer during multiple consecutive horizontal line periods are all equal, after the switch is turned on to output or transmit the data voltage, it is controlled to remain in the on state during those horizontal line periods. This reduces the number of switch switching cycles, achieving power savings.

[0095] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for a display driver circuit, wherein the display driver circuit is used to drive a display screen, the method comprising: determining whether a plurality of first data codes corresponding to a plurality of first data voltages output to a group of data lines on the display screen through a multiplexer during a first horizontal line period are equal; determining whether each of the plurality of first data codes is equal to a corresponding second data code among a plurality of second data codes corresponding to a plurality of second data voltages output to the set of data lines by the multiplexer during a second horizontal line period subsequent to the first horizontal line period; as well as In response to the first data codes being determined to be equal and each of the first data codes being determined to be equal to the corresponding second data code, after a switch of the multiplexer is turned on to output a first data voltage of the first data voltages, a control signal of the plurality of control signals is output to control the switch to remain in an open state; The step of determining whether each of the plurality of first data codes is equal to the corresponding second data code comprises: Determine whether a first data code corresponding to the first data voltage output by the switch of the multiplexer during the first horizontal line period and a second data code corresponding to a second data voltage among the plurality of second data voltages output by the switch of the multiplexer during the second horizontal line period correspond to the same grayscale.

2. The method according to claim 1, wherein In response to the first data codes being determined to be unequal, after the switch is turned on to output the first data voltage, the control signal is output to turn off the switch.

3. The method according to claim 1, wherein In response to at least one first data code among the plurality of first data codes being determined to be unequal to the corresponding second data code, the control signal is output to turn off the switch after the switch is turned on to output the first data voltage.

4. The method according to claim 1, wherein The step of determining whether the plurality of first data codes are equal comprises: It is determined whether each of the plurality of first data codes corresponding to the plurality of first data voltages outputted by the multiplexer during the first horizontal line period corresponds to the same grayscale.

5. The method according to claim 1, wherein The multiplexer includes a plurality of switches, And the method further includes: In response to the first data codes being determined to be equal and each of the first data codes being determined to be equal to the corresponding second data code, after the switches are turned on to output the first data voltages, the control signals are output to control each of the switches to maintain the turned-on state.

6. The method according to claim 1, wherein The step of outputting a control signal from the plurality of control signals to control the switch to maintain the open state includes: The control signal among the plurality of control signals is output to control the switch to maintain the on state at least until the first horizontal line period ends.

7. A display driver circuit for driving a display screen, the display driver circuit comprising: an output buffer configured to output a plurality of first data voltages to a group of data lines on the display screen through a multiplexer during a first horizontal line period, and to output a plurality of second data voltages to the group of data lines through the multiplexer during a second horizontal line period subsequent to the first horizontal line period; a digital-to-analog converter coupled to the output buffer, configured to generate the plurality of first data voltages according to a plurality of first data codes and to generate the plurality of second data voltages according to a plurality of second data codes; as well as A data controller, coupled to the digital-to-analog converter, is configured to: determining whether the plurality of first data codes are equal; determining whether each first data code among the plurality of first data codes is equal to a corresponding second data code among the plurality of second data codes; as well as In response to the first data codes being determined to be equal and each of the first data codes being determined to be equal to the corresponding second data code, after a switch of the multiplexer is turned on to output a first data voltage of the first data voltages, a control signal of the plurality of control signals is output to control the switch to remain in an open state; The step of determining whether each of the plurality of first data codes is equal to the corresponding second data code comprises: Determine whether a first data code corresponding to the first data voltage output by the switch of the multiplexer during the first horizontal line period and a second data code corresponding to a second data voltage among the plurality of second data voltages output by the switch of the multiplexer during the second horizontal line period correspond to the same grayscale.

8. The display driving circuit according to claim 7, wherein: In response to the first data codes being determined to be unequal, the data controller is configured to output the control signal to turn off the switch after the switch is turned on to output the first data voltage.

9. The display driving circuit according to claim 7, wherein: In response to at least one first data code among the plurality of first data codes being determined to be unequal to the corresponding second data code, the data controller is configured to output the control signal to close the switch after the switch is turned on to output the first data voltage.

10. The display driving circuit according to claim 7, wherein: The data controller is further used for determining whether each of the plurality of first data codes corresponds to the same grayscale.

11. The display driving circuit according to claim 7, wherein: The multiplexer includes a plurality of switches, and the data controller is further configured to: In response to the first data codes being determined to be equal and each of the first data codes being determined to be equal to the corresponding second data code, after the switches are turned on to output the first data voltages, the control signals are output to control each of the switches to maintain the turned-on state.

12. The display driving circuit according to claim 7, wherein: The data controller is used for outputting the control signal among the plurality of control signals to control the switch to maintain the on state at least until the first horizontal line period ends.

13. A display driver circuit for driving a display screen, the display driver circuit comprising: an output buffer configured to output a plurality of first output voltages to a group of data lines on the display screen through a multiplexer during a first horizontal line period, and to output a plurality of second output voltages to the group of data lines through the multiplexer during a second horizontal line period subsequent to the first horizontal line period; a digital-to-analog converter, coupled to the output buffer, for receiving a plurality of first data codes and a plurality of second data codes, generating a plurality of first data voltages according to a first portion of the plurality of first data codes, and generating a plurality of second data voltages according to a first portion of the plurality of second data codes; and A data controller, coupled to the digital-to-analog converter, is configured to: determining whether the plurality of first data codes are equal; determining whether each first data code among the plurality of first data codes is equal to a corresponding second data code among the plurality of second data codes; as well as In response to the first data codes being determined to be equal and each of the first data codes being determined to be equal to the corresponding second data code, after a switch of the multiplexer is turned on to output a first output voltage of the first output voltages, outputting a control signal of a plurality of control signals to control the switch to remain in an on state; The output buffer further generates the plurality of first output voltages by interpolation according to the plurality of first data voltages and a second portion of the plurality of first data codes, and generates the plurality of second output voltages by interpolation according to the plurality of second data voltages and a second portion of the plurality of second data codes; The step of determining whether each of the plurality of first data codes is equal to the corresponding second data code comprises: Determine whether a first data code corresponding to the first output voltage output by the switch of the multiplexer during the first horizontal line period and a second data code corresponding to a second output voltage among the plurality of second output voltages output by the switch of the multiplexer during the second horizontal line period correspond to a same grayscale.

14. The display driving circuit according to claim 13, wherein: In response to the first data codes being determined to be unequal, the data controller is configured to output the control signal to turn off the switch after the switch is turned on to output the first output voltage.

15. The display driving circuit according to claim 13, wherein: In response to at least one first data code among the plurality of first data codes being determined to be unequal to the corresponding second data code, the data controller is configured to output the control signal to turn off the switch after the switch is turned on to output the first output voltage.

16. The display driving circuit according to claim 13, wherein: The data controller is further used for determining whether each of the plurality of first data codes corresponds to the same grayscale.

17. The display driving circuit according to claim 13, wherein: The multiplexer includes a plurality of switches, and the data controller is further configured to: In response to the first data codes being determined to be equal and each of the first data codes being determined to be equal to the corresponding second data code, after the switches are turned on to output the first output voltages, the control signals are output to control each of the switches to maintain the turned-on state.

18. The display driving circuit according to claim 13, wherein: The data controller is used for outputting the control signal among the plurality of control signals to control the switch to maintain the on state at least until the first horizontal line period ends.

Images