A method for manufacturing a super junction IGBT

Abstract

The present invention belongs to the technical field of semiconductor power devices, and specifically relates to a method for manufacturing a super-junction IGBT. The present invention can significantly affect the electrical properties of single-crystalline silicon by using fast neutron irradiation. The electrically active defects introduced into the silicon can significantly change the resistivity of the silicon. The method for manufacturing the super-junction IGBT device can enhance the Coulomb interaction between the incident particles and silicon atoms during fast neutron irradiation, better control defects in the silicon, and achieve precise control of the minority carrier lifetime within the silicon wafer during the device manufacturing process, thereby achieving a high yield and better economic benefits. The method for manufacturing the super-junction IGBT of the present invention can reduce the influence of current on the charge equilibrium state, thereby improving the device's stability and reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and in particular relates to a method for manufacturing a super junction IGBT. Background Art

[0002] The traditional IGBT (insulated gate bipolar transistor) device is a device composed of a MOSFET (metal oxide semiconductor field effect transistor) and a bipolar transistor. Its input stage is a MOSFET and the output stage is a PNP transistor. It has the advantages of low driving power and fast switching speed of MOSFET devices, as well as the advantages of low saturation voltage and large capacity of bipolar devices.

[0003] When IGBT devices require higher withstand voltage and lower internal resistance, a superjunction structure is often used. The superjunction structure consists of P-type and N-type doped columnar regions. The superjunction structure works best when the P-type charge and N-type charge are balanced. However, when the MOSFET inside the IGBT passes through a high current density or an avalanche occurs, the P-type and N-type charge balance is lost. The excess charge causes an increase in the electric field, exacerbating the charge imbalance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defect of serious charge imbalance of super junction IGBT devices when passing through high current density or avalanche occurs, thereby providing a method for manufacturing super junction IGBT.

[0005] A method for manufacturing a super junction IGBT comprises the following steps:

[0006] Step S100: forming a field oxide layer, forming a heavily P-type doped implant region at the bottom of the silicon substrate, forming a heavily N-type doped buffer region above the implant region, and forming an N-type doped drift region above the buffer region;

[0007] Step S101: forming a first trench on the left side and a second trench on the right side of the silicon substrate;

[0008] Step S102: ion implantation forms first carrier storage regions on the left and right sides of the upper portions of the first trench and the second trench, respectively, and ions diffuse at the bottoms of the first trench and the second trench, forming second carrier storage regions on the lower left and lower right sides of the first trench and the second trench, respectively;

[0009] Step S103: etching the bottoms of the first trench and the second trench so that they are lower than the bottom of the second carrier storage area and are located in the drift region;

[0010] Step S104: forming gates in the first trench and the second trench;

[0011] Step S105: forming a P-type body region on the upper portion of the silicon substrate, with the bottom of the body region contacting the top of the second carrier storage region; forming an N-type source and drain on the left and right sides of the first trench and the left and right sides of the second trench, and connecting the gate; forming a P-type source and drain on the upper portion of the body region, and connecting the emitter;

[0012] Step S106: irradiating the silicon substrate with fast neutrons.

[0013] The present invention can have a significant impact on the electrical properties of single-crystal silicon by adopting fast neutron irradiation. The electrically active defects introduced into the silicon can cause a significant change in the resistivity of the silicon, thereby reducing the resistivity of the irradiated area after the super junction. The manufacturing method of the super junction IGBT device can enhance the Coulomb interaction between the incident particles and silicon atoms during fast neutron irradiation, better control the defects in the silicon, and achieve precise control of the minority carrier lifetime in the silicon wafer during the device manufacturing process, thereby achieving high yield and better economic benefits. Specifically, in the manufacturing method of the IGBT structure of the present invention, an N-type heavily doped carrier storage area is formed, which can better undergo Coulomb interaction with the irradiated ions during irradiation. In the manufacturing method of the super junction IGBT of the present invention, the N-type and P-type heavily doped areas can improve the stability of the triode in the IGBT device, and the increase in ions can further improve the stability of the IGBT, thereby reducing the influence of the current on the charge equilibrium state, so that the device has better stability and reliability.

[0014] Furthermore, when fast neutrons are used to irradiate the wafer, the irradiated area can be between the N-type source and drain and the implant region, the drift region, or the body region below the N-type source and drain. During irradiation, the wafer absorbs energy and repairs local damage, thereby reducing defects.

[0015] Furthermore, after step S106, the following steps are further included:

[0016] Step S107: performing annealing treatment on the wafer, with the annealing temperature being 300° C. to 700° C. and the annealing time being 0.5 h to 3 h.

[0017] Irradiating silicon after annealing at 450°C can introduce multiple acceptor energy levels in the band gap; annealing above 650°C can quickly eliminate quadrivacancy defects in single-crystal silicon and restore the conductivity type; heat treatment can slow down or uniformly irradiate the formation of thermal donors in single-crystal silicon, and as the irradiation dose increases, the uniform effect on the thermal donors is enhanced.

[0018] Furthermore, the widths of the first trench and the second trench are smaller than the distance between the first trench and the second trench.

[0019] By setting the width of the first and second grooves to be smaller than the spacing between them, adverse effects on subsequent irradiation operations can be avoided. Specifically, during irradiation, the wafer can be prevented from vibrating violently due to energy absorption, potentially leading to defects in the wafer between the first and second grooves.

[0020] Furthermore, the irradiation treatment uses fast neutron irradiation with an electron energy of 400 keV, a beam intensity of 1.67×10 A, and an irradiation dose of 1×10 6 cm -2 ~2×10 6 cm -2 .

[0021] By setting the irradiation dose, it is possible to ensure that vacancies and self-interstitial atomic pairs are generated in the crystal, and that impurities such as oxygen, nitrogen, and phosphorus in the silicon single crystal react to form a complex; the complex can compensate for the original doping of the silicon single crystal, and the vacancy-related complex can also affect the donor during the subsequent heat treatment of the silicon single crystal.

[0022] Furthermore, the beam is scanned laterally during irradiation.

[0023] By scanning the beam laterally during irradiation, uniform irradiation of the wafer's irradiated surface can be ensured.

[0024] Furthermore, during the annealing treatment, the gas used is nitrogen, hydrogen, a mixture of nitrogen and hydrogen, or air.

[0025] By adding helium, neon and nitrogen to the annealing gas, the crystal structure can be better restored and defects can be eliminated.

[0026] Furthermore, the annealing treatment adopts a rapid annealing process.

[0027] By adopting the rapid annealing process, the entire silicon wafer can be heated to a temperature range of 400~1300℃ in a very short time, with a small thermal budget, small impurity movement in silicon, small contamination and short processing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flow chart of the method of the present invention;

[0029] Figure 2 Schematic diagram of the device structure in step S101 of the present invention;

[0030] Figure 3 Schematic diagram of the device structure in step S102 of the present invention;

[0031] Figure 4 Schematic diagram of the device structure in step S103 of the present invention;

[0032] Figure 5 Schematic diagram of the device structure in step S105 of the present invention.

[0033] Figure numerals: 11, first trench; 12, second trench; 21, first carrier storage area; 22, second carrier storage area; 31, N-type source and drain; 32, P-type source and drain; 4, injection region; 5, buffer region; 6, drift region; 7, body region; 8, gate. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0035] This embodiment provides a method for manufacturing a super junction IGBT. Figure 1 As shown, a method for manufacturing a super junction IGBT includes the following steps:

[0036] Step S100: forming a field oxide layer, forming a heavily P-type doped implantation region 4 at the bottom of the silicon substrate, forming a heavily N-type doped buffer region 5 above the implantation region 4, and forming an N-type doped drift region 6 above the buffer region 5;

[0037] Step S101: Refer to Figure 2 As shown, a first trench 11 located on the left and a second trench 12 located on the right are formed on the upper side of the silicon substrate respectively;

[0038] Step S102: Refer to Figure 3 As shown, ion implantation forms first carrier storage areas 21 on the left and right sides of the upper portions of the first trench 11 and the second trench 12, respectively, and ions diffuse at the bottoms of the first trench 11 and the second trench 12, forming second carrier storage areas 22 on the lower left and lower right sides of the first trench 11 and the second trench 12, respectively.

[0039] Step S103: Refer to Figure 4 As shown, the bottoms of the first trench 11 and the second trench 12 are etched so as to be lower than the bottom of the second carrier storage area 22 and located in the drift region 6;

[0040] Step S104: forming a gate 8 in the first trench 11 and the second trench 12;

[0041] Step S105: forming a P-type body region 7 on the upper portion of the silicon substrate, with the bottom of the body region 7 contacting the top of the second carrier storage region 22; forming an N-type source and drain 31 on the left and right sides of the first trench 11 and the left and right sides of the second trench 12, and connecting them to the gate 8; forming a P-type source and drain 32 on the upper portion of the body region 7, and connecting them to the emitter;

[0042] Step S106: irradiating the silicon substrate with fast neutrons.

[0043] The present invention uses fast neutron irradiation to significantly affect the electrical properties of single-crystalline silicon. The electrically active defects introduced into the silicon can significantly change the resistivity of the silicon. The manufacturing method of the super-junction IGBT device can enhance the Coulomb interaction between the incident particles and silicon atoms during fast neutron irradiation, better control the defects in the silicon, and achieve precise control of the minority carrier lifetime in the silicon wafer during the device manufacturing process, thereby achieving high yield and better economic benefits. The manufacturing method of the super-junction IGBT of the present invention can reduce the influence of current on the charge equilibrium state, so that the device has better stability and reliability.

[0044] When the wafer is irradiated with fast neutrons, the irradiated area may be between the N-type source / drain 31 and the implantation region 4 , the drift region 6 , or the body region 7 below the N-type source / drain 31 .

[0045] After step S106, the following steps are further included:

[0046] Step S107: performing annealing treatment on the wafer, with the annealing temperature being 300° C. to 700° C. and the annealing time being 0.5 h to 3 h.

[0047] Irradiating silicon after annealing at 450°C can introduce multiple acceptor energy levels in the band gap; annealing above 650°C can quickly eliminate quadrivacancy defects in single-crystal silicon and restore the conductivity type; heat treatment can slow down or uniformly irradiate the formation of thermal donors in single-crystal silicon, and as the irradiation dose increases, the uniform effect on the thermal donors is enhanced.

[0048] Specifically, the width of the first trench 11 and the second trench 12 is smaller than the distance between the first trench 11 and the second trench 12 .

[0049] By setting the width of the first groove 11 and the second groove 12 to be smaller than the distance between the first groove 11 and the second groove 12 , adverse effects on subsequent irradiation operations can be avoided.

[0050] In some embodiments of the present invention, the irradiation treatment is performed using fast neutron irradiation on a 2 MeV linear electron accelerator with an electron energy of 400 keV, a beam current of 1.67 × 10 A, and an irradiation dose of 1 × 10 6cm -2 ~2×10 6 cm -2 .

[0051] By setting the irradiation dose, it is possible to ensure that vacancies and self-interstitial atomic pairs are generated in the crystal, and that impurities such as oxygen, nitrogen, and phosphorus in the silicon single crystal react to form a complex; the complex can compensate for the original doping of the silicon single crystal, and the vacancy-related complex can also affect the donor during the subsequent heat treatment of the silicon single crystal.

[0052] In some embodiments of the present invention, the beam is scanned laterally during irradiation.

[0053] By scanning the beam laterally during irradiation, uniform irradiation of the wafer's irradiated surface can be ensured.

[0054] In some embodiments of the present invention, the gas used in the annealing process is nitrogen, hydrogen, a mixture of nitrogen and hydrogen, or air.

[0055] By adding helium, neon and nitrogen to the annealing gas, the crystal structure can be better restored and defects can be eliminated.

[0056] Specifically, the annealing treatment adopts a rapid annealing process, which can be pulsed laser rapid annealing, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, and incoherent broadband light source (such as halogen lamp, arc lamp, graphite heating) rapid annealing.

[0057] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. Those skilled in the art will recognize that several equivalent substitutions or obvious modifications can be made without departing from the scope of the present invention, and that any equivalent performance or application should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a super junction IGBT, characterized in that: The following steps are involved: Step S100: forming a field oxide layer, forming a P-type heavily doped injection region (4) at the bottom of the silicon substrate, forming an N-type heavily doped buffer region (5) above the injection region (4), and forming an N-type doped drift region (6) above the buffer region (5); Step S101: forming a first trench (11) on the left side and a second trench (12) on the right side on the upper side of the silicon substrate; Step S102: ion implantation is performed to form first carrier storage areas (21) on the left and right sides of the upper portions of the first trench (11) and the second trench (12), and ions are diffused at the bottoms of the first trench (11) and the second trench (12), forming second carrier storage areas (22) on the lower left and lower right sides of the first trench (11) and the second trench (12); Step S103: etching the bottoms of the first trench (11) and the second trench (12) so that they are lower than the bottom of the second carrier storage area (22) and are located within the drift region (6); Step S104: forming a gate (8) in the first trench (11) and the second trench (12); Step S105: forming a P-type body region (7) on the upper portion of the silicon substrate, wherein the bottom of the body region (7) contacts the top of the second carrier storage region (22); forming an N-type source and drain (31) on the left and right sides of the first trench (11) and the left and right sides of the second trench (12), and connecting the gate (8); forming a P-type source and drain (32) on the upper portion of the body region (7), and connecting the emitter; Step S106: irradiating the silicon substrate with fast neutrons; Step S107: annealing the silicon substrate, introducing acceptor energy levels in the band gap of the irradiated region by annealing at a temperature of 450° C., and restoring the conductivity type in the single crystal silicon by annealing at a temperature above 650° C.

2. The method for manufacturing a super junction IGBT according to claim 1, wherein: When the wafer is irradiated with fast neutrons, the irradiated area may be between the N-type source and drain (31) and the injection area (4), or may be the drift area (6), or may be the body area (7) below the N-type source and drain (31).

3. The method for manufacturing a super junction IGBT according to claim 1, wherein: In step S107 , the annealing time is 0.5 h to 3 h.

4. The method for manufacturing a super junction IGBT according to claim 1, wherein: The width of the first groove (11) and the second groove (12) is smaller than the distance between the first groove (11) and the second groove (12).

5. The method for manufacturing a super junction IGBT according to claim 1, wherein: The irradiation treatment adopts fast neutron irradiation, with electron energy of 400keV, beam intensity of 1.67×10A, and irradiation dose of 1×10 6 cm -2 ~2×10 6 cm -2 .

6. The method for manufacturing a super junction IGBT according to claim 1, wherein: The beam is scanned laterally during irradiation.

7. The method for manufacturing a super junction IGBT according to claim 3, wherein: During the annealing process, the gas used is nitrogen, hydrogen, a mixture of nitrogen and hydrogen, or air.

8. The method for manufacturing a super junction IGBT according to claim 3, wherein: The annealing treatment adopts a rapid annealing process.

Images