Low-resistance reverse-conducting vertical power device and manufacturing method thereof

Abstract

The present invention discloses a low-resistance reverse-conducting vertical power device and a manufacturing method thereof, which mainly solve the problem of large power loss of existing vertical power devices. The device includes: a drain electrode, a substrate, an aperture layer, a channel layer, and a barrier layer. Two symmetrical blocking layers are provided on both sides of the aperture layer. Source electrodes are arranged on the left and right sides of the channel layer and the barrier layer. A plurality of modulation slots are provided in the center of the barrier layer, and a P-type block is provided above each modulation slot. A modulation metal block is provided between these P-type blocks; a modulation electrode is provided above the P-type block and the modulation metal block; left and right gate slots are provided on the inner sides of the two source electrodes, and a P-type gate is provided above each gate slot, and a gate electrode is deposited on the upper parts of these two P-type gates; the barrier layer and the plurality of modulation metal blocks form an embedded Schottky diode to realize the current path from the drain electrode to the modulation electrode. The present invention has a low turn-on voltage, small power loss, and a simple manufacturing process, and can be used as a basic device for a highly reliable power electronic system.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and particularly relates to a vertical power device, which can be used as a basic device of a power electronic system. Technical Background

[0002] Currently, due to the limitations of silicon materials themselves, the performance of traditional silicon-based power switch devices has approached the theoretical limit and cannot meet the requirements of next-generation power electronic systems for high temperature, high voltage, high frequency, high efficiency, and high power density. The third-generation semiconductor material gallium nitride has broad development space and application value in directions such as 5G, fast charging technology, and microwave applications due to its excellent high breakdown electric field, good thermal conductivity, high electron mobility, etc. Based on the AlGaN / GaN heterojunction, researchers have proposed lateral and vertical structures. Among them, the lateral AlGaN / GaN HEMT device has disadvantages such as current collapse effect, uneven surface electric field distribution, and large device area. The vertical GaN-based current aperture heterojunction field effect device, that is, the vertical power device, applies an electric field in the vertical direction so that the peak electric field of the device is located in the drift layer to avoid problems such as electric field breakdown and device performance degradation caused by uneven surface electric field distribution in lateral devices. The structure of a traditional vertical power device is as Figure 1 shown, which includes: a substrate 1, a drift layer 2, an aperture layer 3, a barrier layer 4, a channel layer 5, a barrier layer 6, a P-GaN cap layer 7, a source electrode 8, a gate electrode 9, and a drain electrode 10; the barrier layer 4 is located on both sides of the aperture layer 3, the source electrode 8 is located on both sides of the barrier layer 6 and the channel layer 5, and the gate electrode 9 is deposited on the P-GaN cap layer 7. In the traditional vertical power device, the intrinsic pin diode composed of the barrier layer 4, the drift layer 2, and the substrate 1 can play a freewheeling role. However, this parasitic diode usually exhibits an extremely high turn-on voltage, which will increase the power loss when the freewheeling diode turns on. Summary of the Invention

[0003] The purpose of the present invention is to propose a low-resistance reverse-conducting vertical power device and its manufacturing method for the above-mentioned deficiencies of the prior art, so as to reduce the turn-on voltage during freewheeling operation, reduce the power consumption of the device, and improve the reliability and power characteristics of the device.

[0004] To achieve the above purpose, the technical solution of the present invention is as follows: 1.

[0006] A low-resistance reverse-conducting vertical power device, which includes, from bottom to top: a drain electrode 15, a gallium nitride homogeneous substrate 1, a drift layer 2, an aperture layer 3, a channel layer 5, a barrier layer 6. Two symmetrical barrier layers 4 are provided on both sides of the aperture layer 3, and source electrodes 7 are provided on the left and right sides of both the channel layer 5 and the barrier layer 6. It is characterized in that:

[0007] At the central position inside the barrier layer 6, n modulation slots 8 are arranged at equal intervals. Above each modulation slot, a P-type block 11 is provided. Between these P-type blocks, modulation metal blocks 12 are provided, with a total of n - 1 modulation metal blocks.

[0008] Above the n P-type blocks 11 and the n - 1 modulation metal blocks 12, a modulation electrode 13 is provided.

[0009] On the inner sides of the two source electrodes 7, left and right gate slots 9 are distributed. The lower parts of the gate slots are located in the barrier layer 6. Above the gate slots 9, P-type gates 10 are provided. On the upper parts of these two P-type gates, gate electrodes 14 are deposited.

[0010] The barrier layer 6 and the n - 1 modulation metal blocks 12 form an embedded Schottky diode, that is, the modulation metal block 12 is the anode and the barrier layer 6 is the cathode, so as to realize the current path from the drain electrode 15 to the modulation electrode 13.

[0011] Furthermore, for the embedded Schottky diode to realize the current path from the modulation electrode 13 to the drain electrode 15, when the depletion region of the P-type gate 10 blocks the two-dimensional electron gas channel below, the potential of the modulation metal block 12 is higher than that of the barrier layer 6. When this potential difference is greater than the turn-on voltage of the embedded Schottky diode, the embedded Schottky diode conducts forwardly, and the current flows from the modulation metal block 12 to the drain electrode 15.

[0012] Furthermore, the thickness a of the barrier layer 6 is 10 - 200 nm; the depth b of the n modulation slots 8 is 5 - 150 nm; the depth c of the two gate slots 9 is 8 - 170 nm.

[0013] Furthermore, the distances between the left and right P-type gates 10 and the outermost P-type block 11 are equal, and the distance d > 0.

[0014] Furthermore, the bottom layer metal of the modulation electrode 13 is selected as a metal with a work function close to that of the P-type block 11 to ensure good ohmic contact between the modulation electrode 13 and the P-type block 11.

[0015] Furthermore, the modulation electrode 13 is electrically connected to the source electrode 7.

[0016] 2. The method for fabricating a low-resistance reverse-conducting vertical power device according to the present invention includes the following steps:

[0017] A) Epitaxially grow n - -type GaN semiconductor material on the gallium nitride substrate 1 to form a drift layer 2.

[0018] B) Epitaxially grow n-type GaN semiconductor material on the drift layer 2 to form a doping concentration of 1×10 15 - 5×10 18 cm -3The aperture layer 3;

[0019] C) A mask is fabricated on the aperture layer 3 for the first time, and p-type impurities are implanted on both sides of the aperture layer 3 by using this mask to form two symmetrically arranged barrier layers 4 on the left and right;

[0020] D) GaN semiconductor material is epitaxially grown on the aperture layer 3 and the upper parts of the left and right barrier layers 4 to form a channel layer 5 with a thickness of 0.04 - 0.2 μm;

[0021] E) GaN-based wide-bandgap semiconductor material is epitaxially grown on the upper part of the channel layer 5 to form a barrier layer 6 with a thickness a of 10 - 200 nm;

[0022] F) A mask is fabricated on the upper part of the barrier layer 6 for the second time, and the left and right sides of the channel layer 5 and the barrier layer 6 are etched by using this mask until reaching the upper surface of the barrier layer 4 to form a mesa;

[0023] G) A mask is fabricated on the upper part of the barrier layer 6 and the mesa formed by etching for the third time, and metal is deposited by using this mask, and rapid thermal annealing is performed to complete the fabrication of the source electrode 7;

[0024] H) A mask is fabricated on the upper part of the barrier layer 6 and the source electrode 7 for the fourth time, and the middle position of the barrier layer 6 is etched by using this mask to form n equidistantly distributed modulation grooves 8 with a depth b of 5 - 150 nm;

[0025] I) A mask is fabricated on the upper part of the barrier layer 6, the source electrode 7, and the n modulation grooves 8 for the fifth time, and the inner sides of the two source electrodes 7 are etched by using this mask to form a gate groove 9 with a depth c of 8 - 170 nm;

[0026] J) GaN semiconductor material with a doping concentration of 5×10 15 ~1×10 20 cm -3 is epitaxially grown on the upper part of the barrier layer 6, the source electrode 7, the n modulation grooves 8, and the gate groove 9;

[0027] K) A mask is fabricated on the upper part of the barrier layer 6, the source electrode 7, the n modulation grooves 8, and the gate groove 9 for the sixth time, and the epitaxially grown P-type GaN semiconductor material is etched by using this mask to form two P-type gates 10 on the left and right and n independent P-type blocks 11 with equidistant distribution, and the distance d between the two P-type gates 10 on the left and right and the outermost P-type block 11 is > 0;

[0028] L) A mask is fabricated on the upper part of the barrier layer 6, the source electrode 7, the P-type gates 10, and the n P-type blocks 11 for the seventh time, and metal is deposited between the gaps of the n P-type blocks 11 by using this mask to form n - 1 modulation metal blocks 12;

[0029] M) The mask is fabricated for the eighth time on top of the barrier layer 6, the source electrode 7, the P-type gate 10, the n P-type blocks 11, and the n - 1 modulation metal blocks 12. Using this mask, metal is deposited on top of the n P-type blocks 11 and the n - 1 modulation metal blocks 12 to form the modulation electrode 13;

[0030] N) The mask is fabricated for the ninth time on top of the barrier layer 6, the source electrode 7, the P-type gate 10, and the modulation electrode 13. Using this mask, metal is deposited on top of the left and right P-type gates 10 to form the gate electrode 14;

[0031] O) Metal is deposited on the back of the substrate 1 to form the drain electrode 15, completing the fabrication of the entire device.

[0032] Compared with traditional vertical power devices, the device of the present invention has the following advantages:

[0033] 1. Since the Schottky diode formed by the modulation metal block 12 and the barrier layer 6 is adopted in the device of the present invention, when the two-dimensional electron gas channel is pinched off by the depletion region of the P-type gate 10, the embedded Schottky diode structure provides a reverse conduction channel for the device, that is, the embedded Schottky diode acts as a freewheeling diode when the device is turned off; and the turn-on voltage of the Schottky diode formed by the modulation metal block 12 and the barrier layer 6 is much smaller than that of the intrinsic pin diode in the device, so the power loss in the freewheeling state can be reduced.

[0034] 2. Since the modulation metal block 12 and the P-type block 11 hybrid structure is adopted in the device of the present invention, in the blocking state of the freewheeling diode, the P-type block 11 can broaden the depletion region in the barrier layer 6 below the modulation metal block 12, which can play a role in protecting the Schottky barrier; at the same time, the depletion region blocks the conduction channel of the Schottky diode, which can reduce the leakage current of the Schottky diode in the reverse bias state. In addition, when the embedded Schottky diode is turned on, the voltage will be first applied to the Schottky barrier formed by the modulation metal block 12 and the barrier layer 6, and the P-type block 11 hardly changes the turn-on voltage of the freewheeling diode.

[0035] 3. In the device structure of the present invention, the P-type gate 10 and the P-type block 11 can be fabricated simultaneously, the process is simple and easy to implement, greatly improving the yield of the device. In addition, the carriers in the channel below the P-type block 11 have almost no depletion effect, so the on-resistance of the device is hardly increased. Description of the Drawings

[0036] Figure 1 is the structural diagram of a traditional vertical power device;

[0037] Figure 2 is the structural diagram of the low-resistance reverse-conducting vertical power device of the present invention;

[0038] Figure 3It is a schematic diagram of the implementation process for preparing a low-resistance reverse-conducting vertical power device according to the present invention;

[0039] Figure 4 It is a forward conduction output characteristic curve graph for simulating the device of the present invention and a traditional device;

[0040] Figure 5 It is a reverse conduction output characteristic curve graph for simulating the device of the present invention and a traditional device;

[0041] Figure 6 It is a breakdown characteristic curve graph for simulating the device of the present invention. Specific Embodiments

[0042] The embodiments and effects of the present invention will be further described in detail below with reference to the accompanying drawings.

[0043] Refer to Figure 2 , the low-resistance reverse-conducting vertical power device of this example includes: a gallium nitride substrate 1, a drift layer 2, an aperture layer 3, a blocking layer 4, a channel layer 5, a barrier layer 6, a source electrode 7, a modulation groove 8, a gate groove 9, a P-type gate 10, a P-type block 11, a modulation metal block 12, a modulation electrode 13, a gate electrode 14, and a drain electrode 15. Among them:

[0044] The substrate 1 uses a gallium nitride homogeneous substrate;

[0045] The drift layer 2 is located above the gallium nitride substrate 1, with a thickness of 3 - 100 μm and a doping concentration of 1×10 15 ~1×10 18 cm -3 ;

[0046] The aperture layer 3 is located above the drift layer 2, with a thickness of 0.5 - 3 μm and a doping concentration of 1×10 15 ~1×10 18 cm -3 ; p-type impurities with a dose of 1×10 15 ~1×10 16 cm -2 are implanted on both sides of the aperture layer 3 to form the blocking layer 4;

[0047] The channel layer 5 is located above the two blocking layers 4 and the aperture layer 3, with a thickness of 0.04 - 0.2 μm;

[0048] The barrier layer 6 is located above the channel layer 5 and is composed of several layers of the same or different GaN-based wide-bandgap semiconductor materials, with a thickness a of 10 - 200 nm;

[0049] The source electrode 7 is located on both sides of the channel layer 5 and the barrier layer 6 respectively, and the bottom of the source electrode 7 is located on the upper surface of the blocking layer 4;

[0050] The modulation groove 8 is arranged inside the barrier layer 6 and at the central position of the barrier layer. The depth b of the n modulation grooves 8 is 5-150 nm. The modulation grooves 8 are equally spaced and independent of each other. The P-type block 11 is located above the modulation groove 8. The depth b of the modulation groove 8 is greater than the maximum depletion region width of the n P-type blocks 11, so that the depletion region of the P-type block 11 cannot block the two-dimensional electron gas channel.

[0051] The gate groove 9 is located inside the two source electrodes 7, and the lower part of the gate groove is located in the barrier layer 6. The depth c of the two gate grooves 9 is 8-170 nm. The P-type gate 10 is located above the gate groove 9. When the vertical power device is in the off state, the depletion regions of the left and right P-type gates 10 can block the two-dimensional electron gas channel. The distances d between the left and right P-type gates 10 and the outermost P-type block 11 are equal, and d>0.

[0052] There are n-1 equally spaced modulation metal blocks 12 provided between the P-type blocks 11. These modulation metal blocks 12 and the barrier layer 6 form an embedded Schottky diode, that is, the modulation metal block 12 is the anode and the barrier layer 6 is the cathode.

[0053] The modulation electrode 13 is located above the P-type block 11 and the modulation metal block 12. The bottom layer metal of the modulation electrode 13 is selected as the metal with a work function close to that of the P-type block 11 to ensure a good ohmic contact is formed between the modulation electrode 13 and the P-type block 11. The modulation electrode 13 is electrically connected to the source electrode 7.

[0054] The gate electrode 14 is located above the left and right P-type gates 10, and its length is equal to the length of the P-type gate 10.

[0055] The drain electrode 15 is located below the substrate 1, and its length is equal to the length of the substrate 1.

[0056] When the depletion region of the P-type gate 10 blocks the two-dimensional electron gas channel below, a potential difference is formed between the modulation metal block 12 and the barrier layer 6, that is, the potential of the modulation metal block is greater than the potential of the barrier layer. When the potential difference reaches the turn-on voltage of the embedded Schottky diode, the embedded Schottky diode conducts forward, and the current flows from the modulation metal block 12 to the drain electrode 15.

[0057] Refer to Figure 3 , the process of preparing the low-resistance reverse-conducting vertical power device of the present invention is given in the following three embodiments.

[0058] Embodiment 1: Fabricate a barrier layer with a thickness a of 10 nm, a modulation groove 8 with a depth b of 5 nm, a gate groove with a depth c of 8 nm, having 2 P-type blocks 11 and 1 modulation metal block 12. The distances d between the left and right P-type gates 10 and the outermost P-type block 11 are 8 nm. The aluminum component in the barrier layer 6 is 0.01, and the doping concentrations of the P-type gate 10 and the P-type block 11 are 5×10 15 cm-3 Low-resistance reverse-conducting vertical power device.

[0059] Step 1. Fabricate an n - -type GaN drift layer 2, as shown in Figure 3 a.

[0060] Using metalorganic chemical vapor deposition technology, set the temperature at 950 °C, the pressure at 40 Torr, use SiH4 as the doping source, the hydrogen flow rate at 4000 sccm, the ammonia flow rate at 4000 sccm, and the gallium source flow rate at 100 μmol / min. Under these process conditions, epitaxially grow an n + -type GaN drift layer 2 with a thickness of 100 μm and a doping concentration of 1×10 15 cm -3 -type GaN drift layer 2 on the n - -type GaN substrate 1.

[0061] Step 2. Fabricate an n-type GaN aperture layer 3, as shown in Figure 3 b.

[0062] Using metalorganic chemical vapor deposition technology, set the temperature at 900 °C, the pressure at 40 Torr, use SiH4 as the doping source, the hydrogen flow rate at 4200 sccm, the ammonia flow rate at 4200 sccm, and the gallium source flow rate at 110 μmol / min. Under these process conditions, epitaxially grow an n-type GaN aperture layer 3 with a thickness of 0.5 μm and a doping concentration of 1×10 - -type GaN drift layer 2. 15 cm -3 -type GaN aperture layer 3 on the n

[0063] Step 3. Fabricate a blocking layer 4, as shown in Figure 3 c.

[0064] First, fabricate a mask on the n-type GaN aperture layer 3. Using ion implantation technology, implant p-type impurities Mg with a dose of 1×10 15 cm -2 at both side positions inside the n-type GaN aperture layer to fabricate two left and right blocking layers 4.

[0065] Step 4. Fabricate a GaN channel layer 5, as shown in Figure 3 d.

[0066] Using molecular beam epitaxy technology, set the vacuum degree less than or equal to 1.0×10 -10 mbar, the radio frequency power at 400 W, and use N2 and high-purity Ga source as reactants. Under these process conditions, epitaxially grow GaN material with a thickness of 0.04 μm on the upper part of the aperture layer 3 and the blocking layer 4 to fabricate a GaN channel layer 5.

[0067] Step 5. Epitaxially grow Al 0.01 Ga0.99 N, fabricate the barrier layer 6, such as Figure 3 e.

[0068] Using molecular beam epitaxy technology, set the vacuum degree to be less than or equal to 1.0×10 -10 mbar, the radio frequency power is 400W, and the reactants are N2, high-purity Ga source, and high-purity Al source. Under the process conditions, epitaxially grow Al 0.01 Ga 0.99 N material with a thickness a of 10nm on the GaN channel layer 5 to form the barrier layer 6.

[0069] Step 6. Etch the left and right sides of the channel layer 5 and the barrier layer 6 to fabricate a mesa, such as Figure 3 f.

[0070] Fabricate a mask for the second time on the upper part of the barrier layer 6. Using reactive ion etching technology, set the Cl2 flow rate to be 15sccm, the pressure to be 10mTorr, and the power to be 100W. Use this mask to etch the left and right sides of the channel layer 5 and the barrier layer 6 until reaching the upper surface of the blocking layer 4 to form a mesa.

[0071] Step 7. Fabricate the source electrode 7, such as Figure 3 g.

[0072] Fabricate a mask for the third time on the upper part of the barrier layer 6 and the mesa formed by etching. Set the vacuum degree to be 1.8×10 -3 Pa, the power is 350W, and the evaporation rate is . Under the process conditions, use electron beam evaporation technology to deposit metal on the mesa formed by etching. The deposited metal is a Ti / Au / Ni metal combination, that is, Ti, Au, and Ni from bottom to top, and their thicknesses are 0.02μm, 0.3μm, and 0.05μm in sequence; then set the temperature to be 850°C and the time to be 35s. Perform rapid thermal annealing on the deposited metal to complete the fabrication of the source electrode 7.

[0073] Step 8. Fabricate the modulation slot 8, such as Figure 3 h.

[0074] Fabricate a mask for the fourth time on the upper part of the barrier layer 6 and the source electrode 7. Set the Cl2 flow rate to be 15sccm, the pressure to be 10mT, and the power to be 100W. Use this mask to etch the middle position of the barrier layer 6, and the etching depth b is 5nm; form 2 modulation slots 8 with equidistant distribution in the middle of the barrier layer 6.

[0075] Step 9. Fabricate the gate slot 9, such as Figure 3 i.

[0076] The mask is fabricated for the fifth time above the barrier layer 6, source electrode 7 and modulation groove 8. The process conditions are set as a Cl2 flow rate of 15 sccm, a pressure of 10 mT, and a power of 100 W. The reactive ion etching technology is used to etch the barrier layer inside the source electrode 7 to form a gate groove 9 with a depth c of 8 nm.

[0077] Step 10. Epitaxially grow a P-type GaN semiconductor material above the barrier layer 6, source electrode 7, modulation groove 8 and gate groove 9, such as Figure 3 j.

[0078] Using molecular beam epitaxy technology, set the vacuum degree to be less than or equal to 1.0×10 -10 mbar, the radio frequency power is 400 W, and the reactants are N2, high-purity Ga source, and high-purity Mg source. Under these process conditions, epitaxially grow a P-type GaN semiconductor material with a thickness of 0.02 μm above the barrier layer 6, source electrode 7, modulation groove 8 and gate groove 9, and the doping concentration is 5×10 15 cm -3 .

[0079] Step 11. Fabricate a P-type gate 10 and a P-type block 11, such as Figure 3 k.

[0080] The mask is fabricated for the sixth time above the P-type GaN semiconductor material. Using the reactive ion etching technology, set the process conditions as a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 100 W. Etch the epitaxial P-type GaN semiconductor material to form two left and right P-type gates 10 and two equally spaced and independent P-type blocks 11. The distance d between the two left and right P-type gates 10 and the outermost P-type block 11 is 8 nm.

[0081] Step 12. Fabricate a modulation metal block 12, such as Figure 3 l.

[0082] The mask is fabricated for the seventh time above the barrier layer 6, source electrode 7, P-type gate 10 and two P-type blocks 11. Set the vacuum degree to be less than or equal to 1.6×10 -3 Pa, set the power to 350 W, and the evaporation rate is . Using this mask, deposit metal between the two P-type blocks 11 by electron beam evaporation technology. The deposited metal is Ni, with a thickness of 0.207 μm, to fabricate a Schottky contact.

[0083] Step 13. Fabricate a modulation electrode 13, such as Figure 3 m.

[0084] The mask is fabricated for the eighth time above the barrier layer 6, source electrode 7, P-type gate 10, P-type block 11 and modulation metal block 12. Set the vacuum degree to be less than or equal to 1.6×10 -3Pa, the power is set to 400W, and the evaporation rate is Under the process conditions of

[0085] Step 14. Fabricate the gate 14, as Figure 3 n.

[0086] A mask is fabricated for the ninth time on the barrier layer 6, source electrode 7, P-type gate 10, and modulation electrode 13. Set the vacuum degree to be less than or equal to 1.6×10 -3 Pa, the power is 400W, and the evaporation rate is Under the process conditions of

[0087] Step 15. Fabricate the drain 15, as Figure 3 o.

[0088] Using electron beam evaporation technology, set the vacuum degree to be less than or equal to 1.8×10 -3 Pa, the power is 400W, and the evaporation rate is Under the process conditions of + Deposit metal on the lower part of the entire n

[0089] Example 2: Fabricate a low-resistance reverse-conducting vertical power device with the barrier layer 6 having a thickness a of 100 nm, the modulation groove 8 having a depth b of 60 nm, the gate groove having a depth c of 80 nm, having 4 P-type blocks 11 and 3 modulation metal blocks 12, the distance d between the left and right P-type gates 10 and the outermost P-type block 11 being 50 nm, the aluminum component in the barrier layer 6 being 0.3, and the doping concentrations of the P-type gate 10 and P-type block 11 being 2×10 18 cm -3 .

[0090] Step 1. Fabricate the n - type GaN drift layer 2, as Figure 3 a.

[0091] Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 1000 °C, a pressure of 45 Torr, with SiH4 as the doping source, a hydrogen flow rate of 4400 sccm, an ammonia flow rate of 4400 sccm, and a gallium source flow rate of 110 μmol / min, on an n + -type GaN substrate 1, epitaxially grow an n-type GaN drift layer 2 with a thickness of 20 μm and a doping concentration of 1×10 16 cm -3 -type GaN drift layer 2 to complete the fabrication of the n - -type GaN drift layer 2. - Step Two. Fabricate an n-type GaN aperture layer 3, as shown in

[0092] b. Figure 3 Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 1000 °C, a pressure of 45 Torr, with SiH4 as the doping source, a hydrogen flow rate of 4400 sccm, an ammonia flow rate of 4400 sccm, and a gallium source flow rate of 110 μmol / min, on the n

[0093] -type GaN drift layer 2, epitaxially grow an n-type GaN aperture layer 3 with a thickness of 1.5 μm and a doping concentration of 5×10 - cm 16 -type GaN aperture layer 3 to complete the fabrication of the n-type GaN aperture layer 3. -3 Step Three. Fabricate a blocking layer 4, as shown in

[0094] c. Figure 3 Using ion implantation technology, fabricate a mask for the first time on the n-type GaN aperture layer 3, and implant p-type impurities Mg with a dose of 6×10

[0095] cm 15 -type at both sides inside the n-type GaN aperture layer to complete the fabrication of two blocking layers 4. -2 Step Four. Fabricate a GaN channel layer 5, as shown in

[0096] d. Figure 3 Using molecular beam epitaxy technology, under the process conditions of a vacuum degree less than or equal to 1.0×10

[0097] mbar, a radio frequency power of 400 W, and using N2 and high-purity Ga source as reactants, epitaxially grow GaN material with a thickness of 0.1 μm on the upper part of the aperture layer 3 and the blocking layer 4 to complete the fabrication of the GaN channel layer 5. -10 Step Five. Epitaxially grow Al

[0098] Ga 0.3 N to fabricate a barrier layer 6, as shown in 0.7 e. Figure 3 Step Six. As shown in

[0099] Using molecular beam epitaxy technology, under the process conditions of a vacuum degree less than or equal to 1.0×10 -11 mbar, a radio frequency power of 420 W, and reactants using N2, high-purity Ga source, and high-purity Al source, an Al 0.3 Ga 0.7 N material with a thickness of 100 nm is epitaxially grown on the GaN channel layer 5 to complete the fabrication of the barrier layer 6.

[0100] Step Six. Etch the left and right sides of the channel layer 5 and the barrier layer 6 to fabricate a mesa, as shown in Figure 3 f.

[0101] A mask is fabricated for the second time on the upper part of the barrier layer 6. Using reactive ion etching technology, under the process conditions of a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 110 W, the mask is used to etch the left and right sides of the channel layer 5 and the barrier layer 6 until reaching the upper surface of the blocking layer 4 to form a mesa.

[0102] Step Seven. Fabricate the source electrode 7, as shown in Figure 3 g.

[0103] A mask is fabricated for the third time on the upper part of the barrier layer 6 and the mesa formed by etching. Metal is deposited on the upper part of the mesa formed by etching using electron beam evaporation technology. Under the process conditions of a vacuum degree less than 1.8×10 -3 Pa, a power of 400 W, and an evaporation rate of The deposited metal is a Ti / Al / Ni / Au metal combination, that is, Ti, Al, Ni, and Au from bottom to top, with thicknesses of 0.02 μm, 0.14 μm, 0.055 μm, and 0.045 μm in sequence; then, under the process conditions of a temperature of 860 °C and a time of 30 s, rapid thermal annealing is performed to complete the fabrication of the source electrode 7.

[0104] Step Eight. Fabricate the modulation slot 8, as shown in Figure 3 h.

[0105] A mask is fabricated for the fourth time on the upper part of the barrier layer 6 and the source electrode 7. The mask is used to etch the central position of the barrier layer 6, and the etching depth b is 60 nm; 4 equally spaced modulation slots 8 are formed in the middle of the barrier layer 6.

[0106] Step Nine. Fabricate the gate slot 9, as shown in Figure 3 i.

[0107] A mask is fabricated for the fifth time on the upper part of the barrier layer 6, the source electrode 7, and the 4 modulation slots 8. Using reactive ion etching technology, under the process conditions of an F4 flow rate of 47 sccm, an O2 flow rate of 5 sccm, a pressure of 15 mTorr, and a power of 350 W, the barrier layer inside the source electrode 7 is etched to form a gate slot 9 with a depth c of 80 nm.

[0108] Step Ten. Epitaxially grow P-type GaN semiconductor material on the barrier layer 6, source electrode 7, modulation grooves 8, and gate grooves 9, such as Figure 3 j.

[0109] Using molecular beam epitaxy technology, under the process conditions of a vacuum degree less than or equal to 1.0×10 -10 mbar, a radio frequency power of 400 W, and reactants using N2, high-purity Ga source, and high-purity Mg source, epitaxially grow P-type GaN semiconductor material with a thickness of 0.15 μm on the barrier layer 6, source electrode 7, four modulation grooves 8, and gate groove 9, and the doping concentration is 2×10 18 cm -3 .

[0110] Step Eleven. Fabricate P-type gate 10 and P-type blocks 11, such as Figure 3 k.

[0111] Fabricate a mask for the sixth time on the P-type GaN semiconductor material. Using reactive ion etching technology, under the process conditions of a Cl2 flow rate of 15 sccm, a pressure of 12 mTorr, and a power of 110 W, etch the epitaxial P-type GaN semiconductor material to form two left and right P-type gates 10 and four equally spaced and independent P-type blocks 11. The distance d between the two P-type gates 10 and the outermost P-type block 11 is 50 nm.

[0112] Step Twelve. Fabricate modulation metal blocks 12, such as Figure 3 l.

[0113] Fabricate a mask for the seventh time on the barrier layer 6, source electrode 7, P-type gate 10, and four P-type blocks 11. Using electron beam evaporation technology, under the process conditions of a vacuum degree of 1.6×10 -3 Pa, a power of 350 W, and an evaporation rate of , use this mask to deposit metal between the four P-type blocks 11. The deposited metal is Wu, with a thickness of 0.3 μm, to fabricate Schottky contacts;

[0114] Step Thirteen. Fabricate modulation electrodes 13, such as Figure 3 m.

[0115] Fabricate a mask for the eighth time on the barrier layer 6, source electrode 7, P-type gate 10, four P-type blocks 11, and three modulation metal blocks 12. Deposit metal using electron beam evaporation technology. Under the process conditions of a vacuum degree of 1.6×10 -3 Pa, a power of 400 W, and an evaporation rate of Under the process conditions, metal is deposited on the upper parts of 4 P-type blocks 11 and 3 modulation metal blocks 12. The deposited metal is a Ni / Pd / Au combination, with Ni, Pd, and Au from bottom to top, and the thicknesses are 0.49 μm, 0.012 μm, and 0.013 μm respectively, completing the fabrication of the modulation electrode 13.

[0116] Step Fourteen. Fabricate the gate 14, as Figure 3 n.

[0117] A mask is fabricated for the ninth time on the upper parts of the barrier layer 6, source electrode 7, P-type gate 10, and modulation electrode 13. Using electron beam evaporation technology, under a vacuum of 1.4×10 -3 Pa, a power of 650 W, and an evaporation rate of Under the process conditions, multilayer metal is deposited on the upper parts of the left and right P-type gates 10 to fabricate the gate 14. The deposited metal is a Zr / Pt metal combination, that is, Zr in the lower layer and Pt in the upper layer, with a thickness of 0.18 μm / 0.32 μm.

[0118] Step Fifteen. Fabricate the drain 15, as Figure 3 o.

[0119] Using electron beam evaporation technology, under a vacuum of 1.5×10 -3 Pa, a power of 400 W, and an evaporation rate of Under the process conditions, metal is deposited on the lower part of the entire n + -type GaN substrate 1 to fabricate the drain 15. Among them: the deposited metal is a Ti / Al / Ni / Au metal combination, that is, Ti, Al, Ni, and Au from bottom to top in sequence, and their thicknesses are 0.02 μm, 0.14 μm, 0.055 μm, and 0.045 μm respectively.

[0120] Example Three: Fabricate a low-resistance reverse-conducting vertical power device with a barrier layer thickness a of 200 nm, a modulation groove 8 depth b of 150 nm, a gate groove depth c of 170 nm, having 6 P-type blocks 11 and 5 modulation metal blocks 12, the distance d between the left and right P-type gates 10 and the outermost P-type block 11 is 130 nm, the aluminum component in the barrier layer 6 is 0.5, and the doping concentrations of the P-type gate 10 and P-type block 11 are 1×10 20 cm -3 .

[0121] Step A. Fabricate the n - -type GaN drift layer 2, as Figure 3 a.

[0122] Under the process conditions of a temperature of 950 °C, a pressure of 40 Torr, using SiH4 as the doping source, a hydrogen flow rate of 4000 sccm, an ammonia flow rate of 4000 sccm, and a gallium source flow rate of 100 μmol / min, on the n + -type GaN substrate 1, using metalorganic chemical vapor deposition technology, epitaxially grow an n-type GaN drift layer 2 with a thickness of 3 μm and a doping concentration of 1×10 18 cm -3 -type. -

[0123] Step B. Fabricate the n-type GaN aperture layer 3, as shown in Figure 3 b.

[0124] Under the process conditions of a temperature of 900 °C, a pressure of 40 Torr, using SiH4 as the doping source, a hydrogen flow rate of 4200 sccm, an ammonia flow rate of 4200 sccm, and a gallium source flow rate of 110 μmol / min, using metalorganic chemical vapor deposition technology, on the n - -type GaN drift layer 2, epitaxially grow an n-type GaN aperture layer 3 with a thickness of 3 μm and a doping concentration of 1×10 18 cm -3 -type.

[0125] Step C. Fabricate the barrier layer 4, as shown in Figure 3 c.

[0126] First, fabricate a mask on the n-type GaN aperture layer 3. Using ion implantation technology, implant p-type impurity Mg with a dose of 1×10 16 cm -2 at both sides inside the n-type GaN aperture layer to fabricate two barrier layers 4.

[0127] Step D. Fabricate the GaN channel layer 5, as shown in Figure 3 d.

[0128] Under the process conditions of a vacuum degree less than or equal to 1.0×10 -10 mbar, a radio frequency power of 400 W, and using N2 and high-purity Ga source as reactants, using molecular beam epitaxy technology, epitaxially grow GaN material with a thickness of 0.2 μm on the upper part of the aperture layer 3 and the barrier layer 4 to fabricate the GaN channel layer 5.

[0129] Step E. Epitaxially grow Al 0.5 Ga 0.5 N to fabricate the barrier layer 6, as shown in Figure 3 e.

[0130] Under the process conditions of a vacuum degree less than or equal to 1.0×10 -10 ​mbar, with a radio frequency power of 400 W, using N2, high-purity Ga source, and high-purity Al source as reactants under the process conditions, and using molecular beam epitaxy technology, Al with a thickness of 200 nm is epitaxially grown on the GaN channel layer 5 0.5 Ga 0.5 N material to form the barrier layer 6.

[0131] Step F. Etch the left and right sides of the channel layer 5 and the barrier layer 6 to fabricate a mesa, as shown in Figure 3 f.

[0132] A mask is fabricated for the second time on the upper part of the barrier layer 6. Using the process conditions of a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 100 W, and using reactive ion etching technology, the left and right sides of the channel layer 5 and the barrier layer 6 are etched using this mask until reaching the upper surface of the blocking layer 4 to form a mesa.

[0133] Step G. Fabricate the source electrode 7, as shown in Figure 3 g.

[0134] A mask is fabricated for the third time on the upper part of the barrier layer 6 and the mesa formed by etching. Using the process conditions of a vacuum degree less than 1.8×10 -3 Pa, a power of 500 W, and an evaporation rate of Metal is deposited on the upper part of the mesa formed by etching using electron beam evaporation technology. The deposited metal is a Ti / Al / Mo / Au metal combination, that is, Ti, Al, Mo, and Au from bottom to top, with thicknesses of 0.02 μm, 0.1 μm, 0.03 μm, and 0.03 μm in sequence; rapid thermal annealing is performed under the process conditions of a temperature of 860 °C and a time of 30 s to complete the fabrication of the source electrode 7.

[0135] Step H. Fabricate the modulation groove 8, as shown in Figure 3 h.

[0136] A mask is fabricated for the fourth time on the upper part of the barrier layer 6 and the source electrode 7. Using this mask, the middle position of the barrier layer 6 is etched to a depth b of 150 nm to form 6 equally spaced modulation grooves 8 in the middle of the barrier layer 6.

[0137] Step I. Fabricate the gate groove 9, as shown in Figure 3 i.

[0138] A mask is fabricated for the fifth time on the upper part of the barrier layer 6, the source electrode 7, and the 6 modulation grooves 8. Using the process conditions of a CF4 flow rate of 45 sccm, an O2 flow rate of 5 sccm, a pressure of 15 mTorr, and a power of 300 W, and using reactive ion etching technology to etch the barrier layer inside the source electrode 7 to form a gate groove 9 with a depth c of 170 nm.

[0139] Step J. Epitaxially grow a P-type GaN semiconductor material on the barrier layer 6, source electrode 7, six modulation slots 8, and gate slot 9, such as Figure 3 j.

[0140] Under the process conditions of a vacuum degree less than or equal to 1.0×10 -10 mbar, a radio frequency power of 400 W, and reactants using N2, high-purity Ga source, and high-purity Mg source, use molecular beam epitaxy technology to epitaxially grow a P-type GaN semiconductor material with a thickness of 0.2 μm on the barrier layer 6, source electrode 7, six modulation slots 8, and gate slot 9, and the doping concentration is 1×10 20 cm -3 .

[0141] Step K. Fabricate a P-type gate 10 and a P-type block 11, such as Figure 3 k.

[0142] Fabricate a mask for the sixth time on the P-type GaN semiconductor material. Under the process conditions of a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 100 W, use reactive ion etching technology to etch the epitaxial P-type GaN semiconductor material to form two left and right P-type gates 10 and six equally spaced and independent P-type blocks 11. The distance d between the two P-type gates 10 and the outermost P-type block 11 is 130 nm.

[0143] Step L. Fabricate a modulation metal block 12, such as Figure 3 l.

[0144] Fabricate a mask for the seventh time on the barrier layer 6, source electrode 7, P-type gate 10, and six P-type blocks 11. Set the vacuum degree to 1.6×10 -3 Pa, the power to 350 W, and the evaporation rate to . Adopt electron beam evaporation technology. Use this mask to deposit metal between the six P-type blocks 11. The deposited metal is Mo, with a thickness of 0.2 μm, to fabricate a Schottky contact.

[0145] Step M. Fabricate a modulation electrode 13, such as Figure 3 m.

[0146] Fabricate a mask for the eighth time on the barrier layer 6, source electrode 7, P-type gate 10, six P-type blocks 11, and five modulation metal blocks 12. Adopt a vacuum degree of 1.6×10 -3 Pa, the power to 400 W, and the evaporation rate to . Use electron beam evaporation technology to deposit metal. Deposit metal on the six P-type blocks 11 and five modulation metal blocks 12. The deposited metal is an Ag / Cu combination, with Ag and Cu from bottom to top, and the thicknesses are 0.15 μm and 0.3 μm respectively, to form a modulation electrode 13.

[0147] Step N. Fabricate the gate 14, as Figure 3 n.

[0148] Fabricate a mask for the ninth time on top of the barrier layer 6, source electrode 7, P-type gate 10, and modulation electrode 13. Under the process conditions of a vacuum degree less than 1.8×10 -3 Pa, a power of 500 W, and an evaporation rate of , use electron beam evaporation technology to deposit metal. Deposit metal on top of the left and right P-type gates 10 to form the gate 14. The deposited metal is a Ta / Ni metal combination, that is, Ta is on the lower layer and Ni is on the upper layer, with a thickness of 0.25 μm / 0.38 μm.

[0149] Step O. Fabricate the drain 15, as Figure 3 o.

[0150] Under the process conditions of a vacuum degree of 1.8×10 -3 Pa, a power of 500 W, and an evaporation rate of , use electron beam evaporation technology to deposit a Ti / Al / Ni / Au metal combination on the lower part of the entire n + -type GaN substrate 1, that is, Ti, Al, Ni, and Au from bottom to top, with thicknesses of 0.02 μm, 0.17 μm, 0.055 μm, and 0.045 μm in sequence, to form the drain 15 and complete the fabrication of the entire device.

[0151] The effects of the present invention can be further illustrated by the following simulation results.

[0152] Simulation 1: Respectively perform forward conduction output characteristic simulations on the traditional vertical power device and the device of Embodiment 2 of the present invention. The results are as Figure 4 shown. The results show that the forward conduction characteristic of the device of the present invention is basically unchanged compared with the traditional device, and still maintains a large output current.

[0153] Simulation 2: Respectively perform reverse conduction output characteristic simulations on the traditional vertical power device and the device of Embodiment 2 of the present invention. The results are as Figure 5 shown. The results show that during reverse conduction, the reverse turn-on voltage of the traditional device is 3.5 V, and the reverse turn-on voltage of the device of the present invention is 1.3 V. It can be seen that the reverse turn-on voltage of the device of the present invention is greatly reduced.

[0154] Simulation 3: Perform breakdown characteristic simulations on the traditional vertical power device and the device of Embodiment 2 of the present invention. The results are as Figure 6 shown. The results show that the breakdown voltage of the device of the present invention is about 1700 V, and the breakdown voltage of the traditional device is about 1500 V. The device of the present invention has better voltage withstand ability.

Claims

1. A low-resistance reverse-conducting vertical power device, comprising, from bottom to top: Drain (15), gallium nitride homogeneous substrate (1), drift layer (2), aperture layer (3), channel layer (5), barrier layer (6). Two symmetric blocking layers (4) are provided on both sides of the aperture layer (3). Source electrodes (7) are provided on the left and right sides of the channel layer (5) and the barrier layer (6). It is characterized in that: At the central position inside the barrier layer (6), n modulation slots (8) are arranged at equal intervals. Above each modulation slot, n P-type blocks (11) are provided. Modulation metal blocks (12) are provided between these P-type blocks, and a total of n - 1 modulation metal blocks are provided; Above the n P-type blocks (11) and the n - 1 modulation metal blocks (12), a modulation electrode (13) is provided; On the inner sides of the two source electrodes (7), two left and right gate slots (9) are distributed. The lower part of the gate slot is located in the barrier layer (6). Above the gate slot (9), a P-type gate (10) is provided. Gate electrodes (14) are deposited on the upper parts of these two P-type gates; The barrier layer (6) and the n - 1 modulation metal blocks (12) form an embedded Schottky diode, that is, the modulation metal block (12) is the anode and the barrier layer (6) is the cathode, so as to realize the current path from the modulation electrode (13) to the drain (15).

2. The device according to claim 1, wherein: For the current path of the embedded Schottky diode, when the depletion region of the P-type gate (10) blocks the two-dimensional electron gas channel below, a potential difference is formed between the modulation metal block (12) and the barrier layer (6), that is, the potential of the modulation metal block is greater than the potential of the barrier layer. When the potential difference reaches the turn-on voltage of the embedded Schottky diode, the embedded Schottky diode conducts forward, and the current flows from the modulation metal block (12) to the drain (15).

3. The device according to claim 1, characterized in that: The thickness a of the barrier layer (6) is 10 - 200 nm; The depth b of the n modulation slots (8) is 5 - 150 nm; The depth c of the two gate slots (9) is 8 - 170 nm.

4. The device according to claim 1, characterized in that, The distances d between the left and right P-type gates (10) and the outermost P-type block (11) are equal, and d > 0.

5. The device according to claim 1, wherein The metal of the bottom layer of the modulation electrode (13) is selected as the metal with a work function close to that of the P-type block (11), so as to form a good ohmic contact between the modulation electrode (13) and the P-type block (11).

6. The device according to claim 1, characterized in that, The modulation electrode (13) is electrically connected to the source electrode (7).

7. A manufacturing method of a low-resistance reverse-conducting vertical power device, comprising the following steps: A) Epitaxially grow an n-type GaN semiconductor material on a gallium nitride substrate (1) to form a drift layer (2); - ​ B) Epitaxially grow an n-type GaN semiconductor material on the drift layer (2) to form an aperture layer (3) with a doping concentration of 1×10 15 ~5×10 18 cm -3 ; C) A mask is fabricated on the aperture layer (3) for the first time. Using this mask, p-type impurities are implanted on both sides of the aperture layer (3) to form two symmetric blocking layers (4); D) GaN semiconductor material is epitaxially grown on the aperture layer (3) and the upper parts of the left and right blocking layers (4) to form a channel layer (5) with a thickness of 0.04 - 0.2 μm; E) GaN-based wide-bandgap semiconductor material is epitaxially grown on the upper part of the channel layer (5) to form a barrier layer (6) with a thickness a of 10 - 200 nm; F) A mask is fabricated for the second time on the upper part of the barrier layer (6). Using this mask, etching is performed on the left and right sides of the channel layer (5) and the barrier layer (6) until reaching the upper surface of the blocking layer (4) to form a mesa; G) A mask is fabricated for the third time on the upper part of the barrier layer (6) and the mesa formed by etching. Using this mask, metal is deposited and rapid thermal annealing is carried out to complete the fabrication of the source electrode (7); H) A mask is fabricated for the fourth time on the upper part of the barrier layer (6) and the source electrode (7). Using this mask, the middle position of the barrier layer (6) is etched to form n equally spaced modulation grooves (8) with a depth b of 5 - 150 nm; I) A mask is fabricated for the fifth time on the upper part of the barrier layer (6), the source electrode (7) and the n modulation grooves (8). Using this mask, etching is performed inside the two source electrodes (7) to form gate grooves (9) with a depth c of 8 - 170 nm; J) The upper epitaxial doping concentration of the barrier layer (6), source electrode (7), n modulation slots (8) and gate slot (9) is a P-type GaN semiconductor material with a concentration of 5×10 15 ~1×10 20 cm -3 ; K) A mask is fabricated for the sixth time on the upper part of the barrier layer (6), the source electrode (7), the n modulation grooves (8) and the gate grooves (9). Using this mask, the epitaxial P - type GaN semiconductor material is etched to form two left and right P - type gates (10) and n equally spaced and independent P - type blocks (11). The distance d between the two left and right P - type gates (10) and the outermost P - type block (11) is d > 0; L) A mask is fabricated for the seventh time on the upper part of the barrier layer (6), the source electrode (7), the P - type gates (10) and the n P - type blocks (11). Using this mask, metal is deposited between the gaps of the n P - type blocks (11) to form n - 1 modulation metal blocks (12); M) A mask is fabricated for the eighth time on the upper part of the barrier layer (6), the source electrode (7), the P - type gates (10), the n P - type blocks (11) and the n - 1 modulation metal blocks (12). Using this mask, metal is deposited on the upper part of the n P - type blocks (11) and the n - 1 modulation metal blocks (12) to form a modulation electrode (13); N) A mask is fabricated for the ninth time on the upper part of the barrier layer (6), the source electrode (7), the P - type gates (10) and the modulation electrode (13). Using this mask, metal is deposited on the upper part of the two left and right P - type gates (10) to form gate electrodes (14); O) Metal is deposited on the back surface of the substrate (1) to form a drain electrode (15), completing the fabrication of the entire device.

8. The method according to claim 7, wherein: The epitaxial techniques used in steps A), B), D), E), and J) include: metalorganic chemical vapor deposition method, hydride vapor phase epitaxy method, molecular beam epitaxy method.

9. The method according to claim 7, wherein: The metal deposition processes used in steps G), L), M), N), and O) include: electron beam evaporation process, sputtering process.

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