Control circuits, corresponding electronic converter devices and methods

Abstract

Embodiments of the present disclosure relate to control circuits, corresponding electronic converter devices, and methods. The control circuit operates to control a switching stage of an electronic converter. The control circuit includes: a first terminal for providing a drive signal to an electronic switch of the switching stage; a second terminal for receiving a first feedback signal proportional to the converter output voltage from a feedback circuit; and a third terminal configured to receive a second feedback signal proportional to the inductor current from a current sensor. The driver circuit provides a drive signal based on a PWM signal generated by a generator circuit, the PWM signal being based on first and second feedback signals, a reference voltage, and a slope compensation signal. The mode selection signal is generated based on a comparison between an input voltage and an output voltage. The feedforward compensation circuit is configured to provide and / or absorb a compensation current based on a change in the mode selection signal.

Description

[0001] Priority claim

[0002] This application claims the priority of Italian Patent Application No. 102021000003368, filed on February 15, 2021, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The description relates to DC-DC converters, and in particular to non-isolated converters, such as boost converters.

[0004] One or more embodiments may be applied to power AMOLED technology devices. Background Art

[0005] Power supply circuits such as AC / DC or DC / DC switching mode power supply circuits are well known in the art. There are many types of electronic converters, which are mainly divided into isolated and non-isolated converters. For example, non-isolated electronic converters are "buck", "boost", "buck-boost", "SEPIC" and "ZETA" type converters. In contrast, isolated converters are, for example, "flyback", "forward", "half-bridge" and "full-bridge" type converters. Converters of this type are well known to those skilled in the art, as evidenced by application AN513 / 0393 "Topologies for Switched Mode Power Supplies", L. Wuidart, 1999, STMicroelectronics (incorporated herein by reference).

[0006] DC-DC converters, especially boost converters, can be used in various applications. Depending on the application, in order to provide sufficient efficiency and performance levels, the converter circuit needs to work in different modes (e.g., continuous conduction mode (CCM), discontinuous conduction mode (DCM), asynchronous mode, synchronous mode, etc.) and operate reliably in different scenarios. In such a case, the design of the DC-DC converter is quite complex.

[0007] For example, a DC-DC converter may be used to provide a voltage level to an AMOLED display by converting a battery-fed voltage level VIN (eg, between 2.3-5 Volts) to a (positive) output regulated level VOUT (eg, about 4.6 Volts).

[0008] In such an application scenario, any ripple / transient on the (positive) regulated power supply will directly affect the display performance, for example, causing the display to flicker. This will make the output regulated voltage as flat and smooth as possible. To this end, existing solutions may envisage the use of a buck-boost converter. Disadvantages of this existing solution may include, for example: increased circuit complexity relative to a boost converter; increased complexity, for example due to the use of more power switches than a boost converter; increased silicon area occupancy and cost; and increased leakage current and quiescent current consumption of the power transistors used.

[0009] There is a need in the art for contributions that help overcome the above-mentioned shortcomings. Summary of the invention

[0010] One or more embodiments may be directed to a method.

[0011] A control circuit for controlling a switching stage of an electronic converter may be an example of such a method. For example, the control circuit may be an integrated circuit.

[0012] One or more embodiments may be directed to a corresponding device.A boost electronic converter may be an example of such a device.

[0013] One or more embodiments may relate to a corresponding method of controlling a switching stage of an electronic converter.

[0014] One or more embodiments may facilitate compensation transitions in a closed-loop DC-DC converter, such as compensation transitions from synchronous mode to asynchronous mode and vice versa.

[0015] One or more embodiments may facilitate increasing or improving the performance of a DC-DC converter.

[0016] One or more embodiments may improve the ability to adequately compensate for any transitions between synchronous / asynchronous modes while neglecting the impact on output levels.

[0017] One or more embodiments may have a smaller footprint in terms of area and current consumption, with minimal control logic to achieve improved operation.

[0018] Due to the feed-forward action, one or more embodiments may advantageously maintain the DC-DC open loop characteristic while shifting the operating point of the loop.

[0019] In one or more embodiments, DC gain as well as loop bandwidth and phase margin may be improved, particularly in asynchronous mode.

[0020] One or more embodiments may help provide a faster and more reactive DC-DC loop.

[0021] One or more embodiments may help push the second pole of the transfer function of the converter circuit at a higher frequency range relative to prior art designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0023] Figure 1 An example of a boost type electronic converter is shown;

[0024] Figure 2 Shows Figure 1 An exemplary timing diagram of signals of an electronic converter;

[0025] Figure 3 Shows Figure 1 An embodiment of a first part of a converter;

[0026] Figure 4 Shows Figure 1 An embodiment of a second part of the converter; and

[0027] Figure 5 and Figure 6 Shows Figure 4 An alternative embodiment of a circuit portion of . DETAILED DESCRIPTION

[0028] In the following description, one or more specific details are illustrated to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments can be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that some aspects of the embodiments will not be obscured.

[0029] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0030] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0031] In all the drawings attached herein, the same parts or elements are denoted by the same reference numerals / numbers, and the corresponding description will not be repeated for the sake of brevity.

[0032] The reference signs used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0033] For simplicity, this document may use the same names to designate certain circuit nodes and the signals that appear at those nodes.

[0034] Figure 1 is a circuit diagram of a step-up DC-DC converter circuit 10 configured to provide a power supply voltage level to a load such as an AMOLED display. Figure 1 As illustrated in FIG. 1 , the circuit 10 includes a control circuit 20 configured to operate the boost converter 10 , for example, using a peak current control scheme.

[0035] like Figure 1 As shown, the circuit 10 includes two input terminals 100a and 100b for receiving a DC input voltage V IN (e.g., provided by a battery), and two output terminals 102a and 102b for providing a regulated output voltage V OUT (For example, to load Z L supply).

[0036] Specifically, the boost converter 10 includes two electronic switches S1 and S2 (and their current paths) connected in series (e.g., directly) between the output terminal 102a and the input terminal 100b, wherein an intermediate node S2 between the electronic switch S1 and the electronic switch S2 represents a switching node Lx. Specifically, the electronic switch S2 is a high-side switch connected (e.g., directly) between the (positive) terminal 102a and the switching node Lx, and the electronic switch S1 is a low-side switch connected (e.g., directly) between the switching node Lx and the (negative) terminal 100b, which generally represents ground GND. The (high-side) switch S2 and the (low-side) switch S1 thus represent a device configured to connect the switching node Lx to the terminal 102a (voltage V OUT ) or half bridge of terminal 100b (ground GND).

[0037] For example, switches S1 and / or S2 are typically transistors, such as field effect transistors (FETs), such as metal oxide semiconductor field effect transistors (MOSFETs), for example n-channel FETs, such as NMOS, or p-channel FETs, such as PMOS. Typically, the second electronic switch S2 is also implemented using only a diode, wherein the cathode is connected to the terminal 102a, and the anode is connected to the switching node Lx.

[0038] In the example considered, an inductor L such as an inductor is connected (eg directly) between the switching node Lx and the (positive) input terminal 100a, while the (negative) input terminal 100b is connected (eg directly) to the (negative) output terminal 102b.

[0039] In the example considered, in order to stabilize the output voltage V OUT , the converter 10 includes a capacitor C connected (eg, directly) between the output terminals 102a and 102b. OUT .

[0040] like Figure 1 As shown, the converter circuit 10 is coupled to a control circuit 20 configured to drive switches S1 and S2. Specifically, the control circuit 20 is configured to provide a first control signal DRV1 for switching the first electronic switch S1 and a second control signal DRV2 for switching the second electronic switch S2. According to receiving corresponding control signals from the control circuit 22, the switches S1 and S2 are controlled to switch from a first (e.g., open) state to a second (e.g., closed) state.

[0041] Such a controlled switch helps to control the voltage level Vx at the switching node Lx (ie, the voltage at the first switch S1) and the current I flowing through the inductor L. L .

[0042] like Figure 2 As shown, the switching cycle may start at the falling edge of the clock signal CK, wherein the first switch S1 is switched on at T ON Phase is in the on state.

[0043] Specifically, Figure 2 As shown:

[0044] At the first time t1, the electronic switch S1 is closed (on state) and the electronic switch S2 is opened at the same time, so that the current I in the inductor L L (Basically) linear increase.

[0045] At a time interval T from the first moment t1 ON At the second moment t2, the electronic switch S1 is opened, and the electronic switch S2 is closed (off state), so that the current I L (substantially) linear decrease; and

[0046] At a time interval T between the second time instant t2 OFF At the third instant t3 , the switch S2 (or a similar diode) is therefore closed when the switch S1 is open, and vice versa.

[0047] Current I L Therefore, it can be used to OUT Charging, capacitor C OUT A voltage V is provided at output terminals 102a and 102b. OUT .

[0048] like Figure 1As shown, the control circuit 22 is configured to apply a peak current using a fixed slope compensation ramp control scheme to drive the switching of the switch S1 and possibly the switch S2 for a so-called constant period T CK =T ON +T OFF The switching cycle and the reference clock signal CK synchronization (see Figure 2 ), repeated periodically at intervals of T ON and T OFF , but its duty cycle δ=T ON / T CK Can vary.

[0049] Current mode control is a multi-loop control method in which the inductor current is directly controlled.

[0050] For example, the converter circuit 10 includes:

[0051] The first feedback circuit 12 (such as a voltage divider) is configured to generate a feedback signal FB, the feedback signal FB indicating the output voltage V OUT (and preferably in proportion thereto), and

[0052] A second feedback circuit 14 (such as a current sensing resistor in series with the first switch S1, or any other current sensor arrangement) is used to “read” the coil current I L and obtains a measurement signal in a manner known per se, the measurement signal indicating that at the interval T on During this period, the current flowing in the coil L; the second feedback circuit 14 thus generates a measurement signal CS, which indicates that during the interval T ON During this period, the current I flowing through the inductor L L (and preferably in proportion thereto).

[0053] In one or more embodiments, the measurement signal CS may be a pulsed or averaged current value.

[0054] like Figure 1 As shown, the control circuit 20 is coupled to the first feedback circuit 12 and receives the feedback signal FB, and is coupled to the second feedback circuit 14 and receives the measurement signal CS.

[0055] In the example considered, the control circuit 20 comprises:

[0056] The error amplifier circuit 22, such as an operational amplifier, is configured to perform a comparison between the feedback signal FB and a reference signal (such as a reference voltage V REF ) to generate a control signal V C As a comparison result;

[0057] The summing circuit 24 is configured to add the compensation signal K to the measurement signal CS, thereby generating a sum signal VSUM as a result of the addition; for example, the compensation signal K may be a sawtooth ramp, which is retained to stabilize the current loop feedback, thereby improving the noise immunity;

[0058] The main comparator circuit 26 is coupled to the error amplifier circuit 22 and the summing circuit 24 and is configured to C and performing a comparison between the sum signal VSUM received therefrom, thereby providing a (digital) modulated signal VM as a comparison result, and

[0059] The driver circuit 28 is configured to generate one or more drive signals DRV1, DRV2 according to the pulse width modulation (PWM) signal VM, wherein the driver circuit 28 is configured to change the operation mode of the converter 10 according to the control signal VM. For example, in various embodiments, as described below, the driver circuit 28 is configured to selectively operate the switching stages S1, S2 in a synchronous or asynchronous mode according to the control signal OP.

[0060] According to the control scheme considered in this example, the control circuit 20 can be configured to drive the converter 10 such that:

[0061] At a first time interval t1, the first switch S1 is closed (on state) until the modulation signal VM obtained according to the comparison performed by the main comparator 26 triggers the drive signals DRV1, DRV2 to change the states S1, S2 of the switches, thereby determining the Ton duration of the first phase; and

[0062] At a second time interval t2 separated from the first moment t1 by a duration Ton, the first switch S1 is opened (off state) and the second switch S2 is closed (on state) until the subsequent falling edge of the clock signal CK (i.e. until a new switching cycle starts); this determines the duration Toff of the second phase.

[0063] The main comparator circuit 26, while performing a comparison between the signal VSUM and the level of the control signal VC generated by the error amplifier 22 over time, outputs a modulation signal VM having a first binary value (e.g., 1) if the sum signal VSUM reaches the level of the control signal VC, or outputs a modulation signal VM having a second binary value (e.g., zero) if the sum signal VSUM fails to reach the level of the control signal VC.

[0064] As mentioned, the compensation signal K helps to overcome limitations due to limiting cycles and subharmonic oscillations of the DC-DC converter, for example, by pushing the poles of the transfer function of the converter to a higher frequency range than the frequency range in use. For example, the second pole of such a transfer function is "pulled back" in frequency according to the slope of the compensation signal K, i.e., a sawtooth signal with a larger (i.e., higher amplitude). Preferably, the compensation signal K is used for duty cycles above 50%.

[0065] Figure 1 The arrangement illustrated in FIG. 1 may be such that its input nodes 100 a, 100 b are coupled to a battery, for example, to provide a voltage V IN =(2.3÷5) Volts, and at least one of its output nodes 102a, 102b (e.g. output node 102a) is coupled to the AMOLED display to provide a (positive) voltage supply thereto. For example, at the same time the other output node 102b may be grounded and not directly coupled to the AMOLED panel.

[0066] In such an exemplary application scenario, the converter circuit 10 may be operated as follows:

[0067] In V IN <V OUT In the first “synchronous” mode, the control circuit 20 drives the transistors S1 and S2 to turn on / off via the drive signals DRV1 and DRV2; and

[0068] In V IN ≥V OUT In the second “asynchronous” or “diode” mode, the control circuit 20 drives the first transistor S1 on / off via the drive signal DRV1, while the second transistor S2 acts as a diode, using its body diode conduction.

[0069] Note that diode mode operation helps maintain voltage regulation with a boost DC-DC, especially for output voltages close to V OUT The input voltage V IN The maximum sustainable deviation is related to the body diode voltage drop across the second transistor S2.

[0070] Conventional solutions have difficulty in providing smooth transitions between operating modes, i.e., without noticeable transient disturbances to the regulated output voltage VOUT. Such transients may alter the overall performance.

[0071] The inventors have observed that in order to combat the DC-DC frequency response, it may be useful to detect a threshold for a mode operation change in a substantially automatic manner.

[0072] For example, as input V IN and output V OUTAs a result of the comparison between the voltage levels, the control circuit 20 provides a (eg dedicated) "mode" control signal OP to select one of the first and second operating modes. This may involve a relatively simple circuit implementation, such as Figure 1 The comparator circuit block 28a within the control logic 20 illustrated in FIG. 1 is coupled to the corresponding input / output nodes 100a, 102a and is configured to IN Higher than V OUT , the mode operation signal OP is triggered (possibly with some assumption of increasing the operating margin, for example), and vice versa.

[0073] The inventors have further observed that increasing the DC-DC duty cycle δ helps to counteract any transients in the output voltage when switching from synchronous mode to diode mode.

[0074] For example, the duty cycle δ can be (approximately) expressed as:

[0075]

[0076] Where: V OUT is the output voltage, V IN is the input voltage, I L is the current in the inductor L, DCRL is the DC equivalent series resistance of the coil L, i.e. the equivalent resistance of the inherent parasitic resistance of the inductor L as provided, for example, by the manufacturer of the electronic component, is the (on-state) resistance of the first transistor S1, and is the resistance of the second transistor S2 at least during the synchronous mode of operation.

[0077] Note that during diode mode operation, due to the conduction in the body diode of the second transistor S2, its forward voltage increases with the current I in the inductor L. L The behavior can be modeled as the resistance of the second transistor S2. Much higher than the resistance of the first resistor S1, e.g.

[0078] As reference Figure 1 As discussed, the DC-DC converter 10 may be modeled as a closed-loop system with a certain (eg, finite) loop bandwidth that is less able to quickly compensate for sudden changes, such as a sudden change in synchronous to diode mode transition.

[0079] One or more embodiments may perform a feed-forward action to increase the duty cycle δ, ie, increase the on-state duration Ton at the expense of the off-state duration Toff. For example, this may alternatively involve providing a positive step on the control signal VC, or a negative step on the sum signal VSUM.

[0080] In one or more embodiments, feed-forward actions including dedicated "out-of-loop" compensation actions can be used to overcome this bandwidth limitation. Since these feed-forward actions can be performed outside the DC-DC main loop, they can be designed to be very fast and quickly compensate for specific events, making the main loop "blind" to such input events.

[0081] Figure 3 A possible implementation of applying feed-forward compensation to the control signal VC is shown, when the converter 10 performs synchronous to diode mode conversion, a positive step signal (ie, offset) is added to the output node of the error amplifier 22. For example, the error amplifier 22 may include:

[0082] an operational amplifier 220 , such as an operational transconductance amplifier (OTA);

[0083] an RC compensation network, coupled to an output node of the OTA 220 , configured to provide loop stability for the DC-DC converter 10 ;

[0084] an optional buffer stage 222, e.g., a source follower, coupled to the output node of the OTA; and

[0085] The current generator 224 and a resistor stage R between the OTA output node and the generator are configured to provide a specific current across the resistor R. The optional buffer stage 222 is particularly suitable for use when the error amplifier 22 includes a single OTA stage (such as Figure 3 In this case, buffer 222 is used to decouple resistor R from the OTA output node.

[0086] For simplicity, in the following, the effect of feed-forward compensation is mainly discussed for the transition from synchronous mode to diode mode, otherwise it should be understood that vice versa, one or more embodiments are applicable to diode to synchronous mode transition.

[0087] In one or more embodiments:

[0088] When the converter circuit 10 operates in the synchronous mode, the current generator IDMFF is turned off and the control signal V C Equal to the buffer input voltage V BUFF , since there is no voltage drop across R; and

[0089] When the converter circuit operates in diode mode, the current generator I DMFF In the switching period T CK Initially, for example, via the “mode” control signal OP is enabled, thereby adding a substantially step-shaped positive offset (which can be represented as a resistance R multiplied by the current therethrough) to the control signal V C , that is, VC =V BUFF +I DMFF R. As a result, the on-state duration Ton increases in exactly the same switching cycle.

[0090] like Figure 3 and Figure 4 One or more of the embodiments illustrated in can advantageously shift the operating point of the feedback loop of the converter 10 with negligible impact on the DC-DC open loop characteristics.

[0091] Figure 4 Possible alternative implementations of the embodiments are shown. Figure 4 As shown, a current generator IDMFF is present at a summing circuit 24 configured to provide a sum signal VSUM.

[0092] like Figure 4 As shown, the summing circuit 24 may include:

[0093] The operational amplifier 240 is configured to receive the compensation signal K at a first non-inverting input node and has a feedback loop between an output node and a second, for example, inverting input node, the feedback loop including a resistor R1 and a transistor MB; specifically, the operational amplifier 240 is configured as a voltage-current buffer;

[0094] Current mirrors M0, M1, coupled to the output of operational amplifier 240 and to the AND circuit 24; and

[0095] The switch SW is configured to selectively couple the switching node Lx to the adder resistor R according to the driving signal DRV1 during the time interval Ton.

[0096] like Figure 4 As shown, the fixed sawtooth voltage signal K is buffered, current-converted and mirrored to be superimposed on the signal containing the coil current information with the aid of resistor R. For example, in Figure 4 In the arrangement shown, the compensation signal K is converted into a current flowing through the adder resistor R, resulting in a voltage drop K*R across it. This is added or "offset" during the time interval Ton via the switch SW driven by the signal DRV1, and the voltage drop across Lx is also applied to the adder resistor R. Therefore, the sum signal V SUM is the voltage at the adder resistor R, which is the sum of the value on the switching node Lx and the contribution of the signal proportional to the compensation signal K.

[0097] For simplicity, an exemplary scenario in which the current mirrors M0 and M1 have a single mirror factor is considered below. Otherwise, it should be understood that such a scenario is merely exemplary and not restrictive.

[0098] For example, in the synchronous mode, when the first transistor S1 is in the on state, that is, during the Ton phase, the switching node Lx is coupled to the resistor R. Therefore, the sum signal V SUM can be expressed as:

[0099]

[0100] like Figure 4 As shown, the summing circuit 24 further includes a current generator 23, which is selectively coupled to the summing circuit 24 via a switch SD, the switch SD being driven by a (e.g., dedicated) “mode” control signal OP from the control circuit 20, and the current generator 23 being configured to sink a certain current I from the summing resistor R DMFF For example, when the mode control signal OP switches from "synchronous" to "diode mode", the switch SD is turned on, thereby coupling the current generator 23 to the summing circuit 24. When the converter enters the asynchronous mode, this results in a SUM Apply a negative step offset. For example, the sum signal V in diode mode operation SUM can be expressed as:

[0101]

[0102] In such Figure 3 and Figure 4 In one or more embodiments illustrated in FIG. 1 , the current I supplied / absorbed by the generator 23 is DMFF Both R and the adder resistor R can be selected or tuned to provide the best performance according to the application scenario. For example, the tuning can be achieved through simulation and dedicated trimming.

[0103] In one or more embodiments, an alternative method of increasing the duty cycle to compensate for the transition between circuit operating modes may include reducing the slope of the sawtooth signal K used to perform slope compensation of the sum signal VSUM. This may advantageously increase system bandwidth and gain (e.g., as may be understood via loop AC and stability analysis / modeling).

[0104] Figure 5 and Figure 6 A possible implementation of an adder circuit 24 is shown, which is configured to increase the duty cycle and compensate for transitions between circuit operating modes. This may involve reducing the slope of the sawtooth signal K used to perform slope compensation of the sum signal VSUM.

[0105] These implementations can operate on the slope variation of the sawtooth signal K and may be particularly suitable for scenarios where the duty cycle δ in the diode mode is estimated to be much lower than 25% (due to VIN ≥ VOUT), ie, when the influence of the slope compensation signal K is small.

[0106] like Figure 5 As shown, the current mirror M0, M1 may include a further transistor M2 which may be selectively coupled via a switch SD: as a further transistor of the current mirror arrangement M0, M1 or in parallel with the mirror arrangement M0, M1.

[0107] For simplicity, the current mirrors M0, M1, M2 having p-channel transistors are discussed below, but it should be understood that one or more embodiments may include n-channel or other types of transistors.

[0108] For example, when transistor M2 is coupled to a current mirror arrangement M0, M1, the following expressions may apply:

[0109]

[0110] Wherein: W is the channel width of the transistor, L is the channel length of the transistor, and the subscript outside the brackets indicates the corresponding transistor M0, M1, M2 referred to by the WL ratio.

[0111] like Figure 5 As shown:

[0112] During synchronous mode operation, switch S D can be in a first state, for example an off state, so that transistor M2 forms part of a current mirror arrangement M0, M1, M2; therefore, the sum signal V SUM can be expressed as

[0113]

[0114] When the converter switches to asynchronous mode, the mode signal OP switches S D The transistor M2 is switched to the on state, thereby disconnecting the transistor M2 from the current mirror arrangement M0, M1 and from the mirror output branch, thereby reducing the (P-channel) current mirror M0, M1 at the node V SUM The mirror factor of the converted current sawtooth signal K is provided at ; this is equivalent to reducing the slope of the sawtooth signal, because the sum signal can be expressed as:

[0115]

[0116] Note that the image factor in diode mode can be smaller than the mirror factor in synchronous mode, regardless of its magnitude (e.g., greater than or equal to unity); this ratio indicates a reduction in slope compensation and, therefore, feed-forward strength.

[0117] like Figure 5 As shown, the mirror factor The exact value of can be selected and tuned to obtain the desired circuit performance (eg, either in simulation or in dedicated trimming).

[0118] Figure 6 yes Figure 4 An example of another alternative implementation of the solution of is by reducing the signal V SUM The slope of the slope-compensated sawtooth signal K is used to increase the duty cycle to compensate for the transition between circuit operation modes.

[0119] like Figure 6 As shown, the summing circuit 24 includes a resistor R connected in parallel with a sensing resistor R FF (e.g., resistor), resistance R FF selectively coupled to the signal node V SUM Between the switching node Lx.

[0120] For simplicity, in the following, the resistor R of the summing circuit 24 is FF is considered to have a value equal to the summing resistor R, otherwise it should be understood that the resistance R of the summing circuit 24 FF Such values ​​are purely exemplary and not limiting.

[0121] like Figure 6 As shown:

[0122] During synchronous mode operation, switch S D can be in a first state, such as an off state, so that the resistor R FF decoupled from the switching node Lx and making the sum signal V SUM can be expressed as

[0123]

[0124] When the converter switches to asynchronous mode, the mode signal OP switches the switch SD into the on state, thereby coupling the resistor RFF between the node VSUM and the switching node Lx, in parallel with the summing resistor R. This is equivalent to reducing the slope of the sawtooth signal, because the sum signal can be expressed as:

[0125]

[0126] Note that the resistor R FF The value of can be set and tuned (e.g., in simulation and dedicated tuning) to obtain the desired circuit performance.

[0127] Figure 6 Another alternative embodiment of the solution may involve factoring the added resistance R in a series of different electrical components coupled between them, and changing the slope of the sawtooth signal by selectively short-circuiting some of such series electrical components.

[0128] Figure 5 and Figure 6 One or more of the embodiments illustrated in the can both move the operating point of the converter's feedback loop and change the DC-DC open loop characteristics by reducing the slope compensation. This can support further compensation for the transition from synchronous mode to asynchronous mode (i.e., the DC-DC loop is faster and more responsive due to increased gain and bandwidth). At the same time, the gain margin may be reduced and high frequency sensitivity (i.e., jitter) may be higher. If the system has available gain margin, this situation can be well tolerated.

[0129] Note that while a simple comparator can signal a change in mode operation, this may occur in an asynchronous manner relative to the switching cycle. One or more embodiments contemplate resynchronizing the threshold detection and mode operation change with the start of a new switching cycle, i.e., with the moment when feed-forward compensation occurs. This involves:

[0130] Feedforward compensation is applied synchronously at the beginning of Ton, so that the control signal V C (like Figure 3 as shown) or signal V SUM (like Figures 4 to 6 shown) gradually changes; and

[0131] Assuming that the converter circuit 10 is in a stable state before changing the operating mode, changing the switching point or time at which the PWM comparator is triggered relative to the previous switching cycle (when the converter is operating in synchronous mode) will increase the switching time due to the higher control signal V C (like Figure 3 shown) or with a lower sum signal V SUM (like Figures 4 to 6 As shown), it is expanded by Ton relative to the previous cycle.

[0132] Thus, the proposed solution allows feed-forward control to overcome specific phenomena / events maintaining high performance. The proposed solution has a negligible impact on power consumption since it only involves generating an appropriate current, which is supplied to (or sunk from) the control signal node V C or and node V SUM .

[0133] In terms of system complexity and area consumption, the difference is negligible compared to an implementation without the proposed feedforward compensation, and the advantages overcome this added minor complexity. Finally, a simplified logic 28 can be used to trigger the feedforward of the OP in response to the compensation phenomenon, and the current mirrors M0, M1 can be used to create the appropriate feedforward current I DMFF .

[0134] In general, the proposed feedforward implementation allows multiple feedforwards to work regardless of other feedforwards (ie, the presence of a particular feedforward does not exclude / impair the effect of another feedforward), for example, because multiple feedforward currents can be added therebetween.

[0135] As mentioned above, in various embodiments, the control circuit 20 may also be integrated in an integrated circuit. In this case, the integrated circuit may include:

[0136] - a terminal for connection to a feedback circuit 12, which may also be integrated in the same integrated circuit;

[0137] - terminals for connection to a current sensor 14 , which may also be integrated in the same integrated circuit;

[0138] one or more terminals for providing one or more corresponding drive signals DRV1, DRV2 to a switching stage of the electronic converter 10, wherein one or more of the switches S1, S2 of the switching stage may also be integrated in an integrated circuit;

[0139] a driver circuit 28 configured to generate one or more drive signals in dependence on the PWM signal VM, wherein the driver circuit 28 is configured to change the operation mode in dependence on a comparison between input and output voltages via a mode selection signal OP; and

[0140] - A PWM signal generator circuit 22, 24, 26, configured to generate a PWM signal VM, wherein the PWM signal generator circuit 22, 24, 26 comprises at least one current mirror M0, M1, wherein the corresponding current I DMFF Changes (almost instantaneously) according to the mode selection signal OP.

[0141] It will be further understood that the various individual implementation options illustrated in the accompanying drawings of this description are not necessarily intended to be employed in the same combination illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the drawings.

[0142] The claims are an integral part of the technical teaching provided herein with reference to the embodiments.

[0143] Without prejudice to the underlying principle, the details and embodiments may vary, even significantly, with respect to what is described merely by way of example, without departing from the scope of protection, which is defined by the appended claims.

Claims

1. A control circuit configured to control a switching stage of an electronic converter, the electronic converter comprising an inductor and operative to receive an input voltage at an input terminal and to provide an output voltage at an output terminal, the control circuit comprising: one or more first terminals configured to provide one or more corresponding drive signals to one or more electronic switches of the switching stage; a second terminal configured to receive a first feedback signal proportional to the output voltage from a feedback circuit; a third terminal configured to receive a second feedback signal proportional to the current in the inductor from a current sensor; A driver circuit configured to provide: One or more drive signals, wherein the one or more drive signals are pulse width modulated (PWM) signals; as well as a mode select signal asserted in response to a comparison of the input voltage and the output voltage, the mode select signal indicating a change in an operating mode of the electronic converter; as well as A PWM signal generator circuit is configured to generate the PWM signal according to the first feedback signal, the second feedback signal, a reference voltage and a slope compensation signal, the PWM signal generator circuit comprising: a first amplifier circuit configured to provide a first control signal according to a difference between the reference voltage and the first feedback signal; a summing circuit configured to provide a second control signal indicating a superposition of the slope compensation signal and the second feedback signal; and a comparator circuit configured to compare the first control signal with the second control signal and generate the PWM signal; and A feed-forward compensation circuit is configured to provide a compensation current in response to the assertion of the mode selection signal, wherein the compensation current is at least one of the following: provided to modulate the first control signal output from the first amplifier circuit, or absorbed to modulate the second control signal output from the summing circuit. 2 . The control circuit of claim 1 , wherein assertion of the mode select signal indicates that the electronic converter is changing from a synchronous operating mode to a diode operating mode.

3. The control circuit of claim 1 , wherein the feed-forward compensation circuit comprises a current generator and a series resistor coupled to the output of the first amplifier circuit, wherein in response to assertion of the mode select signal, the current generator is enabled to provide the compensation current to the series resistor.

4. The control circuit according to claim 1, wherein the summing circuit comprises: a second amplifier circuit having a resistive feedback branch and configured to receive the slope compensation signal; a current mirror coupled to the output of the second amplifier circuit; as well as A summing node is coupled to the output of the current mirror and selectively coupled to the third terminal of the control circuit via another switch, the another switch being configured to be driven by the one or more drive signals.

5. The control circuit of claim 4, wherein the feed-forward compensation circuit comprises a current generator selectively coupled to the summing node of the summing circuit via a first switch controlled by the mode selection signal to sink current therefrom.

6. The control circuit of claim 4, wherein the current mirror comprises a current mirror branch that is selectively activated via a second switch operated according to the mode selection signal to change the current at the summing node of the summing circuit.

7. The control circuit of claim 4 , further comprising a bypass branch selectively coupled to the summing node of the summing circuit and the further switch via a third switch operated according to the mode selection signal, the further switch being configured to be driven by the one or more drive signals.

8. The control circuit of claim 7, wherein the bypass branch comprises a resistor equal to a resistor used to obtain the second feedback signal, the second feedback signal being proportional to a current in an inductance of the switching stage.

9. The control circuit of claim 1, wherein the electronic converter is a boost converter having the inductor coupled to an input terminal of the electronic converter.

10. An electronic converter comprising: The control circuit according to claim 1; as well as a switching stage including the inductor and configured to receive the input voltage at the input terminal and to provide the output voltage at the output terminal, and Wherein the control circuit is coupled to the switching stage.

11. A control circuit configured to control a switching stage of an electronic converter, the electronic converter comprising an inductor and operative to receive an input voltage at an input terminal and to provide an output voltage at an output terminal, the control circuit comprising: a driver circuit configured to provide one or more drive signals according to a pulse width modulation (PWM) signal to control the switching stage; a comparator configured to compare the output voltage to the input voltage and, in response to the comparison, assert a mode selection signal indicating a change in an operating mode of the electronic converter from a synchronous mode to a diode mode; PWM signal generator circuit, comprising: an amplifier circuit configured to provide a first control signal based on a difference between a reference voltage and a first feedback signal, the first feedback signal being proportional to the output voltage; a summing circuit configured to provide a second control signal indicating a superposition of the slope compensation signal and a second feedback signal, the second feedback signal being proportional to a current in the inductor; and a comparator circuit configured to compare the first control signal with the second control signal and generate the PWM signal; and A feed-forward compensation circuit is configured to provide a compensation current to modulate the first control signal output from the amplifier circuit in response to the assertion of the mode select signal.

12. The control circuit of claim 11 , wherein the feed-forward compensation circuit comprises a current generator and a series resistor coupled to an output of the amplifier circuit, wherein the current generator is enabled in response to assertion of the mode selection signal to provide the compensation current to the series resistor.

13. The control circuit of claim 11, wherein the electronic converter is a boost converter having the inductor coupled to an input terminal of the electronic converter.

14. An electronic converter comprising: The control circuit according to claim 11; as well as a switching stage including the inductor and configured to receive the input voltage at the input terminal and to provide the output voltage at the output terminal, and Wherein the control circuit is coupled to the switching stage.

15. A control circuit configured to control a switching stage of an electronic converter, the electronic converter comprising an inductor and operative to receive an input voltage at an input terminal and to provide an output voltage at an output terminal, the control circuit comprising: a driver circuit configured to provide one or more drive signals to control the switching stage according to a pulse width modulation (PWM) signal; a comparator configured to compare the output voltage to the input voltage and, in response to the comparison, assert a mode selection signal indicating a change in an operating mode of the electronic converter from a synchronous mode to a diode mode; PWM signal generator circuit, comprising: a first amplifier circuit configured to provide a first control signal based on a difference between a reference voltage and a first feedback signal, the first feedback signal being proportional to the output voltage; a summing circuit configured to provide a second control signal indicating a superposition of the slope compensation signal and a second feedback signal, the second feedback signal being proportional to a current in the inductor; and a comparator circuit configured to compare the first control signal and the second control signal and generate the PWM signal; and A feed-forward compensation circuit is configured to apply a compensation current in response to the assertion of the mode selection signal to modulate the second control signal output from the summing circuit.

16. The control circuit of claim 15, wherein the summing circuit comprises: a second amplifier circuit having a resistive feedback branch and configured to receive the slope compensation signal; a current mirror coupled to the output of the second amplifier circuit; as well as A summing node is coupled to the output of the current mirror and is selectively coupled to receive the second feedback signal via another switch, the another switch being configured to be driven by the one or more drive signals.

17. The control circuit of claim 16, wherein the feed-forward compensation circuit comprises a current generator selectively coupled in response to the assertion of the mode select signal to sink the compensation current from the summing node of the summing circuit.

18. The control circuit of claim 16, wherein the current mirror includes a current mirror branch that is selectively activated in response to the assertion of the mode select signal to change the current at the summing node of the summing circuit.

19. The control circuit of claim 16, further comprising a resistive bypass branch selectively coupled between the another switch and the summing node of the summing circuit in response to the assertion of the mode select signal.

20. The control circuit of claim 16, wherein the electronic converter is a boost converter having the inductor coupled to an input terminal of the electronic converter.

21. An electronic converter comprising: The control circuit according to claim 15; as well as a switching stage including the inductor and configured to receive the input voltage at the input terminal and to provide the output voltage at the output terminal, and Wherein the control circuit is coupled to the switching stage.

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