Feedback for power management of memory dies using shorting

Abstract

This application is directed to feedback for power management of a memory die using shorting. A memory device can short a first rail to a voltage source for communicating feedback about a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device can detect a condition of one or more voltage rails coupled with the array of memory cells for delivering power. The memory device can short a first rail of the network of components for delivering power to a voltage source based on detecting the condition. In some cases, the memory device can generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

Description

[0001] Cross-references

[0002] This patent application is the national phase application of International Patent Application No. PCT / US2020 / 067211, filed by Choi et al. on December 28, 2020, entitled "Feedback for Power Management of a Memory Die Using Shorting," which claims priority to U.S. Provisional Patent Application No. 16 / 740,281, filed by Choi et al. on January 10, 2020, also entitled "Feedback for Power Management of a Memory Die Using Shorting." Both patent applications are assigned to this assignee and are expressly incorporated herein by reference in their entirety. Technical Field

[0003] The technical field relates to feedback for power management of memory dies using shorting. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. For example, volatile memory devices like DRAM may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe a method. The method may include detecting a condition of a network of components for delivering power coupled to a memory array; shorting a first rail of the network of components for delivering power to a voltage source, at least in part based on the detection of the condition; and generating a feedback signal across the first rail of the network of components for delivering power, at least in part based on the shorting of the first rail.

[0007] Describe a device. The device may include a memory cell array, a power management integrated circuit electronically communicating with the memory cell array, and a controller. The controller may be operable such that the device detects conditions of a network of components for delivering power coupled to the memory cell array; shorts a first rail of the network of components for delivering power to a voltage source, at least in part based on the detection of the conditions; and generates a feedback signal across the first rail of the network of components for delivering power, at least in part based on the shorting of the first rail.

[0008] Another device is described. The device may include a detection component operable to detect conditions of a power delivery component network coupled to a memory cell array; a shorting component operable to short a first rail of the power delivery component network to a voltage source, at least in part based on the detection of the conditions; and a feedback component operable to generate a feedback signal across the first rail of the power delivery component network, at least in part based on the shorting of the first rail. Attached Figure Description

[0009] Figure 1 This document describes examples of systems that support feedback on power management of memory dies using shorting, based on the examples disclosed herein.

[0010] Figure 2 This document describes examples of memory systems that support feedback for power management of memory dies using shorting, based on the examples disclosed herein.

[0011] Figure 3 A block diagram of a memory device that supports feedback for power management of the memory die using shorting, according to the examples disclosed herein.

[0012] Figure 4 The flowchart illustrates one or more methods for supporting feedback on power management of memory dies using shorting, based on the examples disclosed herein.

[0013] Figure 5 The flowchart illustrates one or more methods for supporting feedback on power management of memory dies using shorting, based on the examples disclosed herein. Detailed Implementation

[0014] In some memory systems, power management components, such as those in power management integrated circuits (PMICs), can be used to manage the power supplied to one or more memory devices by controlling the voltage on the power rails. The voltage on the power rails can vary for a variety of reasons. For example, due to parasitic capacitance along the rails or other factors, the voltage on the power rails can attenuate at locations farther from the power management component. For memory devices relatively far from the power management component, the voltage on the power rails can attenuate sufficiently below the minimum supply voltage, which can lead to errors at the memory device.

[0015] The power management component may not have access to information about the voltage at various locations along the rail and may not be able to adjust the power supplied to the rail to compensate for such variations (excessive or insufficient voltage). In other instances, the voltage supplied to the memory device may vary within a given range. The functionality of the memory device can be improved by setting tighter tolerances for the supply voltages, thereby minimizing the variance between supply voltages. To improve the functionality of the memory device, it can measure the supply voltage and provide feedback to the power management component.

[0016] The memory device can use the voltage rails themselves to transmit feedback to the power management component. For example, the memory device can generate interference on the voltage rails themselves to indicate feedback information to the power management component. In some cases, the memory device can short-circuit a first voltage rail with a second voltage rail to indicate feedback information. The memory device can detect conditions (i.e., high voltage and / or high temperature of the memory device) and short-circuit both voltage rails. Short-circuiting the two voltage rails causes a voltage pulse to be sent to the power management component. In such cases, the voltage pulse can be an instance of a feedback signal generated by the memory device and transmitted to the power management component so that the power management component can adjust the voltage appropriately. The power management component can use this feedback information to determine whether and how to adjust the power supplied to the memory device via the power rails (e.g., the supply voltage); that is, the power management component can adjust the voltage of the rails based on feedback received from one or more memory devices.

[0017] Initially, in reference Figure 1 The features of this disclosure are described in the context of the memory system and the die. First, as referenced... Figure 2 The features of this disclosure are described in the context of a memory system. (This is achieved through reference to...) Figure 3-5 The device diagrams and flowcharts describing feedback for power management of the memory die using shorting are further illustrated, and these and other features of this disclosure are further described with reference to the device diagrams and flowcharts.

[0018] Figure 1This document describes an example of a system 100 that supports feedback for power management of memory dies using shorting, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0019] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, networked devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0020] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0021] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various physical package dimensions for host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0022] Memory device 110 may be operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0023] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0024] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0025] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0026] In some instances, system 100 or host device 105 may include an I / O controller. The I / O controller can manage data communication between processor 125 and peripheral components, input devices, or output devices. The I / O controller can manage peripheral devices that are not integrated into system 100 or host device 105 or are integrated with said system or host device. In some instances, the I / O controller may represent a physical connection or port to an external peripheral component.

[0027] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0028] In some instances, memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may be coupled to a power management component operable to provide one or more supply voltages to memory die 160. For example, the power management component may use power rails (e.g., conductive lines) to supply VDD voltage, VSS voltage, VDDQ voltage, etc. The power management component is operable to maintain a substantially constant supply voltage on the rails to provide power to memory device 110 or memory die 160 during operation. The power management component may include or be coupled to one or more voltage source components operable to generate an appropriate supply voltage.

[0029] In some cases, the voltage along the power rails can vary along the rails. For example, due to parasitic capacitance along the power rails, the voltage on the rails can decrease with increasing distance from the power management components. Therefore, if multiple memory dies 160 are coupled to the power rails that provide the supply voltage to the memory dies 160, then the memory dies 160 relatively far from the power management components may receive a lower supply voltage than the memory dies 160 closer to the power management components. In some cases, if the supply voltage suddenly drops below a lower voltage threshold, the memory die 160 may encounter an error.

[0030] As described herein, in some cases, memory device 110 may short the first rail to the second rail to provide feedback on the supply voltage on the power rail at memory die 160 to the power management component, thereby enabling the power management component to properly adjust the supply voltage.

[0031] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0032] A local memory controller 165 (e.g., local to memory die 160) may be operable to control the operation of memory die 160. In some instances, the local memory controller 165 may be operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0033] In some cases, the local memory controller 165 of the memory die 160 may be operable to determine whether the voltage meets a voltage threshold and whether the temperature meets a temperature threshold. If the local memory controller 165 determines that the voltage or temperature meets the threshold, then the local memory controller 165 may short-circuit the first rail with the second rail. In some cases, the feedback components of the memory device 110 may be implemented by the device memory controller 155, the local memory controller 165, or a combination thereof.

[0034] External memory controller 120 can be used to enable the transfer of one or more of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0035] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0036] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or double data rate (DDR) signaling may be transmitted via channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0037] Figure 2 This document describes an example of a memory system 200 that supports feedback for power management of memory dies using shorting, based on the examples disclosed herein. The memory system 200 may include a power management component 205 with a feedback component 210, and a memory device 215 including memory dies 220-a and 220-b. The power management component 205 may electronically communicate with the memory device 215 via voltage rails 230-a, 230-b, 230-c, and 230-d. The memory device 215 may also include shorting components 235-a, 235-b, and 235-c and a feedback component 225. The memory device 215 may be a reference... Figure 1 Examples of the described memory device 110 include, for example, a DRAM device.

[0038] A power management component 205 (e.g., a PMIC) may be coupled to memory device 215 or multiple memory devices. The power management component 205 may generate a supply voltage to voltage rails 230-a, 230-b, 230-c, and 230-d of the component network, thereby delivering power to memory device 215. The supply voltage may be generated based on a feedback signal received at feedback component 210. The feedback signal may be transmitted from feedback component 225 of memory device 215 to feedback component 210 of power management component 205.

[0039] Power management component 205 can detect feedback signals and adjust the voltage supplied to memory device 215 (e.g., supply voltage) accordingly. For example, feedback component 210 can increase the supply voltage based on a determination that voltage rail 230 is below a lower voltage threshold. In some instances, feedback component 210 can decrease the supply voltage based on a determination that voltage rail 230 is above a higher voltage threshold. In some instances, power management component 205 can be an example of a PMIC.

[0040] The power management component 205 can electronically communicate with the memory device 215 using voltage rails 230-a, 230-b, 230-c, and 230-d. Voltage rails 230-a, 230-b, 230-c, and 230-d can be configured to receive a supply voltage and deliver power to the memory device 215. In some instances, voltage rails 230-a, 230-b, 230-c, and 230-d can be shorted to each other in any combination such that a feedback signal is transmitted from the feedback component 225 of the memory device 215 to the feedback component 210 of the power management component 205.

[0041] Memory device 215 may include shorting components 235-a, 235-b, and 235-c. Shorting components 235-a, 235-b, and 235-c may each be an example of a transistor or other switching component. In some instances, shorting component 235-a may be in electronic communication with voltage rails 230-a and 230-b. Shorting component 235-b may be in electronic communication with voltage rails 230-b and 230-c. Shorting component 235-c may be in electronic communication with voltage rails 230-c and 230-d.

[0042] Memory device 215 can detect conditions of the memory device, conditions of the component network used for delivering power (e.g., voltage rails 230-a, 230-b, 230-c, and 230-d), or both. In such cases, memory device 215 can use any of shorting components 235-a, 235-b, and 235-c to short the first rail (e.g., voltage rail 230-a) to a voltage source. In some cases, the voltage source may be voltage rails 230-b, 230-c, or 230-d, or different voltage sources (e.g., a ground node). For example, memory device 215 can short voltage rail 230-a to voltage rail 230-b via shorting component 235-a based on the detected conditions. Each shorting component 235-a, 235-b, and 235-c can short any two voltage rails 230-a, 230-b, 230-c, and 230-d together. For example, shorting component 235-b can short voltage rail 230-b to voltage rail 230-c, and shorting component 235-c can short voltage rail 230-c to voltage rail 230-d.

[0043] Memory device 215 may include a feedback component 225. The feedback component 225 may be in electronic communication with shorting components 235-a, 235-b, and 235-c. In this case, the feedback component 225 may generate a feedback signal based on shorting at least two voltage rails 230-a, 230-b, 230-c, and 230-d. The feedback component 225 may transmit the feedback signal to power management component 205. In some cases, the feedback signal may be an example of a voltage pulse. In some instances, the feedback component 225 may be coupled to sensors on memory dies 220-a and 220-b to measure the supply voltage. The feedback component 225 may be derived from... Figure 1 The controller implementation.

[0044] In some instances, memory device 215 may selectively short which voltage rails 230-a, 230-b, 230-c, and 230-d are connected together. For example, memory device 215 may select voltage rail 230-a to be shorted with voltage rails 230-b, 230-c, or 230-d based on the identification that any of voltage rails 230-b, 230-c, or 230-d is faulty. In such cases, the first voltage rail may be selected to be shorted with the second voltage rail containing the fault. In other instances, memory device 215 may select voltage rail 230-a to be shorted with voltage rails 230-b, 230-c, or 230-d based on the identification that voltage rail 230-a is faulty. Voltage rails 230-a, 230-b, 230-c, and 230-d can be shorted together in any combination based on the detection of an error on any of the voltage rails 230-a, 230-b, 230-c, and 230-d.

[0045] The memory device 215 can select which voltage rails 230-a, 230-b, 230-c, and 230-d to short together based on sensed temperature, voltage, or both. For example, the memory device 215 can determine that the temperature at the location of the memory device 215 meets a temperature threshold. In this case, the memory device 215 can short the first voltage rail (e.g., voltage rail 230-a) to a voltage source (e.g., voltage rails 230-b, 230-c, 230-d, or a ground node) via one of the shorting components 235-a, 235-b, or 235-c.

[0046] In other instances, memory device 215 may sense the voltage at its location and determine that the sensed voltage meets a voltage threshold. In such cases, memory device 215 may short-circuit a first voltage rail (e.g., voltage rail 230-a) to a voltage source (e.g., voltage rails 230-b, 230-c, 230-d, or a ground node) via one of shorting components 235-a, 235-b, or 235-c. The voltage of the voltage source may be different from the voltage of the first voltage rail.

[0047] Based on detected conditions (e.g., sensed voltage, temperature, or both), memory device 215 may determine the duration for shorting two of voltage rails 230-a, 230-b, 230-c, and 230-d. In other instances, memory device 215 may determine a pulse pattern for shorting two of voltage rails 230-a, 230-b, 230-c, and 230-d based on the detected conditions. Memory device 215 may short two voltage rails 230-a, 230-b, 230-c, and 230-d according to the determined duration, pulse pattern, or both. The pulse pattern may be based on the voltage of voltage rails 230-a, 230-b, 230-c, and 230-d being below a lower voltage threshold of a target range, the voltage of voltage rails 230-a, 230-b, 230-c, and 230-d being above a higher voltage threshold of a target range, or both. Instances of pulse patterns can include various combinations of pulses of different lengths (e.g., patterns of long pulses and short pulses). In some instances, pulse patterns can include various combinations of pulses of similar or equal length.

[0048] In some instances, memory device 215 may determine that the voltage of voltage rails 230-a, 230-b, 230-c, or 230-d is below a lower voltage threshold of a target range. In such instances, if the voltage of voltage rail 230-a is below the lower voltage threshold of the target range, then shorting component 235-a may short voltage rail 230-a to voltage rails 230-b, 230-c, or 230-d according to a first pulse pattern and a first duration. In some cases, the lower voltage threshold may comprise multiple voltage thresholds.

[0049] In other instances, memory device 215 may also determine that the voltage of voltage rails 230-a, 230-b, 230-c, or 230-d is higher than a higher voltage threshold of a target range. For example, if the voltage of voltage rail 230-a is higher than the higher voltage threshold of the target range, then shorting component 235-a may short voltage rail 230-a to voltage rails 230-b, 230-c, or 230-d according to a second pulse pattern and a second duration different from the first pulse pattern and the first duration. In some cases, the higher voltage threshold may comprise multiple voltage thresholds. Voltage rails 230-a, 230-b, 230-c, and 230-d may be shorted to each other by pulse pattern, duration, or any combination of both.

[0050] This document provides a technique for using voltage rails 230-a, 230-b, 230-c, and 230-d to short two of voltage rails 230-a, 230-b, 230-c, and 230-d based on a detected condition of memory device 215, thereby shorting components 235-a, 235-b, and 235-c to provide feedback to power management component 205. The condition can be detected by power management component 205 (and / or another device, such as a host device) and can be used by power management component 205 to regulate (e.g., maintain or adjust) the voltage supplied to memory device 215 or to regulate another aspect of the operation of memory device 215.

[0051] Figure 3 A block diagram 300 illustrates a memory device 305 that supports feedback for power management of the memory die using shorting, according to an example disclosed herein. The memory device 305 may be referenced. Figure 1 and 2 Examples of aspects of the described memory device. Memory device 305 may include a detection component 310, a shorting component 315, a feedback component 320, a voltage component 325, and a selection component 330. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0052] The detection component 310 can detect conditions of a network of components coupled to the memory array for delivering power. In some instances, the detection component 310 can determine, based on the detected conditions, the duration for shorting the first rail to the voltage source, wherein the shorting of the first rail to the voltage source is performed within said duration.

[0053] In some instances, the detection component 310 may determine a pulse pattern for shorting the first rail to the voltage source based on detected conditions, wherein shorting the first rail to the voltage source is performed according to the pulse pattern. In some cases, the pulse pattern is based on the voltage of the rail of the component network used for delivering power being below a lower voltage threshold of the target range, the voltage of the rail of the component network used for delivering power being above a higher voltage threshold of the target range, or both.

[0054] The shorting component 315 may short-circuit the first rail of the component network used for delivering power to the voltage source based on the detected condition. In some instances, the shorting component 315 may determine that the temperature at the location of the component network or memory array used for delivering power meets a temperature threshold, wherein shorting the first rail to the voltage source is based on determining that the temperature meets the temperature threshold.

[0055] Feedback component 320 may generate a feedback signal across the first rail of the component network used for power delivery based on shorting the first rail. In some instances, feedback component 320 may transmit the feedback signal across a signal path operable to supply voltage to the first rail of the component network used for power delivery to a power management integrated circuit based on generating the feedback signal. In some cases, the feedback signal includes a voltage pulse.

[0056] Voltage component 325 can sense the voltage at a location of a component network or memory array used to deliver power. In some instances, voltage component 325 can determine that the sensed voltage meets a voltage threshold based on the sensed voltage at the location, wherein shorting the first rail to the voltage source is based on determining that the sensed voltage meets the voltage threshold.

[0057] In some instances, voltage component 325 may determine that the voltage of a rail in a component network used for delivering power is below a lower voltage threshold of a target range, wherein the condition for detecting the component network used for delivering power is based on determining that the voltage is below the lower voltage threshold.

[0058] In some instances, voltage component 325 may determine that the voltage of a rail in a component network used for delivering power is higher than a higher voltage threshold of a target range, wherein the condition for detecting the component network used for delivering power is based on determining that the voltage is higher than the higher voltage threshold.

[0059] In some cases, the voltage source includes a second rail for a network of components used to deliver power. In some cases, the first rail contains a first voltage level and the second rail contains a second voltage level different from the first voltage level. In some cases, the voltage source includes a ground node.

[0060] Selection component 330 may select a first rail of the component network used for delivering power to be shorted to a voltage source based on an error identified in the rail of the component network used for delivering power. In some instances, selection component 330 may select a first rail of the component network used for delivering power to be shorted to a voltage source based on an error identified in the first rail of the component network used for delivering power.

[0061] Figure 4 A flowchart illustrating a method 400 for supporting feedback on power management of a memory die using shorting, according to an example disclosed herein. Operation of method 400 can be implemented by a memory device or its components as described herein. For example, it can be implemented by, as referenced... Figure 3 The described memory device performs the operation of method 400. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0062] At 405, the memory device can detect conditions of the component network coupled to the memory array for delivering power. Operation at 405 can be performed according to the methods described herein. In some instances, it can be achieved by referring to... Figure 3 The described detection component performs the 405 operation.

[0063] At 410, the memory device may, based on the detection of said condition, short-circuit the first rail of the component network used for delivering power to the voltage source. Operation 410 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 3 The described aspect of the shorting component performing operation 410.

[0064] At 415, the memory device can generate a feedback signal across the first rail of the component network used for power delivery based on shorting the first rail. Operation at 415 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 3 The described feedback component performs the operation of 415.

[0065] In some instances, the device as described herein may perform one or more methods, such as method 400. The device may include features, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: detecting a condition of a power delivery component network coupled to a memory array; shorting a first rail of the power delivery component network to a voltage source based on the detected condition; and generating a feedback signal across the first rail of the power delivery component network based on the shorting of the first rail.

[0066] Some examples of the method 400 and apparatus described herein may additionally include operations, features, means, or instructions for: transmitting a feedback signal across a signal path operable to supply voltage to a first rail of a component network for delivering power, based on generating a feedback signal. Some examples of the method 400 and apparatus described herein may additionally include operations, features, means, or instructions for: selecting a first rail of a component network for delivering power to be shorted to a voltage source based on identifying an error in a rail of the component network for delivering power. Some examples of the method 400 and apparatus described herein may additionally include operations, features, means, or instructions for: selecting a first rail of a component network for delivering power to be shorted to a voltage source based on identifying an error in a first rail of the component network for delivering power.

[0067] In some examples of the method 400 and apparatus described herein, detecting the condition may additionally include operations, features, means, or instructions for: determining that the temperature at the location of the component network or memory array used for delivering power meets a temperature threshold, wherein shorting the first rail to a voltage source may be based on determining that the temperature meets the temperature threshold. In some examples of the method 400 and apparatus described herein, detecting the condition may additionally include operations, features, means, or instructions for: sensing a voltage at the location of the component network or memory array used for delivering power; and determining that the sensed voltage meets a voltage threshold based on the sensed voltage at the location, wherein shorting the first rail to a voltage source may be based on determining that the sensed voltage meets the voltage threshold.

[0068] Some examples of the method 400 and apparatus described herein may additionally include operations, features, means, or instructions for determining a duration for shorting a first rail to a voltage source based on detected conditions, wherein shorting the first rail to the voltage source can be performed within said duration. Some examples of the method 400 and apparatus described herein may additionally include operations, features, means, or instructions for determining a pulse pattern for shorting the first rail to a voltage source based on detected conditions, wherein shorting the first rail to the voltage source can be performed according to said pulse pattern.

[0069] In some instances of the method 400 and apparatus described herein, the pulse pattern may be based on the voltage of the rails of the component network used for delivering power being below a lower voltage threshold of a target range, the voltage of the rails of the component network used for delivering power being above a higher voltage threshold of a target range, or both. Some instances of the method 400 and apparatus described herein may additionally include operations, features, means, or instructions for determining that the voltage of the rails of the component network used for delivering power may be below a lower voltage threshold of a target range, wherein detecting the condition of the component network used for delivering power may be based on determining that the voltage may be below the lower voltage threshold.

[0070] Some examples of the method 400 and apparatus described herein may additionally include operations, features, means, or instructions for determining that the voltage of a rail of a component network for delivering power is higher than a higher voltage threshold of a target range, wherein detecting conditions of the component network for delivering power may be based on determining that the voltage is higher than the higher voltage threshold. In some examples of the method 400 and apparatus described herein, the voltage source includes a second rail of the component network for delivering power. In some examples of the method 400 and apparatus described herein, the first rail includes a first voltage level and the second rail includes a second voltage level different from the first voltage level. In some examples of the method 400 and apparatus described herein, the voltage source includes a ground node. In some examples of the method 400 and apparatus described herein, the feedback signal includes a voltage pulse.

[0071] Figure 5 A flowchart illustrating a method 500 for supporting feedback on power management of a memory die using shorting, according to an example disclosed herein. Operation of method 500 can be implemented by a memory device or its components as described herein. For example, operation of method 500 can be performed as described in reference... Figure 3 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0072] At point 505, the memory device can detect conditions in the component network coupled to the memory array for delivering power. Operation at point 505 can be performed according to the methods described herein. In some instances, it can be achieved by referring to... Figure 3 The described detection component performs the 505 operation.

[0073] At 510, the memory device may, based on the detection of said condition, short-circuit the first rail of the component network used for delivering power to the voltage source. Operation at 510 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 3 The described aspect of the shorting component performing the operation of 510.

[0074] At 515, the memory device can generate a feedback signal across the first rail of the component network used for power delivery based on shorting the first rail. Operation at 515 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 3 The described feedback component performs the 515 operation.

[0075] At 520, the memory device may, based on generating a feedback signal, transmit the feedback signal across a signal path of a first rail operable to supply voltage to a component network used for power delivery to a power management integrated circuit. Operation of 520 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 3 The described feedback component performs the 520 operation.

[0076] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0077] Describe an apparatus. The apparatus may include a memory cell array, a power management integrated circuit in electronic communication with the memory cell array, and a controller operable such that the apparatus detects conditions of a component network coupled to the memory array for delivering power; shorts a first rail of the component network for delivering power with a voltage source based on the detected conditions; and generates a feedback signal across the first rail of the component network for delivering power based on the shorting of the first rail.

[0078] Some instances may additionally include transmitting a feedback signal across a signal path to a power management integrated circuit, based on generating a feedback signal that is operable to supply voltage to a first rail of the component network used for power delivery. Some instances may additionally include selecting the first rail of the component network used for power delivery to be shorted to a voltage source based on identifying an error in the rail of the component network used for power delivery.

[0079] Describe an apparatus. The apparatus may include a detection component operable to detect a condition of a power delivery component network coupled to a memory cell array; a shorting component operable to short a first rail of the power delivery component network to a voltage source based on the detection of the condition; and a feedback component operable to generate a feedback signal across the first rail of the power delivery component network based on the shorting of the first rail.

[0080] In some instances, the feedback component may be further operable to transmit the feedback signal, based on the generation of the feedback signal, across a signal path of the first rail of the component network for power delivery, operable to supply voltage to the power management integrated circuit. Some instances of the device may include a selection component operable to select the first rail of the component network for power delivery to be shorted from the voltage source based on identifying an error in the rail of the component network for power delivery.

[0081] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0082] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0083] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0084] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0085] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (e.g., the majority carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0086] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0087] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0088] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0089] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0090] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed so that portions of the functions are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…”) indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0091] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0092] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of operating a memory device, comprising: Detect the conditions of the power delivery component network coupled to the memory array; The first rail of the component network for delivering power is shorted to the voltage source, at least in part based on the detection of the condition. and Feedback signals across the first rail of the component network used for delivering power are generated at least in part based on shorting the first rail.

2. The method of claim 1, further comprising: Based at least in part on generating the feedback signal, the feedback signal is transmitted across a signal path of the first rail, which is operable to supply voltage to the component network for delivering power, to the power management integrated circuit.

3. The method of claim 1, further comprising: Based at least in part on the error in identifying the rails of the component network used for delivering power, the first rail of the component network used for delivering power is selected to be shorted to the voltage source.

4. The method of claim 1, further comprising: At least in part, based on the error in identifying the first rail of the component network used for delivering power, the first rail of the component network used for delivering power is selected to be shorted to the voltage source.

5. The method of claim 1, wherein detecting the condition further comprises: Determining that the temperature at the location of the component network for delivering power or the memory array meets a temperature threshold, wherein shorting the first rail to the voltage source is at least in part based on determining that the temperature meets the temperature threshold.

6. The method of claim 1, wherein detecting the condition further comprises: Sensing the voltage at the location of the component network for delivering power or the memory array; and The sensed voltage is determined to satisfy a voltage threshold based at least in part on the voltage at the sensed location, wherein shorting the first rail to the voltage source is based at least in part on the determination that the sensed voltage satisfies the voltage threshold.

7. The method of claim 1, further comprising: The duration for shorting the first rail to the voltage source is determined at least in part based on the detected conditions, wherein shorting the first rail to the voltage source is performed within the duration.

8. The method of claim 1, further comprising: The pulse pattern for shorting the first rail to the voltage source is determined at least in part based on the detected conditions, wherein shorting the first rail to the voltage source is performed according to the pulse pattern.

9. The method of claim 8, wherein the pulse pattern is based at least in part on the voltage of the rail of the component network for delivering power being below a lower voltage threshold of the target range, the voltage of the rail of the component network for delivering power being above a higher voltage threshold of the target range, or both.

10. The method of claim 1, further comprising: Determining that the voltage of a rail in the component network used for delivering power is below a lower voltage threshold of a target range, wherein the condition of the component network used for delivering power is detected at least in part based on determining that the voltage is below the lower voltage threshold.

11. The method of claim 1, further comprising: The voltage of a rail in the component network used for delivering power is determined to be higher than a higher voltage threshold within a target range, wherein the condition of the component network used for delivering power is detected at least in part based on the determination that the voltage is higher than the higher voltage threshold.

12. The method of claim 1, wherein the voltage source comprises a second rail of the component network for delivering power.

13. The method of claim 12, wherein the first rail includes a first voltage level and the second rail includes a second voltage level different from the first voltage level.

14. The method of claim 1, wherein the voltage source includes a grounding node.

15. The method of claim 1, wherein the feedback signal comprises a voltage pulse.

16. A memory device comprising: Memory cell array, Power management integrated circuit, which electronically communicates with the memory cell array, and A controller, which is operable to enable the memory device to: Detect the conditions of the component network for delivering power coupled to the memory cell array; The first rail of the component network for delivering power is shorted to the voltage source, at least in part based on the detection of the condition. and Feedback signals across the first rail of the component network used for delivering power are generated at least in part based on shorting the first rail.

17. The memory device of claim 16, wherein the controller is further operable to cause the memory device to: Based at least in part on generating the feedback signal, the feedback signal is transmitted to the power management integrated circuit across a signal path of the first rail, which is operable to supply voltage to the component network for delivering power.

18. The memory device of claim 16, wherein the controller is further operable to cause the memory device to: Based at least in part on the error in identifying the rails of the component network used for delivering power, the first rail of the component network used for delivering power is selected to be shorted to the voltage source.

19. A memory device comprising: A detection component capable of operating to detect conditions in a network of components coupled to a memory cell array for delivering power; A shorting component, operable to short the first rail of the power delivery component network to a voltage source, at least in part based on the detection of the condition; and A feedback component that is operable to generate a feedback signal across the first rail of the power delivery component network, at least in part, based on shorting the first rail.

20. The memory device of claim 19, wherein the feedback component is further operable to transmit, at least in part, the feedback signal across a signal path of the first rail operable to supply voltage to the power management integrated circuit based on generating the feedback signal.

21. The memory device of claim 19, further comprising: A selection component, operable to select the first rail of the power delivery component network to be shorted by the voltage source, based at least in part on an error in identifying the rail of the power delivery component network.

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