Wide bandgap semiconductor device and method for manufacturing wide bandgap semiconductor device

Abstract

A wide-gap semiconductor device of the present invention includes: a wide-gap semiconductor layer; and a metal layer 20 provided on the wide-gap semiconductor layer, wherein the metal layer 20 has a single-crystal layer 21 at an interface region of an interface between the wide-gap semiconductor layer, and the single-crystal layer 21 at the interface region contains a first region whose lattice constant L1 is 1.5% to 8% smaller than L, in the case where a lattice constant in a balanced state of a metal constituting the metal layer 20 is set to L.

Description

Technical Field

[0001] This invention relates to a wide-bandgap semiconductor device and a method for manufacturing a wide-bandgap semiconductor device. Background Technology

[0002] Previously, wide-gap semiconductor devices using silicon carbide or similar materials were known (see, for example, Japanese Patent Application Publication No. 2015-56543). In wide-gap semiconductor devices, there is a need to reduce the turn-on voltage of the SBD (Schottky barrier diode). Since most of the turn-on voltage of the SBD comes from the built-in voltage of the Schottky junction, the turn-on voltage can be effectively reduced by lowering φB (Schottky barrier).

[0003] Taking n-type silicon carbide (SiC-SBD), a type of wide-gap semiconductor device, as an example, the φBn of SiC-SBD is generally controlled using a Schottky electrode. Common Schottky electrodes for SiC-SBD include Ti, Ni, and Pt. Among these elements, we know that Ti has the smallest φBn, and most commercially available n-type SiC-SBDs use Ti as the Schottky electrode.

[0004] If the previously used electrode is changed, in addition to the film formation process itself, the etching process will also be changed. Therefore, the industry generally hopes to reduce φB without changing the SBD electrode material.

[0005] In view of the above, the object of the present invention is to provide a wide-gap semiconductor device that can reduce φB without changing the material of the conventionally used metal layer. Summary of the Invention

[0006] The wide-bandgap semiconductor device of the present invention includes:

[0007] Wide-gap semiconductor layer; and

[0008] A metal layer is disposed on the wide-gap semiconductor layer.

[0009] The metal layer has a single-crystal layer at the interface region between it and the wide-gap semiconductor layer.

[0010] When the lattice constant of the metal constituting the metal layer in equilibrium is set to L, the single crystal layer at the interface region includes a first region whose lattice constant L1 is 1.5% to 8% smaller than L.

[0011] In the wide-bandgap semiconductor involved in this invention,

[0012] The lattice constants L and L1 are C-axis lattice constants.

[0013] In the wide-bandgap semiconductor involved in this invention,

[0014] More than 20% of the single crystal layer at the interface region contains the first region.

[0015] In the wide-bandgap semiconductor involved in this invention,

[0016] The single-crystal layer at the interface region includes a second region, the lattice constant L1 of which is greater than L.

[0017] In the interface area, the first area occupies a larger area than the second area.

[0018] In the wide-bandgap semiconductor involved in this invention,

[0019] The wide-gap semiconductor layer is composed of a hexagonal silicon carbide layer.

[0020] The crystal structure of the aforementioned metal layer is hexagonal.

[0021] The metal in the aforementioned metal layer is composed of Ti.

[0022] In the wide-bandgap semiconductor involved in this invention,

[0023] The single crystal layer at the interface region includes a first region composed of Ti with a lattice constant L1 below 0.235 nm.

[0024] In the wide-bandgap semiconductor involved in this invention,

[0025] The single crystal layer at the interface region includes a first region, of which more than 20% is composed of Ti with a lattice constant L1 of less than 0.235 nm.

[0026] The present invention relates to a method for manufacturing a wide-bandgap semiconductor device, comprising:

[0027] The process of forming a Ti layer on a wide-gap semiconductor layer; and

[0028] The process of heating the Ti layer at a temperature below 400°C

[0029] The Ti layer has a single crystal layer at the interface region between it and the wide-gap semiconductor layer.

[0030] Invention Effects

[0031] In this invention, a single crystal layer is provided at the interface region 30 nm away from the interface between the wide-gap semiconductor layer and the metal layer. Furthermore, when the lattice constant of the metal constituting the metal layer in equilibrium is set to L, a first region is included in the interface region, and the lattice constant L1 of this first region is 1.5% to 8% smaller than L. By employing this configuration, φB can be reduced. Attached Figure Description

[0032] Figure 1 This is a side cross-sectional view of an n-type silicon carbide semiconductor device that can be used in embodiments of the present invention.

[0033] Figure 2 (a) is a side cross-sectional view showing the consistent spacing of the atoms constituting a single crystal layer. Figure 2 (b) is a side cross-sectional view showing the inconsistent spacing of the atoms that make up a single crystal layer.

[0034] Figure 3 It is a graph showing the relationship between the C-axis lattice constant L1 and the cumulative probability map in Ti single crystal layers at different annealing temperatures.

[0035] Figure 4 It is a graph showing the relationship between the C-axis lattice constant L1 in a Ti monocrystalline layer and φBn (eV) in an n-type silicon carbide device.

[0036] Figure 5 It is a graph showing the relationship between the C-axis lattice constant L1 in a Ti monocrystalline layer and Ef(eV) in a silicon carbide device, which is obtained through theoretical calculation.

[0037] Figure 6 It is a graph showing the relationship between the C-axis lattice constant L1 in a Ti monocrystalline layer and the n value in a silicon carbide device.

[0038] Figure 7 It is a graph showing the relationship between the annealing time of a Ti-based metal electrode at 450°C and the φBn(eV) in the manufactured n-type silicon carbide device.

[0039] Figure 8 It is a graph showing the relationship between the film formation rate of Ti and φBn(eV) in the fabricated n-type silicon carbide device.

[0040] Figure 9 The images shown are a cross-sectional TEM image magnified 600,000 times, a cross-sectional TEM image magnified 3,000,000 times, and a selected area electron diffraction (SADP) pattern. Detailed Implementation

[0041] Implementation

[0042] "constitute"

[0043] In this embodiment, "one side" refers to Figure 1 The upper side of the middle refers to the front side, and the other side refers to the upper side of the middle. Figure 1 The lower side, i.e. the back side.

[0044] In this embodiment, an n-type silicon carbide semiconductor device (hereinafter referred to as "silicon carbide semiconductor device") is used as an example of a wide-gap semiconductor device. However, it is not limited to this, and a special silicon carbide substrate after forming a single-crystal silicon carbide layer on polycrystalline silicon can also be used. In addition to silicon carbide, gallium nitride, gallium oxide, diamond, etc. can also be used as wide-gap semiconductors.

[0045] like Figure 1 As shown, a silicon carbide semiconductor device may have a silicon carbide substrate 11, a silicon carbide layer 12 disposed on one side (front side) of the silicon carbide substrate 11, and a metal electrode 20 disposed on one side of the silicon carbide layer 12, which serves as a metal layer and functions as a front electrode. Figure 1 In the illustrated configuration, as an example, a silicon carbide layer 12 is directly disposed on a silicon carbide substrate 11, and a metal electrode 20 is directly disposed on the silicon carbide layer 12. For example... Figure 2 As shown in (a) and (b), the metal electrode 20 may also have a single-crystal layer 21 at the interface region between it and the silicon carbide layer 12. When the lattice constant of the metal constituting the metal electrode 20 in a C-axis equilibrium state is set to L, the single-crystal layer 21 at the interface region may also include a first region (composed of L1) whose C-axis lattice constant is 1.5% to 8% smaller than L. The single-crystal layer 21 can be formed by heteroepitaxial growth.

[0046] In this embodiment, the "interface region" at the metal electrode 20 refers to the region within a 30 nm range in the thickness direction from the interface between the metal electrode 20 and the silicon carbide layer 12 on one side of the metal electrode 20. Further to one side than the interface region of the metal electrode 20, the metal electrode 20 can be a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0047] like Figure 1 As shown, a connecting electrode 40 can be provided on the metal electrode 20. Alternatively, a connecting portion 30 can be provided on the connecting electrode 40. The connecting portion 30 can be a wire or a connector.

[0048] The connecting electrode 40 can be made of aluminum, silicon-containing aluminum alloy, copper-containing aluminum alloy, titanium alloy, etc., or it can be made of a laminate of silicon-containing aluminum alloy, copper-containing aluminum alloy, or aluminum or titanium alloy. However, it is not limited to these, the connecting electrode 40 can also be made of other metals, such as copper, gold, nickel, etc.

[0049] Alternatively, a back electrode 50 may be provided on the other side (back side) of the silicon carbide semiconductor substrate 11. The back electrode 50 may also be made of nickel, titanium, or the like. Alternatively, an insulating layer 80 made of oxide or the like may be provided on one side (front side) of the silicon carbide layer 12 in an area where the first electrode portion 30 is not provided.

[0050] More than 20% or 30% of the single-crystal layer 21 in the interface region may contain a first region composed of a lattice constant of L1 along the c-axis. In this embodiment, "A% or more containing the first region" means that when an image is captured using a TEM, a first region composed of a lattice constant L1 can be identified in the region of A% or more (see reference). Figure 9 Alternatively, multiple images (e.g., 2 to 10 images) can be captured using a TEM, and the measurement results from multiple images can be used to confirm whether the first region contains more than 20% of the first region.

[0051] When the metal is composed of Ti, the lattice constant L in equilibrium is 0.24 nm. Therefore, the C-axis lattice constant L1 is 1.5% to 8% smaller than L, i.e., 0.2208 nm to 0.2364 nm. Figure 3 The graph shows the cumulative probability of the c-axis lattice constant L1, calculated using the formula 1E-4Pa (1×10⁻⁴Pa). -4 After annealing at 450°C for 30 minutes under a vacuum condition (Pa), the probability of the C-axis lattice constant L1 reaching below approximately 0.236 nm is less than 20%. Measurements were performed using TEM, and the results were obtained through cross-sectional diffraction (see reference). Figure 9 ).exist Figure 9 The image shows a cross-sectional TEM image magnified 600,000 times, a cross-sectional TEM image magnified 3,000,000 times, and a selected area electron diffraction (SADP) pattern. The lattice constant L1 of a single crystal can be measured based on the SADP pattern.

[0052] After confirmation by the inventor, it was found that, Figure 4 As shown, when the C-axis lattice constant L1 decreases, φBn (eV) decreases. Additionally, as... Figure 5 As shown, the verification results calculated based on first-principles calculations confirm that by decreasing the lattice constant, the Fermi level (Ef) will change in the direction of decreasing φBn. Figure 4 The value of the horizontal axis (C-axis lattice constant) is the lattice constant when the cumulative probability is 30%. Furthermore, there exists a relationship that as Ef(eV) increases, φBn(eV) decreases.

[0053] The silicon carbide layer 12 can have a hexagonal crystal structure or a hexagonal close-packed structure. The metal electrode 20 can also have a hexagonal crystal structure or a hexagonal close-packed structure. The metal in the metal electrode 20 at the interface region can be made of Ti. However, it is not limited to this; the metal in the metal electrode 20 at the interface region can also be made of a metal containing Ti as the main component, or it can be made of Ni, Pt, Mo, a metal containing Ni as the main component, a metal containing Pt as the main component, or a metal containing Mo as the main component. However, from the viewpoint of reducing φBn, it is preferable to use a metal electrode 20 made of Ti or a metal electrode 20 made of a metal containing Ti as the main component, and more preferably a metal electrode 20 made of Ti. Furthermore, "main component" refers to a component that accounts for 50% or more by mass percentage, and a metal containing Ti as a main component refers to a metal containing 50% or more by mass of Ti.

[0054] Even if the metal in the metal electrode 20 at the interface region is made of Ti, a metal layer made of Ni, Al, or the like can be provided on one side of the electrode made of Ti.

[0055] The single crystal layer 21 at the interface region may also include a first region composed of Ti with a C-axis lattice constant L1 of less than 0.235 nm.

[0056] Next, an example of the manufacturing method will be described. In the following manufacturing example, Ti is used as the metal electrode 20.

[0057] (Manufacturing Example 1)

[0058] A Ti layer is formed on a substrate having a silicon carbide layer 12 on a silicon carbide substrate 11. The Ti layer can be formed by electron beam evaporation or sputtering. The deposition rate is, for example, 0.1 to 0.3 nm / s (e.g., 0.12 nm / s), and the vacuum level during Ti layer deposition is, for example, 1E-4 Pa to 1E-5 Pa (e.g., 1E-4 Pa).

[0059] Next, the substrate with the Ti layer is annealed (heated) at 400°C or below. For example, the substrate with the Ti layer is annealed at 350°C for 30 minutes to 0 minutes (e.g., 30 minutes). As a result, a metal electrode 20 composed of a Ti layer is formed.

[0060] Immediately after the Ti layer is deposited on the silicon carbide layer 12, the interface region between the silicon carbide layer 12 and the Ti layer contains holes. Once the Ti layer is annealed, the holes diffuse outwards, and the Ti crystallizes. It is generally believed that by setting the annealing temperature to 450℃~500℃, it will become fully crystalline Ti (equilibrium state), and the c-axis lattice constant will increase (see reference). Figure 2 (a)). As a result, φBn saturates at larger values.

[0061] On the other hand, as in this embodiment, since annealing at temperatures below 400°C (e.g., 350°C) suppresses the outward diffusion of voids within the Ti layer, a state containing a large number of voids can be achieved. As a result, stress is generated within the Ti layer, and the spacing of Ti atoms tends to become inconsistent (see [reference]). Figure 2 (b) Furthermore, compared to the case of complete crystallization, where both regions with small lattice constants (first region) and regions with large lattice constants (second region) are generated simultaneously, φBn can be reduced when the number of regions with small lattice constants (first region) is greater than the number of regions with large lattice constants (second region).

[0062] Figure 2 This is a simplified diagram used to understand the above explanation. Figure 2 In (b), in the region formed by the atoms arranged on the far right, the interatomic spacing of the constituent atoms is fixed at L, that is, the average lattice constant along the C-axis is L. Figure 2 In (b), in the region composed of the second-to-last arranged atoms from the right, the interatomic spacing of the constituent atoms is not the same as L1, L2, and L. L1 is smaller than L, and L2 is larger than L. However, since the lattice constants of interatomic spacing L1 and L2 are the same, the average lattice constant along the C-axis in this region is L. Figure 2 In (b), in the region composed of the third atom from the right, the interatomic spacing of the constituent atoms is L1, L, meaning the spacing is inconsistent, with L1 being smaller than L. Therefore, in this region, the average lattice constant along the C-axis is less than L. Figure 2 In (b), in the region consisting of the fourth atom from the right, the interatomic spacing of the constituent atoms is inconsistent with L1 and L, i.e., the spacing is smaller than L. Therefore, in this region, the average lattice constant along the C-axis is smaller than L.

[0063] Based on the above results, Figure 2 In morphology (b), the average lattice constant along the C-axis is less than L. It can be said that... Figure 3 This experimental result has been confirmed. Figure 3In the figure, annealing at temperatures below 400℃ (350℃ in this case) reveals both regions with high lattice constants along the C-axis (the second region, marked at approximately 0.2425 nm) and regions with low lattice constants (the first region). Furthermore, the number of regions with high lattice constants (the second region) is less than the number of regions with low lattice constants (the first region). In other words, on average, the lattice constant along the C-axis decreases. Consequently, as mentioned above, φBn decreases.

[0064] When a single image is captured in a TEM, the decrease in lattice constant can be confirmed because the first region occupies a larger area than the second region. Alternatively, multiple images (e.g., 2 to 10 images) can be captured using a TEM, and the measurements from these multiple images can be used to confirm that the first region occupies a larger area than the second region.

[0065] like Figure 4 As shown, a decrease in φBn can be confirmed even at annealing temperatures above 550℃, but on the other hand, as... Figure 6 As shown, at annealing temperatures above 550°C, there is also a degradation in the n-value (ideality factor). This is because a chemical reaction occurs between the Ti layer and the silicon carbide layer 12. Figure 6 The horizontal axis value (c-axis lattice constant) and Figure 4 Similarly, it is the lattice constant when the cumulative probability is 30%.

[0066] (Manufacturing Example 2)

[0067] Next, a different manufacturing example will be described. Similar to Manufacturing Example 1, a Ti layer is formed on a substrate on which a silicon carbide layer 12 is provided. The Ti layer can be formed by electron beam evaporation or sputtering. The deposition rate is, for example, 0.1 to 0.3 nm / s (e.g., 0.12 nm / s), and the vacuum level during Ti layer deposition is, for example, 1E-4 Pa to 1E-5 Pa (e.g., 1E-4 Pa).

[0068] Next, the substrate with the Ti layer is annealed (heated) at 450°C to 500°C. For example, the substrate with the Ti layer is annealed at 450°C for 2 to 10 minutes (e.g., 8 minutes). Figure 7 The graph shows the relationship between annealing time and φBn(eV) when annealed at 450℃. It can be confirmed that φBn(eV) decreases when the annealing time is shorter.

[0069] As described above, immediately after the Ti layer is formed on the silicon carbide layer 12, the Ti layer at the interface between the silicon carbide layer 12 and the Ti layer is in a state containing holes. After annealing the Ti layer, the holes in the Ti layer diffuse outward while the Ti crystallizes. At this point, even when annealing at 450–500°C, by shortening the annealing time, the outward diffusion of holes in the Ti layer can be suppressed. Therefore, a state containing a large number of holes can be achieved within the Ti layer, generating stress and forming a region with a smaller lattice constant than in fully crystallized conditions. As a result, φBn can be reduced.

[0070] (Manufacturing Example 3)

[0071] Next, we will explain manufacturing example 3, which is different from manufacturing examples 1 and 2 above.

[0072] In Manufacturing Example 3, similar to Manufacturing Examples 1 and 2, a Ti layer was formed on a silicon carbide substrate 11 on which a silicon carbide layer 12 was formed. The Ti layer was formed using electron beam evaporation or sputtering. However, the deposition rate in Manufacturing Example 3 was made less than 0.02 nm / s. For example, the deposition rate could be 0.01 nm / s or less (e.g., 0.01 nm / s), and the vacuum level during Ti layer deposition could be, for example, 1E-4 Pa to 1E-5 Pa (e.g., 1E-4 Pa).

[0073] Next, the substrate with the Ti layer is annealed (heated) at 450–500°C. For example, the substrate with the Ti layer is annealed at 450°C for 30–60 minutes (e.g., 30 minutes).

[0074] As shown in this manufacturing example, by slowing down the film formation rate, the probability of molecules, atoms, and ions other than Ti reaching the surface of the silicon carbide layer 12 during film formation is relatively increased. Therefore, the Ti layer at the interface between the Ti layer and the silicon carbide layer 12 will contain more holes. Thus, even with an annealing temperature of 450°C to 500°C and an annealing time of 30 minutes, more holes will remain in the Ti layer. This can generate stress, forming regions with a smaller lattice constant than in fully crystallized conditions, thereby reducing φB.

[0075] The inventors varied the film-forming rate under the condition of annealing at 450°C for 30 minutes, and the results are shown in Table 1 below. The results are as follows... Figure 8 As shown.

[0076] Table 1

[0077]

[0078]

[0079] (Manufacturing Example 4)

[0080] Next, we will describe manufacturing example 4, which is different from manufacturing examples 1 to 3 described above.

[0081] In Manufacturing Example 4, similar to Manufacturing Examples 1 to 3, a Ti layer was formed on a substrate 11 on which a silicon carbide layer 12 was provided. The Ti layer could be formed using electron beam evaporation or sputtering. However, the vacuum level during film formation in Manufacturing Example 4 was set to 5E-4 Pa or higher. For example, the film formation rate was 0.1 to 0.3 nm / s (e.g., 0.12 nm / s), and the vacuum level during Ti layer formation was 5E-4 Pa or higher (e.g., 9.3E-4 Pa). Furthermore, excessively high vacuum levels can cause various problems; therefore, the upper limit was set to 1E-2 Pa.

[0082] Next, the substrate with the Ti layer is annealed (heated) at 450–500°C. For example, the substrate with the Ti layer is annealed at 450°C for 30–60 minutes (e.g., 30 minutes).

[0083] As shown in this manufacturing example, by increasing the vacuum level, the probability of molecules, atoms, and ions other than Ti reaching the surface of the silicon carbide layer 12 during film formation is relatively increased. Therefore, the Ti layer at the interface between the Ti layer and the silicon carbide layer 12 will contain more vacancies. Thus, even with an annealing temperature of 450–500°C and an annealing time of 30 minutes, more vacancies will remain in the Ti layer. This can generate stress, forming regions with a smaller lattice constant than in fully crystallized conditions, thereby reducing φBn.

[0084] The inventors set the vacuum degree to 9.3E-4Pa under the condition of annealing at 450°C for 30 minutes, and the results are shown in Table 2 below, confirming that φBn can be reduced.

[0085] Table 2

[0086]

[0087]

[0088] "Effect"

[0089] Next, the effects of this embodiment, constructed with the above structure, will be explained. All the forms described in the "Effects" section can be used in the above structure.

[0090] In this embodiment, when the single crystal layer 21 at the interface region of the metal electrode 20 has a first region whose C-axis lattice constant L1 is 1.5% to 8% smaller than the lattice constant L in the equilibrium state, φBn can be reduced without changing the material of the metal electrode 20.

[0091] When 20% or more of the monocrystalline layer 21 at the interface region is a first region composed of a C-axis lattice constant of L1 (a value 1.5% to 8% smaller than L), φBn can be reduced more reliably. Furthermore, when 30% or more of the monocrystalline layer 21 at the interface region is a first region composed of a C-axis lattice constant of L1 (a value 1.5% to 8% smaller than L), φBn can be reduced more reliably (see reference). Figure 3 and Figure 4 ).

[0092] The metal electrode 20 at the interface region is made of hexagonal Ti crystal. When the silicon carbide layer 12 in contact with the Ti crystal is also made of hexagonal crystal, φBn can be reduced more reliably.

[0093] When the single crystal layer 21 in the interface region is composed of Ti, φBn can be further reduced. In the case of a first region containing a C-axis lattice constant L1 of less than 0.235 nm and composed of Ti, φBn can be reduced more reliably.

[0094] Finally, the descriptions in the above embodiments and variations, as well as the illustrations in the accompanying drawings, are merely examples for illustrating the invention described in the claims. Therefore, the invention described in the claims is not limited to the content disclosed in the above embodiments or drawings. The descriptions in the initial claims of this application are merely examples, and appropriate changes can be made to the descriptions in the claims based on the descriptions in the specification, drawings, etc.

[0095] Symbol Explanation

[0096] 12. Silicon carbide layer (wide-gap semiconductor layer)

[0097] 20 Metal Electrodes

[0098] 21 Single Crystal Layer

Claims

1. A wide bandgap semiconductor device, characterized by, comprises: a wide-gap semiconductor layer; and a metal layer provided on the wide-gap semiconductor layer, wherein the metal layer has a single-crystal layer at an interface region at an interface between the wide-gap semiconductor layer and the metal layer, wherein, in a case where a lattice constant in an equilibrium state of a metal constituting the metal layer is L, the single-crystal layer at the interface region includes a first region having a lattice constant L1 that is 1.5% to 8% smaller than L, the single-crystal layer at the interface region includes a second region having a lattice constant L1 that is larger than L, the number of the first regions is larger than the number of the second regions.

2. The wide-gap semiconductor device according to claim 1, wherein: wherein the lattice constant L and the lattice constant L1 are C-axis lattice constants.

3. The wide-gap semiconductor device according to claim 1, wherein: wherein 20% or more of the single-crystal layer at the interface region contains the first regions.

4. The wide-gap semiconductor device according to claim 1, wherein: wherein in the interface region, the first regions occupy a wider region than the second regions.

5. The wide-gap semiconductor device according to claim 1, wherein: wherein the wide-gap semiconductor layer is composed of a hexagonal crystal silicon carbide layer, the metal layer has a hexagonal crystal structure, the metal in the metal layer is composed of Ti.

6. The wide-gap semiconductor device according to claim 5, wherein: wherein the single-crystal layer at the interface region includes a first region composed of Ti having a lattice constant L1 of 0.235 nm or less.

7. The wide-gap semiconductor device according to claim 6, wherein: wherein, 20% or more of the single-crystal layer at the interface region is composed of Ti having a lattice constant L1 of 0.235 nm or less.

8. A method for manufacturing a wide bandgap semiconductor device, for manufacturing a wide bandgap semiconductor device according to any one of claims 1 to 7, characterized in that, comprises: a step of forming a Ti layer on a wide-gap semiconductor layer; and a step of heating the Ti layer at 350°C or less, wherein the Ti layer has a single-crystal layer at an interface region at an interface between the wide-gap semiconductor layer and the Ti layer.

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