Motion sensitive field effect transistor, motion detection system and method

Abstract

Motion sensitive field effect transistors, motion detection systems and methods are disclosed. The MSFET includes a gate structure having an accumulation region containing a conductive fluid and one or more gate electrodes. Given the location of the gate electrode within the accumulation region and the fill level of the fluid, the contact between the gate electrode and the fluid depends on the orientation of the MSFET channel region relative to the top surface of the conductive fluid, and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends on the spatial position and / or motion of the MSFET, particularly the spatial position and / or motion of the chip on which the MSFET is formed. The electrical properties of the MSFET in response to particular bias conditions vary depending on whether or to what extent the gate electrode contacts the fluid, and thus can be measured to sense chip motion.

Description

Technical Field

[0001] This invention generally relates to on-chip motion sensors, and more particularly to embodiments of motion-sensitive field-effect transistors (MSFETs), motion detection systems, and related methods. Background Technology

[0002] Many applications running on computing devices (such as smartphones, digital cameras, security systems, virtual reality (VR) systems, gaming systems, etc.) are motion-sensing applications. These applications include, but are not limited to, autonomous driving / do not disturb mode applications, image stabilization applications, anti-theft or other security applications, motion-sensing audible applications, VR or gaming applications, etc. Motion sensing is typically achieved using micro-electro-mechanical systems (MEMS) accelerometers, which measure acceleration forces on an object without a fixed reference. Acceleration forces can be static (e.g., gravity) or dynamic (e.g., motion or vibration). Acceleration forces can also be directional. The most commonly used MEMS accelerometer is the on-chip capacitive accelerometer. Unfortunately, such accelerometers consume a significant (if not all) surface area of ​​the IC chip. Summary of the Invention

[0003] This document discloses embodiments of a motion sensing field effect transistor (MSFET) exhibiting at least one motion-dependent electrical property, thereby enabling the MSFET to be used as a motion sensor. More specifically, the disclosed MSFET may include a channel region laterally disposed between source and drain regions. The MSFET may also include a gate structure. The gate structure may include an accumulation region having a bottom adjacent to the channel region. Conductive fluid may be contained within the accumulation region, particularly, the accumulation region may only partially fill it. It should be noted that the accumulation region may be covered to prevent fluid leakage, thereby ensuring that the amount of fluid contained within the accumulation region is constant. The gate structure may also include at least one gate electrode located at a fixed position within the accumulation region. Given the fixed position of each gate electrode in the accumulation region and the filling level of the conductive fluid in the accumulation region, the contact between the gate electrode and the conductive fluid depends on the orientation of the channel region relative to the top surface of the conductive fluid, and the orientation of the channel region relative to the top surface of the conductive fluid depends on the spatial position and / or movement of the MSFET, in particular, the spatial position and / or movement (e.g., tilting and / or acceleration) of the chip on which the MSFET is formed.

[0004] For such an MSFET structure, the electrical properties will vary with the total effective gate voltage applied to the conductive fluid through the gate electrode (or its sub-electrode), and this total effective gate voltage applied to the conductive fluid will vary depending on which gate electrodes (or, if applicable, which sub-electrodes) are in contact with the conductive fluid. Since the contact between the conductive fluid and the gate electrode (or its sub-electrode) is motion-dependent, chip movement (e.g., chip tilting and / or acceleration) can be characterized based on measurements of these electrical properties in response to specific bias conditions. Therefore, embodiments of a motion detection system (MDS) incorporating the above-described MSFET and a motion detection method are also disclosed herein.

[0005] Specifically, the disclosed MDS embodiments may include a chip. The chip may include an MSFET, as described above. That is, the MSFET may include a channel region laterally disposed between source and drain regions. The MSFET may also include a gate structure. The gate structure may include an accumulation region having a bottom adjacent to the channel region. Conductive fluid may be contained within the accumulation region, particularly, may only partially fill the accumulation region. The gate structure may also include at least one gate electrode located at a fixed position within the accumulation region. The chip may also include a bias circuit electrically connected to the MSFET and configured to apply a specific bias condition to the MSFET. The chip may also include a sensing circuit electrically connected to the MSFET and configured to sense (e.g., detect and measure) the electrical properties of the MSFET in response to the specific bias condition. The system may also include a controller (e.g., a processor) located on or off the chip, communicating with the bias circuit and the sensing circuit, and capable of characterizing chip movement (e.g., chip tilting and / or acceleration) based on measurements of the electrical properties in response to the specific bias condition.

[0006] Embodiments of the disclosed motion detection method may include providing a chip with an MSFET, as described above. That is, the MSFET may include a channel region laterally disposed between source and drain regions. The MSFET may also include a gate structure. The gate structure may include an accumulation region having a bottom adjacent to the channel region. A conductive fluid may be contained within the accumulation region, particularly, may only partially fill the accumulation region. The gate structure may also include at least one gate electrode located at a fixed position within the accumulation region. The method may also include applying a specific bias voltage condition to the MSFET. This specific bias condition may be applied, for example, by an on-chip bias circuit electrically connected to the MSFET. The method may also include sensing (e.g., detecting and measuring) an electrical property of the MSFET in response to the specific bias condition. This electrical property may be sensed, for example, by an on-chip sensing circuit electrically connected to the MSFET. The method may also include characterizing chip motion (e.g., chip tilting and / or acceleration) based on measurements of the electrical property in response to the specific bias condition. Chip movement can be characterized, for example, by a controller (e.g., a processor) located on or off the chip and communicating with the bias circuitry and the sensing circuitry.

[0007] As discussed further in the detailed description section below, the sensitivity of the disclosed MDS and methods can be improved by increasing the number of gate electrodes and / or by including stacked electrically isolated sub-electrodes within each gate electrode. Attached Figure Description

[0008] The invention will be better understood from the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0009] Figure 1 is a schematic diagram showing an embodiment of a motion detection system (MDS) including a motion sensing field-effect transistor (MSFET) exhibiting at least one motion-dependent electrical property;

[0010] Figures 2A to 2C are cross-sectional views showing one embodiment of an MSFET that can be included in the MDS of Figure 1;

[0011] Figures 3A to 3C-2 are cross-sectional views showing an alternative embodiment of the MSFET that can be included in the MDS of Figure 1;

[0012] Figures 4A to 4C-2 are cross-sectional views showing another alternative embodiment of the MSFET that can be included in the MDS of Figure 1;

[0013] Figures 5A to 5C-2 are cross-sectional views showing yet another alternative embodiment of the MSFET that can be included in the MDS of Figure 1;

[0014] Figures 6A-6D are example layout diagrams of the gate electrodes in some MSFET embodiments;

[0015] Figures 7-9 are cross-sectional views showing alternative gate electrode configurations in some MSFET embodiments;

[0016] Figure 10 is a cross-sectional view showing the gate structure of the MSFET in Figures 5A-5C-2 in more detail;

[0017] Figures 11-12 are tables showing the motion-dependent changes in gate electrode bias conditions versus total effective gate voltage for example;

[0018] Figure 13 is a graph showing the relationship between the change in electrolyte solution depth near a given gate electrode with 10 sub-electrodes and the change in the total effective voltage applied to the electrolyte solution as the value of f varies.

[0019] Figure 14 is a flowchart showing an embodiment of the motion detection method;

[0020] Figures 15A and 15B are cross-sectional views showing the shape of the alternative overlay; and

[0021] Figure 16 is a schematic diagram of a representative computer system for implementing one or more features of the disclosed motion detection system and method. Detailed Implementation

[0022] As described above, many applications running on electronic devices or systems (e.g., smartphones, digital cameras, security systems, virtual reality (VR) systems, gaming systems, etc.) are motion-sensing applications. These motion-sensing applications include, but are not limited to, autonomous driving / do not disturb mode applications, image stabilization applications, anti-theft or other security applications, motion-sensing audible applications, VR or gaming applications, etc. Motion sensing is typically achieved using microelectromechanical systems (MEMS) accelerometers, which measure acceleration forces on an object without a fixed reference. Acceleration forces can be static (e.g., gravity) or dynamic (e.g., motion or vibration). Acceleration forces can also be directional. The most commonly used MEMS accelerometer is a capacitance accelerometer, which comprises a combination of fixed and flexible capacitor plates located on an integrated circuit (IC) chip. When an object containing the IC chip (e.g., an electronic device) and thus the MEMS accelerometer undergoes acceleration, the distance between the fixed and flexible capacitor plates changes, and therefore the capacitance changes. However, in order to accurately detect linear motion, the on-chip MEMS accelerometer must be large (e.g., >50 micrometers (µm)), thus consuming a large (if not all) of the surface area of ​​the IC chip.

[0023] In view of the foregoing, embodiments of motion-sensing field-effect transistors (MSFETs) are disclosed herein, which are configured to exhibit at least one motion-dependent electrical property, thereby enabling their use as motion sensors. Specifically, in this MSFET, the gate structure adjacent to the channel region may include: an accumulation region containing conductive fluid, and one or more gate electrodes located at fixed positions within the accumulation region. Given the fixed positions of the gate electrodes within the accumulation region and the fill level of the conductive fluid within the accumulation region, the contact between the gate electrodes and the conductive fluid depends on the orientation of the channel region relative to the top surface of the conductive fluid, and the orientation of the channel region relative to the top surface of the conductive fluid depends on the spatial position and / or motion of the MSFET, particularly on the spatial position and / or motion (e.g., tilting and / or acceleration) of the chip on which the MSFET is formed. For such an MSFET structure, the electrical property responding to specific bias conditions will vary depending on whether the gate electrode (or, if applicable, its sub-electrode) is in contact with the conductive fluid. Therefore, this electrical property can be measured to characterize chip motion (e.g., chip tilting and / or acceleration). This document also discloses embodiments of motion detection systems (MDS) incorporating such MSFETs and embodiments of motion detection methods employing such MSFETs.

[0024] Referring to Figure 1, embodiments of a motion detection system (MDS) 100 and a motion sensing field-effect transistor (MSFET) 110, which exhibits at least one motion-dependent electrical property and is included in the MDS 100 (e.g., as a motion sensor), are disclosed herein. Example MSFET structures 110 that may be included in the MDS 100 include, but are not limited to, MSFET 110.1 as shown in Figures 2A to 2C, MSFET 110.2 as shown in Figures 3A to 3C-2, MSFET 110.3 as shown in Figures 4A to 4C-2, and MSFET 110.4 as shown in Figures 5A to 5C-2.

[0025] More specifically, MDS 100 may include integrated circuit (IC) chip 102. MDS 100 may be entirely contained on chip 102 (i.e., it may be a system-on-chip (SOC)). Alternatively, MDS 100 may include components located on and off the chip.

[0026] In any case, chip 102 may include semiconductor substrate 101. Semiconductor substrate 101 may be, for example, a bulk semiconductor substrate (e.g., a bulk silicon substrate or some other type of bulk semiconductor substrate), as shown. Alternatively, semiconductor substrate 101 may be a semiconductor-on-insulator (e.g., a silicon-on-insulator (SOI) substrate). An isolation region 105 (e.g., a shallow trench isolation (STI) region) located in substrate 101 (e.g., on top of a bulk semiconductor substrate or in a semiconductor layer of a semiconductor-on-insulator substrate) may define an active device region of motion sensing field-effect transistor (MSFET) 110 (e.g., MSFET 110.1 as shown in Figures 2A-2C, MSFET 110.2 as shown in Figures 3A-3C-2, MSFET 110.3 as shown in Figures 4A-4C-2, or MSFET 110.4 as shown in Figures 5A-5C-2).

[0027] MSFETs 110.1, 110.2, 110.3, and 110.4 can be either N-type or P-type MSFETs. Specifically, MSFETs 110.1, 110.2, 110.3, and 110.4 may include a source / drain region 111 and a channel region 112 laterally disposed between the source / drain regions 111 within the active device region. For example, for an N-type MSFET, the source / drain region 111 can be an N+ source / drain region, doped with N-type dopant to have a higher conductivity level, and the channel region 112 can be a P-channel region, doped with P-type dopant to have a lower conductivity level. For a P-type MSFET, the source / drain region 111 can be a P+ source / drain region, doped with P-type dopant to have a higher conductivity level, and the channel region 112 can be an N-channel region, doped with N-type dopant to have a lower conductivity level. One or more dielectric material layers 106 may cover MSFETs 110.1, 110.2, 110.3, 110.4, and particularly the source / drain region 111. The dielectric material 106 may include an interlayer dielectric (ILD) material. The ILD material 106 may include, for example, silicon dioxide, doped silicon glass (e.g., phophosilicate glass (PSG) or borophosphosilicate glass (BPSG)), or any other suitable ILD material.

[0028] MSFETs 110.1, 110.2, 110.3, and 110.4 may also include a gate structure 113, particularly a gate structure incorporating a conductive fluid, wherein the gate metal or doped polysilicon is replaced by a conductive fluid (e.g., an electrolyte solution). Specifically, the gate structure 113 may include an accumulation region 114 (also referred to herein as a receptor, microwell, trench, cavity, etc.), which is patterned within a dielectric material 106, aligned with the channel region 112, and having a bottom adjacent to the channel region 112. For illustrative purposes, the sidewalls of the accumulation region 114 are shown as substantially vertical. However, it should be understood that these figures are not intended to be limiting, and the shape of the accumulation region 114 may vary depending on the technique used to form the accumulation region 114. For example, as with the accumulation regions used in various known ISFET structures, the accumulation regions 114 of the disclosed MSFETs 110.1, 110.2, 110.3, 110.4 can be angled, stepped, curved, etc. The gate structure 113 may also include one or more gate dielectric layers 115 (e.g., silicon dioxide layers or other suitable gate dielectric layers) located immediately adjacent to the channel region 112 at the bottom of the accumulation region 114. For illustrative purposes, the gate dielectric layer 115 is shown only within and at the bottom of the accumulation region 114. However, it should be understood that these figures are not intended to be limiting. For example, alternatively, the gate dielectric layer 115 may conformally liner the bottom and sidewalls of the accumulation region 114, or the gate dielectric layer 115 may be a layer embedded within the dielectric material 106, and the accumulation region 114 may be patterned and etched so that the bottom of the accumulation region 114 lands on the gate dielectric layer. The gate structure 113 may also include a conductive fluid 116 contained within the accumulation region 114 and one or more gate electrodes. Finally, the accumulation region 114 may be covered (e.g., by a cap layer 107).

[0029] Those skilled in the art will recognize that conventional ion-sensitive FETs (ISFETs) similarly have a gate structure containing a fluid. In the case of an ISFET, the fluid can be an electrolyte solution that flows into the accumulation region, thereby adjacent to the gate dielectric layer. A reference gate electrode can be in continuous contact with the fluid. Specific bias conditions can be applied to the terminals of the ISFET, and the electrical response can be measured to characterize and / or identify targets in the fluid. For example, the drain current (Id) of an ISFET responding to a fixed drain-source voltage and a fixed gate voltage can be considered ion-sensitive. In this case, changes in the concentration of ions in the fluid flowing into the accumulation region (e.g., the concentration of hydrogen (H+) ions or other such ions) can cause a change in the surface potential at the interface between the gate dielectric layer and the fluid, and this change in surface potential can cause a change in the threshold voltage. Such a change in threshold voltage will correspondingly cause a change in the drain current (Id). Therefore, this ISFET can be used to measure and / or characterize targets (e.g., pH or other targets) in the fluid and is often used as a biosensor.

[0030] Although the gate structure 113 of MSFETs 110.1, 110.2, 110.3, and 110.4 is similar to the gate structure of ISFETs in that it is a gate structure containing fluid, it is different from the gate structure of ISFETs because it is specifically configured to characterize the movement (e.g., tilting and / or acceleration) of the chip 102 on which the MSFET is formed (as opposed to measuring or characterizing a target within a fluid).

[0031] Specifically, in the gate structure 113, the accumulation region 114 is only partially filled with a fixed amount of conductive fluid 116 (e.g., filled with the conductive fluid to a fixed level less than the full volume of the accumulation region). The conductive fluid 116 may be an electrolyte solution. Examples of electrolyte solutions that can be used in the gate structure 113 include, but are not limited to, solutions of calcium chloride, potassium chloride, calcium hydroxide, and nitrogen hydroxide. Alternatively, any other suitable electrolyte solution may be used. However, it should be understood that electrolyte solutions that may cause corrosion of the exposed materials (e.g., the ILD layer and / or the capping layer) should be avoided. Solutions that may cause semiconductor device failure should also be avoided. For example, electrolyte solutions containing sulfuric acid should be avoided unless the ILD layer 106 and the capping layer 107 are made of glass. Electrolyte solutions containing sodium salts should be avoided because sodium ions entering the semiconductor substrate may cause semiconductor device failure. Other considerations for the electrolyte solution include stability and viscosity, and (optionally) additives to optimize performance.

[0032] The capping layer 107 may cover the accumulation region 114 to prevent loss or leakage of conductive fluid 116 from the accumulation region 114, thereby maintaining the amount of conductive fluid 116 at a constant level. The capping layer 107 may be an insulating layer. This insulating layer may be an organic planarization layer (OPL), a spin-coated glass layer, a silica layer, a polymer layer, a Teflon layer, or some other suitable insulating layer, as discussed in more detail below. The capping layer 107 may be a single-layer structure, or, alternatively, a multi-layer structure (e.g., a laminated structure). Optionally, the capping layer 107 may include a port 108 (i.e., an opening extending vertically through the capping layer 107 to the accumulation region 114) to facilitate the addition of a fixed amount of conductive fluid 116 to the accumulation region 114 after manufacturing rather than during manufacturing (e.g., injecting conductive fluid 116 into the accumulation region). Once the conductive fluid 116 is added to the accumulation area, the port 108 can be sealed (e.g., using an adhesive plug or a plug made of some other suitable type of material), thereby preventing subsequent loss or leakage of the conductive fluid.

[0033] Given the fixed positions of each gate electrode within the accumulation region 114 and the filling level 150 of the conductive fluid 116 within the accumulation region 114, the contact between the gate electrode and the conductive fluid 116 depends on the orientation of the channel region 112 relative to the top surface 119 of the conductive fluid 116, and the orientation of the channel region 112 relative to the top surface 119 of the conductive fluid 116 depends on the spatial position and / or movement of the MSFETs 110.1, 110.2, 110.3, 110.4, and in particular, depends on the spatial position and / or movement (e.g., tilting and / or acceleration) of the chip 102 on which the MSFET is formed.

[0034] For the disclosed MSFET structure, the electrical properties will vary with the total effective gate voltage applied to the conductive fluid 116 through the gate electrode (or its sub-electrode), and the total effective gate voltage applied to the conductive fluid 116 will vary with which gate electrodes (or, if applicable, which sub-electrodes) are in contact with the conductive fluid. Since the contact between the conductive fluid 116 and the gate electrode (or its sub-electrode) is motion-dependent, chip movement (e.g., chip tilting and / or acceleration) can be characterized based on measurements of these electrical properties in response to specific bias conditions.

[0035] More specifically, the volume of the conductive fluid 116 contained within the accumulation region 114 may be a fixed portion (e.g., half, two-thirds, etc.) of the total volume of the accumulation region 114. This fixed amount of conductive fluid 116 may be selected such that, when the chip 102 is vertical (i.e., the bottom surface of the substrate 101 is closest to the Earth's surface), horizontal (i.e., the bottom surface of the substrate 101 is parallel to the Earth's surface), and stationary (i.e., not moving), at least the following conditions are met: (a) the conductive fluid 116 will be adjacent to and completely cover the gate dielectric layer 115 (or a portion thereof) located at the bottom of the accumulation region 114; (b) The exposed surface 119 of the conductive fluid 116 (not immediately adjacent to the bottom or sidewall of the accumulation region 114, also referred to herein as the top surface of the conductive fluid 116) will be parallel to the bottom surface of the substrate 101 (and thus parallel to the channel region 112 located within the substrate 101), and will further be at a fixed fill level 150 between the gate dielectric layer 115 and the top of the accumulation region 114; and (c) the accumulation region 114 between the top surface 119 of the conductive fluid 116 and the capping layer 107 located on top of the accumulation region 114 will also include an air or gas-filled space 117. This fixed amount of the conductive fluid 116 may also be selected to change the orientation of the channel region 112 relative to the top surface 119 of the conductive fluid 116, particularly in response to movement of the chip 102 (i.e., in response to tilting or rotating the chip 102 in a certain direction and / or accelerating the chip 102 in a certain direction) from parallel to angled. For example, the fixed amount of conductive fluid 116 can be selected to retain a space 117 filled with air or gas within the accumulation region 114, thereby allowing the conductive fluid to move within the accumulation region 114 in response to the movement of the chip (e.g., tilting and / or acceleration). The ratio of the volume of conductive fluid 116 to the volume of the air or gas filling space 117 should be such that if a rotational force causes the chip 102 to tilt / rotate, the top surface 119 of the conductive fluid 116 will remain parallel to the Earth's surface due to gravity on the conductive fluid 116. Therefore, the channel region 112 will be angled relative to the top surface 119 of the conductive fluid 116. Alternatively, the ratio of the volume of conductive fluid 116 to the volume of the air or gas filling space 117 should be such that if an accelerating force causes the chip 102 to accelerate in one direction (e.g., parallel to the Earth's surface), the conductive fluid 116 will slide backward in the opposite direction. Therefore, the channel region 112 will similarly be angled relative to the top surface 119 of the conductive fluid 116.

[0036] The number, location, and arrangement of the gate electrodes in the accumulation region 114 of the gate structure 113 of the disclosed MSFETs 110.1, 110.2, 110.3, and 110.4 are different, and therefore their motion sensitivities are also different.

[0037] For example, referring to Figures 2A through 2C, the MSFET 110.1 may include a single gate electrode 118. The gate electrode 118 may be made of a metal or metal alloy material. This metal or metal alloy material of the gate electrode may be pre-selected to avoid the possibility of corrosion and / or oxygen formation thereon. Examples of the metal or metal alloy material of the gate electrode include, but are not limited to, platinum or gold. In any case, the gate electrode 118 may be located at a fixed position within the accumulation region 114. For example, this fixed position of the gate electrode 118 may be between the bottom and top of the accumulation region 114, such that when the chip 102 is vertical, horizontal, and stationary, the following conditions are met: (a) the channel region 112 of the conductive fluid 116 is parallel to the top surface 119; (b) the top surface 119 of the conductive fluid 116 is at a given fill level 150; and (c) the gate electrode 118 is in contact with the conductive fluid 116, as shown in Figure 2A. The fixed position of the gate electrode 118 can also be closer to the first side of the accumulation region 114, rather than the second side opposite to the first side. Therefore, due to the upward tilt of the chip 102 on the first side (e.g., as shown in FIG2B) and / or the acceleration of the chip 102 from the second side to the first side along the first direction, a (For example, as shown in FIG2C), the channel region 112 forms an angle of at least one specific angle (e.g., at least one specific angle (θ)) with respect to the top surface 119 of the conductive fluid 116 and the liquid level of the conductive fluid 116 on the first side of the accumulation region 114 drops, thereby physically separating the gate electrode 118 from the conductive fluid 116.

[0038] Referring to Figures 3A to 3C-2, the MSFET 110.2 may include multiple gate electrodes, particularly at least a first gate electrode 118a and a second gate electrode 118b. Each gate electrode may be made of a metal or metal alloy material. The metal or metal alloy material of the gate electrode may be pre-selected to avoid the possibility of corrosion and / or oxygen formation thereon. Examples of metal or metal alloy materials for the gate electrode include, but are not limited to, platinum or gold. In any case, the first gate electrode 118a and the second gate electrode 118b may be located at different fixed positions within the accumulation region 114. For example, the fixed position of the gate electrode (including the fixed positions of the first and second gate electrodes 118a-118b) may be between the bottom and top of the accumulation region 114, such that when the chip 102 is vertical, horizontal, and stationary, the following conditions are met: (a) the channel region 112 is parallel to the top surface 119 of the conductive fluid 116; (b) the top surface 119 of the conductive fluid 116 is at a given fill level 150; and (c) all the gate electrodes (including the first and second gate electrodes 118a-118b) are in contact with the conductive fluid 116, as shown in FIG3A. The fixed position of the gate electrode may be further located at different positions along the accumulation region. For example, the first gate electrode 118a may be located at a first position adjacent to a first side of the accumulation region 114, and the second gate electrode 118b may be located at a second position adjacent to a second side opposite to the first side. Therefore, due to the upward tilt of chip 102 on the first side (e.g., as shown in FIG3B-1) and / or the acceleration of chip 102 from the second side to the first side along the first direction, a 1. (For example, as shown in FIG3C-1), the channel region 112 forms at least one specific first-level angle (e.g., at least a specific first angle (θ1)) relative to the top surface 119 of the conductive fluid 116, and the liquid level of the conductive fluid 116 on this first side of the accumulation region 114 decreases, thereby physically separating the first gate electrode 118a from the conductive fluid 116 (while the liquid level of the conductive fluid 116 on this second side of the accumulation region 114 increases, thereby keeping the second gate electrode 118b in contact with the conductive fluid 116). Moreover, due to the chip 102 tilting upward on this second side (e.g., as shown in FIG3B-2) and / or the chip 102 accelerating from the first side to the second side along the second direction. a 2 (for example, as shown in FIG3C-2), the channel region 112 forms an angle of at least one specific second angle (e.g., at least one specific second angle (θ2)) with respect to the top surface 119 of the conductive fluid 116 and the liquid level of the conductive fluid 116 on the second side of the accumulation region 114 decreases, thereby physically separating the second gate electrode 118b from the conductive fluid 116 (while the liquid level of the conductive fluid 116 on the first side of the accumulation region increases, thereby keeping the first gate electrode 118a in contact with the conductive fluid 116).

[0039] Referring to Figures 4A to 4C-2, the MSFET 110.3 may include multiple gate electrodes, particularly at least a first gate electrode 118a. 1-n and the second gate electrode 118b 1-n However, the gate electrodes are not made entirely of metal or metal alloys; rather, each gate electrode may comprise a stack of electrically isolated sub-electrodes. For example, the first gate electrode 118a 1-n It may include a stack of electrically isolated first sub-electrodes (1-n) and a second gate electrode 118b 1-n A stack of electrically isolated second sub-electrodes (1-n) may be included. Each electrically isolated sub-electrode stack may include alternating layers of insulating material and metal or metal alloy material, such that the metal or metal alloy material of one sub-electrode is electrically isolated from the metal or metal alloy material of all other sub-electrodes in the stack. The metal or metal alloy material may be pre-selected to avoid the possibility of corrosion and / or oxygen formation thereon. Example metal or metal alloy materials include, but are not limited to, platinum or gold. In any case, as in the embodiments described above, the gate electrode may be located at different fixed locations within the accumulation region 114. For example, this fixed location of the gate electrode (including the first and second gate electrodes 118a) 1-n and 118b 1-n The fixed position of the channel region 112 can be between the bottom and top of the accumulation region 114, such that when the chip 102 is vertical, horizontal and stationary, the following conditions are met: (a) the channel region 112 is parallel to the top surface 119 of the conductive fluid 116; (b) the top surface 119 of the conductive fluid 116 is at a given fill level 150; and (c) all the sub-electrodes of all the gate electrodes (including the first gate electrode 118a) are in a given fill level 150. 1-n The first sub-electrode 1-n and the second gate electrode 118b 1-n The second sub-electrodes 1-n) are all in contact with the conductive fluid 116, as shown in FIG4A. This fixed position of the gate electrode can be located at different positions along the accumulation region. For example, the first gate electrode 118a 1-n It can be located at a first position adjacent to the first side of the accumulation region 114, and the second gate electrode 118b 1-n It can be located at a second position adjacent to the second side opposite to the first side. Therefore, due to the chip 102 tilting upward on the first side (e.g., as shown in FIG4B-1) and / or the chip 102 accelerating from the second side to the first side along the first direction. a1 (for example, as shown in FIG4C-1), the channel region 112 forms an angle with respect to the top surface 119 of the conductive fluid 116 at a gradually increasing first angle (e.g., a gradually increasing first angle (θ1)), and the liquid level of the conductive fluid 116 on this first side of the accumulation region 114 decreases, thereby causing the first gate electrode 118a to... 1-n The first sub-electrodes 1-n are physically separated from the conductive fluid 116 sequentially from top to bottom (that is, 1 to n). (Meanwhile, the liquid level of the conductive fluid 116 on the second side of the accumulation area rises, thereby causing the second gate electrode 118b to...) 1-n The second sub-electrode 1-n remains in contact with the conductive fluid 116. Furthermore, due to the chip 102 tilting upwards on this second side (e.g., as shown in FIG4B-2) and / or the chip 102 accelerating from the first side to the second side along the second direction... a 2 (for example, as shown in FIG4C-2), the channel region 112 forms an angle with respect to the top surface 119 of the conductive fluid 116 at a gradually increasing second angle (e.g., a gradually increasing second angle (θ2)), and the liquid level of the conductive fluid 116 on this second side of the accumulation region 114 decreases, thereby causing the second gate electrode 118b to... 1-n The second sub-electrodes 1-n are physically separated from the conductive fluid 116 sequentially from top to bottom (that is, 1-n). (Meanwhile, the liquid level of the conductive fluid 116 on the first side of the accumulation region 114 rises, thereby raising the level of the first gate electrode 118a.) 1-n The first sub-electrode 1-n remains in contact with the conductive fluid 116.

[0040] Referring to Figures 5A to 5C-2, the MSFET 110.4 may include multiple gate electrodes, particularly at least a first gate electrode 118a. 1-n and the second gate electrode 118b 1-n Similar to MSFET 110.3, the gate electrodes are not made entirely of metal or metal alloy, but rather each gate electrode may comprise a stack of electrically isolated sub-electrodes 1-n. That is, the first gate electrode 118a 1-n It may include a stack of electrically isolated first sub-electrodes 1-n, and a second gate electrode 118b. 1-nA stack of electrically isolated second sub-electrodes 1-n may be included. Each electrically isolated sub-electrode stack may include alternating layers of insulating material and metal or metal alloy material, such that the metal or metal alloy material of one sub-electrode is electrically isolated from the metal or metal alloy material of all other sub-electrodes in the stack. The metal or metal alloy material may be pre-selected to avoid the possibility of corrosion and / or oxygen formation thereon. Examples of metal or metal alloy materials include, but are not limited to, platinum or gold. In any case, the gate electrode may be located at different fixed locations within the accumulation region 114. For example, this fixed location of the gate electrode (including the first and second gate electrodes 118a) 1-n and 118b 1-n The fixed position of the channel region 112 can be between the bottom and top of the accumulation region 114, such that when the chip 102 is vertical, horizontal and stationary, the following conditions are met: (a) the channel region 112 is parallel to the top surface 119 of the conductive fluid 116; (b) the top surface 119 of the conductive fluid 116 is at a given fill level 150; and (c) only the lower sub-electrode of each gate electrode (including the first gate electrode 118a) is at a given fill level 150. 1-n The lower sub-electrode in the first sub-electrode and the second gate electrode 118b 1-n The lower sub-electrode of the second sub-electrode is in contact with the conductive fluid 116, while each of the first and second gate electrodes 118a 1-n and 118b 1-n The upper sub-electrode of this sub-electrode is located horizontally above the top surface 119 of the conductive fluid 116, as shown in FIG5A. This fixed position of the gate electrode can be located at different positions along the accumulation region 114. For example, the first gate electrode 118a 1-n It can be located at a first position adjacent to the first side of the accumulation region 114, and the second gate electrode 118b 1-n It can be located at a second position adjacent to the second side opposite to the first side. Therefore, due to the chip 102 tilting upward on the first side (e.g., as shown in FIG5B-1) and / or the chip 102 accelerating from the second side to the first side along the first direction. a 1 (for example, as shown in FIG5C-1), the channel region 112 forms an angle with respect to the top surface 119 of the conductive fluid 116 at a gradually increasing first angle (e.g., a gradually increasing first angle (θ1)), and the liquid level of the conductive fluid 116 on this first side of the accumulation region 114 decreases, thereby causing the first gate electrode 118a to... 1-n The lower sub-electrode in the first sub-electrode is physically separated from the conductive fluid 116 sequentially from top to bottom (while the liquid level of the conductive fluid 116 on the second side of the accumulation region 114 rises, thereby the second gate electrode 118b 1-nThe upper sub-electrode of the second sub-electrode sequentially contacts the conductive fluid 116 from bottom to top. Furthermore, due to the chip 102 tilting upwards on the second side (e.g., as shown in FIG5B-2) and / or the chip 102 accelerating from the first side to the second side along the second direction... a 2 (for example, as shown in FIG5C-2), the channel region 112 forms an angle with respect to the top surface 119 of the conductive fluid 116 at a gradually increasing second angle (e.g., a gradually increasing second angle (θ2)), and the liquid level of the conductive fluid 116 on this second side of the accumulation region 114 decreases, thereby causing the second gate electrode 118b to... 1-n The lower second sub-electrode in the second sub-electrode is physically separated from the conductive fluid 116 in sequence from top to bottom (that is, 1-n) (while the liquid level of the conductive fluid 116 on the first side of the accumulation region 114 rises, thereby the first gate electrode 118a 1-n The upper sub-electrode of the first sub-electrode contacts the conductive fluid 116 from bottom to top.

[0041] It should be understood that the gate electrode described above and shown in the accompanying drawings is not intended to be limiting.

[0042] For example, an MSFET may include any number of one or more gate electrodes (e.g., see example gate electrode 618 in the layout diagrams of Figures 6A-6D). Moreover, if the MSFET has more than two gate electrodes, these gate electrodes 618 (whether they are stacks of single electrodes or electrically isolated sub-electrodes) may be uniformly distributed along the width of the accumulation region (e.g., as shown in Figure 6C), placed on each side of the accumulation region (e.g., as shown in Figure 6D), and so on.

[0043] Furthermore, in the gate structure 113 of MSFETs 110.3 and 110.4, each gate electrode 118a 1-n and 118b 1-n The electrically isolating sub-electrode stack can contain any number of sub-electrodes (e.g., 2, 3, 4, 5, etc. as shown in the figure).

[0044] Finally, various known processing techniques can be used to form the gate electrode 118 of the MSFET 110.1, 118a and 118b of the MSFET 110.2, and 118a of the MSFET 110.3 or 110.4 at fixed locations within the accumulation region 114. 1-n and 118b 1-nThe gate electrodes illustrated in these figures allow the reader to focus on the distinctive features of the disclosed embodiments. However, it should be understood that although the chip 102 on which the MSFET is formed moves (e.g., tilts and / or accelerates), a support structure is still required to hold (i.e., anchor, fix, etc.) the gate electrodes in fixed positions within the accumulation region 114 (i.e., relative to the bottom, top, and sides of the accumulation region). For example, in some embodiments, as shown in the layout diagrams of Figures 6A-6D, each gate electrode 618 may be a strip that extends laterally from one sidewall to the opposite sidewall along the entire width of the interior of the accumulation region 114 and has ends attached to those sidewalls. In the case of the structure shown in Figure 6D, gate electrodes extending through the accumulation region in different directions may be located at different heights to avoid direct electrical connection. In other embodiments, each gate electrode 718 may be a bump protruding from one sidewall into the interior of the accumulation region 114, as shown in Figure 7. In other embodiments, each gate electrode 818 may be embedded in the dielectric material 106, and only one vertical surface may be exposed inside the accumulation region 114, as shown in FIG8. In other embodiments, each gate electrode 918 may be embedded in a dielectric pillar that extends vertically through the interior of the accumulation region 114 and has an end attached to the bottom of the accumulation region and / or the dielectric capping layer (see, for example, FIG9). In any case, one or more metal or metal alloy side surfaces of each gate electrode (or each of its sub-electrodes) should be exposed inside the accumulation region 114 to allow contact with the conductive fluid 116.

[0045] In addition to the features described above, interconnects (e.g., vias and / or lines) may be included in the dielectric material 106 and / or the dielectric support structure of the gate electrode to provide discrete electrical connections to each gate electrode, and, if applicable, to each sub-electrode within each gate electrode.

[0046] As described above, for such an MSFET structure, the electrical properties will vary with the total effective gate voltage applied to the conductive fluid through the gate electrode (or its sub-electrode), and the total effective gate voltage applied to the conductive fluid will vary depending on which gate electrodes (or, if applicable, which sub-electrodes) are in contact with the conductive fluid. Since the contact between the conductive fluid and the gate electrode (or its sub-electrode) is motion-dependent, chip movement (e.g., chip tilting and / or acceleration) can be characterized based on measurements of these electrical properties in response to specific bias conditions.

[0047] Therefore, referring again to FIG1, the disclosed motion detection system (MDS) 100 may further include a bias circuit 199 located on chip 102, electrically connected to the MSFET (e.g., MSFET 110.1, 110.2, 110.3, or 110.4), and configured to apply a specific bias condition to the MSFET. The MDS 100 may also include a sensing circuit 198 also located on chip 102, electrically connected to the MSFET (e.g., MSFET 110.1, 110.2, 110.3, or 110.4), and configured to sense (e.g., detect and measure) the electrical properties of the MSFET 110.1, 110.2, 110.3, or 110.4 in response to the specific bias condition. MDS 100 may also include a controller (e.g., a processor) located on chip 102 (e.g., see controller 190) or located outside chip 102 but communicating with chip 102 (e.g., see controller 190'). Specifically, the controller communicates with bias circuitry 199 and sensing circuitry 198 and can characterize chip motion (e.g., chip tilting and / or acceleration) based on measurements of the electrical properties in response to a particular bias condition.

[0048] As described above and discussed in more detail below, motion sensitivity can be improved by increasing the number of gate electrodes within the MSFET and / or by including stacked electrically isolated sub-electrodes within each gate electrode of the MSFET. That is, the MDS 100 including MSFET 110.2 will be more motion-sensitive (i.e., provide better chip motion characterization) than the MDS 100 including MSFET 110.1, the MDS 100 including MSFET 110.3 will be more motion-sensitive than the MDS 100 including MSFET 110.2, and so on.

[0049] Various operating modes can be employed to use this MSFET as a motion sensor within the MDS 100.

[0050] In an example embodiment, the bias circuit 199 may be electrically connected to the source / drain region 111, and optionally, to the body region of the MSFET, and may be configured to apply a fixed drain-source voltage (Vds) between the source / drain regions 111. The bias circuit 199 may also be electrically connected to each gate electrode and may be configured to apply a specific gate voltage to that gate electrode. In the case of multiple gate electrodes, the bias circuit 199 may be configured to apply different gate voltages to the different gate electrodes. In the case where the gate electrodes comprise a stack of electrically isolated sub-electrodes, the bias circuit 199 may be electrically connected to each sub-electrode (e.g., via a corresponding bus) so that the same gate voltage can be applied simultaneously to each sub-electrode of the gate electrode (e.g., see FIG. 4A or FIG. 5A). In the case of multiple gate electrodes, each gate electrode has a corresponding stack of electrically isolated sub-electrodes, and the bias circuit 199 may be configured to apply the same gate voltage to all sub-electrodes in the same stack, but apply different gate voltages to sub-electrodes in different stacks. As discussed in more detail below, the specific gate voltage applied to the gate electrode (or its sub-electrode) can be pre-selected to achieve optimal chip motion detection sensitivity while minimizing electrode-to-electrode leakage in the conductive fluid. In these example embodiments, the sensing circuit 198 can be electrically connected to the drain region of the MSFET and can be configured to sense (i.e., detect and measure) the drain current (Id).

[0051] For example, for the MSFET 110.1 shown in Figures 2A-2C and described above, the bias circuit 199 may be electrically connected to the gate electrode 118 and may be configured to apply a fixed gate voltage (V) to the gate electrode 118. g V gThe threshold voltage (Vt) of the MSFET 110.1 can be set to be equal to or higher than that of the MSFET 110.1. The sensing circuit 198 can be configured to detect and measure the drain current (Id). Since there is only one gate electrode, the MSFET 110.1 will be in an on-state (current flows through the channel region) or an off-state (no current flows through the channel region). Since the gate electrode is adjacent to one side of the accumulation region (e.g., the first side), the MSFET 110.1 will be in an off-state only when the channel region 112 forms an angle greater than a certain level with respect to the top surface 119 of the conductive fluid 116 (e.g., due to chip tilting and / or acceleration) such that the level of the conductive fluid 116 on the first side drops to the point where the gate electrode 118 is no longer in contact with the conductive fluid 116. Therefore, in this case, when the MSFET 110.1 is in the off-state, the controller 190 (or 190') can characterize chip movement as the chip tilting in one direction to a threshold level or the chip accelerating in one direction to a threshold rate. When MSFET 110.1 is in the ON state, controller 190 (or 190') can characterize chip motion as undetected. However, it should be understood that since there is only one gate electrode on one side of the accumulation region, certain chip motions (e.g., slight tilting and / or tilting in different directions; slight chip acceleration and / or acceleration in different directions) will not be detected.

[0052] For the MSFET 110.2 shown in Figures 3A-3C-2 and described above, the bias circuit 199 can be electrically connected to the first and second gate electrodes 118a-118b and can be configured to apply first and second gate voltages (V0 and V2 respectively) to the first and second gate electrodes. g1 and V g2 V g1 Different from V g2 (For example, V) g1 <V g2 Both can be higher than the threshold voltage (Vt) of the MSFET 110.2. The sensing circuit 198 can be configured to detect and measure the drain current (Id). In this case, the controller 190 (or 190') can characterize chip movement based on the value of Id as no movement detected, chip movement in one direction, or chip movement in different directions. Specifically, when the chip 102 is vertical, horizontal, and stationary, such that both the first and second gate electrodes 118a-118b are in contact with the conductive fluid 116 and Vt... g1 With V g2When the sum is applied to the conductive fluid, Id will be at its highest level. When the channel region 112 forms an angle of at least one specific first angle (e.g., at least a specific first angle (θ1)) with respect to the top surface 119 of the conductive fluid 116 due to the chip 102 tilting upward on the first side (e.g., as shown in FIG3B-1) and / or the chip 102 accelerating from the second side to the first side along the first direction (e.g., as shown in FIG3C-1), and the level of the conductive fluid 116 on the first side of the accumulation region 114 decreases, thereby physically separating the first gate electrode 118a from the conductive fluid 116 (while the level of the conductive fluid 116 on the second side of the accumulation region 114 increases, thereby keeping the second gate electrode 118b in contact with the conductive fluid 116), Id will be at an intermediate level. Therefore, only V g2 The conductive fluid is applied. When the chip 102 tilts upward on the second side (e.g., as shown in FIG3B-2) and / or the chip 102 accelerates from the first side to the second side along the second direction (e.g., as shown in FIG3C-2), the channel region 112 forms an angle of at least one specific second angle (e.g., at least one specific second angle (θ2)) with respect to the top surface 119 of the conductive fluid 116, and the level of the conductive fluid 116 on the second side of the accumulation region 114 decreases, thereby physically separating the second gate electrode 118b from the conductive fluid 116 (while the level of the conductive fluid 116 on the first side of the accumulation region increases, thereby keeping the first gate electrode 118a in contact with the conductive fluid 116), Id will be at a low level. Therefore, only V g1 A conductive fluid 116 is applied. Therefore, in this case, the controller 190 (or 190') can characterize the chip motion based on the drain current (Id) as one of the following: no motion is detected (e.g., when Id is at its highest level); the chip tilts in one direction to a threshold level or the chip accelerates in one direction to a threshold rate (e.g., when Id is at an intermediate level); and the chip tilts in the opposite direction to a threshold level or the chip accelerates in the opposite direction to a threshold rate (e.g., when Id is at its lowest level).

[0053] For the MSFET 110.3 shown in Figures 4A-4C-2 and described above, or the MSFET 110.4 shown in Figures 5A-5C-2 and described above, the bias circuit 199 can be connected to the first gate electrode 118a via the first bus. 1-n Each of the first sub-electrodes (1-n) is electrically connected and connected to the second gate electrode 118b via the second bus. 1-n Each of the second sub-electrodes (1-n) is electrically connected. The bias circuit 199 can also be configured to apply the same first gate voltage (V) to each of the first sub-electrodes. g1 And apply the same second gate voltage (V) to each second sub-electrode.g2 The sensing circuit 198 can be configured to detect and measure the drain current (Id). In this case, the controller 190 (or 190') can characterize the chip motion based on the value of Id as any of the following: no motion is detected, the chip moves in one direction to one of several possible degrees, or the chip moves in different directions to one of several possible degrees.

[0054] Specifically, in MSFET 110.3, due to the upward tilt of chip 102 on the first side (e.g., as shown in FIG4B-1) and / or the acceleration of chip 102 from the second side to the first side along a first direction (e.g., as shown in FIG4C-1), the channel region 112 forms an angle with respect to the top surface 119 of the conductive fluid 116 at a gradually increasing first angle (e.g., a gradually increasing first angle (θ1)), and the liquid level of the conductive fluid 116 on the first side of the accumulation region 114 decreases, thereby causing the first gate electrode 118a to... 1-n The first sub-electrode is physically separated from the conductive fluid 116 sequentially from top to bottom (i.e., 1 to n) (while the liquid level of the conductive fluid 116 on the second side of the accumulation area rises, thereby causing the second gate electrode 118b to be physically separated). 1-n The second sub-electrode remains in contact with the conductive fluid 116. Furthermore, due to the chip 102 tilting upwards on this second side (e.g., as shown in FIG4B-2) and / or the chip 102 accelerating from the first side to the second side along a second direction (e.g., as shown in FIG4C-2), the channel region 112 forms an angle with respect to the top surface 119 of the conductive fluid 116 at a gradually increasing second angle (e.g., a gradually increasing second angle (θ2)), and the level of the conductive fluid 116 on the second side of the accumulation region 114 decreases, thereby causing the second gate electrode 118b to... 1-n The second sub-electrode is physically separated from the conductive fluid 116 sequentially from top to bottom (i.e., 1-n) (while the liquid level of the conductive fluid 116 on the first side of the accumulation region 114 rises, thereby raising the level of the first gate electrode 118a). 1-n (Maintain contact with conductive fluid 116).

[0055] Similarly, in MSFET 110.4, due to the upward tilt of chip 102 on the first side (e.g., as shown in FIG5B-1) and / or the acceleration of chip 102 from the second side to the first side along a first direction (e.g., as shown in FIG5C-1), the channel region 112 forms an angle with respect to the top surface 119 of the conductive fluid 116 at a gradually increasing first angle (e.g., a gradually increasing first angle (θ1)), and the liquid level of the conductive fluid 116 on the first side of the accumulation region 114 decreases, thereby causing the first gate electrode 118a to... 1-nThe lower sub-electrode in the first sub-electrode is physically separated from the conductive fluid 116 sequentially from top to bottom (while the liquid level of the conductive fluid 116 on the second side of the accumulation region 114 rises, thereby the second gate electrode 118b 1-n The upper sub-electrode of the second sub-electrode sequentially contacts the conductive fluid 116 from bottom to top. Furthermore, due to the chip 102 tilting upwards on the second side (e.g., as shown in FIG5B-2) and / or the chip 102 accelerating from the first side to the second side along a second direction (e.g., as shown in FIG5C-2), the channel region 112 forms an angle with respect to the top surface 119 of the conductive fluid 116 at a gradually increasing second angle (e.g., a gradually increasing second angle (θ2)), and the liquid level of the conductive fluid 116 on the second side of the accumulation region 114 decreases, thereby causing the second gate electrode 118b to... 1-n The lower sub-electrode in the second sub-electrode is physically separated from the conductive fluid 116 in sequence from top to bottom (i.e., 1-n) (while the liquid level of the conductive fluid 116 on the first side of the accumulation region 114 rises, thereby raising the level of the first gate electrode 118a). 1-n The upper sub-electrode of the first sub-electrode contacts the conductive fluid 116 from bottom to top.

[0056] Therefore, in any case, given the V applied to each of the first sub-electrodes g1 and V applied to each of the second sub-electrodes g2 The selection of the drain current (Id) indicates how many of the first sub-electrodes and how many of the second sub-electrodes remain in contact with the conductive fluid 116, thereby indicating the total effective gate voltage applied to the conductive fluid, and correspondingly indicating the orientation (in particular, the actual angle) of the channel region 112 relative to the top surface of the conductive fluid 116. Since the drain current (Id) is a function of the total effective gate voltage, the chip motion characterization by the controller 190 based on the drain current (Id) can include not only the direction of chip tilt but also the degree of chip tilt, or not only the direction of chip acceleration but also the rate of chip acceleration.

[0057] More specifically, consider the gate structure 113 of the MSFET 110.4, as shown in more detail in Figure 10. In this case, the total effective gate voltage applied to the conductive fluid 116 will vary in response to chip movement (e.g., when the chip tilts or accelerates) because of the first gate electrode 118a in contact with the conductive fluid 116. 1-n The number of first sub-electrodes and the second gate electrode 118b 1-n The number of second sub-electrodes will change. Specifically, the following formula applies:

[0058] V 1=nV g1 ,

[0059] V 2= nV g2 ,

[0060] V 1+ V 2= V T ,

[0061] V 1= fV 2,

[0062] ,

[0063] ,

[0064] ,

[0065] ,

[0066] n 2= n - n 1

[0067] , and

[0068] ,

[0069] Wherein, V1 is the total possible voltage that can be applied to the conductive fluid 116 through the first sub-electrode of the first gate electrode 118a.

[0070] V g1 It is the first gate voltage applied to each of the first sub-electrodes.

[0071] V2 is the total possible voltage that can be applied to the conductive fluid 116 through the second sub-electrode of the second gate electrode 118b.

[0072] V g2 It is the second gate voltage applied to each of the second sub-electrodes, V T It is the total possible voltage that can be applied to the conductive fluid 116 through the first sub-electrode and the second sub-electrode.

[0073] n is the total number of sub-electrodes in each gate electrode.

[0074] n1 is the number of first sub-electrodes of the first gate electrode that are in contact with the conductive fluid 116 at any given time.

[0075] n2 is the number of second sub-electrodes of the second gate electrode that are in contact with the conductive fluid 116 at any given time, and

[0076] f is a coefficient that defines the relationship between V1 and V2.

[0077] The formulas listed above can be used to determine optimal gate bias conditions, and in particular to determine the optimal Vb for each of the first sub-electrodes of the first gate electrode 118a of the gate structure 113 of the MSFET 110.4. g1 And the optimal Vo of each second sub-electrode of the second gate electrode 118b of the gate structure 113 of the MSFET 110.4. g2 The goal of these formulas is to maximize the potential difference (i.e., the difference between V1 and V2) to improve the chip's motion detection sensitivity, while also choosing the coefficient f to minimize inter-electrode leakage in the conductive fluid, which would otherwise reduce the overall effective voltage and thus the drain current.

[0078] Consider the example MSFET 110.4, where the total possible gate voltage (V) T The voltage is 1.5V, where n is 10 (that is, each gate electrode has 10 sub-electrodes). The table in Figure 11 shows the voltage V to obtain 1.5V. TPossible values ​​of V1 and V2 can be adopted depending on different coefficients. As shown in Figure 11, if f=1, V1 and V2 will be equal; however, if f=0.1, V1 and V2 will have the largest possible difference. The table in Figure 12 shows how, for different values ​​of f (assuming n1 is the number of first sub-electrodes in contact with the conductive fluid 116 at any given time, and n2 is the number of second sub-electrodes in contact with the conductive fluid 116 at any given time and equal to n-n1), the changes in the liquid level of the conductive fluid 116 adjacent to the first gate electrode 118a and the simultaneous changes in the liquid level of the conductive fluid 116 adjacent to the second gate electrode 118b (e.g., due to chip tilting and / or chip acceleration) result in changes in the total effective gate voltage applied to the conductive fluid. If f=1 (that is, if the same voltage is applied to each sub-electrode in each of the gate electrodes), the total effective gate voltage applied to the conductive fluid will always be 0.75V. In this case, the drain current (Id) will remain constant with chip movement, and no information about chip movement will be known. However, if f < 1, an asymmetric segmentation will exist between V1 and V2. Due to the resulting orientation of the channel region relative to the top surface of the conductive fluid, the total effective gate voltage applied to the conductive fluid 116 of the gate structure 113 of the MSFET 110.4 will vary with chip movement (e.g., due to the chip tilting to different degrees in different directions and / or the chip accelerating to different rates in different directions). Therefore, the drain current (Id) will also vary with chip movement and can be used by the controller 190 (or 190') to characterize chip movement with significant sensitivity. Figure 13 is a graph further showing the relationship between the depth variation of the electrolyte solution adjacent to a given gate electrode having n sub-electrodes (e.g., 10 sub-electrodes) and the variation of the total effective voltage applied to the electrolyte solution as a function of different values ​​of f.

[0079] Those skilled in the art will recognize that on-chip biasing circuits configured to apply different bias voltages to different on-chip components and on-chip sensing circuits configured to sense the electrical properties of FETs (e.g., drain current (Id)) are well known in the art. Therefore, details of such biasing and sensing circuits have been omitted from the specification to allow the reader to focus on the salient features of the disclosed embodiments.

[0080] Figure 14 is a flowchart showing an embodiment of the motion detection method.

[0081] The method may include providing a motion detection system (MDS), such as the MDS 100 described in detail above and shown in Figure 1 (see process step 1402). That is, the MDS 100 may include a chip 102, a motion-sensitive field-effect transistor (MSFET) located on the chip 102, a bias circuit 199 electrically connected to the MSFET, and a sensing circuit 198 electrically connected to the MSFET. The MDS 100 may also include a controller located on the chip 102 (e.g., see controller 190) or located outside the chip 102 but communicating with the chip 102 (e.g., see controller 190').

[0082] It should be noted that the MSFET can be any of the MSFET embodiments described above, including but not limited to: MSFET 110.1 shown in Figures 2A-2C; MSFET 110.2 shown in Figures 3A to 3C-2; MSFET 110.3 shown in Figures 4A to 4C-2; or MSFET 110.4 shown in Figures 5A to 5C-2. Each such MSFET 110.1-110.4 includes: a source / drain region 111; a channel region 112 laterally disposed between the source / drain regions 111; and a gate structure 113 adjacent to the channel region 112. The gate structure includes: an accumulation region 114 having a bottom adjacent to the channel region 112; a conductive fluid 116 contained within the accumulation region 114, particularly partially filling the accumulation region 114; and at least one gate electrode (e.g., see gate electrode 118 of gate structure 113 in MSFET 110.1; see gate electrodes 118a-118b of gate structure 113 in MSFET 110.2; and see gate electrode 118a of MSFETs 110.3 and 110.4). 1-n and 118b 1-n The gate electrode is located at a fixed position within the accumulation region 114. Given the fixed position of each gate electrode within the accumulation region and the fill level of the conductive fluid within the accumulation region, the contact between the gate electrode (or, if applicable, its sub-electrode) and the conductive fluid depends on the orientation of the channel region 112 relative to the top surface 119 of the conductive fluid 116, and the orientation of the channel region 112 relative to the top surface 119 of the conductive fluid 116 depends on the spatial position and / or movement of the MSFET, particularly on the spatial position and / or movement (e.g., tilting and / or acceleration) of the chip 102 on which the MSFET is formed.

[0083] For such an MSFET structure, the electrical properties will vary with the total effective gate voltage applied to the conductive fluid, and this total effective gate voltage will vary depending on which gate electrodes (or, if applicable, which sub-electrodes) are in contact with the conductive fluid. Since the contact between the conductive fluid and the gate electrode (or its sub-electrodes) is motion-dependent, chip motion can be characterized by measuring the electrical properties of the MSFET in response to specific bias conditions.

[0084] Therefore, the method also includes applying a specific bias condition to the MSFET using bias circuit 199 (see process step 1404), and using sensing circuit 198 to sense (e.g., detect and measure) the electrical properties of the MSFET in response to the specific bias condition (see process step 1406). Various operating modes can be employed to use the MSFET as a motion sensor. That is, different electrical properties can be sensed in response to different bias conditions. However, in the example method embodiment, the specific bias condition used in process step 1404 may include, for example, a fixed drain-source voltage (Vds) between the source / drain regions 111 and one or more specific gate voltages applied to each gate electrode (or, if applicable, each sub-electrode of the gate electrode). It should be noted that optimal bias conditions and, in particular, optimal gate voltages have been discussed in more detail above with respect to various MSFET structural embodiments and Figures 10-13. In this case, the electrical property sensed in process step 1406 in response to the specific bias condition may be the drain current (Id).

[0085] Finally, the method may further include using the controller 190 (or 190') to characterize chip motion (e.g., chip tilt and / or acceleration) based on measurements of the electrical property (e.g., a measured drain current (Id) value) (see process step 1408). In an example embodiment, the drain current (Id) will vary with the total effective gate voltage applied to the conductive fluid, and the total effective gate voltage applied to the conductive fluid will vary depending on which gate electrode(s)(or, if applicable,) is in contact with the conductive fluid. Since the contact between the conductive fluid and the gate electrode(s) (or sub-electrode) is motion-dependent, chip motion can be characterized by the controller based on the drain current (Id).

[0086] For illustrative purposes, the capping layer 107 is shown in the figures as substantially planar and extending through the accumulation zone 114 without sinking into it. Those skilled in the art will recognize that the orientation of the capping layer 107 relative to the accumulation zone 114 can vary depending on the processing technology, the materials used, and / or the size of the accumulation zone 114, as well as the thickness of the deposited capping layer 107.

[0087] For example, in some embodiments, the processing techniques may include forming an accumulation region 114 (e.g., a trench) in the ILD layer 106, forming an electrode in and / or adjacent to the accumulation region 114 (as described above), filling the remaining space within the accumulation region 114 with a sacrificial filler material, and removing the sacrificial filler material from above the ILD layer 106 (e.g., by performing a chemical mechanical polishing (CMP) process). Next, a capping layer 107 may be formed (e.g., deposited) above the coplanar top surface of the ILD layer 106 and the sacrificial filler material within the accumulation region 114, making it substantially planar. Subsequently, a port 108 (e.g., an opening) may be formed through the capping layer 107 to expose the sacrificial filler material, through which the sacrificial filler material may be selectively removed from the accumulation region 114, through which a conductive fluid 116 may be added to the accumulation region 114, and through which the port 108 may be sealed. It should be noted that the materials used for the ILD layer 106, capping layer 107, the electrode, and the sacrificial filler should be selected so that the sacrificial filler can be selectively removed from the accumulation region 114 via port 108 without damaging other exposed surfaces. For example, the ILD layer 106 and capping layer 107 may be silicon dioxide, and the sacrificial filler may be: (a) a silicon filler (e.g., polysilicon), which can be removed after port formation by XeF2 vapor phase etching or SF6 plasma etching; or (b) a polymer filler, which can be removed after port formation by oxygen plasma etching. Thus, such processing will result in the capping layer 107 being substantially planar, as shown in FIG15A (and in the other figures above).

[0088] In other embodiments, the processing techniques may include forming an accumulation region 114 (e.g., a trench) in the ILD layer 106, and forming electrodes in and / or adjacent to the accumulation region 114 (as described above). A capping layer 107 may then be formed on the top surface of the ILD layer 106 above the trench, thereby forming an air-filled chamber. This capping layer may be formed using existing capping techniques (e.g., introduced from the chip package). Depending on the size of the trench opening at the top surface of the ILD layer, and also depending on the thickness of the deposited layer, such processing may cause the capping layer 107 to sink into the accumulation region 114 and close or pinching off at the top of the accumulation region, as shown in FIG15B. Optionally, the trench may be partially filled with a conductive fluid 116 prior to capping layer formation. Alternatively, after capping layer formation, a port 108 may be formed in the capping layer 107, the conductive fluid 116 may be added to the accumulation region 114, and the port 108 may be sealed.

[0089] It should be understood that the accompanying drawings and processing techniques discussed above are not intended to be limiting. The accumulation zone 114 and the covering layer 107 covering the accumulation zone 114 can be formed using any suitable technique to ensure that when the accumulation zone 114 is partially filled with the conductive fluid 116 and covered by the covering layer 107, leakage or loss of the conductive fluid 116 is prevented, and air or gas filling space is retained within the accumulation zone 114, thereby allowing the conductive fluid to move and making the movement detectable, as described above.

[0090] It should be understood that in the above methods and structures, semiconductor materials refer to materials whose conductivity properties can be altered by doping with impurities. Example semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon-germanium, germanium-silicon carbide, silicon carbide, etc.) and group III-V compound semiconductors (i.e., obtained by combining group III elements such as aluminum (Al), gallium (Ga), or indium (In) with group V elements such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). Pure semiconductor materials, especially semiconductor materials undoped with impurities used to increase conductivity (i.e., undoped semiconductor materials), are referred to in the art as intrinsic semiconductors. Semiconductor materials doped with impurities used to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as extrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same substrate. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon-germanium will be more conductive than intrinsic silicon-germanium, and so on. Furthermore, it should be understood that different impurities (i.e., different dopants) can be used to obtain different types of conductivity (e.g., P-type and N-type conductivity), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with Group III dopants such as boron (B) or indium (In) to obtain P-type conductivity, and typically doped with Group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to obtain N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to obtain P-type conductivity, and with silicon (Si) or oxygen doping to obtain N-type conductivity. Those skilled in the art will also recognize that different levels of conductivity will depend on the relative concentration levels of the dopants in a given semiconductor region.

[0091] This document also discloses embodiments of a computer program product for implementing one or more features of the above-described motion detection system and method. Specifically, the computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon to cause a processor to execute the present invention.

[0092] The computer-readable storage medium may be a tangible device that holds and stores instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of the computer-readable storage medium includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in recesses (on which instructions are recorded), and any combination thereof. The computer-readable storage medium as used herein is not to be construed as a transient signal, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0093] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to their respective computing / processing devices or downloaded via a network such as the Internet, local area network, wide area network, and / or wireless network to an external computer or external storage device. The network may include copper transmission cables, fiber optic cables, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. Network adapter cards or network interfaces in each computing / processing device receive the computer-readable program instructions from the network and forward them to computer-readable storage media within their respective computer / processing devices.

[0094] The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuits including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) can execute computer-readable program instructions by using state information of the computer-readable program instructions to personalize the electronic circuits and thereby execute the state of the present invention.

[0095] This document describes the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0096] These computer-readable program instructions may be provided to the processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions (executed by the processor of the computer or other programmable data processing apparatus) create a manner for implementing the functions / actions specified in the flowchart and / or block diagram blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that directs a computer, programmable data processing apparatus, and / or other means to function in a particular manner such that the computer-readable storage medium containing the instructions includes an article of manufacture comprising instructions for implementing the functions / actions specified in the flowchart and / or block diagram blocks.

[0097] These computer-readable program instructions may also be loaded onto a computer, other programmable data processing equipment or other device to perform a series of operational steps on the computer, other programmable equipment or other device, thereby creating a computer implementation process so that the instructions executed on the computer, other programmable equipment or other device perform the functions / actions specified in the flowchart and / or block diagram blocks.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions to perform a specified logical function. In some alternative implementations, the functions shown in the blocks may occur outside the order shown in the drawings. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or sometimes the blocks may be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a system based on dedicated hardware that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0099] Figure 16 is a schematic diagram showing a representative computer system for implementing one or more features of the disclosed motion detection system and method. This schematic diagram shows the hardware configuration of an information processing / computer system according to embodiments herein. The system includes at least one processor or central processing unit (CPU) 10. The CPU 10 is interconnected via a system bus 12 to various devices such as random access memory (RAM) 14, read-only memory (ROM) 16, and input / output (I / O) adapter 18. The I / O adapter 18 may connect to peripheral devices such as disk units 11 and tape drives 13, or other program storage devices readable by the system. The system may read inventive instructions on the program storage device and follow these instructions to perform the methods of embodiments herein. The system also includes a user interface adapter 19, which connects a keyboard 15, a mouse 17, a speaker 24, a microphone 22, and / or other user interface devices such as a touchscreen device (not shown) to the bus 12 to collect user input. In addition, communication adapter 20 connects bus 12 to data processing network 25, and display adapter 21 connects bus 12 to display device 23, which may be implemented as an output device, such as a monitor, printer or transmitter.

[0100] It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, unless the context clearly indicates otherwise, the singular forms “a” and “the” as used herein are also intended to include the plural forms. Furthermore, the terms “comprising” and / or “including” as used herein indicate the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Additionally, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “below,” “above,” “parallel,” “vertical,” etc., as used herein, are intended to describe their relative positions when oriented and shown in the accompanying drawings (unless otherwise indicated), and terms such as “touching,” “direct contact,” “adjacent,” “directly adjacent,” “closely adjacent,” etc., are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term "lateral" as used herein describes the relative position of elements when they are oriented and shown in the accompanying drawings, specifically indicating that one element is located to the side of another element rather than above or below it. For example, an element laterally adjacent to another element will be next to that other element; an element laterally close to another element will be directly next to that other element; and an element laterally surrounding another element will be adjacent to and encircle the outer wall of that other element. All the manner or step plus the corresponding structure, material, action, and equivalents of the functional element in the following claims are intended to include any structure, material, or action that performs the function in combination with the other claimed elements.

[0101] The descriptions of various embodiments of the invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements upon technical techniques known in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A transistor, characterized in that, include: Channel area; as well as A gate structure, adjacent to the channel region and including: Accumulation zone, configured to contain conductive fluid; The gate dielectric layer is located at the bottom of the accumulation region; and At least one gate electrode is located at a fixed position within the accumulation region and between the bottom and top of the accumulation region, wherein the conductive fluid is adjacent to and completely covers the gate dielectric layer, wherein the orientation of the channel region relative to the top surface of the conductive fluid depends on the movement of the transistor, and wherein the contact between the at least one gate electrode and the conductive fluid depends on the orientation of the channel region relative to the top surface of the conductive fluid.

2. The transistor as claimed in claim 1, characterized in that, The gate structure includes a single gate electrode, and The fixed position of the single gate electrode within the accumulation region and the filling level of the conductive fluid within the accumulation region result in: When the channel region is parallel to the top surface of the conductive fluid, the single gate electrode contacts the conductive fluid, and When the channel region forms an angle with respect to the top surface of the conductive fluid at at least a certain angle, the single gate electrode is physically separated from the conductive fluid.

3. The transistor as claimed in claim 1, characterized in that, The gate structure includes: a first gate electrode adjacent to a first side of the accumulation region; and a second gate electrode adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, the first gate electrode and the second gate electrode are in contact with the conductive fluid. When the channel region forms an angle with respect to the top surface of the conductive fluid at a first angle, the first gate electrode is physically separated from the conductive fluid, while the second gate electrode remains in contact with the conductive fluid. When the channel region forms an angle with respect to the top surface of the conductive fluid at a second angle, the second gate electrode is physically separated from the conductive fluid, while the first gate electrode remains in contact with the conductive fluid.

4. The transistor as claimed in claim 1, characterized in that, The gate structure includes: a first gate electrode comprising a stack of electrically isolated first sub-electrodes adjacent to a first side of the accumulation region; and a second gate electrode comprising a stack of electrically isolated second sub-electrodes adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, all the first sub-electrodes and all the second sub-electrodes are in contact with the conductive fluid. When the channel region forms a gradually increasing first-level angle relative to the top surface of the conductive fluid, the first sub-electrode physically separates from the conductive fluid sequentially from top to bottom, while the second sub-electrode remains in contact with the conductive fluid. When the channel region forms a gradually increasing second-level angle relative to the top surface of the conductive fluid, the second sub-electrode is physically separated from the conductive fluid sequentially from top to bottom, while the first sub-electrode remains in contact with the conductive fluid.

5. The transistor as claimed in claim 1, characterized in that, The gate structure includes: a first gate electrode comprising a stack of electrically isolated first sub-electrodes adjacent to a first side of the accumulation region; and a second gate electrode comprising a stack of electrically isolated second sub-electrodes adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, the lower first sub-electrode of the first sub-electrode and the lower second sub-electrode of the second sub-electrode are in contact with the conductive fluid, while the upper first sub-electrode of the first sub-electrode and the upper second sub-electrode of the second sub-electrode are physically separated from the conductive fluid. When the channel region forms a gradually increasing first-level angle relative to the top surface of the conductive fluid, the lower first sub-electrode of the first sub-electrode physically separates from the conductive fluid sequentially from top to bottom, and the upper second sub-electrode of the second sub-electrode contacts the conductive fluid sequentially from bottom to top. When the channel region forms an angle with the top surface of the conductive fluid at a gradually increasing second angle, the lower second sub-electrode of the second sub-electrode is physically separated from the conductive fluid from top to bottom, and the upper first sub-electrode of the first sub-electrode contacts the conductive fluid from bottom to top.

6. The transistor as claimed in claim 1, characterized in that, The gate structure includes more than two gate electrodes located at fixed positions within the accumulation region.

7. The transistor as claimed in claim 1, characterized in that, The accumulation area is covered to prevent leakage of the conductive fluid.

8. A motion detection system, characterized in that, include: A transistor, located on a chip, comprising: Channel area; and A gate structure, adjacent to the channel region and including: Accumulation zone, configured to contain conductive fluid; The gate dielectric layer is located at the bottom of the accumulation region; and At least one gate electrode is located at a fixed position within the accumulation region and between the bottom and top of the accumulation region, wherein the conductive fluid is adjacent to and completely covers the gate dielectric layer, wherein the orientation of the channel region relative to the top surface of the conductive fluid depends on the movement of the transistor, and wherein the contact between the at least one gate electrode and the conductive fluid depends on the orientation of the channel region relative to the top surface of the conductive fluid. A bias circuit, electrically connected to the transistor, wherein the bias circuit is configured to apply specific bias conditions to the transistor; and A sensing circuit electrically connected to the transistor, wherein the sensing circuit is configured to sense at least one electrical property of the transistor in response to the particular bias condition.

9. The motion detection system as described in claim 8, characterized in that, The gate structure includes a single gate electrode. The fixed position of the single gate electrode within the accumulation region and the filling level of the conductive fluid within the accumulation region result in: When the channel region is parallel to the top surface of the conductive fluid, the single gate electrode contacts the conductive fluid, and When the channel region forms an angle of at least a certain level relative to the top surface of the conductive fluid, the individual gate electrode is physically separated from the conductive fluid. This specific bias condition includes a fixed drain-source voltage and a fixed gate voltage. This electrical property is the drain current. The drain current indicates whether the transistor is in the off state, and This off state indicates either chip tilting or chip acceleration.

10. The motion detection system as described in claim 8, characterized in that, The gate structure includes: a first gate electrode adjacent to a first side of the accumulation region; and a second gate electrode adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, the first gate electrode and the second gate electrode are in contact with the conductive fluid. When the channel region forms an angle of at least a first angle with respect to the top surface of the conductive fluid, the first gate electrode is physically separated from the conductive fluid, while the second gate electrode remains in contact with the conductive fluid. When the channel region forms an angle of at least a second angle with respect to the top surface of the conductive fluid, the second gate electrode is physically separated from the conductive fluid, while the first gate electrode remains in contact with the conductive fluid. The specific bias conditions include a fixed drain-source voltage, a fixed first gate voltage on the first gate electrode, and a fixed second gate voltage on the second gate electrode. The fixed first gate voltage is less than the fixed second gate voltage. This electrical property is the drain current, and The drain current indicates either the chip tilt direction and angle, or the chip acceleration direction and rate.

11. The motion detection system as described in claim 8, characterized in that, The gate structure includes: a first gate electrode comprising a stack of electrically isolated first sub-electrodes adjacent to a first side of the accumulation region; and a second gate electrode comprising a stack of electrically isolated second sub-electrodes adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, all the first sub-electrodes and all the second sub-electrodes are in contact with the conductive fluid. When the channel region forms an angle with respect to the top surface of the conductive fluid at a gradually increasing first angle, the first sub-electrode physically separates from the conductive fluid sequentially from top to bottom, while the second sub-electrode remains in contact with the conductive fluid. When the channel region forms an angle with respect to the top surface of the conductive fluid at a gradually increasing second angle, the second sub-electrode physically separates from the conductive fluid sequentially from top to bottom, while the first sub-electrode remains in contact with the conductive fluid. The specific bias conditions include a fixed drain-source voltage, a fixed first gate voltage on each of the first sub-electrodes, and a fixed second gate voltage on each of the second sub-electrodes. The fixed first gate voltage is less than the fixed second gate voltage. This electrical property is the drain current, and The drain current indicates either the chip tilt direction and angle, or the chip acceleration direction and rate.

12. The motion detection system as described in claim 8, characterized in that, The gate structure includes: a first gate electrode comprising a stack of electrically isolated first sub-electrodes adjacent to a first side of the accumulation region; and a second gate electrode comprising a stack of electrically isolated second sub-electrodes adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, the lower first sub-electrode of the first sub-electrode and the lower second sub-electrode of the second sub-electrode are in contact with the conductive fluid, while the upper first sub-electrode of the first sub-electrode and the upper second sub-electrode of the second sub-electrode are physically separated from the conductive fluid. When the channel region forms an angle with respect to the top surface of the conductive fluid at a gradually increasing first angle, the lower first sub-electrode of the first sub-electrode physically separates from the conductive fluid sequentially from top to bottom, and the upper second sub-electrode of the second sub-electrode contacts the conductive fluid sequentially from bottom to top. When the channel region forms an angle with respect to the top surface of the conductive fluid at a gradually increasing second angle, the lower second sub-electrode of the second sub-electrode physically separates from the conductive fluid sequentially from top to bottom, and the upper first sub-electrode of the first sub-electrode contacts the conductive fluid sequentially from bottom to top. The specific bias conditions include a fixed drain-source voltage, a fixed first gate voltage on each of the first sub-electrodes, and a fixed second gate voltage on each of the second sub-electrodes. The fixed first gate voltage is less than the fixed second gate voltage, and This electrical property is the drain current, and The drain current indicates either the chip tilt direction and angle, or the chip acceleration direction and rate.

13. The motion detection system as described in claim 8, characterized in that, The gate structure includes more than two gate electrodes located at fixed positions within the accumulation region.

14. The motion detection system as described in claim 8, characterized in that, The accumulation area is covered to prevent leakage of the conductive fluid.

15. A motion detection method, characterized in that, include: A specific bias condition is applied to a transistor located on the chip via a bias circuit, wherein the transistor includes: Channel area; and A gate structure, adjacent to the channel region and including: Accumulation zone, configured to contain conductive fluid; The gate dielectric layer is located at the bottom of the accumulation region; and At least one gate electrode is located at a fixed position within the accumulation region and between the bottom and top of the accumulation region, wherein the conductive fluid is adjacent to and completely covers the gate dielectric layer, wherein the orientation of the channel region relative to the top surface of the conductive fluid depends on the movement of the chip, and wherein the contact between the at least one gate electrode and the conductive fluid depends on the orientation of the channel region relative to the top surface of the conductive fluid; and The sensing circuit senses at least one electrical property of the transistor in response to the specific bias condition.

16. The motion detection method as described in claim 15, characterized in that, The gate structure includes a single gate electrode. The fixed position of the single gate electrode and the filling level of the conductive fluid in the accumulation region result in: When the channel region is parallel to the top surface of the conductive fluid, the single gate electrode contacts the conductive fluid, and When the channel region forms an angle of at least one specific angle with respect to the top surface of the conductive fluid, the single gate electrode is physically separated from the conductive fluid. This specific bias condition includes a fixed drain-source voltage and a fixed gate voltage. This electrical property is the drain current. The method also includes determining whether the transistor is in a turned-off state based on the drain current, and This off state indicates that the chip is in either tilt or acceleration mode.

17. The motion detection method as described in claim 15, characterized in that, The gate structure includes: a first gate electrode adjacent to a first side of the accumulation region; and a second gate electrode adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, the first gate electrode and the second gate electrode are in contact with the conductive fluid. When the channel region forms an angle of at least a first angle with respect to the top surface of the conductive fluid, the first gate electrode is physically separated from the conductive fluid, while the second gate electrode remains in contact with the conductive fluid. When the channel region forms an angle of at least a second angle with respect to the top surface of the conductive fluid, the second gate electrode is physically separated from the conductive fluid, while the first gate electrode remains in contact with the conductive fluid. The specific bias conditions include a fixed drain-source voltage, a fixed first gate voltage on the first gate electrode, and a fixed second gate voltage on the second gate electrode. The fixed first gate voltage is less than the fixed second gate voltage. This electrical property is the drain current, and The method also includes estimating either the chip tilt direction and angle, or the chip acceleration direction and rate, based on the drain current.

18. The motion detection method as described in claim 15, characterized in that, The gate structure includes: a first gate electrode comprising a stack of electrically isolated first sub-electrodes adjacent to a first side of the accumulation region; and a second gate electrode comprising a stack of electrically isolated second sub-electrodes adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, all the first sub-electrodes and all the second sub-electrodes are in contact with the conductive fluid. When the channel region forms an angle with respect to the top surface of the conductive fluid at a gradually increasing first angle, the first sub-electrode physically separates from the conductive fluid sequentially from top to bottom, while the second sub-electrode remains in contact with the conductive fluid. When the channel region forms an angle with respect to the top surface of the conductive fluid at a gradually increasing second angle, the second sub-electrode physically separates from the conductive fluid sequentially from top to bottom, while the first sub-electrode remains in contact with the conductive fluid. The specific bias conditions include a fixed drain-source voltage, a fixed first gate voltage on each of the first sub-electrodes, and a fixed second gate voltage on each of the second sub-electrodes. The fixed first gate voltage is less than the fixed second gate voltage. This electrical property is the drain current, and The method also includes estimating either the chip tilt direction and angle, or the chip acceleration direction and rate, based on the drain current.

19. The motion detection method as described in claim 15, characterized in that, The gate structure includes: a first gate electrode comprising a stack of electrically isolated first sub-electrodes adjacent to a first side of the accumulation region; and a second gate electrode comprising a stack of electrically isolated second sub-electrodes adjacent to a second side of the accumulation region. The fixed positions of the first gate electrode and the second gate electrode within the accumulation region, and the filling level of the conductive fluid within the accumulation region, result in: When the channel region is parallel to the top surface of the conductive fluid, the lower first sub-electrode of the first sub-electrode and the lower second sub-electrode of the second sub-electrode are in contact with the conductive fluid, while the upper first sub-electrode of the first sub-electrode and the upper second sub-electrode of the second sub-electrode are physically separated from the conductive fluid. When the channel region forms an angle with respect to the top surface of the conductive fluid at a gradually increasing first angle, the lower first sub-electrode of the first sub-electrode physically separates from the conductive fluid sequentially from top to bottom, and the upper second sub-electrode of the second sub-electrode contacts the conductive fluid sequentially from bottom to top. When the channel region forms an angle with respect to the top surface of the conductive fluid at a gradually increasing second angle, the lower second sub-electrode of the second sub-electrode physically separates from the conductive fluid sequentially from top to bottom, and the upper first sub-electrode of the first sub-electrode contacts the conductive fluid sequentially from bottom to top. The specific bias conditions include a fixed drain-source voltage, a fixed first gate voltage on each of the first sub-electrodes, and a fixed second gate voltage on each of the second sub-electrodes. The fixed first gate voltage is less than the fixed second gate voltage, and This electrical property is the drain current, and The method also includes estimating either the chip tilt direction and angle, or the chip acceleration direction and rate, based on the drain current.

20. The motion detection method as described in claim 15, characterized in that, The gate structure includes more than two gate electrodes located at fixed positions within the accumulation region, and The accumulation area is covered to prevent leakage of the conductive fluid.

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