Patch Device Loss Testing Apparatus and Method

Abstract

This application relates to a loss test device and method for a chip component. The device includes: a test board; a plurality of first test lines, the first ends of which are located within a set area of the test board and arranged in a multi-row and two-column array, and the second ends are located outside the set area of the test board and have the same loss; at least one second test line, the loss of which is equal to the loss of one or two first test lines; a plurality of ground lines, which are provided between adjacent two first test lines, between the second test line and the first test line; a network analyzer, which is used to respectively connect the second ends of the two first test lines welded to the chip component and at least one ground line after the chip component is welded to the first ends of at least two first test lines, to determine the loss of the test circuit, and respectively connect the two ends of the second test line and at least one ground line to determine the loss of the de-embedded circuit, so as to obtain the loss of the chip component according to the loss of the test circuit and the loss of the de-embedded circuit. This application can meet the actual needs.

Description

Technical Field

[0001] This application relates to the field of testing technologies, and particularly to a loss testing device and method for patch devices. Background Art

[0002] With the development of communication technologies, better requirements are put forward for the performance of patch devices such as capacitors and inductors. The loss of patch devices will have a crucial impact on signal transmission, and accurately measuring the loss of patch devices is an accurate measurement of the device performance.

[0003] In traditional technologies, a patch device is fixed by a fixture, and an impedance analyzer is used to test the patch device to obtain the loss of the patch device. However, the current testing methods cannot meet the actual needs. Summary of the Invention

[0004] Based on this, it is necessary to provide a loss testing device and method for patch devices that can meet the actual needs in view of the above technical problems.

[0005] A loss testing device for patch devices, the device includes:

[0006] A test board;

[0007] Multiple first test lines, arranged on the test board at intervals; the first ends of the multiple first test lines are located within a set area of the test board and are arranged in an array of multiple rows and two columns, and the second ends of the multiple first test lines are located outside the set area of the test board; the losses of the multiple first test lines are the same;

[0008] At least one second test line, arranged on the test board; the loss of one second test line is equal to the loss of one or two first test lines;

[0009] Multiple ground lines, arranged on the test board and connected to each other; ground lines are provided between adjacent two first test lines, between the second test line and the first test lines;

[0010] A network analyzer, configured to, after a patch device is welded to the first ends of at least two first test lines, connect the second ends of the two first test lines to which the patch device is welded and at least one ground line respectively to determine the loss of the test circuit, and connect the two ends of the second test line and at least one ground line respectively to determine the loss of the de-embedded circuit, so as to obtain the loss of the patch device according to the loss of the test circuit and the loss of the de-embedded circuit.

[0011] In one embodiment, the lengths of the first test lines are the same.

[0012] In one embodiment, the second end of the first test line and both ends of the second test line are located at the edge of the test board.

[0013] In one embodiment, conductors penetrating the test board are provided at both ends of the ground wire, and the conductors are used to ground the network analyzer.

[0014] In one embodiment, the device further includes:

[0015] At least two connectors, having a first through-hole and two second through-holes; the first through-hole extends to the second end of the first test line or one end of the second test line for placing the test head of the network analyzer; the two second through-holes are located on opposite sides of the first through-hole, and fasteners penetrating the test board are provided in the second through-holes, and the connectors are fixed to the test board through the fasteners.

[0016] In one embodiment, third through-holes are provided at both ends of the ground wire, and the third through-holes are used to set conductors or fasteners.

[0017] In one embodiment, the first test line, the second test line, and the ground wire extend along the row direction of the array.

[0018] In one embodiment, the first test line is alternately arranged with the ground wire in the column direction of the array.

[0019] In one embodiment, two ground wires are provided between the first test line and the second test line.

[0020] A method for testing the loss of a chip device, the method including:

[0021] Providing a test board; wherein, multiple first test lines, at least one second test line, and multiple ground wires are provided on the test board, and the multiple first test lines and the at least one second test line are arranged at intervals; the first ends of the multiple first test lines are located within a set area of the test board and are arranged in an array of multiple rows and two columns, and the second ends of the multiple first test lines are located outside the set area of the test board; the losses of the multiple first test lines are the same, and the loss of one second test line is equal to the loss of one or two first test lines; the multiple ground wires are connected to each other, and the ground wires are provided between adjacent two first test lines, between the second test line and the first test line;

[0022] Welding the chip device to the first ends of at least two of the first test lines;

[0023] Connect the network analyzer to the second ends of the two first test lines to which the patch device is welded and at least one ground wire respectively, so as to obtain the loss of the test line;

[0024] Connect the network analyzer to both ends of the second test line and at least one ground wire respectively, so as to obtain the loss of the de-embedded line;

[0025] Determine the loss of the patch device according to the loss of the test line and the loss of the de-embedded line.

[0026] In the above patch device loss testing device and method, a plurality of first test lines, at least one second test line and a plurality of ground wires are arranged on the test board. The plurality of first test lines and at least one second test line are arranged at intervals from each other, and the first ends of the plurality of first test lines are located within the set area of the test board and arranged in an array of multiple rows and two columns. The patch device can be welded to the first ends of at least two first test lines, so as to fix the patch device on the test board and realize electrical connection with at least two first test lines. The second ends of the plurality of first test lines are located outside the set area of the test board. The plurality of ground wires are connected to each other, and a ground wire is provided between two adjacent first test lines. Connect the network analyzer to the second ends of the two first test lines to which the patch device is welded and at least one ground wire respectively, and the loss of the test line can be obtained. The losses of the plurality of first test lines are the same. The loss of one second test line is equal to the loss of one or two first test lines, and a ground wire is provided between the second test line and the first test line. Connect the network analyzer to both ends of the second test line and at least one ground wire respectively, and the loss of the de-embedded line can be obtained. Furthermore, according to the loss of the test line and the loss of the de-embedded line, the loss of the patch device can be determined. In this way, the patch device is fixed on the test board by welding, and the connection is firm, which can avoid introducing error factors such as poor contact. And by using the network analyzer to determine the losses of the test line and the de-embedded line respectively, the test error introduced by the test board can be eliminated, the test accuracy is high, and the accuracy of the test result can meet the actual needs. The connection between the patch device and the test board is firm, the test frequency range of the network analyzer is relatively wide, and the highest test frequency of the whole device can reach 110 GHz. The test frequency range can meet the actual needs. In addition, the first ends of multiple first test lines can be welded to patch devices with different numbers of pins, and the types of devices that can be tested are not limited, which can also meet the actual needs. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings.

[0028] Figure 1 It is a schematic structural diagram of a loss test device for a chip device in an embodiment;

[0029] Figure 2 It is a schematic structural diagram of a test board in an embodiment;

[0030] Figure 3 It is a schematic diagram of the principle for obtaining the loss of a chip device in an embodiment;

[0031] Figure 4 It is a schematic electrical connection diagram of a network analyzer and a test board in an embodiment;

[0032] Figure 5 It is a schematic structural diagram of a connector in an embodiment;

[0033] Figure 6 It is a schematic structural diagram of a test board in another embodiment;

[0034] Figure 7 It is a schematic flow diagram of a method for testing the loss of a chip device in an embodiment.

[0035] Explanation of reference numerals:

[0036] 10 - Test board;

[0037] 11 - First test line, 111 - First connection pad;

[0038] 12 - Second test line, 121 - Second connection pad;

[0039] 13 - Ground wire, 131 - Conductor, 132 - Third through hole;

[0040] 20 - Network analyzer, 21 - Test head, 22 - Probe;

[0041] 30 - Connector, 31 - First through hole, 32 - Second through hole;

[0042] 40 - Fastener, 41 - Bolt, 42 - Nut. Detailed implementation manners

[0043] For the convenience of understanding the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0045] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0046] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to the other element or connected to the other element through an intermediate element. In addition, in the following embodiments, "connection", if there is a transfer of electrical signals or data between the connected objects, should be understood as "electrical connection", "communication connection", etc.

[0047] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include", "has" or the like specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0048] As described in the background art, there are problems in the existing testing methods that cannot meet the actual needs. After research by the inventor, it is found that the reason for this problem is that the fixture fixes the patch device by clamping. The volume of the patch device is small, and it is easy to have an unstable clamping situation, introducing test errors, resulting in poor accuracy of the test results and unable to meet the actual needs. Moreover, the fixture and the patch device are connected in a contact manner, and the connection stability is poor. Coupled with the limited measurement frequency of the impedance analyzer, the measurable frequency is low, and frequencies above 120 MHz cannot be measured to meet the actual needs. In addition, due to the limitation of the fixture structure, only patch devices with two terminals such as capacitors and inductors can be tested, and patch devices with multiple pins such as triodes and filters cannot be tested. The types of devices that can be tested are limited and cannot meet the actual needs.

[0049] For the above reasons, the present invention provides a patch device loss test apparatus and method. A plurality of first test lines, at least one second test line, and a plurality of ground lines are provided on a test board. The plurality of first test lines and the at least one second test line are arranged at intervals from each other. And the first ends of the plurality of first test lines are located within a set area of the test board and are arranged in an array of multiple rows and two columns. A patch device can be soldered to the first ends of at least two first test lines, thereby fixing the patch device on the test board and achieving electrical connection with at least two first test lines. The second ends of the plurality of first test lines are located outside the set area of the test board. The plurality of ground lines are connected to each other, and a ground line is provided between adjacent two first test lines. By connecting a network analyzer to the second ends of the two first test lines to which the patch device is soldered and at least one ground line respectively, the loss of the test circuit can be obtained. The losses of the plurality of first test lines are the same. The loss of one second test line is equal to the loss of one or two first test lines. And a ground line is provided between the second test line and the first test line. By connecting the network analyzer to the two ends of the second test line and at least one ground line respectively, the loss of the de-embedded circuit can be obtained. Furthermore, based on the loss of the test circuit and the loss of the de-embedded circuit, the loss of the patch device can be determined. In this way, the patch device is fixed on the test board by soldering, with a firm connection, which can avoid introducing error factors such as poor contact. And by using the network analyzer to determine the losses of the test circuit and the de-embedded circuit respectively, the test error introduced by the test board can be eliminated, with high test accuracy and the accuracy of the test results meeting the actual requirements. The connection between the patch device and the test board is firm. The test frequency range of the network analyzer is relatively wide, and the highest test frequency of the entire device can reach 110 GHz, and the test frequency range can meet the actual requirements. In addition, the first ends of multiple first test lines can be soldered to patch devices with different numbers of pins, and the types of devices that can be tested are not limited, which can also meet the actual requirements.

[0050] In one embodiment, as Figure 1 and Figure 2As shown in the figure, a loss test device for a patch device is provided, which includes a test board 10, a plurality of first test lines 11, at least one second test line 12, a plurality of ground lines 13, and a network analyzer 20. The plurality of first test lines 11 are arranged on the test board 10 at intervals. The first ends of the plurality of first test lines 11 are located within a set area of the test board 10 and are arranged in an array of multiple rows and two columns, and the second ends of the plurality of first test lines 11 are located outside the set area of the test board 10. The losses of the plurality of first test lines 11 are the same. At least one second test line 12 is arranged on the test board 10. The loss of one second test line 12 is equal to the loss of one or two first test lines 11. The plurality of ground lines 13 are arranged on the test board 10 and are connected to each other. Ground lines 13 are provided between two adjacent first test lines 11, and between the second test line 12 and the first test lines 11. The network analyzer 20 is used to, after the patch device is welded to the first ends of at least two first test lines 11, connect the second ends of the two first test lines 11 to which the patch device is welded and at least one ground line 13 respectively to determine the loss of the test line, and connect the two ends of the second test line 12 and at least one ground line 13 respectively to determine the loss of the de-embedded line, so as to obtain the loss of the patch device according to the loss of the test line and the loss of the de-embedded line.

[0051] Among them, the loss is the relationship between the output power and the input power.

[0052] Specifically, the test board 10 adopts a printed circuit board (English: Printed Circuit Board, abbreviated as: PCB), and the first test line 11, the second test line 12, and the ground line 13 are arranged on the test board 10 by means of electronic printing technology. In practical applications, a plurality of first test lines 11, at least one second test line 12, and a plurality of ground lines 13 that are spaced apart from each other are formed on the front surface of the test board 10, and a partial area of the ground line 13 penetrates to the back surface of the test board 10 for grounding, so that the plurality of ground lines 13 are connected to each other.

[0053] The network analyzer 20 is an instrument that can perform comprehensive microwave measurements. It can scan and measure within a wide frequency band. By using its own signal source to compare and measure whether the electrical characteristics and performance parameters of other electronic devices, electronic components, electronic parts, network connectors, cable lines, etc. meet the standards and requirements, it can accurately measure the amplitude and phase information in the incident wave, reflected wave, and transmitted wave, and quantitatively describe the reflection and transmission characteristics of the device under test through the ratio measurement method.

[0054] In the above patch device loss test device, multiple first test lines are arranged on the test board at intervals. The first ends of the multiple first test lines are located within a set area of the test board and are arranged in a multi-row and two-column array. A patch device can be welded to the first ends of at least two first test lines, so that the patch device is fixed on the test board and electrically connected to at least two first test lines. The second ends of the multiple first test lines are located outside the set area of the test board. Multiple ground lines are arranged on the test board and are connected to each other, and a ground line is provided between two adjacent first test lines. By connecting a network analyzer to the second ends of the two first test lines to which the patch device is welded and at least one ground line respectively, the loss of the test line can be obtained. The losses of the multiple first test lines are the same. The loss of one second test line is equal to the loss of one or two first test lines, and a ground line is provided between the second test line and the first test line. By connecting a network analyzer to the two ends of the second test line and at least one ground line respectively, the loss of the de-embedded line can be obtained. Furthermore, based on the loss of the test line and the loss of the de-embedded line, the loss of the patch device can be determined. In this way, the patch device is fixed on the test board by welding, with a firm connection, which can avoid introducing error factors such as poor contact. And by using a network analyzer to determine the losses of the test line and the de-embedded line respectively, the test error introduced by the test board can be eliminated, with high test accuracy, and the accuracy of the test result can meet the actual needs. The connection between the patch device and the test board is firm. The test frequency range of the network analyzer is relatively wide, and the highest test frequency of the entire device can reach 110 GHz, and the test frequency range can meet the actual needs. In addition, the first ends of multiple first test lines can be welded to patch devices with different numbers of pins, and the types of devices that can be tested are not restricted, which can also meet the actual needs.

[0055] In one embodiment, as Figure 2 shown, the widths a of the first test lines 11 are the same, which is convenient for the design and formation of multiple first test lines 11.

[0056] Exemplarily, as Figure 2 shown, the lengths b of the first test lines 11 are the same.

[0057] The widths of the first test lines 11 are usually the same. By defining that the lengths of the first test lines 11 are the same, it is convenient to achieve the same losses of multiple first test lines 11.

[0058] Specifically, the orthographic projection of the first test line 11 on the test board 10 is a rectangle, the length of the rectangle is the length of the first test line 11, and the width of the rectangle is the width of the first test line 11.

[0059] In one implementation, as Figure 2As shown, the width c of the second test line 12 is the same as the width a of the first test line 11, which facilitates the design and formation of the first test line 11 and the second test line 12.

[0060] In one implementation, the length of the second test line 12 is the same as the length of the first test line 11, and the loss of one second test line 12 can be made equal to the loss of one first test line 11.

[0061] In another implementation, the length of the second test line 12 is twice the length of the first test line 11, and the loss of one second test line 12 can be made equal to the loss of two first test lines 11.

[0062] In practical applications, as Figure 2 shown, the length of the second test line 12 is greater than twice the length of the first test line 11. At this time, the length difference is equal to the distance between the first ends of the two first test lines 11, so that the two ends of the second test line 12 can be aligned with the second ends of the two first test lines 11, which is conducive to the second ends of the first test lines 11 and the two ends of the second test line 12 being distributed on the edge of the test board 10 at the same time. Meanwhile, the distance between the first ends of the two first test lines 11 is equal to the distance between the two pins of the surface-mounted device. Since the distance between the two pins of the surface-mounted device is very short, the difference between the length of the second test line 12 and twice the length of the first test line 11 is small, and the loss of the second test line 12 is approximately equal to the loss of the two first test lines 11.

[0063] As Figure 3 shown, when the loss of one second test line 12 is equal to the loss of one or two first test lines 11, by measuring the loss of the second test line 12, the loss of the first test line 11 in the loss of the test line where the surface-mounted device is located can be removed, so as to obtain the loss of the surface-mounted device.

[0064] Exemplarily, as Figure 2 shown, the length d of the ground wire 13 is the same as the length e of the second test line 12, which facilitates the layout of the first test line 11, the second test line 12 and the ground wire 13 on the test board 10.

[0065] Exemplarily, as Figure 2 shown, the width f of the ground wire 13 is greater than the width c of the second test line 12, which is conducive to fully grounding the network analyzer 20 and reducing interference during the test.

[0066] In one embodiment, as Figure 2 shown, the second ends of the first test lines 11 and the two ends of the second test line 12 are located on the edge of the test board 10.

[0067] In this embodiment, the second end of the first test line 11 and both ends of the second test line 12 are located at the edge of the test board 10, which facilitates the electrical connection of the probes of the network analyzer 20 and reduces the area of the test board 10 at the same time.

[0068] Exemplarily, both ends of the ground wire 13 are located at the edge of the test board 10 and are aligned with the second end of the first test line 11 and both ends of the second test line 12, which facilitates the network analyzer 20 to be electrically connected to the first test line 11 and the ground wire 13 at the same time, or to be electrically connected to the second test line 12 and the ground wire 13 at the same time.

[0069] In one embodiment, as Figure 2 shown, conductors 131 penetrating the test board 10 are provided at both ends of the ground wire 13, and the conductors 131 are used to ground the network analyzer 20.

[0070] In this embodiment, conductors 131 penetrating the test board 10 are provided at both ends of the ground wire 13, and the probes of the network analyzer 20 are pressed on the ground wire 13, so that the network analyzer 20 can be grounded.

[0071] In practical applications, as Figure 4 shown, the network analyzer 20 is electrically connected to the test board 10 through two test heads 21, and each test head 21 includes three probes 22 arranged side by side. The probe 22 in the middle is electrically connected to the second end of the first test line 11 or one end of the second test line 12, realizing the electrical connection between the network analyzer 20 and the first test line 11 or the second test line 12; the probes 22 on both sides are electrically connected to one end of the ground wire 13, realizing the grounding of the network analyzer 20.

[0072] In one embodiment, as Figure 5 shown, the device further includes at least two connectors 30, and the connector 30 has a first through hole 31 and two second through holes 32. The first through hole 31 extends to the second end of the first test line 11 or one end of the second test line 12 and is used to place the test head of the network analyzer 20. The two second through holes 32 are located on opposite sides of the first through hole 31, and fasteners 40 penetrating the test board 10 are provided in the second through holes 32, and the connector 30 is fixed to the test board 10 through the fasteners 40.

[0073] In this embodiment, at least two connectors 30 are provided on the test board 10. Each connector 30 has a first through hole 31 extending to the second end of the first test line 11 or one end of the second test line 12. The test head of the network analyzer 20 is placed in the first through hole 31, and the probe on the test head contacts the second end of the first test line 11 or the second test line 12, so that the network analyzer 20 can be electrically connected to the first test line 11 or the second test line 12. Each connector 30 also has two second through holes 32 located on opposite sides of the first through hole 31. A fastener 40 passing through the test board 10 is provided in each second through hole 32. On the one hand, the connector 30 can be fixed on the test board 10, which is beneficial to the stable electrical connection between the network analyzer 20 and the first test line 11 or the second test line 12 and improves the accuracy of the test results. On the other hand, when the test head of the network analyzer 20 contacts the connector 30, the network analyzer 20 can be grounded. In addition, the connector 30 has excellent performance and will not be damaged after multiple uses, and the implementation cost is low.

[0074] In practical applications, the network analyzer is electrically connected to the test board 10 through two test heads. Each test head may include a probe and a housing. The probe is insulated and arranged on the housing. The housing is inserted into the first through hole 31 of the connector 30, and the probe abuts against the second end of the first test line 11 or one end of the second test line 12, so as to realize the electrical connection between the network analyzer 20 and the first test line 11 or the second test line 12. A fastener 40 passing through the test board 10 is provided in the second through hole 32 of the connector 30 to ground the network analyzer 20.

[0075] Exemplarily, as Figure 5 shown, the depth of the first through hole 31 is greater than the depth of the second through hole 32.

[0076] In this embodiment, the larger depth of the first through hole 31 is beneficial to fixing the test head inserted in the first through hole 31. The smaller depth of the second through hole 32 is beneficial to the fastener 40 to fix the connector 30 on the test board 10.

[0077] In practical applications, an external thread is provided on the test head, and an internal thread 33 (as Figure 5 shown) matching the external thread is provided on the first through hole 31. The test head can be threadedly connected in the first through hole 31, which is beneficial to the stable electrical connection between the probe on the test head and the first test line 11 or the second test line 12.

[0078] Specifically, as Figure 5 shown, the fastener 40 includes a bolt 41 and a nut 42. The bolt 41 passes through the second through hole 32 and is threadedly connected to the nut 42.

[0079] Exemplarily, as Figure 2 orFigure 5 As shown, both ends of the ground wire 13 have third through holes 132 for setting a conductor 131 or a fastener 40.

[0080] In the above embodiment, as Figure 6 shown, the second end of the first test line 11 is provided with a first connection pad 111, and the diameter of the first connection pad 111 is greater than the width of the first test line 11; both ends of the second test line 12 are provided with second connection pads 121, and the diameter of the second connection pads 121 is greater than the width of the second test line 12.

[0081] By providing the first connection pad 111 at the second end of the first test line 11 and making the diameter of the first connection pad 111 greater than the width of the first test line 11, it is convenient for the probe on the test head to be electrically connected to the first test line 11. By providing the second connection pads 121 at both ends of the second test line 12 and making the diameter of the second connection pads 121 greater than the width of the second test line 12, it is convenient for the probe on the test head to be electrically connected to the second test line 12.

[0082] In one embodiment, as Figure 2 and Figure 6 shown, the first test line 11, the second test line 12, and the ground wire 13 extend along the row direction of the array.

[0083] In this embodiment, the first test line 11, the second test line 12, and the ground wire 13 extend in the same direction, which is convenient for arranging the first test line 11, the second test line 12, and the ground wire 13 on the test board 10 and is beneficial to reducing the area of the test board 10.

[0084] In one embodiment, as Figure 2 and Figure 6 shown, the first test line 11 and the ground wire 13 are alternately arranged in the column direction of the array.

[0085] In this embodiment, the first test line 11 and the ground wire 13 are alternately arranged in the column direction of the array. On the basis of ensuring that there are ground wires 13 on both opposite sides of each first test line 11, the number of ground wires 13 is reduced, the area of the test board 10 is reduced, and the implementation cost of the device is lowered.

[0086] In one embodiment, as Figure 2 and Figure 6 shown, there are two ground wires 13 provided between the first test line 11 and the second test line 12.

[0087] In this embodiment, there are two ground wires 13 provided between the first test line 11 and the second test line 12. In this way, there are independent ground wires 13 on both opposite sides of the second test line 12, which can minimize the influence of the surface-mounted device on the de-embedded circuit and improve the accuracy of the test result.

[0088] Based on the same inventive concept, a method for testing the loss of a chip device is also provided. As Figure 7 shown, the method includes:

[0089] Step S702: Provide a test board.

[0090] Among them, multiple first test lines, at least one second test line, and multiple ground lines are provided on the test board. The multiple first test lines and the at least one second test line are arranged at intervals. The first ends of the multiple first test lines are located within a set area of the test board and are arranged in a multi-row and two-column array, and the second ends of the multiple first test lines are located outside the set area of the test board. The losses of the multiple first test lines are the same, and the loss of one second test line is equal to the loss of one or two first test lines. The multiple ground lines are connected to each other, and ground lines are provided between adjacent two first test lines, between the second test line and the first test line.

[0091] Specifically, this step S702 includes:

[0092] Form multiple first test lines, at least one second test line, and multiple ground lines on the first surface of the test board, and penetrate both ends of each ground line to the second surface of the test board to connect the multiple ground lines to each other; where the second surface is the opposite surface of the first surface.

[0093] Step S704: Weld the chip device to the first ends of at least two first test lines.

[0094] In practical applications, the number of first test lines to which the chip device is welded is the same as the number of pins of the chip device.

[0095] Step S706: Connect the network analyzer to the second ends of two first test lines to which the chip device is welded and at least one ground line respectively to obtain the loss of the test line.

[0096] In practical applications, the ground line connected by the network analyzer is located on the opposite sides of the first test line connected by the network analyzer.

[0097] Step S708: Connect the network analyzer to both ends of the second test line and at least one ground line respectively to obtain the loss of the de-embedded line.

[0098] In practical applications, the ground line connected by the network analyzer is located on the opposite sides of the second test line connected by the network analyzer.

[0099] Step S710: Determine the loss of the chip device according to the loss of the test line and the loss of the de-embedded line.

[0100] Specifically, this step S710 includes:

[0101] Subtract the loss of the test line from the loss of the de-embedded line to obtain the loss of the chip device.

[0102] In practical applications, the network analyzer comes with an Automatic Fixture Removal (AFR) function. After measuring the losses of the test line and the de-embedded line respectively, the loss of the chip device can be obtained.

[0103] Optionally, before steps S706 and S708, the method further includes:

[0104] Electrically connect the RF probe to the network analyzer through an RF cable;

[0105] Perform probe calibration using a probe calibration wafer.

[0106] Correspondingly, after step S704, the method further includes:

[0107] Fix the test board on the probe station.

[0108] It should be understood that although Figure 7 the steps in the flowchart of Figure 7 are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover,

[0109] At least a part of the steps in

[0110] may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of the steps or stages in other steps.

[0109] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0110] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0111] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A loss testing device for a chip component, characterized in that The device includes: A test board; A plurality of first test lines, which are arranged on the test board at intervals; the first ends of the plurality of first test lines are located within a set area of the test board and are arranged in an array of multiple rows and two columns, and the second ends of the plurality of first test lines are located outside the set area of the test board; the losses of the plurality of first test lines are the same; At least one second test line, which is arranged on the test board; the loss of one second test line is equal to the loss of one or two of the first test lines; A plurality of ground lines, which are arranged on the test board and are connected to each other; ground lines are provided between adjacent first test lines in different rows, and between the second test line and the first test lines; A network analyzer, which is used to connect the second ends of two first test lines welded to the patch device and at least one ground line respectively after the patch device is welded to the first ends of at least two first test lines, to determine the loss of the test line, and connect the two ends of the second test line and at least one ground line respectively to determine the loss of the de-embedded line, so as to obtain the loss of the patch device according to the loss of the test line and the loss of the de-embedded line.

2. The device according to claim 1, characterized in that The lengths of the first test lines are the same.

3. The device according to claim 2, characterized in that, The second ends of the first test lines and the two ends of the second test line are located at the edge of the test board.

4. The device according to claim 3, characterized in that Conductors penetrating the test board are provided at both ends of the ground line, and the conductors are used to ground the network analyzer.

5. The device according to claim 3, characterized in that, The device further includes: At least two connectors, which have a first through hole and two second through holes; the first through hole extends to the second end of the first test line or one end of the second test line, and is used to place the test head of the network analyzer; the two second through holes are located on opposite sides of the first through hole, and fasteners penetrating the test board are provided in the second through holes, and the connector is fixed to the test board through the fasteners.

6. The device according to claim 4 or 5, characterized in that, Third through holes are provided at both ends of the ground line, and the third through holes are used to set conductors or fasteners.

7. The device according to any one of claims 1 to 5, characterized in that, The first test line, the second test line and the ground line extend along the row direction of the array.

8. The device according to claim 7, characterized in that, The first test line and the ground line are alternately arranged in the column direction of the array.

9. The device according to claim 8, wherein Two ground lines are provided between the first test line and the second test line.

10. A method for testing the loss of a chip device, characterized in that, The method includes: Providing a test board; wherein, a plurality of first test lines, at least one second test line and a plurality of ground lines are provided on the test board, and the plurality of first test lines and the at least one second test line are arranged at intervals; the first ends of the plurality of first test lines are located within a set area of the test board and are arranged in an array of multiple rows and two columns, and the second ends of the plurality of first test lines are located outside the set area of the test board; the losses of the plurality of first test lines are the same, and the loss of one second test line is equal to the loss of one or two of the first test lines; the plurality of ground lines are connected to each other, and ground lines are provided between adjacent first test lines in different rows and between the second test line and the first test lines; Welding a patch device to the first ends of at least two first test lines; Connect the network analyzer to the second ends of the two first test lines soldered to the patch device and at least one ground wire respectively to obtain the loss of the test line; Connect the network analyzer to both ends of the second test line and at least one ground wire respectively to obtain the loss of the de-embedded line; Determine the loss of the patch device according to the loss of the test line and the loss of the de-embedded line.

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