Multi-screen display system

Abstract

The present application discloses a multi-screen display system, which includes: N display devices and a processor, where N is a positive integer greater than or equal to 2. The processor includes a plurality of system data pins, and the plurality of system data pins are divided into N groups of data pin groups. The number of pins in the Nth group of data pin groups corresponds to the number of display color levels of the Nth display device, and the Nth group of data pin groups is used to output horizontal image data and vertical image data of the Nth display device. The Nth display device captures the horizontal image data output by the Nth group of data pin groups in the horizontal effective time section, and captures the vertical image data output by the Nth group of data pin groups in the vertical effective time section. Therefore, the number of processors used in the current products with multi-screen display function can be saved, thereby reducing costs.

Description

Technical Field

[0001] The present application relates to a display system, and in particular to a multi-screen display system. Background Art

[0002] With the rapid development of science and technology, there are more and more devices with multiple display interfaces, such as foldable mobile phones with dual screens, three-dimensional display devices with multiple display surfaces, and other products. In other words, products with a single screen can no longer meet the needs of consumers. Therefore, products with multi-screen display functions are the future development trend.

[0003] Generally speaking, each display device needs to be paired with a processor, and the processor sends a set of timing control signals to control the display screen of the display device. For example, when a product with a multi-screen display function is equipped with two display devices, the two display devices will receive image data sent from different processors (one display device corresponds to one processor); in this case, the two display devices can capture image data according to different effective data times.

[0004] However, as the number of display devices increases, the number of processors in the above-mentioned products with multi-screen display functions also increases, which increases the cost of the product and makes it difficult for the product to be thin and small. Therefore, how to reduce the number of processors used in products with multi-screen display functions has become an urgent issue for products with multi-screen display functions. Summary of the invention

[0005] The main purpose of the present application is to provide a multi-screen display system to solve the problem in the prior art that products with multi-screen display functions have high costs and are difficult to develop into a thin and light product because each display device needs to be connected to a processor to control the display image.

[0006] In order to achieve the above purpose, this application is implemented as follows:

[0007] The present application provides a multi-screen display system, which includes: N display devices and a processor, where N is a positive integer greater than or equal to 2. The processor includes a plurality of system data pins, and the plurality of system data pins are divided into N groups of data pins. The number of pins in the Nth group of data pins corresponds to the number of display color levels of the Nth display device, and the Nth group of data pins is used to output horizontal image data and vertical image data of the Nth display device. The Nth display device captures the horizontal image data output by the Nth group of data pins in the horizontal effective time segment, and captures the vertical image data output by the Nth group of data pins in the vertical effective time segment.

[0008] In the embodiment of the present application, a processor is used to control the hardware wiring method of multiple display devices (multiple display devices share multiple system data pins of a processor), thereby reducing the usage of processors and peripheral devices of products with multi-screen display functions that use the multi-screen display system of the present application, thereby reducing the cost of products with multi-screen display functions and reducing the size of products with multi-screen display functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0010] Figure 1 A block diagram of an embodiment of a multi-screen display system according to the present application;

[0011] Figure 2 for Figure 1 A schematic diagram of a control method for a horizontal scanning period of an embodiment of a multi-screen display system;

[0012] Figure 3 for Figure 1 A schematic diagram of a control method for a vertical scanning period of an embodiment of a multi-screen display system;

[0013] Figure 4 for Figure 1 A schematic diagram of a control method for a horizontal scanning period of another embodiment of a multi-screen display system;

[0014] Figure 5 for Figure 1 A schematic diagram of a control method for a vertical scanning period of another embodiment of a multi-screen display system;

[0015] Figure 6 A block diagram of another embodiment of the multi-screen display system of the present application;

[0016] Figure 7 A schematic diagram of an embodiment of image data of the present application;

[0017] Figure 8 A schematic diagram of image data segmentation according to an embodiment of the present application;

[0018] Fig. 9 A schematic diagram of an embodiment of the control method of the present application;

[0019] Fig.10 A schematic diagram of another embodiment of the image data of the present application;

[0020] Fig.11 A schematic diagram of another embodiment of image data segmentation of the present application;

[0021] Fig.12 A schematic diagram of another embodiment of the control method of the present application;

[0022] Fig.13 A block diagram of another embodiment of the multi-screen display system of the present application;

[0023] Fig.14 A schematic diagram of another embodiment of the image data of the present application;

[0024] Fig.15 A schematic diagram of segmentation of image data according to another embodiment of the present application; and

[0025] Fig.16 This is a schematic diagram of another embodiment of the control method of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0027] It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processing, components and / or components, but do not exclude the addition of more technical features, values, method steps, operation processing, components, components, or any combination of the above.

[0028] It should be understood that when a component is described as being "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, and intermediate components may be present. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0029] See also Figure 1 , which is a block diagram of an embodiment of a multi-screen display system according to the present application. Figure 1 As shown, the multi-screen display system 100 includes: two display devices (i.e., display device 110a and display device 110b) and a processor 120. In this embodiment, the number of display devices is two, but this embodiment is not intended to limit the present application; for example, the number of display devices can be a positive integer greater than two.

[0030] In this embodiment, the processor 120 includes a system data pin 122a, a system data pin 122b, a system data pin 122c, a system data pin 122d, a system data pin 122e, a system data pin 122f, a system data pin 122g, and a system data pin 122h (i.e., the processor 120 includes a plurality of system data pins), wherein the system data pin 122a, the system data pin 122b, the system data pin 122c, and the system data pin 122d are a first group of data pins 50a, and the system data pin 122e, the system data pin 122f, the system data pin 122g, and the system data pin 122h are a second group of data pins 50b ( That is, multiple system data pins are divided into two groups of data pin groups), the first group of data pins 50a corresponds to the display color gradation number of the first display device 110a, and the second group of data pins 50b corresponds to the display color gradation number of the second display device 110b (that is, the number of pins in the Nth group of data pins corresponds to the display color gradation number of the Nth display device), the first group of data pins 50a is used to output the horizontal image data 81 and the vertical image data 91 of the first display device 110a, and the second group of data pins 50b is used to output the horizontal image data 82 and the vertical image data 92 of the second display device 110b (that is, the Nth group of data pins is used to output the horizontal image data and the vertical image data of the Nth display device).

[0031] In more detail, the system data pin 122a, the system data pin 122b, the system data pin 122c, the system data pin 122d, the system data pin 122e, the system data pin 122f, the system data pin 122g and the system data pin 122h are 8-bit data buses of the processor 120; the display device 110a includes a driving circuit 112a, and the driving circuit 112a includes a display pin group 114a; the display device 110b includes a driving circuit 112b, and the driving circuit 112b includes a display pin group 114b; when the display device 110a and the display device 110b respectively display four-bit (16-color gradation) color gradation data (that is, the display device 110a and the display device 110b do not need to display eight-bit (256-color gradation) color gradation data), the display device 110a and the display device 110b are connected. 10a and 10b can share the eight-bit data bus of the processor 120 (i.e., the first data pin group 50a including the system data pins 122a, 122b, 122c and 122d is connected to the display pin group 114a of the display device 110a, and the second data pin group 50b including the system data pins 122e, 122f, 122g and 122h is connected to the display pin group 114b of the display device 110b). In other words, a plurality of display devices can share the data bus with a plurality of bit widths of the processor 120 according to the number of color gradations displayed by themselves; in one embodiment, when the display device 110a displays three-bit (8-color gradation) color gradation data and the display device 110b displays six-bit (32-color gradation) color gradation data, the display device 110a and the display device 110b can share the nine-bit data bus of the processor 120. It should be noted that each display device included in the multi-screen display system 100 can display color gradation data of odd bits or color gradation data of even bits.

[0032] In this example, see Figures 1 to 3 , Figure 2 for Figure 1 A schematic diagram of a control method for a horizontal scanning period of an embodiment of a multi-screen display system, Figure 3 for Figure 1 A schematic diagram of a control method for a vertical scanning period of an embodiment of a multi-screen display system, wherein: Figure 2 It includes a waveform timing diagram of the output signal of the data pin group 50a and the data pin group 50b in a horizontal scanning cycle and a waveform timing diagram of the received signal of the display pin group 114a and the display pin group 114b, Figure 3The waveform timing diagram includes the waveform timing diagram of the output signal of the data pin group 50a and the data pin group 50b and the waveform timing diagram of the received signal of the display pin group 114a and the display pin group 114b in a vertical scanning cycle. Figures 1 to 3 As shown, since the first data pin group 50a is used to output the horizontal image data 81 and the vertical image data 91 of the first display device 110a, the first display device 110a is in the horizontal effective time section t HACT The horizontal image data 81 outputted by the first data pin group 50a is captured and the horizontal image data 81 is outputted by the first data pin group 50a during the vertical effective time period t VACT The vertical image data 91 outputted by the first data pin group 50a is captured; since the second data pin group 50b is used to output the horizontal image data 82 and the vertical image data 92 of the second display device 110b, the second display device 110b is in the horizontal effective time segment t HACT The horizontal image data 82 outputted by the second data pin group 50b is captured and the horizontal image data 82 ... outputted by the second data pin group 50b during the vertical effective time period t VACT The vertical image data 92 outputted by the second data pin group 50b is captured.

[0033] It should be noted that the horizontal image data output by each data pin group includes horizontal blanking data and horizontal valid data. The horizontal valid data is the horizontal image data output by each data pin group in the horizontal valid time segment t HACT The output data is also the pixel data of each row of valid pixels displayed by the corresponding connected display device; the vertical image data output by each group of data pins includes vertical blank data and vertical valid data, and the vertical valid data is the vertical blank data of each group of data pins in the vertical valid time segment t VACT The output data is also the row number data of the effective pixels of each frame displayed by the corresponding connected display device; therefore, each display device in the multi-screen display system 100 has a horizontal effective time segment t HACT Capture the horizontal image data output by the corresponding data pin group, and in the vertical effective time segment t VACT The vertical image data outputted by the corresponding data pin group is captured to display a picture data. In addition, Figure 2 and Figure 3 In the embodiment, the horizontal blank data and the vertical blank data output by the data pin group 50a and the data pin group 50b are invalid data for the display device 110a and the display device 110b, and therefore, are not drawn in Figure 2 and Figure 3 .

[0034] In one embodiment, when any two data pin groups have the same number of pins, the display devices connected to the two data pin groups have the same resolution. In more detail, since any two data pin groups have the same number of pins, it means that the number of bits of data received by the display devices connected to the two data pin groups is also the same, and therefore, the display devices connected to the two data pin groups have the same resolution.

[0035] See also Figures 1 to 3 In this embodiment, the processor 120 further includes a vertical synchronization pin 124, a horizontal synchronization pin 126 and a clock pin 128. The vertical synchronization pin 124 is used to output a vertical synchronization signal VS to the display device 110a and the display device 110b, the horizontal synchronization pin 126 is used to output a horizontal synchronization signal HS to the display device 110a and the display device 110b, and the clock pin 128 is used to output a clock signal DCLK to the display device 110a and the display device 110b; the driving mode of the display device 110a and the display device 110b can be a driving mode of a synchronization signal, and the clock signal DCLK is used to indicate the transmission frequency of the horizontal image data 81, 82; that is, the display device 110a and the display device 110b can be driven by the horizontal synchronization signal HS and the vertical synchronization signal VS. Among them, Figure 2 It also includes a waveform timing diagram of the output signals of the horizontal synchronization pin 126 and the clock pin 128 in a horizontal scanning cycle. Figure 3 It also includes a waveform timing diagram of the output signals of the vertical synchronization pin 124 and the horizontal synchronization pin 126 in a vertical scanning cycle.

[0036] Specifically, the horizontal image data output by each data pin group includes horizontal blank data and horizontal valid data, and the vertical image data output by each data pin group includes vertical blank data and vertical valid data. The display device 110a outputs the horizontal image data in the horizontal valid time segment t according to the clock signal DCLK and the horizontal synchronization signal HS. HACT The horizontal image data 81 outputted by the data pin group 50a is captured (ie, the horizontal image data 81 outputted by the data pin group 50a is captured during the horizontal effective time period t HACT Output horizontal valid data), and according to the horizontal synchronization signal HS and the vertical synchronization signal VS in the vertical effective time segment t VACT The vertical image data 91 outputted by the data pin group 50a is captured (ie, the vertical image data 91 outputted by the data pin group 50a in the vertical effective time section t VACT The driving circuit 112a and the driving circuit 112b can calculate the horizontal back porch time segment t of the output horizontal blanking data by using the pulse of the horizontal synchronization signal HS and its front porch period and back porch period.HBP The horizontal front time segment t HFP And the horizontal effective time period t of the output horizontal effective data HACT The driving circuit 112a and the driving circuit 112b can calculate the vertical back porch time segment t of the output vertical blank data by using the pulse of the vertical synchronization signal VS and its leading edge period and trailing edge period. VBP Time segment t with vertical front VFP And the vertical effective time period t of output vertical effective data VACT .

[0037] Similarly, the display device 110b generates a signal according to the clock signal DCLK and the horizontal synchronization signal HS in the horizontal effective time section t HACT The horizontal image data 82 outputted by the data pin group 50b is captured (ie, the horizontal image data 82 outputted by the data pin group 50b is captured during the horizontal effective time period t HACT Output horizontal valid data), and according to the horizontal synchronization signal HS and the vertical synchronization signal VS in the vertical effective time segment t VACT The vertical image data 92 outputted by the data pin group 50b is captured (ie, the vertical image data 92 outputted by the data pin group 50b in the vertical effective time section t VACT Output vertical valid data) to display a picture data.

[0038] In addition, since the data pin group 50a is in the horizontal trailing time section t HBP The horizontal front time segment t HFP Therefore, the display device 110a outputs horizontal blank data according to the clock signal DCLK and the horizontal synchronization signal HS in the horizontal back porch time segment t HBP The horizontal front time segment t HFP The horizontal image data 81 outputted by the data pin group 50a is not captured. HBP The horizontal front time segment t HFP The time period between the data pin group 50a outputting pixel data of different rows of valid pixels (ie, two adjacent horizontal valid data), that is, the horizontal back porch time period t HBP The horizontal front time segment t HFP The preparation time required for the data pin group 50a to output a horizontal valid data. HACT Located in the horizontal trailing edge time segment t HBP The horizontal front time segment t HFP The horizontal effective time period t HACT , horizontal trailing edge time segment t HBP The horizontal front time segment t HFP The sum of is one horizontal scanning period.

[0039] Similarly, since the data pin group 50b is in the horizontal trailing time section t HBP The horizontal front time segment t HFP Therefore, the display device 110b outputs horizontal blank data according to the clock signal DCLK and the horizontal synchronization signal HS in the horizontal back porch time section t HBP The horizontal front time segment t HFP The horizontal image data 82 outputted by the data pin group 50b is not captured. HBP The horizontal front time segment t HFP The time period between the pixel data of different rows of valid pixels (ie, two adjacent horizontal valid data) outputted by the data pin group 50b, that is, the horizontal back porch time period t HBP The horizontal front time segment t HFP The preparation time required for the data pin group 50b to output a horizontal valid data.

[0040] In addition, since the data pin group 50a is in the vertical back porch time section t VBP Time segment t with vertical front VFP Therefore, the display device 110a outputs vertical blank data according to the vertical synchronization signal VS and the horizontal synchronization signal HS in the vertical back porch time segment t VBP Time segment t with vertical front VFP The vertical image data outputted by the data pin group 50a is not captured. VBP Time segment t with vertical front VFP The time segment between the row number data of valid pixels of different frames outputted by the data pin group 50a (ie, two adjacent vertical valid data), that is, the vertical back porch time segment t VBP Time segment t with vertical front VFP The preparation time required for the data pin group 50a to output a vertical valid data. Vertical valid time section t VACT Located in the vertical trailing edge time segment t VBP Time segment t with vertical front VFP Between, vertical effective time segment t VACT , vertical back porch time segment t VBP Time segment t with vertical front VFP The sum of is a vertical scanning period.

[0041] Similarly, since the data pin group 50b is in the vertical back porch time segment t VBP Time segment t with vertical front VFPTherefore, the display device 110b outputs vertical blank data according to the vertical synchronization signal VS and the horizontal synchronization signal HS in the vertical back porch time segment t VBP The vertical image data outputted by the data pin group 50b is not captured during the vertical front porch time segment tVFP. VBP Time segment t with vertical front VFP The time segment between the row number data of valid pixels of different frames outputted by the data pin group 50b (ie, two adjacent vertical valid data), that is, the vertical back porch time segment t VBP Time segment t with vertical front VFP The preparation time required for the data pin group 50b to output one vertical valid data.

[0042] In one embodiment, see Figure 1 , Figure 4 and Figure 5 , Figure 4 for Figure 1 A schematic diagram of a control method for a horizontal scanning period of another embodiment of a multi-screen display system, Figure 5 for Figure 1 A schematic diagram of a control method for a vertical scanning period of another embodiment of a multi-screen display system. Figure 1 , Figure 4 and Figure 5 As shown, the processor 120 further includes a clock pin 128 and a data enable pin 129. The clock pin 128 is used to output a clock signal DCLK to the display device 110a and the display device 110b, and the data enable pin 129 is used to output a data enable signal DE to the display device 110a and the display device 110b. The driving mode of the display device 110a and the display device 110b can be a data-enabled driving mode, and the clock signal DCLK is used to indicate the transmission frequency of the horizontal image data. In other words, the display device 110a and the display device 110b can be driven by the data enable signal DE. Figure 4 It includes a waveform timing diagram of the output signals of the clock pin 128, the data enable pin 129, the data pin group 50a and the data pin group 50b in one horizontal scanning cycle, and a waveform timing diagram of the received signals of the display pin group 114a and the display pin group 114b, Figure 5 It includes a waveform timing diagram of output signals of the data enable pin 129, the data pin group 50a and the data pin group 50b, and a waveform timing diagram of received signals of the display pin group 114a and the display pin group 114b in a vertical scanning cycle.

[0043] Specifically, the horizontal image data output by each data pin group includes horizontal blank data and horizontal valid data, and the vertical image data output by each data pin group includes vertical blank data and vertical valid data. The display device 110a generates a plurality of data signals in the horizontal valid time segment t according to the data enable signal DE and the clock signal DCLK. HACT The horizontal image data 81 outputted by the data pin group 50a is captured (ie, the horizontal image data 81 outputted by the data pin group 50a is captured during the horizontal effective time period t HACT Output horizontal valid data), and according to the data enable signal DE in the vertical valid time segment t VACT The vertical image data 91 outputted by the data pin group 50a is captured (ie, the vertical image data 91 outputted by the data pin group 50a in the vertical effective time section t VACT The driving circuit 112a and the driving circuit 112b can obtain the horizontal blanking time section t of outputting horizontal blanking data by the pulse of the data enable signal DE. HBL , Output horizontal valid data horizontal valid time period t HACT , the vertical blank time segment t for outputting vertical blank data VBL And the vertical effective time period t of output vertical effective data VACT .

[0044] Similarly, the display device 110b generates a signal in a horizontal valid time segment t according to the data enable signal DE and the clock signal DCLK. HACT The horizontal image data 82 outputted by the data pin group 50b is captured (ie, the horizontal image data 82 outputted by the data pin group 50b is captured during the horizontal effective time period t HACT Output horizontal valid data), and according to the data enable signal DE in the vertical valid time segment t VACT The vertical image data 92 outputted by the data pin group 50b is captured (ie, the vertical image data 92 outputted by the data pin group 50b in the vertical effective time section t VACT Output vertical valid data) to display a picture data.

[0045] It should be noted that Figure 4 and Figure 5 In the embodiment, the horizontal blank data and the vertical blank data output by the data pin group 50a and the data pin group 50b are invalid data for the display device 110a and the display device 110b, and therefore, are not drawn in Figure 4 and Figure 5 .

[0046] In addition, since the data pin group 50a is in the horizontal blanking time section t HBL Therefore, the display device 110a outputs horizontal blank data according to the data enable signal DE and the clock signal DCLK in the horizontal blank time section tHBL The horizontal image data 81 outputted by the data pin group 50a is not captured. HBL The time period between the data pin group 50a outputting pixel data of different rows of valid pixels (ie, two adjacent horizontal valid data), that is, the horizontal blanking time period t HBL The preparation time required for the data pin group 50a to output a horizontal valid data; the horizontal valid time section t HACT and horizontal blanking time segment t HBL The sum of is one horizontal scanning period.

[0047] Similarly, since the data pin group 50b is in the horizontal blanking period t HBL Therefore, the display device 110b outputs horizontal blank data according to the data enable signal DE and the clock signal DCLK in the horizontal blank time section t HBL The horizontal image data 82 outputted by the data pin group 50b is not captured. HBL The time period between the data pin group 50b outputting pixel data of different rows of valid pixels (ie, two adjacent horizontal valid data), that is, the horizontal blanking time period t HBL The preparation time required for the data pin group 50b to output a horizontal valid data.

[0048] In addition, since the data pin group 50a is in the vertical blanking time segment t VBL Therefore, the display device 110a outputs vertical blank data in the vertical blank time section t VBL The vertical image data 91 outputted by the data pin group 50a is not captured. VBL The time period between the row number data of valid pixels of different frames outputted by the data pin group 50a (ie, two adjacent vertical valid data), that is, the vertical blank time period t VBL The preparation time required for the data pin group 50a to output a vertical valid data; the vertical valid time segment t VACT Vertical blank time segment t VBL The sum of is one vertical scanning period.

[0049] Similarly, since the data pin group 50b is in the vertical blanking time segment t VBL Therefore, the display device 110b outputs vertical blank data in the vertical blank time section t VBL The vertical image data 92 outputted by the data pin group 50b is not captured. VBLThe time period between the row number data of valid pixels of different frames outputted by the data pin group 50b (ie, two adjacent vertical valid data), that is, the vertical blank time period t VBL The preparation time required for the data pin group 50b to output one vertical valid data.

[0050] See also Figures 6 to 9 , which are respectively a block diagram of another embodiment of the multi-screen display system of the present application, a schematic diagram of an embodiment of image data, a schematic diagram of an embodiment of image data segmentation, and a schematic diagram of an embodiment of a control method. As shown in the figure, the multi-screen display system 1 includes a processor 10, a first display device 11, and a second display device 12. In other words, in this embodiment, the number of displays is 2, that is, n=2. The processor 10 outputs a data enable signal DE, image data D, and a valid data time t.

[0051] In this embodiment, the image data D output by the processor 10 has a data size of M x N. Specifically, the image data D is composed of horizontal image data HD_MCU(TX) and vertical image data VD_MCU(TX) corresponding to the data enable signal DE. The size of the horizontal image data HD_MCU(TX) is M, and the size of the vertical image data VD_MCU(TX) is N. In order to allow the first display device 11 and the second display device 12 to display different screens, the image data D is further divided into image data of a size of M x N1 and image data of a size of M x N2, wherein the image data of a size of M x N1 corresponds to the first display device 11, and the image data of a size of M x N2 corresponds to the second display device 12. That is, in the image data D, the horizontal image data HD_LCD1(RX) of the first display device 11 and the horizontal image data HD_LCD2(RX) of the second display device 12 are of the same size (both M), but the vertical image data VD_LCD1(RX) of the first display device 11 and the vertical image data VD_LCD2(RX) of the second display device 12 are of different sizes (N1 and N2, respectively), so that the first display device 11 and the second display device 12 have different image data and display different pictures. The effective data time t includes the first vertical effective data time interval t VD1 _ delay , the second vertical valid data time interval t VD2_delay , the first vertical valid data time t VD1 , the second vertical valid data time t VD2 , 1st level valid data time interval t HD1_delay , the second level valid data time interval t HD2_delay , 1st level valid data time t HD1, and the second level valid data time t HD2 .

[0052] In addition, Fig. 9 For ease of understanding, the data enable signal DE can be divided into a data enable signal DE_MCU (TX) issued by the processor 10, a data enable signal DE_LCD1 (RX) corresponding to the first display device 11, and a data enable signal DE_LCD2 (RX) corresponding to the second display device 12. The first display device 11 displays an image through a high level of the data enable signal DE_LCD1 (RX), and the second display device 12 displays an image through a high level of the data enable signal DE_LCD2 (RX).

[0053] The first display device 11 includes a first driving circuit 111, and the first display device 11 receives a data enable signal DE, image data D, and a valid data time t from the processor 10. The first driving circuit 111 generates a first vertical valid data time t VD1 The vertical image data VD_MCU(TX) in the image data D is captured and based on the first horizontal valid data time t HD1 The horizontal image data HD_MCU(TX) in the image data D is captured. Since the vertical image data VD_MCU(TX) includes both the vertical image data VD_LCD1(RX) corresponding to the first display device 11 and the vertical image data VD_LCD2(RX) corresponding to the second display device 12, the first driving circuit 111 needs to generate a first vertical valid data time t VD1 The vertical image data VD_LCD1 (RX) corresponding to the first display device 11 in the vertical image data VD_MCU (TX) is captured, and the vertical image data VD_LCD2 (RX) corresponding to the second display device 12 in the vertical image data VD_MCU (TX) cannot be captured. On the other hand, the first driving circuit 111 needs to HD1 The horizontal image data HD_LCD1 (RX) corresponding to the first display device 11 in the horizontal image data HD_MCU (TX) is captured. In this embodiment, since the horizontal image data HD_LCD1 (RX) of the first display device 11 and the horizontal image data HD_LCD2 (RX) of the second display device 12 have the same size, the first horizontal valid data time t HD1 And the second level valid data time t HD2 In other words, the horizontal image data HD_MCU (TX) is equal to the horizontal image data HD_LCD1 (RX) and the horizontal image data HD_LCD2 (RX).

[0054] More specifically, for the first display device 11, a vertical synchronization signal VS (or a frame) can be divided into two intervals, which are the first vertical valid data time interval t VD1 _ delay And the first vertical valid data time t VD1 First, the first driving circuit 111 is driven according to the first vertical effective data time interval t VD1 _ delay The first display device 11 is controlled to start accessing the vertical image data VD_MCU(TX), and the first vertical valid data time interval t VD1 _ delay Next, the first display device 11 displays the first vertical valid data time t VD1 Capture vertical image data VD_MCU(TX) and send it to the first vertical valid data time t VD1 After the vertical image data VD_MCU(TX) is finished, the first display device 11 stops capturing the vertical image data VD_MCU(TX). In this way, the first display device 11 only accesses the vertical image data VD_LCD1(RX) corresponding to the first display device 11 in the vertical image data VD_MCU(TX), and does not access the vertical image data VD_LCD2(RX) corresponding to the second display device 12 in the vertical image data VD_MCU(TX).

[0055] On the other hand, a horizontal synchronization signal HS (or a horizontal line) can also be divided into two intervals, which are the first horizontal valid data time interval t HD1_delay And the first level valid data time t HD1 First, the first driving circuit 111 is driven according to the first horizontal valid data time interval t HD1_delay The first display device 11 is controlled to start accessing the horizontal image data HD_MCU(TX). Next, the first display device 11 receives the first horizontal valid data time t HD1 Capture horizontal image data HD_MCU (TX) and at the first horizontal valid data time t HD1 After the completion, the horizontal image data HD_MCU (TX) is stopped to be captured. In the present embodiment, the first display device 11 accesses the complete horizontal image data HD_MCU (TX).

[0056] The second display device 12 includes a second driving circuit 121, and the second display device 12 receives a data enable signal DE, image data D, and a valid data time t from the processor 10. The second driving circuit 121 generates a second vertical valid data time t VD2 The vertical image data VD_MCU(TX) in the image data D is captured and based on the second horizontal valid data time t HD2The horizontal image data HD_MCU(TX) in the image data D is captured. Since the vertical image data VD_MCU(TX) includes both the vertical image data VD_LCD1(RX) corresponding to the first display device 11 and the vertical image data VD_LCD2(RX) corresponding to the second display device 12, the second driving circuit 121 needs to generate a second vertical effective data time t VD2 The vertical image data VD_LCD2 (RX) corresponding to the second display device 12 in the vertical image data VD_MCU (TX) is captured, and the vertical image data VD_LCD1 (RX) corresponding to the first display device 11 in the vertical image data VD_MCU (TX) cannot be captured. On the other hand, the second driving circuit 121 needs to HD2 The horizontal image data HD_LCD2 (RX) corresponding to the second display device 12 in the horizontal image data HD_MCU (TX) is extracted. In the present embodiment, the horizontal image data HD_MCU (TX) is equal to the horizontal image data HD_LCD1 (RX) and the horizontal image data HD_LCD2 (RX).

[0057] More specifically, for the second display device 12, one vertical synchronization signal VS (or one frame) can be divided into two intervals, which are the second vertical valid data time interval t VD2 _delay, and the second vertical valid data time t VD2 First, the second driving circuit 121 is driven according to the second vertical effective data time interval t VD2 _delay controls the second display device 12 to start accessing the vertical image data VD_MCU(TX), and the second vertical valid data time interval t VD2 _delay is equal to the first vertical valid data time interval t VD1 _ delay And the first vertical valid data time t VD1 Next, the second display device 12 displays the second vertical effective data time t VD2 Capture vertical image data VD_MCU(TX) and send it to the MCU at the second vertical valid data time t VD2 After the vertical image data VD_MCU(TX) is finished, the second display device 12 stops capturing the vertical image data VD_MCU(TX). In this way, the second display device 12 only accesses the vertical image data VD_LCD2(RX) corresponding to the second display device 12 in the vertical image data VD_MCU(TX), and does not access the vertical image data VD_LCD1(RX) corresponding to the first display device 11 in the vertical image data VD_MCU(TX).

[0058] On the other hand, a horizontal synchronization signal HS (or a horizontal line) can also be divided into two intervals, which are the second horizontal valid data time interval t HD2_delay And the second level valid data time t HD2 First, the second driving circuit 121 is driven according to the second horizontal valid data time interval t HD2_delay The second display device 12 is controlled to start accessing the horizontal image data HD_MCU(TX). Next, the second display device 12 starts accessing the horizontal image data HD_MCU(TX) according to the second horizontal valid data time t HD2 Capture horizontal image data HD_MCU (TX) and at the second horizontal valid data time t HD2 After the completion, the horizontal image data HD_MCU (TX) is stopped to be captured. In the present embodiment, the second display device 12 accesses the complete horizontal image data HD_MCU (TX).

[0059] See also Figure 6 as well as Figures 10 to 12 . Figures 10 to 12 1 and 2 are respectively another embodiment schematic diagram of image data of the multi-screen display system of the present application, another embodiment schematic diagram of image data segmentation, and another embodiment schematic diagram of a control method. As shown in the figure, the multi-screen display system 1 includes a processor 10, a first display device 11, and a second display device 12. In the first embodiment and the second embodiment, the same component symbols represent similar or identical components, so they are not repeated here. In this embodiment, the data size of the image data D output by the processor 10 is M x N. The image data D is further divided into image data of size M1 x N and image data of size M2 x N, wherein the image data of size M1 x N corresponds to the first display device 11, and the image data of size M2 x N corresponds to the second display device 12. That is to say, in this image data D, the sizes of the horizontal image data HD_LCD1(RX) of the first display device 11 and the horizontal image data HD_LCD2(RX) of the second display device 12 are different (M1 and M2 respectively), while the sizes of the vertical image data VD_LCD1(RX) of the first display device 11 and the vertical image data VD_LCD2(RX) of the second display device 12 are the same (both are N), so that the first display device 11 and the second display device 12 have different image data and display different pictures.

[0060] The first driving circuit 111 generates a first vertical effective data time interval t VD1_delay The first display device 11 is controlled to start accessing the vertical image data VD_MCU(TX). Next, the first display device 11 receives the first vertical valid data time t VD1 Capture vertical image data VD_MCU(TX) and send it to the first vertical valid data time tVD1 After the process is completed, the vertical image data VD_MCU(TX) is stopped. In the present embodiment, the first display device 11 stores the complete vertical image data VD_MCU(TX).

[0061] On the other hand, the first driving circuit 111 is driven according to the first horizontal valid data time interval t HD1_delay The first display device 11 is controlled to start accessing the horizontal image data HD_MCU(TX), and the first horizontal valid data time interval t HD1_delay Next, the first display device 11 displays the first vertical valid data time t VD1 Capture horizontal image data HD_MCU (TX) and at the first horizontal valid data time t HD1 After the completion, the horizontal image data HD_MCU (TX) is stopped to be captured. In this way, the first display device 11 only accesses the horizontal image data HD_LCD1 (RX) corresponding to the first display device 11 in the horizontal image data HD_MCU (TX), and does not access the horizontal image data HD_LCD2 (RX) corresponding to the second display device 12 in the horizontal image data HD_MCU (TX).

[0062] The second driving circuit 121 generates a second vertical effective data time interval t VD2_delay The second display device 12 is controlled to start accessing the vertical image data VD_MCU(TX). Next, the second display device 12 receives the second vertical valid data time t VD2 Capture vertical image data VD_MCU(TX) and send it to the MCU at the second vertical valid data time t VD2 After the process is completed, the second display device 12 stops capturing the vertical image data VD_MCU(TX). In the present embodiment, the second display device 12 stores the complete vertical image data VD_MCU(TX).

[0063] On the other hand, the second driving circuit 121 is driven according to the second horizontal valid data time interval t HD2_delay The second display device 12 is controlled to start accessing the horizontal image data HD_MCU(TX), and the second horizontal valid data time interval t HD2_delay The first level valid data time interval t HD1_delay The first level valid data time t HD1 Next, the second display device 12 displays the second horizontal valid data time t HD2 Capture horizontal image data HD_MCU (TX) and at the second horizontal valid data time t HD2After the completion, the horizontal image data HD_MCU (TX) is stopped. In this way, the second display device 12 only accesses the horizontal image data HD_LCD2 (RX) corresponding to the second display device 12 in the horizontal image data HD_MCU (TX), and does not access the horizontal image data HD_LCD1 (RX) corresponding to the first display device 11 in the horizontal image data HD_MCU (TX).

[0064] See also Figures 13 to 16 . Figures 13 to 16 1 and 2 are respectively another embodiment block diagram of a multi-screen display system of the present application, another embodiment schematic diagram of image data, another embodiment segmentation schematic diagram of image data, and another embodiment schematic diagram of a control method. As shown in the figure, the multi-screen display system 2 includes a processor 10, a first display device 11, a second display device 12, and a third display device 13. In this embodiment, the number of displays is 3, that is, n=3. In the first embodiment and the third embodiment, the same component symbols represent similar or identical components, so they are not repeated. In this embodiment, the data size of the image data D output by the processor 10 is M x N. The image data D is further divided into image data of size M x N1, image data of size M x N2, and image data of size M x N3, wherein the image data of size M x N1 corresponds to the first display device 11, the image data of size M x N2 corresponds to the second display device 12, and the image data of size M x N3 corresponds to the third display device 13. That is to say, in this image data D, the sizes of the vertical image data VD_LCD1(RX) of the first display device 11, the vertical image data VD_LCD2(RX) of the second display device 12 and the vertical image data VD_LCD3(RX) of the third display device 13 are different from each other (N1, N2 and N3 respectively), while the sizes of the horizontal image data HD_LCD1(RX) of the first display device 11, the horizontal image data HD_LCD2(RX) of the second display device 12 and the horizontal image data HD_LCD1(RX) of the third display device 13 are the same (all M), so that the first display device 11, the second display device 12 and the third display device 13 have different image data and display different pictures.

[0065] First, the first driving circuit 111 is driven according to the first vertical effective data time interval t VD1 _ delay The first display device 11 is controlled to start accessing the vertical image data VD_MCU(TX), and the first vertical valid data time interval t VD1 _ delay Next, the first display device 11 displays the first vertical valid data time t VD1Capture vertical image data VD_MCU(TX) and send it to the first vertical valid data time t VD1 After the process is completed, the vertical image data VD_MCU(TX) is stopped. In this way, the first display device 11 only accesses the vertical image data VD_LCD1(RX) corresponding to the first display device 11 in the vertical image data VD_MCU(TX), and does not access the vertical image data VD_LCD2(RX) corresponding to the second display device 12 and the vertical image data VD_LCD3(RX) corresponding to the third display device 13 in the vertical image data VD_MCU(TX).

[0066] On the other hand, the first driving circuit 111 is driven according to the first horizontal valid data time interval t HD1_delay The first display device 11 is controlled to start accessing the horizontal image data HD_MCU(TX). Next, the first display device 11 receives the first horizontal valid data time t HD1 Capture horizontal image data HD_MCU (TX) and at the first horizontal valid data time t HD1 After the completion, the horizontal image data HD_MCU (TX) is stopped to be captured. In the present embodiment, the first display device 11 accesses the complete horizontal image data HD_MCU (TX).

[0067] The second driving circuit 121 generates a second vertical effective data time interval t VD2 _delay controls the second display device 12 to start accessing the vertical image data VD_MCU(TX), and the second vertical valid data time interval t VD2 _delay is equal to the first vertical valid data time interval t VD1 _ delay And the first vertical valid data time t VD1 Next, the second display device 12 displays the second vertical effective data time t VD2 Capture vertical image data VD_MCU(TX) and send it to the MCU at the second vertical valid data time t VD2 After the process is completed, the vertical image data VD_MCU(TX) is stopped. In this way, the second display device 12 only accesses the vertical image data VD_LCD2(RX) corresponding to the second display device 12 in the vertical image data VD_MCU(TX), and does not access the vertical image data VD_LCD1(RX) corresponding to the first display device 11 and the vertical image data VD_LCD3(RX) corresponding to the third display device 13 in the vertical image data VD_MCU(TX).

[0068] On the other hand, the second driving circuit 121 is driven according to the second horizontal valid data time interval t HD2_delayThe second display device 12 is controlled to start accessing the horizontal image data HD_MCU(TX). Next, the second display device 12 starts accessing the horizontal image data HD_MCU(TX) according to the second horizontal valid data time t HD2 Capture horizontal image data HD_MCU (TX) and at the second horizontal valid data time t HD2 After the completion, the horizontal image data HD_MCU (TX) is stopped to be captured. In the present embodiment, the second display device 12 accesses the complete horizontal image data HD_MCU (TX).

[0069] The third driving circuit 131 generates a third vertical effective data time interval t VD3_delay The third display device 13 is controlled to start accessing the vertical image data VD_MCU(TX), and the third vertical valid data time interval t VD3_delay Equal to the first vertical valid data time interval t VD1 _ delay , the first vertical valid data time t VD1 And the second vertical valid data time t VD2 Next, the third display device 13 displays the third vertical effective data time t VD3 Capture vertical image data VD_MCU(TX) and send it to the 3rd vertical valid data time t VD3 After the vertical image data VD_MCU(TX) is finished, the third display device 13 stops capturing the vertical image data VD_MCU(TX). In this way, the third display device 13 only accesses the vertical image data VD_LCD3(RX) corresponding to the third display device 13 in the vertical image data VD_MCU(TX), and does not access the vertical image data VD_LCD1(RX) corresponding to the first display device 11 in the vertical image data VD_MCU(TX).

[0070] On the other hand, the third driving circuit 131 is driven according to the third horizontal valid data time interval t HD3_delay The third display device 13 is controlled to start accessing the horizontal image data HD_MCU(TX). Next, the third display device 13 starts accessing the horizontal image data HD_MCU(TX) according to the third horizontal valid data time t HD3 Capture horizontal image data HD_MCU (TX) and at the third horizontal valid data time t HD3 After the completion, the horizontal image data HD_MCU (TX) is stopped. In the present embodiment, the first display device 11 accesses the complete horizontal image data HD_MCU (TX) and the vertical image data VD_LCD2 (RX) corresponding to the second display device 12 .

[0071] It should be noted that in this application Figures 6 to 16 In the embodiment of the present invention, the display device can control the display effect through the data enable signal DE, but the present application is not limited thereto. Figures 6 to 16In the three embodiments or other embodiments, the processor 10 may further output a pixel clock signal DCLK, a vertical synchronization signal VS, and a horizontal synchronization signal HS to correspond to display devices with different operation modes.

[0072] In summary, the multi-screen display system of the embodiment of the present application controls the hardware wiring mode of multiple display devices through one processor (multiple display devices share multiple system data pins of one processor), thereby reducing the usage of the processor and its peripheral devices of the product with multi-screen display function to which the multi-screen display system of the present application is applied, thereby reducing the cost of the product with multi-screen display function and reducing the volume of the product with multi-screen display function. In addition, the multi-screen display system can also send effective data time including the first vertical effective data time to the nth vertical effective data time, and the first horizontal effective data time and the nth horizontal data effective time through the processor, so that each of the n display devices respectively captures the corresponding vertical image data and horizontal image data through the effective data time corresponding to the data enable signal, so as to realize the technical effect of one processor controlling multiple display devices.

[0073] Although the above-described components are included in the drawings of the present application, it does not exclude the use of more additional components to achieve better technical effects without violating the spirit of the invention.

[0074] Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, the present invention covers obvious modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest way to include all obvious modifications and similar arrangements.

Claims

1. A multi-screen display system, characterized in that: include: N display devices, where N is a positive integer greater than or equal to two; and A processor, comprising a plurality of system data pins, wherein the plurality of system data pins are divided into N data pin groups, wherein the number of pins in the Nth data pin group corresponds to the number of display color levels of the Nth display device, and the Nth data pin group is used to output horizontal image data and vertical image data of the Nth display device; The Nth display device captures the horizontal image data output by the Nth data pin group in a horizontal effective time period, and captures the vertical image data output by the Nth data pin group in a vertical effective time period; Among them, the processor is used to output a vertical synchronization signal, a horizontal synchronization signal and a clock signal to the N display devices, so that the Nth display device captures the horizontal image data output by the Nth group of data pins in the horizontal effective time period according to the clock signal and the horizontal synchronization signal, and captures the vertical image data output by the Nth group of data pins in the vertical effective time period according to the horizontal synchronization signal and the vertical synchronization signal.

2. The multi-screen display system according to claim 1, characterized in that: The Nth display device does not capture the horizontal image data output by the Nth group of data pin groups in the horizontal trailing edge time segment and the horizontal leading edge time segment according to the clock signal and the horizontal synchronization signal. The horizontal effective time segment is located between the horizontal trailing edge time segment and the horizontal leading edge time segment. The sum of the horizontal effective time segment, the horizontal trailing edge time segment and the horizontal leading edge time segment is a horizontal scanning cycle. In the one horizontal scanning cycle, the horizontal trailing edge time segment is the time segment from the trailing edge of the previous pulse of the horizontal synchronization signal to the start of output of horizontal valid data, the horizontal leading edge time segment is the time segment from the end of output of the horizontal valid data to the trailing edge of the current pulse of the horizontal synchronization signal, and the horizontal valid data is the data output by each group of data pin groups in the horizontal effective time segment.

3. The multi-screen display system according to claim 1, characterized in that: The Nth display device does not capture the vertical image data output by the Nth group of data pin groups in the vertical trailing edge time segment and the vertical leading edge time segment according to the horizontal synchronization signal and the vertical synchronization signal. The vertical effective time segment is located between the vertical trailing edge time segment and the vertical leading edge time segment. The sum of the vertical effective time segment, the vertical trailing edge time segment and the vertical leading edge time segment is a vertical scanning cycle. In the one vertical scanning cycle, the vertical trailing edge time segment is the time segment from the trailing edge of the previous pulse of the horizontal synchronization signal to the start of the output of vertical effective data, the vertical leading edge time segment is the time segment from the end of the output of the vertical effective data to the trailing edge of the current pulse of the horizontal synchronization signal, and the vertical effective data is the data output by each group of data pin groups in the vertical effective time segment.

4. The multi-screen display system according to claim 1, characterized in that: When any two of the N data pin groups have the same number of pins, the display devices connected to the any two data pin groups have the same resolution.

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