Method, circuit and radar for detecting a register

Abstract

The present application relates to a method, a circuit and a radar for detecting a register. The circuit for detecting the register includes: performing a signature operation on a first piece of data to obtain a first signature; storing the first piece of data in a data register; performing a signature operation on a second piece of data stored in the data register to obtain a second signature; and comparing the first signature and the second signature to detect the data register. The present application can improve the reliability of the register, and further improve the personal safety and property safety of users.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a method, circuit, and radar for detecting registers. Background Art

[0002] With the rapid development of computer technology, information technology, etc., information security issues have attracted more and more attention. For autonomous driving technology, information security is also related to the personal and property safety of users.

[0003] As an important component for realizing autonomous driving technology, the high reliability of the output data of the radar is the basis for protecting the personal and property safety of users. The main control chip of the radar can implement specific functions based on the information stored in the internal register. The applicant has found that whether the information in the register is correct greatly affects the normal operation of the lidar. Summary of the Invention

[0004] To solve or partially solve the problems existing in the related art, this application provides a method, circuit, and radar for detecting registers, which can detect registers, improve information security, and further improve the personal and property safety of users.

[0005] In the first aspect of this application, a method for detecting a register is provided, including: performing a signature operation on the first data to obtain a first signature; storing the first data in the data register; performing a signature operation on the second data stored in the data register to obtain a second signature; comparing the first signature and the second signature to detect the data register.

[0006] In the second aspect of this application, a circuit for detecting a register is provided, including: a first signature operation unit, a data register, a second signature operation unit, and a comparator. Among them, the first signature operation unit is configured to perform a signature operation on the first data to obtain a first signature; the data register is connected to the first signature operation unit and is configured to store the first data; the second signature operation unit is connected to the data register and is configured to perform a signature operation on the second data stored in the data register to obtain a second signature; the comparator is respectively connected to the first signature operation unit and the second signature operation unit and is configured to compare the first signature and the second signature to detect the data register.

[0007] In the third aspect of this application, a board card is provided, including the circuit for detecting a register as described above.

[0008] In the fourth aspect of this application, a radar is provided, including the circuit for detecting a register as described above.

[0009] A fifth aspect of the present application provides an electronic device, including: a processor; and a memory storing executable code thereon, which, when executed by the processor, causes the processor to execute the method as described above.

[0010] A sixth aspect of the present application provides a computer-readable storage medium storing executable code thereon, which, when executed by a processor of an electronic device, causes the processor to execute the method as above.

[0011] A seventh aspect of the present application provides a computer program product including executable code, which, when executed, implements the method as above.

[0012] The technical solution provided by the present application may include the following beneficial effects:

[0013] In the embodiments of the present application, in some embodiments of the present application, a signature operation is performed on the data to be stored in the register to obtain a first signature. Then, a signature operation is performed on the data stored in the register to obtain a second signature. By comparing the first signature and the second signature, it is determined whether the data stored in the register is correct, thereby realizing the detection of the register, effectively improving the reliability of the register, and contributing to improving the personal safety and property safety of users.

[0014] In addition, in some embodiments of the present application, a random number is introduced in the process of calculating the signature, improving the reliability of the signature.

[0015] In addition, in some embodiments of the present application, a technical solution of low-bit fast digital signature is provided, which can balance the contradiction between the generation manufacturing cost and information security.

[0016] In addition, in some embodiments of the present application, the signature strength for the first data and the like is enhanced through two-level signature, improving information security.

[0017] In addition, in some embodiments of the present application, when the register is attacked and its value is changed, the signature anomaly can be quickly detected through digital signature, and signals such as an interrupt alarm and a chip reset are issued, improving the personal safety and property safety of users.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By describing the exemplary embodiments of the present application in more detail in conjunction with the drawings, the above and other objects, features, and advantages of the present application will become more obvious, where, in the exemplary embodiments of the present application, the same reference numerals generally represent the same components.

[0020] Figure 1It is a schematic diagram of an application scenario of a method, circuit, and radar for detecting registers shown in an embodiment of the present application;

[0021] Figure 2 It is a schematic diagram of another application scenario of a method, circuit, and radar for detecting registers shown in an embodiment of the present application;

[0022] Figure 3 It is a flowchart of a method for detecting registers shown in an embodiment of the present application;

[0023] Figure 4 It is a data flow schematic diagram of detecting registers shown in an embodiment of the present application;

[0024] Figure 5 It is another data flow schematic diagram of detecting registers shown in an embodiment of the present application;

[0025] Figure 6 It is another data flow schematic diagram of detecting registers shown in an embodiment of the present application;

[0026] Figure 7 It is another data flow schematic diagram of detecting registers shown in an embodiment of the present application;

[0027] Figure 8 It is another data flow schematic diagram of detecting registers shown in an embodiment of the present application;

[0028] Figure 9 It is another data flow schematic diagram of detecting registers shown in an embodiment of the present application;

[0029] Figure 10 It is a block diagram of a circuit for detecting registers shown in an embodiment of the present application;

[0030] Figure 11 It is a block diagram of a circuit for detecting registers shown in an embodiment of the present application;

[0031] Figure 12 It is a block diagram of a circuit for detecting registers shown in an embodiment of the present application;

[0032] Figure 13 It is a block diagram of a first signature operation unit shown in an embodiment of the present application;

[0033] Figure 14 It is a circuit diagram of a signature circuit shown in an embodiment of the present application;

[0034] Figure 15 It is a circuit diagram of an exclusive - OR logic operation circuit shown in an embodiment of the present application;

[0035] Figure 16It is a schematic structural diagram of a device for detecting a register shown in an embodiment of the present application;

[0036] Figure 17 It is a schematic structural diagram of a radar shown in an embodiment of the present application;

[0037] Figure 18 It is a schematic structural diagram of an electronic device shown in an embodiment of the present application. Detailed implementation manners

[0038] Hereinafter, the embodiments of the present application will be described in more detail with reference to the accompanying drawings. Although the embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0039] The terms used in the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a" and "the" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0040] It should be understood that although the terms "first", "second", "third", etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0041] For the convenience of understanding the present application, some concepts related to the present application will be described first.

[0042] Vehicle-mounted radar: The detection range is, for example, from 200 meters to 500 meters, and the physical properties that can be recognized may only include distance and reflectivity, and it can be used for small machines such as vehicles and robots. Vehicle-mounted radars include vehicle-mounted lidar, vehicle-mounted millimeter-wave radar, vehicle-mounted ultrasonic radar, etc.

[0043] Vehicle-mounted lidar: By emitting outgoing light (such as a laser beam) with a wavelength of about 900 nm, the outgoing light will be reflected by an obstacle when it encounters the obstacle, and the processing unit calculates the distance between the obstacle and the vehicle-mounted lidar based on the time difference between the reflected light and the outgoing light. In addition, the processing unit can also estimate the reflectivity of the target according to the waveform area of the reflected light. Vehicle-mounted lidar is small in size and high in integration.

[0044] In an autonomous driving scenario, the system architecture applicable to the autonomous driving scenario may include a mobile device, a network, and a cloud. The mobile device includes, but is not limited to: cars, ships, robots, aircraft, etc. Electronic devices such as sensors can be set on the mobile device to obtain obstacle information in the surrounding environment of the mobile device. The electronic devices may include: radar, image sensors, etc. Multiple electronic devices need to use registers during operation or communication.

[0045] The embodiments of the present application provide a method, circuit, and radar for detecting registers. By performing signature operations on the data stored in the register and the data stored in the register respectively, two signatures are obtained. In this way, by comparing these two signatures, it is possible to detect whether the register has an abnormality, effectively improving the security and reliability of the register, enabling the electronic device to safely and reliably implement specific functions based on the information stored in the register, and thus ensuring the personal safety and property safety of users.

[0046] The technical solutions of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0047] Figure 1 It is a schematic diagram of an application scenario of a method, circuit, and radar for detecting registers shown in an embodiment of the present application.

[0048] Figure 1 It shows the hardware composition of a vehicle 10 that supports assisted driving or autonomous driving functions. For example, at least one lidar (Light Detection and Ranging, abbreviated as LIDAR) 11 is mounted on the roof and / or side of the vehicle 10. The detection area of the LIDAR 11 can be fixed. For example, a certain LIDAR 11 can be only used to detect a preset area. The detection area of the LIDAR 11 can be adjustable. For example, the lidar on the vehicle body can scan multiple detection areas by adjusting the attitude, etc., or can scan multiple detection areas by adjusting the field of view angle range of the lidar itself. Specifically, the vehicle 10 can be equipped with 5 LIDARs 11: on the top of the vehicle, the front side of the vehicle, the rear side of the vehicle, the left side of the vehicle, and the right side of the vehicle. Through multiple LIDARs 11, it is possible to detect the contour of an object existing in the area around the vehicle and the distance to the object.

[0049] In addition, a photographing device may be mounted on the vehicle 10. The photographing device can photograph the environment in front of the viewing angle at a specified viewing angle. For example, the photographing device may be a monocular camera, a multi-camera, etc.

[0050] In addition, a plurality of millimeter-wave radars may be mounted on the vehicle 10 in a manner surrounding the vehicle 10. For example, four millimeter-wave radars are mounted on the vehicle 10 to use the left side in front of the vehicle, the right side in front of the vehicle, the left side behind the vehicle, and the right side behind the vehicle as detection ranges. Through the millimeter-wave radar, the distance of an object existing in each detection area can be detected, and the relative speed between the object and the vehicle 10 can be detected.

[0051] Furthermore, a positioning device 12, such as a Beidou positioning device, a Global Positioning System (GPS), etc., may be mounted on the vehicle 10. The current position of the vehicle 10 can be determined through the positioning device 12.

[0052] In addition, an Electronic Control Unit (ECU) may be mounted on the vehicle 10. Detection signals of at least one of the above LIDAR 11, millimeter-wave radar, and positioning device 12 are sent to the ECU. The ECU can detect and identify obstacles (such as roadblocks, moving objects, trees, adjacent vehicles, etc. around the vehicle 10) based on these signals. In addition, the ECU may be physically divided into multiple units according to functions, and in this application, they are collectively referred to as the ECU.

[0053] It should be noted that although the movable device is described as an automobile, such a description is not restrictive, and various movable devices are applicable, such as land robots, water robots, etc.

[0054] Figure 2 It is a schematic diagram of another application scenario of the method, circuit, and radar for detecting registers shown in an embodiment of the present application.

[0055] Figure 2 The shown aircraft 20 may be an aircraft with an assisted driving function or an autonomous driving function. The aircraft 20 may include a sensing system 21 and a power mechanism 22.

[0056] Among them, the sensing system 21 may include one or more sensors to sense at least one of the surrounding obstacles, spatial orientation, speed, or acceleration of the aircraft 20. The types of sensors include, but are not limited to: ranging sensors, position sensors, motion sensors, inertial sensors, or imaging sensors. The sensing data provided by the sensing system 21 can be used to control the spatial orientation, speed, and / or acceleration of the aircraft 20. The sensing system 21 is used to collect relevant information of the aircraft 20. Different types of sensors can sense different types of signals or signals from different sources. For example, the sensors include radar, inertial sensors, GPS sensors, or vision / imaging sensors (such as cameras), etc.

[0057] The method, circuit, and radar for detecting registers in the embodiments of the present application can be applied to any one or more electronic devices that require a clock, such as Figure 1 or Figure 2 the LIDAR 11, millimeter-wave radar, positioning device 12, ECU, sensing system 21, or communication system shown, etc.

[0058] In the above application scenarios such as assisted driving, autonomous driving, and intelligent transportation, quickly and accurately perceiving the surrounding environment of a movable device is a key point.

[0059] Here, an example of the autonomous driving scenario of a vehicle is used for illustrative purposes. According to the vehicle position information, obstacle information, road information, etc. sensed by the sensing system, coordinate the road signal control, so as to improve the quality and efficiency of road management. Specifically, the corresponding autonomous driving vehicle decision can be determined according to the information sensed by the sensing system, and the safety distance between autonomous driving vehicles can be adjusted, so that it is convenient to realize that the vehicle can drive safely and reliably on the road.

[0060] As one of the most important sensors for autonomous driving, lidar can quickly and accurately sense the surrounding environment information in the fields of intelligent transportation, assisted driving, and autonomous driving, so as to coordinate the road control signals according to the road, vehicle position, and obstacle information, thereby improving the quality and efficiency of road management. In addition, lidar can also assist in determining driving decisions and adjusting the safety distance between vehicles to ensure that the vehicle can drive safely and reliably on the road. For example, it is particularly important for lidar to provide information such as the position, size, and motion information of traffic participants to the decision-making system. For autonomous driving vehicles, lidar is equivalent to the human eye. How to protect the reliability of the data output by lidar is particularly important, which directly relates to the personal safety, property safety, and even life safety of the passengers in the vehicle.

[0061] The main control chip of a lidar is the core component of the lidar. The main control chip is responsible for collecting, processing, and transmitting at least part of the lidar information. At least some of the functions of the main control chip (such as timing control, waveform algorithm processing, laser driver, and controlling non-main control chips) can be implemented based on the information stored in internal registers (such as configuration registers). Therefore, whether the information stored in the registers is correct will greatly affect the normal operation of the lidar.

[0062] However, the applicant has found that registers may physically fail due to manufacturing or aging factors. In addition, registers can also be attacked and controlled by hackers in an attempt to break through the chip security system, causing the chip to operate in the mode expected by the hackers. In both cases, there will be great risks in the entire chip-based system.

[0063] Related technologies can be defended at the software system level. For example, the information stored in the registers (such as configuration information) can be backed up, and the software can regularly poll the information in the registers to detect whether there are unexpected changes for detection purposes. Or, related technologies can also build a software security world where all important configurations are only carried out in the security world, preventing hackers from entering the software security world. However, there is less research on defense monitoring from the underlying hardware of the chip. Compared with software, the implementation method based on chip hardware has higher real-time monitoring and does not rely on the software system. Even when the software system crashes or is breached, the chip can still continue to work, making it more difficult and costly for hackers to break through.

[0064] In some embodiments of the present application, at least some data registers of the main control chip (such as the main control chip of a lidar) are detected. For example, when configuring the key registers, a digital signature is automatically generated, and the digital signature is verified in real time after the configuration is completed. When the values of the key registers are attacked and changed, the detection circuit can immediately discover through the digital signature and issue an interrupt alarm and a chip reset to notify the system to protect and handle the main control chip.

[0065] For example, by performing a signature operation on the first data to be stored in the data register to obtain a first signature, and then performing a signature operation on the second data read from the data register to obtain a second signature, it is possible to determine whether there is an abnormality in the data register by comparing the first signature and the second signature. In addition, to ensure the correctness of the correspondence between the first signature and the second data stored in the data register, the first data can be written into the data register after the first signature is determined. In addition, the first signature can be written into the signature register to implement synchronous detection of the signature register and the data register. When an abnormality occurs in the signature register, there will be a difference between the first signature and the second signature stored in it, resulting in a comparison failure. In addition, a multi-level signature method can be adopted to increase the risk of the signature algorithm being broken. By detecting register abnormalities from multiple perspectives as above, the security and reliability of the data stored in the register can be effectively improved, thus facilitating better realization of the safe operation and data protection of the main control chip of the lidar, and further enhancing the personal safety and property safety of users.

[0066] In addition, in some embodiments, after detecting an abnormality in the data register, an interrupt signal or a reset signal may be issued to enable the system to protect and handle the main control chip.

[0067] Figure 3 It is a flowchart of a method for detecting a register shown in an embodiment of the present application.

[0068] See Figure 3 , the method for detecting a register includes operations S310 to S340.

[0069] In operation S310, a signature operation is performed on the first data to obtain a first signature.

[0070] In this embodiment, the first data may be data to be stored in the data register, especially data to be stored in a key register. For example, the first data may be configuration information. For example, there is a mapping relationship between the configuration information and the state to control the laser to change the state. The first data may be from a processing unit inside the lidar or from a processing unit outside the lidar, such as an ECU, etc., which is not limited here.

[0071] Among them, the signature operation can be implemented by a specific signature algorithm, that is, the signature algorithm is an algorithm for digital signature. A digital signature is a digital string that can only be generated by the sender of the information and cannot be forged by others. This digital string can also be used to verify whether the data has been attacked, tampered with, etc.

[0072] The signature operation can be implemented by hardware, or the signature operation can be implemented by software, or the signature operation can be implemented by hardware and software.

[0073] An exemplary illustration is given by taking the implementation of the signature operation through hardware as an example. The hardware may include multiple logic operation units. By processing the first data through the logic operation units, a first signature is obtained. Or through the combined application of multiple logic operation units and processing the first data, a first signature is obtained.

[0074] Among them, the logic operations include but are not limited to: "OR", "AND", "NOT", "NOR", "NAND", "XOR", etc. The logic operation units include but are not limited to: "OR operation unit", "AND operation unit", "NOT operation unit", "NOR operation unit", "NAND operation unit", "XOR operation unit", etc. These logic operation units can also be called logic operation circuits. In order to obtain the first signature for the first data, the combined application of multiple logic operations can be used to achieve it. Correspondingly, the combined use of multiple logic operation units can be used to achieve it, which is not limited here.

[0075] An exemplary illustration is given by taking the implementation of the signature operation through software as an example. For example, a digital signature can be a string obtained by processing the first data to be signed through a one-way function, which is used to verify whether the information has changed during the transmission process. For example, the signature algorithms include but are not limited to at least one of Rabin signature, DSS signature, and RSA signature.

[0076] An exemplary illustration is given by taking the implementation of the signature operation through hardware and software as an example. For example, after processing the first data through hardware, a string is obtained, and then the string is processed based on the signature algorithm to obtain the first signature. Of course, it can also be processed by software and then by hardware in sequence. In addition, the number of times of hardware processing and software processing is not limited to once and can be multiple times, which is not limited here.

[0077] In operation S320, the first data is stored in the data register.

[0078] The function of the data register is to store binary codes, which is composed of a combination of flip-flops with storage functions. One flip-flop can store 1 bit of binary code. Therefore, a register for storing n bits of binary code requires the use of n flip-flops. For example, the data register can be used to temporarily store the data participating in the operation (such as configuration information) and operation results, etc. A register is a commonly used sequential logic circuit, but this sequential logic circuit only contains a storage circuit.

[0079] Specifically, the data register includes a latch or a flip-flop. A latch or a flip-flop can store 1 bit of binary number, so an N-bit register can be constituted by N latches or flip-flops. The data register is a high-speed storage component with a limited storage capacity, and they can be used to temporarily store instructions, data, addresses, etc. Taking a 16-bit data register as an example, the first data stored therein can be 0110110011101010, such as this first data corresponding to an initialization operation (for example only).

[0080] In this embodiment, after determining that the signature operation for the first data is completed, the first data can be written into the data register. In addition, the first data can also be written into the data register after receiving the first data.

[0081] Among them, writing the first data into the data register to be detected, so that it can be determined whether the data register is abnormal by detecting whether the data output by the data register is consistent with the first data. For example, if the data output by the data register is abnormal (such as the output data is inconsistent with the original first data), it can be determined that the data register is abnormal, such as register aging or being attacked, etc. Since the signature operation is performed on the first data, the first signature for the first data can be obtained. Compared with directly comparing the first data, the risk of the first data being leaked can be reduced, and the information security can be improved. In addition, compared with the method of comparing data, the method of comparing signatures does not directly operate on the data, reducing the risk of data errors and improving the security and reliability of the data stored in the data register.

[0082] It should be noted that in some embodiments, operation S310 and operation S320 do not have a sequential order. Operation S310 can be executed first, and then operation S320. Or operation S320 can be executed first, and then operation S310. In addition, operation S310 and operation S320 can also be executed simultaneously.

[0083] In operation S330, a signature operation is performed on the second data stored in the data register to obtain a second signature.

[0084] In this embodiment, in order to facilitate verifying whether the first data and the second data are consistent by comparing signatures, the above signature operation can be performed on the second data to obtain a second signature. In this way, it can be realized to verify whether the first data and the second data stored in the data register are consistent by comparing the first signature and the second signature, and further realize the detection of the data register.

[0085] It should be noted that the signature operation performed in operation S330 is the same as the signature operation performed in operation S310. For example, the logical operation performed in the signature operation in operation S330 is the same as the logical operation performed in the signature operation in operation S310. For example, the signature algorithm performed in the signature operation in operation S330 is the same as the signature algorithm performed in the signature operation in operation S310.

[0086] In addition, the implementation manner of the signature operation performed in operation S330 and the implementation manner of the signature operation performed in operation S310 may be the same or different. For example, the signature operation performed in operation S310 is implemented by hardware, and the signature operation performed in operation S330 is implemented by hardware, and the two may be implemented using the same hardware circuit or different hardware circuits. For example, the signature operation performed in operation S310 is implemented by hardware, and the signature operation performed in operation S330 may be implemented by software. For example, the signature operation performed in operation S310 is implemented by software, and the signature operation performed in operation S330 may be implemented by hardware.

[0087] In operation S340, the first signature and the second signature are compared to detect the data register.

[0088] In this embodiment, by detecting whether the first data before being stored in the data register is consistent with the second data corresponding to the first data stored in the data register, it is determined whether the data register is abnormal. Specifically, by comparing the first signature for the first data and the second signature for the second data, it is determined whether the first data and the second data are consistent, which effectively improves the security and reliability of the first data (such as important information such as configuration information).

[0089] Figure 4 is a schematic data flow diagram of a detection register shown in an embodiment of the present application.

[0090] See Figure 4 , which shows the data flows 1 and 2 between the components in the method for detecting a register. For data flow 1, first, the first data from the processing unit is stored in the data register. Then, the second data read from the data register is transmitted to the signature operation unit. Next, the signature operation unit processes the second data to obtain the second signature. Then, the signature operation unit sends the second signature to the signature comparator for signature comparison. For data flow 2, first, the first data from the processing unit is transmitted to the signature operation unit. Then, the signature operation unit processes the first data to obtain the first signature. Next, the signature operation unit sends the first signature to the signature comparator for signature comparison.

[0091] In some embodiments, the first data includes (2×n) bits, where n is an integer greater than or equal to 1. Performing a specific logical operation on the random number and multiple bits of the first data to obtain the first signature may include: performing a specific logical operation on the bits from the 0th bit to the (n - 1)th bit of the first data and the bits from the nth bit to the (2×n - 1)th bit of the first data to obtain the first signature.

[0092] Taking the first-level signature operation on the first data including 16 bits (i.e., n is 8) as an example, an exemplary illustration is given. For example, performing an exclusive OR logical operation on the bits from the 0th to the 7th bit of the first data and the bits from the 8th to the 15th bit of the first data to obtain the first signature.

[0093] It should be noted that the first-level signature operation shown above should not be construed as a limitation to this application. Two-level signature or more-level signature operations can also be adopted, and relevant examples will be given in the subsequent part.

[0094] In some embodiments, after detecting a data register exception, risks caused by the register exception can be reduced through, such as, interrupt and / or reset processing, etc.

[0095] Specifically, when the above method detects that the first signature and the second signature are inconsistent, it may further include the following operations: If the first signature and the second signature are inconsistent, at least one of interrupting or resetting the register is performed.

[0096] In some embodiments, a reset signal and / or an interrupt signal are output when it is detected that the first signature and the second signature are inconsistent. The reset signal can cause a lidar or a main control chip of the lidar, etc. to be reset, so as to attempt to eliminate the register exception by resetting. The interrupt signal can cause the lidar to stop outputting information, or prompt that the reliability of the information output by the system is in doubt, so as to prompt the user to perform exception handling as soon as possible, etc.

[0097] In addition, a signature inconsistency count threshold (or a consecutive signature inconsistency count threshold) corresponding to the number of signature inconsistencies can also be set, and a corresponding processing method is determined based on the cumulative number of signature inconsistencies (or the consecutive number of signature inconsistencies) and this threshold.

[0098] For example, the consecutive signature inconsistency count threshold includes a first threshold and a second threshold, corresponding to an occasional exception threshold level and an exception threshold level, etc. Among them, when the consecutive inconsistency count is greater than the occasional exception threshold level and less than the exception threshold level, a reset signal can be output, and an alarm signal can also be output. When the consecutive inconsistency count is greater than the exception threshold level, an interrupt signal can be output. It should be noted that the conditions for outputting the reset signal and / or the interrupt signal above are only for exemplary illustration and should not be construed as a limitation to this application.

[0099] Specifically, the reset signal resets the main circuit and clears the critical information. The interrupt signal can be sent to the CPU, enabling the CPU to respond to the interrupt signal and perform corresponding processing according to the interrupt type, such as destroying important information, restarting, or shutting down the lidar, etc.

[0100] It should be noted that in addition to reset and interrupt handling, other processing methods can also be introduced, such as replacing registers, alarming, etc. The processing methods are not limited herein.

[0101] In some embodiments, the above method may further include: configuring the above first threshold and / or second threshold. This allows the user to set and / or modify the threshold, etc.

[0102] In some embodiments, the above method may further include: an anomaly analysis unit. Among them, the anomaly analysis unit can be part of the anomaly handling module or a separate module.

[0103] For example, the anomaly analysis unit is configured to determine the anomaly type based on the first anomaly detection sub-result and the second anomaly detection sub-result, and output the anomaly type. The anomaly type can be output to the CPU, ECU, etc., so as to take corresponding processing methods.

[0104] To facilitate understanding of the technical solution of the present application, the signature operation process is exemplarily described below.

[0105] In some embodiments, to enhance the anti-attack ability and reliability of the first signature and / or the second signature, the first signature can be generated based on a random number and the first data.

[0106] For example, performing a signature operation on the first data to obtain the first signature may include the following operations. Performing a specific logical operation on multiple bits of the random number and the first data to obtain the first signature.

[0107] In this embodiment, when configuring the register (such as a critical register), the digital signature is automatically completed, and the digital signature is verified in real time after the configuration is completed. When the critical register is attacked and the first data is changed, the above anomaly can be detected in time by comparing the digital signatures. In addition, an interrupt signal and / or a reset signal can be issued to notify the system for protection and disposal, such as the system protecting and disposing of the main control chip of the lidar.

[0108] In some embodiments, to increase the security and reliability of the signature, a random number generation unit can be used to generate a random number, and the first signature is generated based on the random number and the first data.

[0109] Figure 5 It is another data flow diagram of the detection register shown in an embodiment of the present application.

[0110] See Figure 5 In the process of generating the first signature based on a random number and first data, data stream 1 and data stream 2 may be included. For example, data stream 1 includes: First, the processing unit outputs the first data to the data register. Then, the second data stored in the data register and the random number output by the random number generation unit are jointly sent to the signature operation unit. Next, the signature operation unit generates a second signature based on the second data and the random number. Then, the signature operation unit sends the second signature to the signature comparator for signature comparison.

[0111] Data stream 2 includes: First, the processing unit outputs the first data to the signature operation unit. Next, the signature operation unit generates the first signature based on the first data and the random number from the random number generation unit. Then, the signature operation unit sends the first signature to the signature comparator for signature comparison.

[0112] Among them, the random number can be divided into a true random number or a pseudo-random number.

[0113] For example, in the process of generating a true random number, a random physical process (such as environmental noise, thermal noise of a circuit, radioactive decay, etc.) can be used as a random number source and implemented using an analog circuit, and a true random number is obtained through a digital post-processing process. A true random number has no regularity and is unpredictable. An attacker cannot predict the next generated data through a large amount of data analysis. A true random number can be generated by a true random number generation unit (True Random Number Generator, abbreviated as TRNG). The unpredictability of the true random number generation unit makes it impossible for an attacker to guess the first data corresponding to the first signature through general rules, thereby enhancing the security of the first data.

[0114] A pseudo-random number can be generated using a certain fixed generation algorithm. To increase the unpredictability of the pseudo-random number, an initial seed can be set. However, the pseudo-random number still has a pattern. For example, an attacker can obtain the generation algorithm of the pseudo-random number through a large amount of data analysis. However, the pseudo-random number has the advantages of being convenient to use and not requiring additional hardware devices. A pseudo-random number can be generated by a pseudo-random number generation unit (Pseudo Random Number Generator, abbreviated as PRNG).

[0115] It should be noted that in scenarios with high requirements for information security that may affect the personal safety and / or property safety of users, true random numbers can be used to enhance security.

[0116] There are various implementation methods for true random number generation units in circuit design, such as discrete-time chaos implementation methods, oscillation sampling methods, direct amplification of thermal noise methods, etc. Among them, the random source of the oscillation sampling method mainly comes from the phase jitter and noise of the oscillator. The metastability in the circuit generates phase jitter, and the thermal noise in the circuit generates phase noise. The implementation circuit of the oscillation sampling method is relatively simple, the generated true random numbers have high quality, and it is widely used. Specifically, the random number source part can be implemented using analog circuits, and the post-processing part can be implemented using digital circuits.

[0117] In this embodiment, the introduction of random numbers effectively improves the cracking difficulty and reliability of signatures, enhances information security, and further enhances the personal and property safety of users.

[0118] In some embodiments, in order to further improve the cracking difficulty and reliability of the first signature and / or the second signature, the signature strength for the first data and / or the second data can be enhanced through at least two levels of signatures.

[0119] For example, the first data includes (2×n) bit positions, where n is an integer greater than or equal to 1. Correspondingly, performing a specific logical operation on the random number and multiple bit positions of the first data to obtain the first signature can include: performing a specific logical operation on the 0th bit position to the (n - 1)th bit position of the first data and the first sub-result to obtain the first signature, where the first sub-result is determined by performing a specific logical operation based on the first random number and the nth bit position to the (2×n - 1)th bit position of the first data.

[0120] Figure 6 It is another data flow diagram of the detection register shown in an embodiment of the present application.

[0121] Figure 6 It shows a data flow diagram of two-level signature for 16-bit first data. The first data includes bit0 to bit15, where the 0th bit position to the 7th bit position of the first data are bit0 to bit7, and the 8th bit position to the 15th bit position of the first data are bit8 to bit15. Figure 6 First, perform a logical operation on bit8 to bit15 of the first data and the first random number to obtain the first sub-result, where the number of bits of the first random number can be the same as or different from the number of bits of bit8 to bit15 of the first data. After obtaining the first sub-result, the first sub-result can be logically operated with bit0 to bit7 of the first data to obtain the first signature.

[0122] It should be noted that the calculation process of the second signature can refer to the calculation process of the first signature, which will not be elaborated here.

[0123] For another example, the first data includes (2×n) bits, where n is an integer greater than or equal to 1. Correspondingly, performing a specific logical operation on the random number and multiple bits of the first data to obtain the first signature may include: performing a specific logical operation on the nth bit to the (2×n - 1)th bit of the first data and the second sub-result to obtain the first signature, where the second sub-result is determined by performing a specific logical operation based on the second random number and the 0th bit to the (n - 1)th bit of the first data.

[0124] Figure 7 It is another data flow diagram of the detection register shown in an embodiment of the present application.

[0125] Figure 7 It shows a data flow diagram of performing two-level signature on 16-bit first data. The first data includes bit0 to bit15, where the 0th bit to the 7th bit of the first data are bit0 to bit7, and the 8th bit to the 15th bit of the first data are bit8 to bit15. Figure 7 First, perform a logical operation on bit0 to bit7 of the first data and the second random number to obtain a second sub-result. The number of bits of the second random number may be the same as or different from the number of bits of bit0 to bit7 of the first data. After obtaining the second sub-result, the second sub-result may be logically operated with bit8 to bit15 of the first data to obtain the first signature.

[0126] It should be noted that the calculation process of the second signature can refer to the calculation process of the first signature, which will not be elaborated here.

[0127] In this embodiment, through the two-level signature operation process shown above, the cracking difficulty and reliability of the first signature and / or the second signature are effectively improved.

[0128] In some embodiments, in order to further improve the cracking difficulty and reliability of the first signature and / or the second signature, the signature strength for the first data and / or the second data can also be enhanced in the following manner.

[0129] Specifically, the first sub-result is obtained in the following manner.

[0130] First, perform a specific logical operation on the third signature and the 0th bit to the (n / 2 - 1)th bit of the first data to obtain a first sub-operation result, and perform a specific logical operation on the third signature and the n / 2th bit to the (n - 1)th bit of the first data to obtain a second sub-operation result, where the third signature is determined based on the first random number and the nth bit to the (2×n - 1)th bit of the first data. The specific logical operation may be an exclusive OR logical operation, etc.

[0131] Then, splice the first sub-operation result and the second sub-operation result to obtain the first sub-result.

[0132] For example, the third signature is obtained by performing a specific logical operation on the first random number and the nth to (2×n−1)th bits of the first data to obtain the third signature. Among them, the specific logical operation may be the same as the specific logical operation in the previous embodiment.

[0133] Figure 8 It is another data flow schematic diagram of the detection register shown in an embodiment of the present application.

[0134] See Figure 8 , and an exemplary description is given by taking a configuration register with a data register of 16 bits as an example. Figure 8 A signature register is also shown in. The data register and the signature register together form a register bank.

[0135] After obtaining the first signature by the above method, store the first signature in the signature register. Correspondingly, comparing the first signature and the second signature may include: reading the first signature from the register bank to compare the first signature and the second signature.

[0136] Specifically, the reset value of the register in the register bank is the digital signature corresponding to the initial register information and the initial value of the register.

[0137] Taking a key register (a register for storing configuration information) as an example, when the central processing unit (CPU) performs a write operation on the key register for the first data, one path directly updates it to the data register (register 16 bits), and at the same time, the output of the digital signature operation monitoring unit becomes update incomplete, and the control register writing unit waits until the digital signature operation is completed and then writes to the signature register (digital signature 4 bits) and the data register simultaneously with the signature. Thus, it is avoided that one of the signature register or the data register is updated first, resulting in an error in signature comparison.

[0138] The first data is simultaneously split into high 8 bits and low 8 bits. The high 8-bit data and the first random number generated by the random number generation unit (such as 8 bits or 4 bits, etc.) are sent to the exclusive OR operation unit to complete the logical operation by bit (such as exclusive OR operation). Taking the first random number as 8 bits as an example, the obtained 8-bit result is sent to the high-bit signature operation unit (for implementing the high-bit signature such as Figure 8 ). The specific signature algorithm and circuit are shown in the subsequent related embodiments.

[0139] The signature result is 4 bits. After the signature result is XORed with the higher 4 bits and the lower 4 bits of the lower 8 bits of the first data respectively, they are concatenated to form a new data. The new concatenated data is then XORed with the lower 8 bits of the first data, and the result is sent to the low - level signature operation unit (for implementing the low - level signature as shown in Figure 8 to complete the final digital signature operation.

[0140] After the low - level signature operation unit completes the digital signature operation, it notifies the digital signature operation completion monitoring unit, and then updates the signature register and the data register together with the register writing unit.

[0141] The signature operation unit is responsible for performing signature calculations on the data stored in the data register and sending the calculation result (i.e., the second signature) to the signature comparator.

[0142] The signature comparator is responsible for comparing the digitally signed data calculated in real - time with the digital signature stored in the digital signature register. When the signatures do not match, it indicates that the register has been attacked or the register is aging, etc., and it can output an interrupt and a reset, notifying the system to protect and handle the main control chip.

[0143] In this embodiment, instead of signing the first data, restoring the first data based on the first signature, and then storing the first data, this effectively reduces the risk of the first data being incorrect and improves the security and reliability of the first data.

[0144] In some embodiments, the above - mentioned second sub - result is obtained in the following manner.

[0145] First, perform a specific logical operation on the fourth signature and the n - th bit to the (3×n / 2 - 1) - th bit of the first data to obtain a third sub - operation result, and perform a specific logical operation on the fourth signature and the (3×n / 2) - th bit to the (2×n - 1) - th bit of the first data to obtain a fourth sub - operation result, where the fourth signature is determined based on the first random number and the 0 - th bit to the (n - 1) - th bit of the first data.

[0146] Then, concatenate the third sub - operation result and the fourth sub - operation result to obtain the second sub - result.

[0147] For example, the above - mentioned fourth signature can be obtained in the following manner: perform a specific logical operation on the second random number and the n - th bit to the (2×n - 1) - th bit of the first data to obtain the fourth signature.

[0148] Figure 9 It is another data - flow schematic diagram of the detection register shown in an embodiment of the present application.

[0149] See Figure 9, taking the configuration register with a 16-bit data register as an example for illustrative purposes. Figure 9 The signature register is also shown in Figure 9 . The data register and the signature register together form a register bank.

[0150] Specifically, the reset value of the registers in the register bank is the digital signature corresponding to the initial register information and the initial register value.

[0151] Taking the key register (the register storing configuration information) as an example, when the CPU performs a write operation on the key register for the first data, one path directly updates the data register (16-bit register), and at the same time, the output of the monitoring unit for the digital signature operation becomes update not completed. The control register writing unit waits until the digital signature operation is completed and then writes to the signature register (4-bit digital signature) and the data register simultaneously with the signature. This avoids the signature comparison error caused by the update of either the signature register or the data register first.

[0152] The first data is simultaneously split into the high 8 bits and the low 8 bits. The low 8-bit data and the second random number generated by the random number generation unit are sent to the exclusive OR operation unit to complete the logical operation bit by bit (such as the exclusive OR operation). The result obtained is sent to the high-order signature operation unit. The specific signature algorithm and circuit are shown in the subsequent related embodiments.

[0153] The signature result is 4 bits. Next, this signature result is XORed with the lower 4 bits and the higher 4 bits of the high 8 bits of the first data, and then spliced into new data. The new data after splicing is XORed with the high 8 bits of the first data, and the result is sent to the low-order signature operation unit to complete the final digital signature operation.

[0154] After the low-order signature operation unit completes the digital signature operation, it notifies the monitoring unit for the completion of the digital signature operation, and then updates the signature register and the data register together with the register writing unit.

[0155] The signature operation unit is responsible for performing real-time signature calculation on the data register and sending the calculation result (i.e., the second signature) to the signature comparator.

[0156] The signature comparator is responsible for comparing the real-time calculated digital signature and the digital signature stored in the digital signature register. When the signatures are inconsistent, it indicates that the register has been attacked or the register is aging, etc. It outputs an interrupt and a reset, and notifies the system to protect and handle the main control chip.

[0157] In this embodiment, the control register writing unit waits until the digital signature operation is completed and then writes to the configuration register and the digital signature register simultaneously with the signature, which can effectively reduce the risk of signature comparison error caused by the update of either the signature or the configuration register first.

[0158] Another aspect of the present application also provides a circuit for detecting a register.

[0159] Figure 10 It is a block diagram of a circuit for detecting a register shown in an embodiment of the present application.

[0160] See Figure 10 , the circuit 1000 for detecting a register may include: a first signature operation unit 1010, a data register 1020, a second signature operation unit 1030, and a comparator 1040.

[0161] Specifically, the first signature operation unit 1010 is configured to perform a signature operation on the first data to obtain a first signature.

[0162] The data register 1020 is connected to the first signature operation unit and is configured to store the first data.

[0163] The second signature operation unit 1030 is connected to the data register and is configured to perform a signature operation on the second data stored in the data register to obtain a second signature.

[0164] The comparator 1040 is respectively connected to the first signature operation unit and the second signature operation unit and is configured to compare the first signature and the second signature to detect the data register.

[0165] Among them, the first signature operation unit 1010 and the second signature operation unit 1030 may be the same operation unit or different operation units.

[0166] In some embodiments, in order to reduce the risk of signature comparison errors caused by the update of either the signature or the configuration register first, it is possible to monitor whether the signature operation is completed and wait until the signature operation is completed before writing the first data into the data register.

[0167] Figure 11 It is a block diagram of a circuit for detecting a register shown in an embodiment of the present application.

[0168] See Figure 11 , the above-mentioned circuit 1000 for detecting a register may further include: a signature operation completion monitoring unit 1050 and a register writing unit 1060.

[0169] Among them, the signature operation completion monitoring unit 1050 is connected to the first signature operation unit 1010 and is configured to output a write signal in response to the first signature operation unit outputting the first signature.

[0170] The register writing unit 1060 is respectively connected to the signature operation completion monitoring unit 1050 and the data register 1020 and is configured to write the first data into the data register in response to the write signal.

[0171] In some embodiments, after the digital signature operation is completed, the first data and the first signature are written into the data register and the signature register simultaneously, so as to reduce the risk that the first signature and the second signature compared in the comparator correspond to the first data and the second data in different cycles, respectively.

[0172] The circuit 1000 of the detection register described above may further include: a signature register.

[0173] Figure 12 It is a block diagram of the circuit of the detection register shown in an embodiment of the present application.

[0174] See Figure 12 , the signature register and the data register 1020 together form a register bank for storing the first signature.

[0175] The comparator 1040 is also connected to the register bank, and is specifically configured to read the first signature from the register bank and compare the first signature with the second signature.

[0176] In some embodiments, the circuit 1000 of the detection register described above may also perform exception handling when the first signature and the second signature are inconsistent.

[0177] Figure 13 It is a block diagram of the first signature operation unit shown in an embodiment of the present application.

[0178] See Figure 13 , the circuit 1000 of the detection register described above may further include: an exception handling unit 1070.

[0179] For example, the exception handling unit 1070 includes at least one of the following: a reset generation unit and / or an interrupt generation unit.

[0180] The reset generation unit is configured to output a reset signal when the exception detection result is an exception. For example, the first threshold and the second threshold may include multiple levels: an occasional exception threshold level, an exception threshold level, etc. Among them, when the number of inconsistencies (or the number of consecutive inconsistencies) between the first signature and the second signature is greater than the occasional exception threshold level and less than the exception threshold level, a reset signal may be output. When the number of inconsistencies (or the number of consecutive inconsistencies) between the first signature and the second signature is greater than the exception threshold level, a reset signal and an alarm signal may be output.

[0181] The quality of the register is improved by the reset signal. It should be noted that the above conditions for outputting the reset signal are exemplary descriptions and should not be construed as a limitation of the present application. Specifically, the reset signal will reset the main circuit and clear the key information.

[0182] The interruption generating unit is configured to output an interruption signal when the anomaly detection result is an anomaly. For example, the first threshold and the second threshold may include multiple levels: an occasional anomaly threshold level, an anomaly threshold level, etc. Among them, when the number of inconsistencies (or the consecutive number of inconsistencies) between the first signature and the second signature is greater than the anomaly threshold level, an interruption signal may be output. The potential risk brought to the user by the anomaly register is reduced through the interruption signal. Specifically, the interruption signal may be sent to the CPU, so that the CPU can, in response to the interruption signal, perform corresponding processing according to the interruption type, such as destroying important information, restarting, shutting down the TRNG module, etc.

[0183] It should be noted that, in addition to reset, interruption handling, etc., other processing methods may also be introduced: such as using a register generating unit, alarming, etc. for processing, which are not limited herein.

[0184] In some embodiments, the circuit of the detection register may further include: a threshold configuration unit, in which at least one threshold value may be stored.

[0185] In some embodiments, the circuit 1000 of the detection register may further include: an anomaly analysis unit. Among them, the anomaly analysis unit may be part of an anomaly processing module or a separate module.

[0186] For example, the anomaly analysis unit is configured to analyze the cause of the anomaly based on the relationship between the first data, the second data, the first signature, and the second signature. For example, if the first data and the second data are consistent and the first signature and the second signature are inconsistent, it may be determined that the data register is normal and the anomaly may be the signature operation unit and the signature register. If the first data and the second data are inconsistent and the first signature and the second signature are inconsistent, it may be determined that the data register and / or the signature register has an anomaly.

[0187] Among them, the anomaly type may be output to the CPU, ECU, etc. so as to adopt corresponding processing methods.

[0188] In some embodiments, the security and reliability of the first signature and / or the second signature may be increased by a random number.

[0189] Specifically, the above-mentioned circuit 1000 of the detection register may further include: a random number generating unit, which is configured to output a random number.

[0190] Correspondingly, the first signature operation unit 1010 includes at least one of a first logic operation unit, a second logic operation unit, a third logic operation unit, etc.

[0191] Among them, the first logic operation unit is configured to perform a specific logic operation on the 0th bit to the (n - 1)th bit of the first data and the first sub-result to obtain a first signature, where the first sub-result is determined by performing a specific logic operation based on the first random number and the nth bit to the (2×n - 1)th bit of the first data. Specifically, refer to Figure 6 the relevant partial embodiments, which will not be elaborated here.

[0192] The second logic operation unit is configured to perform a specific logic operation on the nth bit to the (2×n - 1)th bit of the first data and the second sub-result to obtain a first signature, where the second sub-result is determined by performing a specific logic operation based on the second random number and the 0th bit to the (n - 1)th bit of the first data. Specifically, refer to Figure 7 the relevant partial embodiments, which will not be elaborated here.

[0193] The third logic operation unit is configured to perform a specific logic operation on the 0th bit to the (n - 1)th bit of the first data and the nth bit to the (2×n - 1)th bit of the first data to obtain a first signature.

[0194] In some embodiments, the circuit 1000 of the above detection register may further include: a fourth logic operation unit, a fifth logic operation unit, and a first splicing unit.

[0195] Among them, the fourth logic operation unit, connected to the first logic operation unit, is configured to perform a specific logic operation on the third signature and the 0th bit to the (n / 2 - 1)th bit of the first data to obtain a first sub-operation result, where the third signature is determined based on the first random number and the nth bit to the (2×n - 1)th bit of the first data.

[0196] The fifth logic operation unit is connected to the first logic operation unit and is configured to perform a specific logic operation on the third signature and the n / 2th bit to the (n - 1)th bit of the first data to obtain a second sub-operation result.

[0197] The first splicing unit is respectively connected to the fourth logic operation unit and the fifth logic operation unit and is configured to splice the first sub-operation result and the second sub-operation result to obtain a first sub-result.

[0198] Specifically, the functions implemented by the fourth logic operation unit, the fifth logic operation unit, and the first splicing unit can refer to Figure 8 the relevant embodiments, which will not be elaborated here.

[0199] In some embodiments, the circuit 1000 of the above detection register may further include: a sixth logic operation unit, a seventh logic operation unit, and a second splicing unit.

[0200] Among them, the sixth logic operation unit is connected to the second logic operation unit and is configured to perform a specific logic operation on the nth bit to the (3×n / 2 - 1)th bit of the fourth signature and the first data to obtain a third sub-operation result, where the fourth signature is determined based on the first random number and the 0th bit to the (n - 1)th bit of the first data.

[0201] The seventh logic operation unit is connected to the second logic operation unit and is configured to perform a specific logic operation on the (3×n / 2)th bit to the (2×n - 1)th bit of the fourth signature and the first data to obtain a fourth sub-operation result.

[0202] The second splicing unit is respectively connected to the sixth logic operation unit and the seventh logic operation unit and is configured to splice the third sub-operation result and the fourth sub-operation result to obtain a second sub-result.

[0203] Specifically, the functions implemented by the sixth logic operation unit, the seventh logic operation unit, and the second splicing unit can refer to Figure 9 related embodiments and will not be elaborated here.

[0204] The following gives an exemplary description of the signature operation unit (which may include a signature circuit to implement the high-order signature and the low-order signature as in Figure 8 ). For ease of understanding, an exemplary description of the logic operation principle of the signature circuit is given.

[0205] Table 1 is a table for simulating modulo division operation. Among them, the first row in Table 1 represents bits. The second row to the ninth row are schematic diagrams of the modulo division process. The result of modulo division (also known as modulus, modulo operation, modulo arithmetic) is the remainder when one number is divided by another number.

[0206] Table 1 Table for Simulating Modulo Division Operation

[0207]

[0208]

[0209] Please refer to Figure 8The XOR operation on the random number and the lower 8 bits can implement the modulo division operation. The irreducible polynomial (i.e., the divisor, which can correspond to the random number, etc. in the foregoing embodiments) in the simulated modulo division operation is 10011 in the lower right corner. The first row represents the bit positions. The d7, d6, d5... d1, d0 in the second row are the 8-bit data to be signed as input, and the following is to XOR and eliminate these 8 bits. The irreducible polynomial is 10011. The third row shows the effect of 10011·d7. In order to eliminate d7 of the data to be signed, the following rows are to eliminate d6 to d0 in sequence, and the remaining lower 4-bit remainder is the result of the digital signature. In the modulo division operation, XOR operations are all performed. When two identical bits appear, that bit can be eliminated. Therefore, it can be seen that after the modulo division, only the lowest 4 bits remain in the bits of the final result. Among them, the operation formulas for bit0 to bit3 are shown in Formulas (1) to (4) respectively.

[0210] bit0 = d0^d3^d4^d6 Formula (1)

[0211] bit1 = d0^d1^d3^d5^d6^d7 Formula (2)

[0212] bit2 = d1^d2^d4^d6^d7 Formula (3)

[0213] bit3 = d2^d3^d5^d7 Formula (4)

[0214] Therefore, the corresponding signature circuit is the direct corresponding implementation of the above operations.

[0215] Figure 14 It is the circuit diagram of the signature circuit shown in an embodiment of the present application.

[0216] Figure 14 The circuit diagram of the signature circuit with the first data of 8 bits is shown. The signature circuit may include 15 XOR logic operation circuits to implement XOR logic operations 1 to 15.

[0217] Among them, XOR logic operation 1 is used to perform an XOR logic operation on d7 and d5.

[0218] XOR logic operation 2 is used to perform an XOR logic operation on d3 and d2.

[0219] XOR logic operation 3 is used to perform an XOR logic operation on d7 and d6.

[0220] XOR logic operation 4 is used to perform an XOR logic operation on d4 and d2.

[0221] XOR logic operation 5 is used to perform an XOR logic operation on d7 and d6.

[0222] The exclusive - OR logic operation 6 is used to perform an exclusive - OR logic operation on d5 and d3.

[0223] The exclusive - OR logic operation 7 is used to perform an exclusive - OR logic operation on d1 and d0.

[0224] The exclusive - OR logic operation 8 is used to perform an exclusive - OR logic operation on d0 and d3.

[0225] The exclusive - OR logic operation 9 is used to perform an exclusive - OR logic operation on d6 and d4.

[0226] The exclusive - OR logic operation 10 is used to perform an exclusive - OR logic operation on the respective results of the exclusive - OR logic operation 1 and the exclusive - OR logic operation 2.

[0227] The exclusive - OR logic operation 11 is used to perform an exclusive - OR logic operation on the respective results of the exclusive - OR logic operation 3 and the exclusive - OR logic operation 4.

[0228] The exclusive - OR logic operation 12 is used to perform an exclusive - OR logic operation on the respective results of the exclusive - OR logic operation 5 and the exclusive - OR logic operation 6.

[0229] The exclusive - OR logic operation 13 is used to perform an exclusive - OR logic operation on the respective results of the exclusive - OR logic operation 8 and the exclusive - OR logic operation 9.

[0230] The exclusive - OR logic operation 14 is used to perform an exclusive - OR logic operation on the result of the exclusive - OR logic operation 11 and d1.

[0231] The exclusive - OR logic operation 15 is used to perform an exclusive - OR logic operation on the respective results of the exclusive - OR logic operation 12 and the exclusive - OR logic operation 7.

[0232] Figure 15 It is the circuit diagram of the exclusive - OR logic operation circuit shown in an embodiment of the present application.

[0233] See Figure 15 , and an exemplary illustration is given with 1 - bit exclusive - OR logic operation. Exclusive - OR (abbreviated as xor) is a mathematical operator. It is applied to logical operations. If two values a and b are different, the exclusive - OR result is 1. If a and b are the same, the exclusive - OR result is 0. Figure 15 If a is 0 and b is 1 in, then a xor b = 1.

[0234] This embodiment provides a low - bit fast digital signature calculation method and the corresponding circuit, which can quickly calculate the first signature of the first data with fewer registers, and can speed up the calculation speed while reducing the hardware cost.

[0235] Figure 16 It is the structural schematic diagram of the device for detecting registers shown in an embodiment of the present application.

[0236] SeeFigure 16 For the apparatus of the detection register, the apparatus 1600 may include a logic operation circuit 1610, a register 1620, and a comparator 1630.

[0237] Among them, the logic operation circuit 1610 is configured to perform a logic operation on the obtained first data and / or second data to obtain a first signature corresponding to the first data and / or a second signature corresponding to the second data.

[0238] The register 1620 is configured to store at least one of the first data, the second data, the first signature, or the second signature.

[0239] The comparator 1630 is configured to compare the first data and the second data, or compare the first signature and the second signature to detect the register.

[0240] Regarding the apparatus in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated herein.

[0241] Another aspect of the present application further provides a radar.

[0242] Figure 17 is a schematic structural diagram of a radar shown in an embodiment of the present application.

[0243] Referring to Figure 17 , the radar 1700 may include a circuit for generating a register as shown above. For example, the circuit for generating a register may include a circuit for detecting a register as shown above. The circuit for generating a register may be disposed on a circuit board 1710, and a plurality of chips, such as a central control chip, etc., may be disposed on the circuit board 1710. The circuit board 1710 may be disposed in a housing 1720.

[0244] The radar may be a lidar, a millimeter-wave radar, an ultrasonic radar, etc. The radar may be a scanning radar or a non-scanning radar.

[0245] The following takes a scanning lidar as an example for illustrative purposes.

[0246] For example, a MEMS-based lidar can dynamically adjust its scanning mode to focus on special objects, collect detailed information of farther and smaller objects, and identify them. The inertial torque of the MEMS-based lidar is not large, and it can move quickly, fast enough to track a 2D scanning mode in less than one second.

[0247] For example, a Flash-based lidar can quickly record the entire scene, avoiding various troubles caused by the movement of the target or the lidar during the scanning process. The radar system uses a micro sensor array to collect laser beams reflected from different directions.

[0248] For example, a row of transmitters on a phased array lidar can change the emission direction of the laser beam by adjusting the relative phase of the signals.

[0249] For example, the mechanically rotating lidar is a lidar that has been developed earlier. Currently, the technology is relatively mature. However, the mechanical structure of the mechanically rotating lidar system is very complex, and the prices of its core components are also quite expensive, mainly including lasers, scanners, optical components, photodetectors, receiving ICs, and position and navigation devices, etc.

[0250] Taking the MEMS solid-state lidar as an example, since the MEMS solid-state lidar scans through the simple harmonic vibration of the galvanometer mirror, the scanning path can be, for example, a scanning field of view where the slow axis goes from top to bottom and the fast axis reciprocates from left to right in terms of spatial order. Therefore, the detection range of the MEMS solid-state lidar is generally divided by the field of view angle corresponding to the slow axis. For example, the vertical field of view angle corresponding to the slow axis of the MEMS solid-state lidar is from -13° to 13°.

[0251] Taking the mechanical lidar in the scanning sensor as an example, since the mechanical lidar drives the optical system to rotate 360 degrees through a mechanical drive device to achieve scanning, it is a cylindrical detection area centered on the lidar. Therefore, the detection range corresponding to the 360° rotation of the mechanical lidar is the detection range corresponding to detecting one frame of data. So, the division of the detection range of the mechanical lidar in one cycle is generally based on the division of the rotation degrees.

[0252] For non-scanning lidars, the internal photosensitive component circuit and control component process the image and convert it into a digital signal that can be recognized by a computer, and then it is input into the computer through a parallel port or USB connection and the image is restored by software.

[0253] Another aspect of the present application also provides an electronic device.

[0254] Figure 18 It is a schematic structural diagram of the electronic device shown in the embodiments of the present application.

[0255] See Figure 18 , the electronic device 1800 may include a memory 1810 and a processor 1820. In addition, at least one of a register generation circuit, a register detection circuit, or a radar may also be provided on the electronic device 1800.

[0256] The processor 1820 can be a Central Processing Unit (CPU), or it can also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0257] The memory 1810 can include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices. Among them, the ROM can store static data or instructions required by the processor 1820 or other modules of the computer. The permanent storage device can be a read-write storage device. The permanent storage device can be a non-volatile storage device that does not lose the stored instructions and data even when the computer is powered off. In some embodiments, the permanent storage device uses a mass storage device (such as a magnetic or optical disk, flash memory) as the permanent storage device. In some other embodiments, the permanent storage device can be a removable storage device (such as a floppy disk, optical drive). The system memory can be a read-write storage device or a volatile read-write storage device, such as dynamic random access memory. The system memory can store some or all of the instructions and data required by the processor during operation. In addition, the memory 1810 can include any combination of computer-readable storage media, including various types of semiconductor storage chips (such as DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and magnetic disks and / or optical disks can also be used. In some embodiments, the memory 1810 can include a removable storage device that is readable and / or writable, such as a compact disc (CD), read-only digital versatile disc (such as DVD-ROM, dual-layer DVD-ROM), read-only Blu-ray disc, super density disc, flash memory card (such as SD card, min SD card, Micro-SD card, etc.), magnetic floppy disk, etc. The computer-readable storage medium does not include carrier waves and instantaneous electronic signals transmitted wirelessly or by wire.

[0258] An executable code is stored on the memory 1810, and when the executable code is processed by the processor 1820, it can cause the processor 1820 to execute some or all of the methods described above.

[0259] In addition, the method according to the present application can also be implemented as a computer program or a computer program product, which includes computer program code instructions for performing some or all of the steps in the above-mentioned method of the present application.

[0260] Alternatively, the present application can also be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium), on which executable code (or a computer program or computer instruction code) is stored. When the executable code (or the computer program or computer instruction code) is executed by a processor of an electronic device (or a server, etc.), the processor is caused to execute some or all of the steps of the above-mentioned method according to the present application.

[0261] The embodiments of the present application have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. A method for detecting a register, characterized in that, comprising: Performing a signature operation on the first data to obtain a first signature, including: performing a specific logical operation on a random number and multiple bit positions of the first data to obtain the first signature; Storing the first data in a data register; Performing the signature operation on the second data stored in the data register to obtain a second signature; Comparing the first signature and the second signature to detect the data register; wherein, the first data includes (2×n) bit positions, n is an integer greater than or equal to 1, and performing a specific logical operation on a random number and multiple bit positions of the first data to obtain the first signature includes: Performing a specific logical operation on the 0th bit position to the (n-1)th bit position of the first data and a first sub-result to obtain the first signature, wherein the first sub-result is determined by performing a specific logical operation based on a first random number and the nth bit position to the (2×n-1)th bit position of the first data; wherein, the first sub-result is obtained by the following method: Performing a specific logical operation on a third signature and the 0th bit position to the (n / 2-1)th bit position of the first data to obtain a first sub-operation result, and performing a specific logical operation on the third signature and the n / 2th bit position to the (n-1)th bit position of the first data to obtain a second sub-operation result, wherein the third signature is determined based on the first random number and the nth bit position to the (2×n-1)th bit position of the first data; Concatenating the first sub-operation result and the second sub-operation result to obtain the first sub-result.

2. The method according to claim 1, characterized in that, Performing a specific logical operation on a random number and multiple bit positions of the first data to obtain the first signature further includes: Performing a specific logical operation on the nth bit position to the (2×n-1)th bit position of the first data and a second sub-result to obtain the first signature, wherein the second sub-result is determined by performing a specific logical operation based on a second random number and the 0th bit position to the (n-1)th bit position of the first data; wherein, the second sub-result is obtained by the following method: Performing a specific logical operation on a fourth signature and the nth bit position to the (3×n / 2-1)th bit position of the first data to obtain a third sub-operation result, and performing a specific logical operation on the fourth signature and the (3×n / 2)th bit position to the (2×n-1)th bit position of the first data to obtain a fourth sub-operation result, wherein the fourth signature is determined based on the first random number and the 0th bit position to the (n-1)th bit position of the first data; Concatenating the third sub-operation result and the fourth sub-operation result to obtain the second sub-result.

3. The method according to claim 1, characterized in that, The third signature is obtained by the following method: Performing a specific logical operation on the first random number and the nth bit position to the (2×n-1)th bit position of the first data to obtain the third signature.

4. The method according to claim 2, wherein, the fourth signature is obtained by the following method: Performing a specific logical operation on the second random number and the nth bit to the (2×n - 1)th bit of the first data to obtain the fourth signature.

5. The method according to any one of claims 1 to 4, wherein, further comprising: After obtaining the first signature, storing the first signature in a signature register, and the data register and the signature register together form a register bank; The comparing the first signature and the second signature includes: Reading the first signature from the register bank to compare the first signature and the second signature.

6. The method according to any one of claims 1 to 4, wherein, further comprising: If the first signature and the second signature are inconsistent, performing at least one of interrupt processing or reset processing on the register.

7. A circuit for detecting a register, wherein, comprising: A first signature operation unit configured to perform a signature operation on first data to obtain a first signature, including: performing a specific logical operation on a random number and multiple bits of the first data to obtain the first signature; A data register connected to the first signature operation unit and configured to store the first data; A second signature operation unit connected to the data register and configured to perform a signature operation on second data stored in the data register to obtain a second signature; A comparator connected to the first signature operation unit and the second signature operation unit respectively and configured to compare the first signature and the second signature to detect the data register; wherein, the first data includes (2×n) bits, n is an integer greater than or equal to 1, and the first signature operation unit includes: A first logic operation unit configured to perform a specific logical operation on the 0th bit to the (n - 1)th bit of the first data and a first sub-result to obtain the first signature, wherein the first sub-result is determined by performing a specific logical operation based on a first random number and the nth bit to the (2×n - 1)th bit of the first data; wherein, further comprising: A fourth logic operation unit connected to the first logic operation unit and configured to perform a specific logical operation on a third signature and the 0th bit to the (n / 2 - 1)th bit of the first data to obtain a first sub-operation result, wherein the third signature is determined based on the first random number and the nth bit to the (2×n - 1)th bit of the first data; A fifth logic operation unit connected to the first logic operation unit and configured to perform a specific logical operation on the third signature and the n / 2th bit to the (n - 1)th bit of the first data to obtain a second sub-operation result; A first splicing unit connected to the fourth logic operation unit and the fifth logic operation unit respectively and configured to splice the first sub-operation result and the second sub-operation result to obtain the first sub-result.

8. The circuit according to claim 7, It is characterized in that It further includes: A signature operation completion monitoring unit, connected to the first signature operation unit, and configured to output a write signal in response to the first signature operation unit outputting the first signature; A register write unit, connected to the data register, and configured to write the first data into the data register in response to the write signal.

9. The circuit according to claim 7, It is characterized in that It further includes: A signature register, which together with the data register constitutes a register bank for storing the first signature; The comparator is also connected to the register bank, and is specifically configured to read the first signature from the register bank and compare the first signature and the second signature.

10. The circuit according to any one of claims 7 to 9, It is characterized in that It further includes: A random number generation unit, configured to output a random number; The first signature operation unit further includes: A second logic operation unit, configured to perform a specific logic operation on the nth bit to the (2×n−1)th bit of the first data and a second sub-result to obtain the first signature, wherein the second sub-result is determined by performing a specific logic operation based on a second random number and the 0th bit to the (n−1)th bit of the first data; Wherein, it further includes: A sixth logic operation unit, connected to the second logic operation unit, and configured to perform a specific logic operation on a fourth signature and the nth bit to the (3×n / 2−1)th bit of the first data to obtain a third sub-operation result, wherein the fourth signature is determined based on the first random number and the 0th bit to the (n−1)th bit of the first data; A seventh logic operation unit, connected to the second logic operation unit, and configured to perform a specific logic operation on the fourth signature and the (3×n / 2)th bit to the (2×n−1)th bit of the first data to obtain a fourth sub-operation result; A second splicing unit, respectively connected to the sixth logic operation unit and the seventh logic operation unit, and configured to splice the third sub-operation result and the fourth sub-operation result to obtain the second sub-result.

11. A radar, including the circuit of the detection register according to any one of claims 7 to 10.

12. An electronic device, It is characterized in that It includes: A processor; And A memory, on which executable code is stored, and when the executable code is executed by the processor, the processor is caused to execute the method according to any one of claims 1 to 6.

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