Automatic wiring methods, devices, computer equipment, and storage media

Abstract

An automatic routing method, apparatus, computer device, storage medium, and program product for silicon photonics chip layout. The automatic routing method includes: reading a netlist to establish a device list and a port list, wherein the device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with the at least one device; constructing a two-dimensional mesh model based on the netlist information; determining, using a path search algorithm, a corresponding path from the at least one start port to the corresponding end port in the two-dimensional mesh model based on the device list and port list; and obtaining the corresponding path coordinates in the two-dimensional mesh model.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic integrated chips, and in particular to an automatic routing method, apparatus, computer equipment, storage medium, and program product for silicon photonic chip layout. Background Technology

[0002] Although the placement and routing technology for integrated circuit chips has been widely adopted, the development of placement and routing tools for silicon photonics chips is still in its early stages, and therefore cannot meet the needs of automated silicon photonics layout design. Unlike integrated circuit chips, which can use multiple metal layers, silicon photonics chips typically use only one optical waveguide layer for routing, and the routing rules are very complex. Therefore, compared to integrated circuits, the amount of routing for silicon photonics chips is smaller, but the routing rules are more complex, making it relatively more difficult. Summary of the Invention

[0003] It would be beneficial to provide a mechanism to alleviate, reduce, or even eliminate one or more of the aforementioned problems.

[0004] According to one aspect of this disclosure, an automatic routing method for silicon photonics chip layout is provided, comprising: reading a netlist to establish a device list and a port list, wherein the device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with the at least one device; constructing a two-dimensional mesh model based on the netlist information in the netlist; determining, using a path search algorithm, a corresponding path from the at least one start port to the corresponding end port in the two-dimensional mesh model based on the device list and the port list; and obtaining the corresponding path coordinates in the two-dimensional mesh model.

[0005] According to another aspect of this disclosure, an automatic routing apparatus for silicon photonics chip layout is provided, comprising: a reading unit for reading a netlist to establish a device list and a port list, wherein the device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with the at least one device; a modeling unit for constructing a two-dimensional mesh model based on the netlist information in the netlist; a calculation unit for determining, based on the device list and the port list, a path search algorithm in the two-dimensional mesh model a corresponding path from the at least one start port to the corresponding end port of the at least one end port; and a result unit for obtaining the corresponding path coordinates in the two-dimensional mesh model.

[0006] According to another aspect of this disclosure, a computer device is provided, comprising: a memory, a processor, and a computer program stored on the memory. The processor is configured to execute the computer program to implement the steps of any of the methods of the first aspect.

[0007] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided, on which a computer program is stored. When executed by a processor, the computer program implements the steps of any of the methods of the first aspect.

[0008] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program. When executed by a processor, the computer program implements the steps of any of the methods of the first aspect.

[0009] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0010] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A schematic diagram of a layout application scenario in which the various methods described herein can be implemented, according to exemplary embodiments, is shown;

[0012] Figure 2 A flowchart of an automated wiring method for a silicon photonics chip according to an exemplary embodiment is shown;

[0013] Figure 3 An exemplary embodiment is shown. Figure 2 A flowchart illustrating an example of the steps involved in constructing a two-dimensional mesh model in the method;

[0014] Figure 4 An exemplary embodiment is shown. Figure 2 A flowchart illustrating an example process for determining a path while considering a fixed-length constraint in the method;

[0015] Figure 5 A flowchart of an automated wiring method for a silicon photonics chip according to another exemplary embodiment is shown;

[0016] Figure 6 A schematic block diagram of an automated wiring apparatus for a silicon photonics chip, according to an exemplary embodiment, is shown.

[0017] Figure 7 This is a block diagram illustrating an exemplary computer device that can be applied to exemplary embodiments. Detailed Implementation

[0018] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0019] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0020] Before introducing exemplary embodiments of this disclosure, some exemplary design factors involved herein will first be explained.

[0021] 1. Silicon photonics wiring rules, including:

[0022] 1) Device Port Constraints. Based on wavelength and polarization, typical integrated optoelectronic device port waveguide types can be broadly categorized into 450nm and 380nm widths, or deep, shallow, and fully etched waveguides. Interconnecting different ports requires either port conversion (i.e., routing with standardized ports) or port identification, placing the conversion between different ports within the routing waveguide. Therefore, when modeling the device, specific methods (e.g., auxiliary layers) are needed to identify port types (e.g., port waveguide type, angle, etc.) for routing algorithm identification.

[0023] 2) Waveguide Constraints for Routing. Since silicon waveguides used for routing are also functional devices, they need to be constrained to ensure no design rule violations. For example, the spacing between waveguides should typically not be less than, for example, 2 micrometers. Secondly, unlike metal waveguides which can make right-angle turns, silicon waveguides typically only allow bends, with strict requirements on the local turning radius. Adding S-bend or Spiral waveguides to the routing algorithm can significantly reduce the algorithm's convergence time. Furthermore, shallow etching of waveguides is often used in manual routing to reduce the waveguide's own transmission loss; therefore, the routing waveguide itself must be selectable. Finally, unlike the transmission of electrical signals in metal lines, the transmission of optical signals in waveguides involves a change in phase; therefore, the waveguide length must be precisely controlled in the algorithm.

[0024] 3) Routing constraints. These constraints are similar to those for printed circuit board (PCB) routing, requiring the routing waveguide to meet conditions such as obstacle avoidance. However, unlike circuit routing, optical waveguides allow right-angle cross routing using optical crossing devices, but strict requirements must be placed on the number and location of the cross points.

[0025] 2. Silicon Photonics Layout Design Rules

[0026] The coordinates within the device's area are set as obstacles, and lines are not allowed to pass through them. For silicon photonics layout design, in order to avoid the mutual interference of optical fields between the device and the waveguide, the device and the waveguide usually need to be spaced apart, for example, by more than 5 micrometers. Therefore, traces cannot be run within 5 micrometers outside the device's area.

[0027] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0028] Figure 1 A schematic diagram of a layout application scenario 100 in which various methods described herein may be implemented, according to an exemplary embodiment, is shown.

[0029] refer to Figure 1 The layout application scenario 100 includes a two-dimensional planar mesh and devices and ports to be connected, such as ports 131-135 of devices 121-125. These ports, together with multiple optical waveguide paths (e.g., paths 141-145), form an integrated optical path.

[0030] Each device has a corresponding port. For example Figure 1 As shown, port 131 is for device 121, and port 132 is for device 122. In silicon photonics chips, each optoelectronic device typically has devices to be connected to; therefore, each port also has a corresponding device to be connected to. That is, silicon photonics chips typically include at least one waveguide path connecting at least one start port and at least one end port.

[0031] Taking waveguide path 141, starting from port 131 of device 121 and ending at port 132 of device 122, as an example, in chip layout design, the starting point is first set as port 131 and the ending point as port 132. Multiple routing schemes will then appear, and the optimal route 141 that meets the requirements will be selected. By repeatedly using this method, the starting and ending ports that need to be connected are redefined until all device ports in the grid are connected.

[0032] Currently, optoelectronic integrated chip design still relies primarily on manual placement and routing. Designers select components and draw layouts based on their own experience, which leads to low design efficiency, a tendency to produce structures that violate design rules, and difficulty in meeting the requirements of large-scale device integration or higher-level designs. Furthermore, the routing rules and schemes for integrated circuit placement cannot be directly applied to optoelectronic chip design. Therefore, research into automated placement and routing technologies applicable to optoelectronic chip design rules is of great significance for improving chip design efficiency, reducing human error, and lowering the design threshold.

[0033] Figure 2 A flowchart of an automated routing method 200 for a silicon photonics chip according to an exemplary embodiment is shown. The various steps of method 200 are described in detail below.

[0034] refer to Figure 2 In step 210, the netlist is read to create a device list and a port list. The device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with at least one device.

[0035] In this embodiment, specifically, the netlist information read into the netlist may include layout routing range and device information. The layout routing range restricts the routing boundaries in the four directions (up, down, left, and right) of the traces; traces are not allowed beyond these boundaries. The device information includes the coordinates of the four vertices of the device's corresponding contour (e.g., a rectangle), the coordinates of the start port and the end port, and the directions of the start port and the end port. In this embodiment, the ports have four directions: up, down, left, and right. In some embodiments, since optical waveguides allow for routing at various angles, four other directions—up-left, up-right, down-left, and down-right—may also be included.

[0036] In step 220, a two-dimensional mesh model is constructed based on the netlist information in the netlist.

[0037] In this embodiment, a planar grid with horizontal and vertical coordinates is constructed (e.g., as shown in the image). Figure 1 The grid shown should be sized to fit the routing area. Boundaries should be established in four directions: top, bottom, left, and right. Grid point attributes within these boundaries include the grid point's x-coordinate, y-coordinate, and path cost. Additionally, the grid can contain device information, design rules, and already routed net information from the netlist.

[0038] In step 230, based on the device list and port list, a path search algorithm is used to determine the corresponding path from at least one starting port to the corresponding ending port in the two-dimensional mesh model.

[0039] In some embodiments, step 230 may include performing turn control on each path during the search process to meet the design rules of the silicon photonics chip. Further, the turn control includes defining each turn as an arc with a turn radius of at least a first value. In the example, after a turn is completed, the search must proceed at least 3 micrometers forward before another turn can occur; that is, the minimum turn radius cannot be less than 3 micrometers and varies depending on the waveguide type. Therefore, when searching a path, if the path direction changes, the search path is fixed at at least 3 micrometers forward before normal searching is performed. Further, the turn control may also include increasing the total path cost of the path by a second value for each additional turn. In some embodiments, the first value is determined based on the type of waveguide used in the path, and the second value is determined based on the grid path costs of other grid points besides the grid point where the added turn is located.

[0040] In some embodiments, the path search algorithm may include Dijkstra's algorithm to ensure that the search result is the path with the minimum cost.

[0041] Specifically, first, a starting set open_set and an ending set close_set are created.

[0042] Furthermore, the grid point P0 with coordinates (x0, y0) at the starting port is taken as the starting point, and the grid point with coordinates (x0, y0) at the ending port is taken as the ending point. end, y end ) lattice point P end As the destination. The path cost of the starting point is 0, the shortest path distance is 0, the parent node is 0, the shortest path distance of the parent node is 0, and the starting point P0(x0, y0) is placed in close_set.

[0043] Furthermore, the neighboring grid points in the four directions of up, down, left, and right are added to the open_set, and then a search is performed to select the grid point P1(x) with the minimum path cost in the open_set. 1, y1), add P1 to close_set and remove P1 from open_set, set P0 as the parent node of P1, and the shortest path distance of P1 is equal to the cost of P1.

[0044] Furthermore, add the grid points that are adjacent to the newly added grid point in close_set but are not in close_set to open_set.

[0045] Furthermore, calculate the cost of each grid point in the open_set plus the distance of that point's parent node, and select the point P2(x) with the smallest cost + father.distance value. 2, y2).

[0046] Furthermore, P2 is added to the close_set and removed from the open_set. The shortest path distance of P2 is P2.distance = P2.cost + P2.father.distance.

[0047] Furthermore, when P n (x n, y n ) = P end (x end, y end (i.e., x) n =x end And y n =y end When the search is complete, the destination port has been found.

[0048] Furthermore, starting from the endpoint port, a reverse search is performed, tracing back through all parent nodes in the close_set to the starting coordinates. This backtracking path is the optimal path from the starting port to the endpoint port.

[0049] Furthermore, if all grid point searches are completed and the endpoint coordinates P are not found in close_set... end (x end, y end If the result is 0, it indicates that no path was found.

[0050] In step 240, the corresponding path coordinates in the two-dimensional mesh model are obtained.

[0051] According to embodiments of this disclosure, the automatic routing result is obtained by applying a path algorithm to the silicon photonics chip, thereby realizing the automatic circuit generation function of silicon photonics layout. In practical applications, when using layout tools with automatic routing function to design silicon photonics chip layout, the design efficiency is effectively improved and human judgment errors are significantly reduced.

[0052] Figure 3 An exemplary embodiment is shown. Figure 2 The flowchart below illustrates an example of step 220 in method 200, which involves constructing a two-dimensional mesh model. The individual operations of step 220 are described in detail below.

[0053] refer to Figure 3 In this embodiment, the netlist information includes boundary information about the wiring range of the silicon photonics chip layout, for use in constructing a two-dimensional mesh model.

[0054] In step 310, a planar mesh array with dimensions corresponding to the wiring range is constructed as a two-dimensional mesh model based on the boundary information. In the example, a planar mesh array with multiple grid points is constructed, each grid point having its own x-coordinate, y-coordinate, and grid point path cost. This planar mesh array can also include the path costs of the already laid lines and the grid points surrounding the laid lines to further improve the accuracy of the path algorithm and facilitate wiring structure optimization.

[0055] Furthermore, the netlist information may also include device information about at least one device in the silicon photonics chip layout, the device information including at least one of the waveguide shape and waveguide type used in the corresponding path.

[0056] In step 320, the grid path cost is set based on at least one of the waveguide shape and waveguide type.

[0057] The grid path cost is added based on process information and design rules to meet the constraints of optical waveguide routing. Optionally, the process information and design rules may include, but are not limited to, waveguide shape, waveguide type, length constraints on the line, and turning control.

[0058] Furthermore, the netlist information may also include device information about at least one device in the silicon photonics chip layout. The device information includes the vertex coordinates of each device in the device list.

[0059] In step 330, the contour coordinates of each device are obtained based on the vertex coordinates of each device.

[0060] In step 340, the contour coordinates of each device are added to the obstacle list. Coordinates in the obstacle list do not allow routing through. Setting obstacles is a bypass condition used to prevent routing from passing through without violating Design Rule Check (DRC).

[0061] Furthermore, the device information may also include the coordinates and orientation of each starting port and the coordinates and orientation of each ending port.

[0062] In step 350, for each device, the contour coordinates of the device are extended by a first distance along the direction toward the outside of the device to obtain the extended contour coordinates of the device.

[0063] This step is to avoid the interaction of optical fields between the device and the waveguide. In some embodiments, the device and the waveguide need to be spaced at least 5 micrometers apart, therefore, no traces can be routed within 5 micrometers outside the device outline (e.g., a rectangle). The outline coordinates of all devices are obtained using the four vertices in the device information. The outline may include the four sides of a rectangle, and the expanded outline includes the four sides of the expanded rectangle.

[0064] In this embodiment, the step of expanding the device contour coordinates includes, but is not limited to: translating the coordinates of the device port by 5 micrometers onto the expanded contour according to the port orientation. If the port is upward, the y-coordinate increases by 5 micrometers. If the port is downward, the y-coordinate decreases by 5 micrometers. If the port is to the left, the x-coordinate increases by 5 micrometers. If the port is to the right, the x-coordinate decreases by 5 micrometers.

[0065] Step 360: Add the extended contour coordinates of each device to the obstacle list. With the extended contour coordinates added to the obstacle list, when coordinates within the obstacle list are found, these coordinates cannot be accessed for wiring, thus achieving obstacle avoidance.

[0066] Step 370: The coordinates of each of the at least one start port and the at least one end port are translated by a first distance along the direction of the port to the extended contour of the corresponding device in the at least one device.

[0067] Step 380: Delete the original rectangular outline coordinates of each device in the obstacle list before expansion. By deleting the original rectangular outline of the device and retaining only the expanded rectangular outline coordinates, the problem of excessively long mesh coordinate reading time caused by an overly large obstacle list can be avoided when accessing the obstacle list.

[0068] Step 390 yields a two-dimensional mesh model.

[0069] According to embodiments of this disclosure, a two-dimensional mesh model is constructed by following silicon photonics layout design rules and optoelectronic device rules, thereby realizing a silicon photonics layout automatic circuit generation method with high accuracy, high efficiency, meeting various design requirements and not violating DRC rules.

[0070] Figure 4 An exemplary embodiment is shown. Figure 2 The flowchart below illustrates an example process for step 230 of method 200, which involves determining the path while considering a fixed length constraint. The individual steps of method 230 are described in detail below.

[0071] refer to Figure 4 In step 410, for a specified path within the corresponding path, a path search is performed while considering a fixed length constraint. This step is to meet the customized requirement of a fixed line length. Furthermore, the path cost can be determined based on the fixed length. In some embodiments, port-to-port connections must ensure a path length of, for example, 30 micrometers, because a length greater than or less than 30 micrometers will affect the optical path difference between the two waveguides, causing the final light intensity to fail to reach the expected output. Therefore, the line length needs to be fixed, and the final line length must be the same as the set value.

[0072] Step 420: In response to determining that the length of the specified path obtained by the search is not equal to the fixed length, the priority of the fixed length constraint relative to the path cost constraint is increased, and the path search algorithm is executed again.

[0073] In this embodiment, the path cost used for the first path search is determined based on the waveguide type, waveguide shape, number of turns, and fixed length. When the search result is not equal to the fixed length, the path cost is set to prioritize the fixed length before performing the search.

[0074] Step 430: Determine whether there exists at least one candidate path of a fixed length.

[0075] Step 440: In response to determining that the length of at least one candidate path obtained by repeatedly executing the path search algorithm is equal to a fixed length, a candidate path is selected from the at least one candidate path as the specified path. The selected candidate path has the minimum total path cost among the at least one candidate path. In this embodiment, the minimum total path cost may depend on the waveguide type, waveguide shape, number of turns, or other customized requirements.

[0076] Step 450: In response to determining that the lengths of the multiple candidate paths obtained by repeatedly executing the path search algorithm are not equal to the fixed length, and that the length of at least one of the multiple candidate paths is less than the fixed length, select the candidate path with the smallest length from the multiple candidate paths.

[0077] In step 460, a straight segment of the selected candidate path is deleted, and an S-shaped routing segment is used to replace the deleted straight segment until the remaining path length plus the extended path length equals the required path length, so that the length of the selected candidate path is equal to the fixed length. Using S-shaped routing avoids right-angle turns in the waveguide and extends the path length compared to straight routing.

[0078] In some embodiments, to meet design requirements, the extended S-shaped line can also be designed so that it does not intersect with other existing lines.

[0079] Step 470: Determine the corresponding path from at least one starting port to the corresponding ending port among at least one ending port.

[0080] According to embodiments of this disclosure, the automatic routing method is made to meet more customized needs, thereby optimizing the automatic routing generation function.

[0081] Figure 5 A flowchart of an automated routing method 500 for a silicon photonics chip according to another exemplary embodiment is shown. The various steps of method 500 are described in detail below.

[0082] In step 510, netlist information is extracted from the silicon photonics chip layout.

[0083] In this embodiment, the netlist information may include device location, port location, port orientation, and port connection relationships.

[0084] In step 520, the netlist information is entered into the netlist.

[0085] In step 530, the netlist is read to create a device list and a port list.

[0086] In step 540, a two-dimensional mesh model is constructed based on the netlist information.

[0087] In step 550, based on the device list and port list, a path search algorithm is used to determine the corresponding path from at least one starting port to at least one ending port in the two-dimensional mesh model.

[0088] In this embodiment, the operations of steps 530, 540 and 550 can be the same as the operations of steps 210, 220 and 230 described above, and therefore will not be repeated for the sake of simplicity.

[0089] In step 560, in response to the determination that there are unconnected ports in the port list, the path search algorithm is repeated until all ports in the port list are connected. This step ensures that all ports are connected, thus ensuring the correct wiring result and improving the accuracy of the automatic routing method.

[0090] In some embodiments, all ports in the read port list that need to be connected are traversed until all ports in the netlist are connected. If a connection fails, the coordinates of the unconnected ports can be recorded for later review.

[0091] In step 570, in response to determining that there is an intersection between the corresponding paths, the intersection is deleted from the path containing the intersection to divide the path containing the intersection into paths without intersection, and a crossover device is added at the deleted intersection so that the divided paths still form a complete path.

[0092] In some embodiments, unlike integrated circuit traces, optical path traces require cross-connect devices at their intersections to achieve optical path intersection. Therefore, when intersections occur in the routing results, the grid coordinates at the intersection points need to be deleted, and the complete line is divided into several shorter segments without intersections based on the intersection locations. Then, cross-connect devices are added at the deleted intersection points so that the segmented paths still form complete paths.

[0093] In step 580, the corresponding path coordinates in the two-dimensional mesh model are obtained.

[0094] In this embodiment, the path coordinates may include the coordinates of the path grid points after the final extension and division, and the coordinates of the intersection points of the paths.

[0095] According to embodiments of this disclosure, the automatic routing method for silicon photonics chips achieves high accuracy, high efficiency, meets various design requirements, and does not violate DRC rules for automatic silicon photonics layout generation. In practical applications, when using layout tools with automatic routing capabilities for silicon photonics chip layout design, design efficiency is effectively improved, and human error is significantly reduced.

[0096] Although the operations are depicted in the accompanying drawings in a specific order, this should not be construed as requiring that the operations be performed in the specific order shown or in chronological order, nor should it be construed as requiring that all the operations shown be performed to obtain the desired result.

[0097] Figure 6 A schematic block diagram of an automated routing apparatus 600 for a silicon photonics chip, according to an exemplary embodiment, is shown. The apparatus 600 is described in detail below. Figure 6 As shown, the automatic wiring device 600 includes a reading unit 610, a modeling unit 620, a path determination unit 630, and a coordinate derivation unit 640.

[0098] The reading unit 610 is configured to read a netlist to create a device list and a port list, wherein the device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with at least one device.

[0099] Modeling unit 620 is configured to construct a two-dimensional mesh model based on netlist information in the netlist.

[0100] The path determination unit 630 is configured to determine the corresponding path from at least one starting port to the corresponding ending port in the two-dimensional mesh model based on the device list and the port list, using a path search algorithm.

[0101] The coordinate deriving unit 640 is configured to derive the corresponding path coordinates in the two-dimensional mesh model.

[0102] In one embodiment, the coordinate deriving unit 640 may further include an output unit (not shown) for outputting the obtained path coordinates.

[0103] According to embodiments of this disclosure, an automatic circuit generation function for silicon photonics layouts is achieved by applying a path algorithm to the silicon photonics chip to obtain the automatic routing result. In practical applications, when using layout tools with automatic routing functions for silicon photonics chip layout design, design efficiency is effectively improved, and human error is significantly reduced.

[0104] It should be understood that Figure 6 Each unit of the device 600 shown can be connected to a reference. Figure 2 The steps in method 200 described correspond to each other. Therefore, the operations, features, and advantages described above for method 200 also apply to apparatus 600 and its constituent units. For the sake of brevity, some operations, features, and advantages will not be repeated here.

[0105] While specific functions have been discussed above with reference to specific units, it should be noted that the functions of the units discussed herein may be divided into multiple units, and / or at least some functions of multiple units may be combined into a single unit. The specific unit performing the method discussed herein includes the specific unit itself performing the method, or alternatively, the specific unit calling or otherwise accessing another component or unit that performs the method (or performs the method in conjunction with the specific unit). Therefore, a specific unit performing a method may include the specific unit performing the method itself and / or another unit that performs the method, called or otherwise accessed by the specific unit. For example, the reading unit 610 / modeling unit 620 described above may be combined into a single unit in some embodiments. As another example, the coordinate derivation unit 640 may include an output unit in some embodiments.

[0106] It should also be understood that this article can describe various technologies in the general context of software and hardware components or program units. The above regarding... Figure 6 The described units can be implemented in hardware or in hardware in combination with software and / or firmware. For example, these units can be implemented as computer program code / instructions configured to execute in one or more processors and stored in a computer-readable storage medium. Alternatively, these units can be implemented as hardware logic / circuit. For example, in some embodiments, one or more of the read unit 610, modeling unit 620, path determination unit 630, and coordinate derivation unit 640 can be implemented together in a System on Chip (SoC). The SoC may include an integrated circuit chip (which includes a processor (e.g., a Central Processing Unit (CPU), microcontroller, microprocessor, digital signal processor (DSP), etc.), memory, one or more communication interfaces, and / or one or more components of other circuitry) and may optionally execute received program code and / or include embedded firmware to perform functions.

[0107] According to one aspect of this disclosure, a computer device is provided, including a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0108] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0109] According to one aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0110] In the following text, combined with Figure 7 Illustrative examples describing such computer devices, non-transitory computer-readable storage media, and computer program products.

[0111] Figure 7 An example configuration of a computer device 700 that can be used to implement the methods described herein is shown. The above-described automatic routing apparatus for silicon photonic chips can also be implemented wholly or at least partially by the computer device 700 or similar devices or systems.

[0112] Computer device 700 can be a variety of different types of devices, such as a service provider's server, a device associated with a client (e.g., a client device), a system-on-a-chip, and / or any other suitable computer device or computing system. Examples of computer device 700 include, but are not limited to: desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablets, cellular or other wireless phones (e.g., smartphones), notebook computers, mobile stations), wearable devices (e.g., glasses, watches), entertainment devices (e.g., entertainment appliances, set-top boxes communicatively coupled to a display device, game consoles), televisions or other display devices, automotive computers, and so on. Therefore, the range of computer device 700 can be from full-resource devices with large amounts of memory and processor resources (e.g., personal computers, game consoles) to low-resource devices with limited memory and / or processing resources (e.g., traditional set-top boxes, handheld game consoles).

[0113] Computer device 700 may include at least one processor 702, memory 704, multiple communication interfaces 706, display device 708, other input / output (I / O) devices 710, and one or more mass storage devices 712 capable of communicating with each other, such as via system bus 714 or other suitable connections.

[0114] Processor 702 may be a single processing unit or multiple processing units, and all processing units may include single or multiple computing units or multiple cores. Processor 702 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operating instructions. Among other capabilities, processor 702 may be configured to acquire and execute computer-readable instructions stored in memory 704, mass storage device 712, or other computer-readable media, such as program code of operating system 716, program code of application program 718, program code of other program 720, etc.

[0115] Memory 704 and mass storage device 712 are examples of computer-readable storage media for storing instructions executed by processor 702 to perform the various functions described above. For example, memory 704 can generally include both volatile and non-volatile memory (e.g., RAM, ROM, etc.). Furthermore, mass storage device 712 can generally include hard disk drives, solid-state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CDs, DVDs), storage arrays, network-attached storage, storage area networks, etc. Both memory 704 and mass storage device 712 can be collectively referred to herein as memory or computer-readable storage media, and can be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code, which can be executed by processor 702 as a specific machine configured to perform the operations and functions described in the examples herein.

[0116] Multiple program units may be stored on mass storage device 712. These programs include operating system 716, one or more application programs 718, other programs 720, and program data 722, and they may be loaded into memory 704 for execution. Examples of such application programs or program units may include, for example, computer program logic (e.g., computer program code or instructions) for implementing the following components / functions: reading unit 610, modeling unit 620, path determination unit 630, coordinate derivation unit 640, method 200 and / or method 500 (including any suitable steps of method 200, 500), and / or other embodiments described herein.

[0117] Although Figure 7The elements are illustrated as being stored in memory 704 of computer device 700, but units 716, 718, 720, and 722, or portions thereof, may be implemented using any form of computer-readable medium accessible by computer device 700. As used herein, "computer-readable medium" includes at least two types of computer-readable media: computer storage media and communication media.

[0118] Computer storage media includes volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program units, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD, or other optical storage devices, magnetic cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or any other non-transfer medium that can be used to store information for access by computer equipment.

[0119] In contrast, communication media can embody computer-readable instructions, data structures, program units, or other data within modulated data signals such as carrier waves or other transmission mechanisms. Computer storage media as defined herein do not include communication media.

[0120] The computer device 700 may also include one or more communication interfaces 706 for exchanging data with other devices, such as via a network, direct connection, etc., as discussed above. Such communication interfaces can be one or more of the following: any type of network interface (e.g., a network interface card (NIC)), wired or wireless (such as IEEE 802.11 Wireless LAN (WLAN)) wireless interface, Wi-MAX interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth. TM Interfaces include near-field communication (NFC) interfaces. Communication interface 706 facilitates communication across various network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. Communication interface 706 can also provide communication with external storage devices (not shown) such as storage arrays, network-attached storage, storage area networks, etc.

[0121] In some examples, a display device 708, such as a monitor, may be included for displaying information and images to the user. Other I / O devices 710 may be devices that receive various inputs from the user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and so on.

[0122] Although this disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and suggestive, not restrictive; this disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and implement variations of the disclosed embodiments in practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, and the words "a" or "an" do not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be beneficial.

[0123] Aspect 1. An automatic routing method for silicon photonics chip layout, the method comprising:

[0124] Read the netlist to build a device list and a port list, wherein the device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with the at least one device;

[0125] The aspect constructs a two-dimensional mesh model based on the netlist information in the netlist;

[0126] Based on the device list and the port list, a path search algorithm is used to determine the corresponding path from the at least one starting port to the corresponding ending port among the at least one ending port in the two-dimensional mesh model; and

[0127] The corresponding path coordinates in the two-dimensional mesh model are obtained.

[0128] Aspect 2. According to the method described in aspect 1,

[0129] The netlist information includes boundary information regarding the wiring range of the silicon photonics chip layout.

[0130] The construction of a two-dimensional mesh model based on the netlist information in the netlist includes:

[0131] Based on the boundary information, a planar mesh array with dimensions corresponding to the wiring range is constructed as the two-dimensional mesh model.

[0132] The planar grid array includes multiple grid points, each grid point having its own horizontal coordinate, vertical coordinate, and grid point path cost.

[0133] Aspect 3. According to the method described in aspect 2,

[0134] The netlist information further includes device information about the at least one device in the silicon photonics chip layout, the device information including at least one of the waveguide shape and waveguide type used by the corresponding path.

[0135] The step of constructing a planar mesh array with dimensions corresponding to the wiring range as the two-dimensional mesh model according to the netlist information includes:

[0136] The grid path cost is set based on at least one of the waveguide shape and waveguide type.

[0137] Aspect 4. According to the method described in aspect 2,

[0138] The netlist information further includes device information about the at least one device in the silicon photonics chip layout, wherein the device information includes the vertex coordinates of each device in the device list.

[0139] The step of constructing a planar mesh array with dimensions corresponding to the wiring range as the two-dimensional mesh model according to the netlist information further includes:

[0140] Based on the vertex coordinates of each device, the contour coordinates of each device are obtained; and

[0141] Add the outline coordinates of each device to an obstacle list, where the coordinates in the obstacle list do not allow routing to pass through.

[0142] Aspect 5. According to the method described in aspect 4,

[0143] The device information also includes the coordinates and direction of each starting port and the coordinates and direction of each ending port.

[0144] The step of constructing a planar mesh array with dimensions corresponding to the wiring range as the two-dimensional mesh model according to the netlist information further includes:

[0145] For each device, the device's contour coordinates are extended by a first distance along the direction toward the outside of the device to obtain the device's extended contour coordinates.

[0146] Add the expanded contour coordinates of each device to the obstacle list; and

[0147] The coordinates of each of the at least one starting port and the at least one ending port are translated along the direction of the port by the first distance to the extended contour of the corresponding device in the at least one device.

[0148] Aspect 6. The method according to aspect 5, wherein constructing a planar mesh array with dimensions corresponding to the wiring range as the two-dimensional mesh model according to the netlist information further includes:

[0149] Remove the extended outline coordinates of each device in the obstacle list.

[0150] Aspect 7. The method according to Aspect 2, wherein determining the corresponding path from the at least one starting port to the corresponding ending port among the at least one ending port in the two-dimensional mesh model based on the device list and the port list using a path search algorithm includes:

[0151] During the search process for each path, turning control is performed on that path, and the turning control includes:

[0152] Each turn is defined as an arc with a turning radius of at least a first value; and

[0153] For each additional turn, the total path cost of the path increases by a second value.

[0154] Aspect 8. The method according to aspect 7, wherein the first value is determined based on the type of waveguide used in the path.

[0155] Aspect 9. The method according to aspect 7, wherein the second value is determined based on the grid path cost of the other grid points among the plurality of grid points, excluding the grid point where the added turn is located.

[0156] Aspect 10. The method according to Aspect 2, wherein determining the corresponding path from the at least one starting port to the corresponding ending port among the at least one ending port in the two-dimensional mesh model based on the device list and the port list using a path search algorithm includes:

[0157] For a specified path in the corresponding path, a path search is performed while considering a fixed length constraint; and

[0158] In response to determining that the length of the specified path obtained by the search is not equal to the fixed length, the priority of the fixed length constraint relative to the path cost constraint is increased, and the path search algorithm is repeated.

[0159] Aspect 11. The method according to aspect 10, wherein applying a fixed length constraint to the specified path in the corresponding path further includes:

[0160] In response to determining that the length of at least one candidate path obtained by repeatedly executing the path search algorithm is equal to the fixed length, a candidate path is selected from the at least one candidate path as the designated path, the selected candidate path having the minimum total path cost among the at least one candidate path.

[0161] Aspect 12. The method according to aspect 10, wherein applying a fixed length constraint to the specified path in the corresponding path further includes:

[0162] In response to determining that the lengths of all candidate paths obtained by repeatedly executing the path search algorithm are not equal to the fixed length, and that at least one candidate path has a length less than the fixed length, the candidate path with the shortest length is selected from the candidate paths; and

[0163] Modify the selected candidate path so that the length of the modified candidate path is equal to the fixed length.

[0164] Aspect 13. The method according to aspect 12, wherein the modification of the selected candidate path includes:

[0165] Delete a straight section from the selected candidate path;

[0166] The deleted straight section is replaced with an S-shaped wiring section so that the length of the selected candidate path is equal to the fixed length.

[0167] Aspect 14. The method according to any one of Aspects 1 to 13, wherein determining, based on the device list and the port list, a path search algorithm in the two-dimensional mesh model for a corresponding end port from the at least one start port to the at least one end port includes:

[0168] In response to determining that there are unconnected ports in the port list, the path search algorithm is repeated until all ports in the port list are connected.

[0169] Aspect 15. The method according to any one of aspects 1 to 13 further includes:

[0170] In response to determining that an intersection exists between the corresponding paths, the intersection is deleted from the path containing the intersection, thereby splitting the path containing the intersection into paths without the intersection; and

[0171] Add cross-connectors at the deleted intersections so that the split paths still form complete paths.

[0172] Aspect 16. The method according to any one of Aspects 1 to 13, wherein the path search algorithm includes Dijkstra's algorithm.

[0173] Aspect 17. The method according to any one of aspects 1 to 13 further includes:

[0174] Before reading the netlist to build the device list and port list:

[0175] Extracting the netlist information from the silicon photonics chip layout; and

[0176] Enter the netlist information into the netlist.

[0177] Aspect 18. An automatic routing apparatus for silicon photonics chip layout, comprising:

[0178] The reading unit is configured to read a netlist to build a device list and a port list, wherein the device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with the at least one device.

[0179] The modeling unit is configured to construct a two-dimensional mesh model based on the netlist information in the netlist;

[0180] A path determination unit is configured to determine, based on the device list and the port list, a path search algorithm in the two-dimensional mesh model, a corresponding path from the at least one starting port to a corresponding ending port among the at least one ending ports; and

[0181] The coordinate deriving unit is configured to derive the corresponding path coordinates in the two-dimensional mesh model.

[0182] Aspect 19. A computer device comprising:

[0183] A memory, a processor, and a computer program stored on the memory, wherein the processor is configured to execute the computer program to implement the steps of the method described in any one of aspects 1-17.

[0184] Aspect 20. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method of any one of aspects 1-17.

[0185] Aspect 21. A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of aspects 1-17.

Claims

1. An automatic routing method for silicon photonics chip layout, the method comprising: Read the netlist to build a device list and a port list, wherein the device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with the at least one device; A two-dimensional mesh model is constructed based on the netlist information. Based on the device list and the port list, a path search algorithm is used to determine the corresponding path from the at least one starting port to the corresponding end port among the at least one ending port in the two-dimensional mesh model. The determination of the corresponding path from the at least one starting port to the corresponding end port among the at least one ending port in the two-dimensional mesh model using the path search algorithm includes: For a specified path in the corresponding path, a path search is performed considering a fixed length constraint, wherein the fixed length is set to a predetermined value so as not to affect the optical path difference between waveguides. In response to determining that the length of the specified path obtained by the search is not equal to the fixed length, the priority of the fixed length constraint relative to the path cost constraint is increased, and the path search algorithm is repeated; In response to determining that the length of at least one candidate path obtained by repeatedly executing the path search algorithm is equal to the fixed length, a candidate path is selected from the at least one candidate path as the designated path, the selected candidate path having the minimum total path cost among the at least one candidate path; and In response to determining that the lengths of all candidate paths obtained by repeatedly executing the path search algorithm are not equal to the fixed length, and that at least one candidate path has a length less than the fixed length, the candidate path with the shortest length is selected from the candidate paths; a straight segment of the selected candidate path is deleted; and the deleted straight segment is replaced with an S-shaped wiring section so that the length of the selected candidate path is equal to the fixed length; and The corresponding path coordinates in the two-dimensional mesh model are obtained.

2. The method according to claim 1, in, The netlist information includes boundary information regarding the wiring range of the silicon photonics chip layout. The construction of a two-dimensional mesh model based on the netlist information in the netlist includes: Based on the boundary information, a planar mesh array with dimensions corresponding to the wiring range is constructed as the two-dimensional mesh model. The planar grid array includes multiple grid points, each grid point having its own horizontal coordinate, vertical coordinate, and grid point path cost.

3. The method according to claim 2, in, The netlist information also includes device information about the at least one device in the silicon photonics chip layout, the device information including at least one of the waveguide shape and waveguide type used by the corresponding path. The step of constructing a planar mesh array with dimensions corresponding to the wiring range as the two-dimensional mesh model according to the netlist information includes: The grid path cost is set based on at least one of the waveguide shape and waveguide type.

4. The method according to claim 2, in, The netlist information also includes device information about the at least one device in the silicon photonics chip layout, the device information including the vertex coordinates of each device in the device list. The step of constructing a planar mesh array with dimensions corresponding to the wiring range as the two-dimensional mesh model according to the netlist information further includes: Based on the vertex coordinates of each device, the contour coordinates of each device are obtained; and Add the outline coordinates of each device to an obstacle list, where the coordinates in the obstacle list do not allow routing to pass through.

5. The method according to claim 4, in, The device information also includes the coordinates and direction of each starting port and the coordinates and direction of each ending port. The step of constructing a planar mesh array with dimensions corresponding to the wiring range as the two-dimensional mesh model according to the netlist information further includes: For each device, the device's contour coordinates are extended by a first distance along the direction toward the outside of the device to obtain the device's extended contour coordinates. Add the expanded contour coordinates of each device to the obstacle list; and The coordinates of each of the at least one starting port and the at least one ending port are translated along the direction of the port by the first distance to the extended contour of the corresponding device in the at least one device.

6. The method according to claim 5, wherein, The step of constructing a planar mesh array with dimensions corresponding to the wiring range as the two-dimensional mesh model according to the netlist information further includes: Remove the extended outline coordinates of each device in the obstacle list.

7. The method according to claim 2, wherein, The step of determining the corresponding path from the at least one starting port to the corresponding ending port among the at least one ending port in the two-dimensional mesh model based on the device list and the port list using a path search algorithm includes: During the search process for each path, turning control is performed on that path, and the turning control includes: Each turn is defined as an arc with a turning radius of at least a first value; and For each additional turn, the total path cost of the path increases by a second value.

8. The method according to claim 7, wherein, The first value is determined based on the type of waveguide used in the path.

9. The method according to claim 7, wherein, The second value is determined based on the grid path cost of the other grid points among the plurality of grid points, excluding the grid point where the added turn is located.

10. The method according to any one of claims 1 to 9, wherein, The step of determining the corresponding path from the at least one starting port to the corresponding ending port among the at least one ending port in the two-dimensional mesh model based on the device list and the port list using a path search algorithm includes: In response to determining that there are unconnected ports in the port list, the path search algorithm is repeated until all ports in the port list are connected.

11. The method according to any one of claims 1 to 9, further comprising: In response to determining that there is an intersection between the corresponding paths, the intersection is deleted from the path containing the intersection, so as to split the path containing the intersection into paths without the intersection; and Add cross-connectors at the deleted intersections so that the split paths still form complete paths.

12. The method according to any one of claims 1 to 9, wherein, The path search algorithm includes Dijkstra's algorithm.

13. The method according to any one of claims 1 to 9, further comprising: Before reading the netlist to build the device list and port list: Extract the netlist information from the silicon photonics chip layout; as well as Enter the netlist information into the netlist.

14. An automatic routing apparatus for silicon photonics chip layout, comprising: The reading unit is configured to read a netlist to build a device list and a port list, wherein the device list includes at least one device in the silicon photonics chip layout, and the port list includes at least one start port and at least one end port associated with the at least one device. The modeling unit is configured to construct a two-dimensional mesh model based on the netlist information in the netlist; A path determination unit is configured to determine, based on the device list and the port list, a path search algorithm in the two-dimensional mesh model, a corresponding path from the at least one starting port to a corresponding ending port among the at least one ending ports, wherein the path determination unit includes: The path search unit is configured to perform a path search for a specified path in the corresponding path, taking into account a fixed length constraint, wherein the fixed length is set to a predetermined value so as not to affect the optical path difference between waveguides. The priority determination unit is configured to, in response to determining that the length of the specified path obtained by the search is not equal to the fixed length, increase the priority of the fixed length constraint relative to the path cost constraint and repeat the path search algorithm; A designated path determination unit is configured to, in response to determining that the length of at least one candidate path obtained by repeatedly executing the path search algorithm is equal to the fixed length, select a candidate path as the designated path from the at least one candidate path, wherein the selected candidate path has the minimum total path cost among the at least one candidate path; and A candidate path determination unit is configured to, in response to determining that the lengths of multiple candidate paths obtained by repeatedly executing the path search algorithm are all not equal to the fixed length, and that the length of at least one of the multiple candidate paths is less than the fixed length, select the candidate path with the shortest length from the multiple candidate paths; delete a straight segment from the selected candidate path; replace the deleted straight segment with an S-shaped wiring section so that the length of the selected candidate path is equal to the fixed length; and The coordinate deriving unit is configured to derive the corresponding path coordinates in the two-dimensional mesh model.

15. A computer device, comprising: A memory, a processor, and a computer program stored on the memory, wherein the processor is configured to execute the computer program to implement the steps of the method according to any one of claims 1-13.

16. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-13.

17. A computer program product comprising a computer program, wherein, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-13.

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