Memory card that can operate with multiple host interfaces

Abstract

The present invention is entitled "Memory Card Operable with Multiple Host Interfaces". The memory card has multiple pads, including: a first set of pads positioned for connection to host contacts arranged in a first configuration for communication according to the microSD standard; a second set of pads positioned for connection to host contacts arranged in a second configuration for communication according to the PCIe protocol; and a third set of pads positioned for connection to host contacts arranged in a third configuration for communication according to the Universal Flash Storage (UFS) standard. The multiple pads include one or more shared pads shared by the second and third sets of pads.

Description

Background Technology

[0001] This technology relates to memory cards and their operation.

[0002] Semiconductor memory devices have become increasingly common in a wide variety of electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices (host devices).

[0003] Memory devices include memory cells that can be arranged in series, for example, in NAND strings, wherein select gate transistors are disposed at the ends of the NAND strings to selectively connect the channels of the NAND strings to source lines or bit lines.

[0004] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers.

[0005] Memory devices can take the form of memory cards configured to be removably coupled to a host device using an interface. For example, pads on the memory card can physically contact and electrically connect to corresponding host contacts on the host device. These connections enable data transfer between the memory card and the host device. The interface can be defined by a standard that allows the memory card to be coupled to any host device conforming to the same standard. Attached Figure Description

[0006] Figure 1 A block diagram of an exemplary memory device is shown, including non-volatile memory cells.

[0007] Figure 1A A block diagram illustrating one embodiment of a memory device connected to a host computer is shown.

[0008] Figure 1B A block diagram of one embodiment of the front-end processor circuitry is shown. In some embodiments, the front-end processor circuitry is part of a controller.

[0009] Figure 1C A block diagram of one embodiment of the back-end processor circuitry is shown. In some embodiments, the back-end processor circuitry is part of a controller.

[0010] Figure 1D A block diagram illustrating one embodiment of the memory package is shown.

[0011] Figure 2A block diagram illustrating one embodiment of a memory die is shown.

[0012] Figure 3 An example of a 3D memory structure is shown.

[0013] Figure 4 An example of a microSD fast memory card is shown.

[0014] Figure 5 An example of a UFS storage card is shown.

[0015] Figures 6A-6C An example of a memory card pad that can operate with microSD, PCIe, and UFS host interfaces is shown.

[0016] Figures 7A-7B Implementation shown Figures 6A-6C Example of a memory card with solder pads.

[0017] Figure 8 This shows another example of the pads for a memory card that can operate with microSD, PCIe, and UFS host interfaces.

[0018] Figures 9A-9B Implementation shown Figure 8 An example of a memory card with pad layout.

[0019] Figure 10 An example of a microSD UHS-II memory card is shown.

[0020] Figure 11 An example of a memory card that can operate with microSD UHS-II and UFS host interfaces is shown.

[0021] Figure 12 The circuitry connected to the pads of the memory card is shown.

[0022] Figure 13 An example of a detection circuit is shown.

[0023] Figure 14A Another example of a detection circuit is shown.

[0024] Figure 14B Show Figure 14A An example implementation of the detection circuit.

[0025] Figure 15 The methods that can be used with memory cards are shown. Detailed Implementation

[0026] Memory cards are typically designed to connect to a host according to an interface standard. When a memory card conforming to the same interface standard is inserted into a host slot conforming to the same interface standard, the host contacts align with and make physical and electrical contact with the pads on the surface of the memory card, thus enabling communication (the host contacts in the slot are arranged in a configuration aligned with the corresponding pads on the memory card). Generally, memory cards conforming to a given interface standard are incompatible with host slots conforming to other interface standards (although some interface standards can provide backward compatibility with earlier versions). In some cases, the card cannot be physically inserted into a slot of a different standard. Even if such a card can be physically inserted, the different configurations of the memory card pads and host contacts mean that the pads often cannot be aligned with the host contacts as required for communication (for example, the memory card has pad patterns, but if the host slot has a different host contact pattern, these two patterns cannot be aligned).

[0027] Examples of interface standards include the Secure Digital (SD) standard and the microSD standard. Another example is the microSD Fast standard, which is backward compatible with older microSD standards (traditional microSD) and adds Peripheral Component Interface Fast (PCIe) capabilities. Memory cards based on the microSD Fast standard have traditional microSD pads for backward compatibility and PCIe pads for high-speed communication using the PCIe protocol. Another memory example is the Universal Flash Storage (UFS) interface standard. MicroSD Fast memory cards have a similar form factor to UFS memory cards, and both types of cards can physically insert into the same host slot. However, when a memory card with pads configured according to one interface standard (e.g., PCIe pads for microSD and microSD Fast) is inserted into a slot with host contacts configured according to another interface standard (e.g., UFS), the pads are typically not aligned with the host contacts according to either standard, and communication is not enabled.

[0028] To overcome the aforementioned problems, the memory card includes pads arranged to contact host contacts in different configurations conforming to two or more different interface standards. A common pad on the memory card can extend such that it physically contacts the corresponding host contact of one interface standard (e.g., a PCIe pad for the microSD Fast standard) at a first location and the corresponding host contact of another interface standard (e.g., UFS) at a second location. The interface standard may specify pads arranged in rows (each row extending parallel to the leading edge of the memory card), and the common pad can extend perpendicular to such rows to overlap different rows (e.g., overlapping pad positions for PCIe communication in one row and pad positions for UFS communication in another row). Appropriate control circuitry can be connected to such common pads to detect which type of host interface is required (e.g., detect which interface standard the host uses) and configure the interface circuitry accordingly. Such a memory card can then be inserted into a host slot conforming to different interface standards (e.g., traditional microSD, microSD Fast, and UFS), and the pads (including the common pad) can contact the corresponding host contacts. The circuitry within the memory card can detect the host's interface type (e.g., microSD, PCIe, or UFS) based on the voltage or current at one or more pads. The interface circuitry can be appropriately configured according to the host's interface standard and enable communication. A single memory card can operate in hosts using different interface standards, thereby reducing the need for different memory cards with different devices and / or adapters for compatibility between the memory card and the host. For example, a single memory card can operate with a host having a microSD interface, a microSD Fast (PCIe) interface, or a UFS interface.

[0029] Figure 1 This is a block diagram of an exemplary memory device that can be implemented as a memory card. Memory device 100, such as a non-volatile data storage system or data storage device (DSD, such as a hard disk drive (HDD), solid-state drive (SSD), tape drive, hybrid drive, etc.), may include one or more memory dies 108. Memory die 108 includes a memory structure 126 of memory cells (such as an array of memory cells), control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines through a row decoder 124 and via bit lines through a column decoder 132.

[0030] The read / write circuitry 128 includes multiple sensing blocks 51, 52, ... 53 (sensing circuitry) and enables the parallel reading or programming of pages of memory cells. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable memory card or other non-volatile storage device) as one or more memory dies 108. The controller may be separate from the memory dies. Commands and data are transmitted between the host 140 and the controller 122 via an interface such as a data bus 120, and between the controller and one or more memory dies 108 via line 118.

[0031] The memory structure 126 can be 2D or 3D. The memory structure may include one or more memory cell arrays, including 3D arrays. The memory structure may include a monolithic 3D memory structure in which multiple memory stages are formed on (but not in) a single substrate (such as a wafer), without intermediate substrates. The memory structure may include any type of non-volatile memory, which is monolithically formed in one or more physical stages of memory cell arrays having active regions disposed on a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is on or within the substrate.

[0032] The control circuit 110 cooperates with the read / write circuit 128 to perform memory operations including reading, writing and erasing on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, a temperature sensing circuit 115, a power control module 116, a power-on detection circuit 117 and a timer 119.

[0033] State machine 112 provides chip-level control for memory operations. A memory area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, the state machine is programmed by software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry). On-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Temperature indication obtained from temperature sensing circuitry 115 can be used to adjust read operations, as further described below.

[0034] Power control module 116 controls the power and voltage supplied to word lines, select gate lines, bit lines, and source lines during memory operation. This power control module may include drivers for data and dummy word lines, SGS transistors and SGD transistors, and source lines. In one method, sensing blocks 51-53 may include bit line drivers. Power-on detection circuitry can be used to detect when the memory device is powered on. Detection circuitry 117 may include an event handler, which may be a software or firmware routine or a routine implemented in hardware. Timer 119 can be used to determine the time elapsed since the last operation (such as a read or write operation). Timer 119 may increment based on a clock signal used in the memory device.

[0035] In some specific implementations, some of the components may be combined. In various designs, one or more components (alone or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any one or a combination of control circuit 110, state machine 112, on-chip address decoder 114, power control module 116, sensing blocks 51, 52, ..., 53, read / write circuit 128, controller 122, etc.

[0036] The off-chip controller 122 (in one embodiment, circuitry) may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct many read errors.

[0037] A host interface 122d is also provided. The host interface 122d, which communicates with ROM 122a, RAM 122b, and processor 122c, is a circuit that provides an electrical interface between controller 122 and host 140 via data bus 120. For example, the host interface can change the format or timing of signals, provide buffers, isolate surges, latch I / O, etc. In some cases, host interface 122d can be configured for different hosts and may include or communicate with circuitry that appropriately configures host interface 122d for a given host.

[0038] Memory devices include code such as a set of instructions, and a processor can operate to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, the processor can access the code from memory structures, such as reserved regions of memory cells in one or more word lines.

[0039] For example, the controller can use code to access memory structures, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is the software that initializes the controller during boot or startup and enables it to access memory structures. The controller can use the code to control one or more memory structures. Upon power-up, processor 122c fetches boot code from ROM 122a or memory structure 126 for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0040] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host device (host) may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0041] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0042] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0043] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0044] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND string is an example of a group of transistors connected in series, including memory cells and select-gate transistors.

[0045] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0046] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as 2D or 3D memory structures. In a 2D memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate can be a wafer on which layers of the memory elements are formed, or it can be a carrier substrate attached to the memory elements after they are formed. As a non-limiting example, the substrate can include a semiconductor, such as silicon.

[0047] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0048] Arrange a 3D memory array such that the memory elements occupy multiple planes or multiple memory device levels to form a three-dimensional structure (i.e., in the x, y and z directions, where the z direction is substantially perpendicular to the main surface of the substrate and the x and y directions are substantially parallel to the main surface of the substrate).

[0049] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements. These columns can be arranged in a 2D configuration, for example, in the xy-plane, resulting in a 3D arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a 3D memory array.

[0050] By way of non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The 3D memory array can also be designed in both NOR and ReRAM configurations.

[0051] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layer constituting each memory device level of the array is typically formed on the layer of the lower memory device level of the array. However, the layers of adjacent memory device levels in a monolithic 3D memory array may be shared between memory device levels or there may be intermediate layers between memory device levels.

[0052] 2D arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0053] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read, write, and erase operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0054] Those skilled in the art will recognize that this technology is not limited to the described 2D and 3D exemplary structures, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0055] In one embodiment, one or more control circuits are formed on a first die called a control die, and the memory array is formed on a second die called a memory die. For example, some or all of the control circuitry associated with the memory (e.g., control circuitry 110, row decoder 124, column decoder 132, and read / write circuitry 128) may be formed on the same control die. The control die may be bonded to one or more corresponding memory dies to form an integrated memory assembly. The control die and the memory die may have bonding pads arranged for electrical connection to each other. The bonding pads of the control die and the memory die can be aligned and bonded together using any of a variety of bonding techniques, depending in part on the bonding pad size and bonding pad spacing (i.e., bonding pad pitch). In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are bonded directly to each other without solder or other additional material. In some embodiments, the dies are bonded in a one-to-one arrangement (e.g., one control die to one memory die). In some embodiments, more than one control die and / or more than one memory die may be present in the integrated memory assembly. In some implementations, the integrated memory assembly includes a stack of multiple control dies and / or multiple memory dies. In some implementations, the control dies are connected to or otherwise communicate with a memory controller. For example, the memory controller may receive data to be programmed into a memory array. The memory controller forwards the data to the control dies, enabling the control dies to program the data into the memory array on the memory dies.

[0056] Although Figure 1 The memory device 100 is one embodiment of a non-volatile memory device, but other embodiments of non-volatile memory devices can be implemented using this technology. Figure 1 The controller 122 is represented in a simple way, with details omitted for simplicity. Figures 1A-1D The following example provides a more detailed example of the controller and how it connects to multiple memory dies.

[0057] Figure 1A This is a block diagram of one embodiment of a memory device 101 connected to a host 140, which implements the techniques proposed herein. Memory device 101 can be considered another embodiment of a non-volatile memory device. Many different types of memory devices can be used with the techniques proposed herein. One exemplary memory device is a solid-state drive (“SSD”); another example is a memory card; however, other types of memory devices can also be used. Memory device 101 includes a controller 102, non-volatile memory 104 for storing data, and local memory 106 (e.g., DRAM, SRAM, or ReRAM). In one embodiment, controller 102 includes front-end processor (FEP) circuitry 141 and one or more back-end processor (BEP) circuits 142. In one embodiment, FEP circuitry 141 is implemented on an ASIC. In one embodiment, each BEP circuit 142 is implemented on a separate ASIC. In one embodiment, the ASIC for each of the BEP circuitry 142 and FEP circuitry 141 is implemented on the same semiconductor, such that controller 102 is fabricated as a system-on-a-chip (“SoC”). Both FEP circuitry 141 and BEP circuitry 142 include their own processors. In one implementation, FEP circuit 141 and BEP circuit 142 are used in a master-slave configuration, where FEP circuit 141 is the master device and each BEP circuit 142 is a slave device. For example, FEP circuit 141 implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation management of the SSD (or other non-volatile memory system). BEP circuit 142 manages memory operations within the memory package / die according to requests from FEP circuit 141. For example, BEP circuit 142 can perform read, erase, and program processes. Additionally, BEP circuit 142 can perform buffer management, set specific voltage levels required by FEP circuit 141, perform error correction (e.g., generate error correction codes (ECC)), control the switching mode interface to the memory package, etc. In one implementation, each BEP circuit 142 is responsible for its own set of memory packages. Controller 102 is an example of control circuitry.

[0058] In one embodiment, the non-volatile memory 104 includes multiple memory packages. Each memory package includes one or more memory dies. Therefore, the controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other types of memory.

[0059] Controller 102 communicates with host 140 via an interface (e.g., data bus 120). In one embodiment, data bus 120 implements a Universal Flash Memory (“UFS”) interface. In one embodiment, data bus 120 implements a Secure Digital (“SD”) interface. In one embodiment, data bus 120 implements a Peripheral Component Interface Fast (PCIe) interface. Embodiments include memory devices, including memory cards, configured to implement two, three, or more such interfaces to communicate with different hosts.

[0060] Host 140 is configured to run software application 143 that requires access to (e.g., writing and reading) memory device 101. To access memory device 101, application 143 communicates with driver 144, which is software used to enable communication between application 143 and memory device 101. The software implementing driver 144 can be executed by a microprocessor in host 140. Driver 144 communicates with host controller 146 (e.g., microprocessor and software or other type of processor) that communicates with memory device 101 via device interface 129. In one embodiment, device interface 129 includes a series of connectors, port capacitors, etc., for physical connection to memory device 101. Host controller 146 is also connected to host memory 130, which is the host's physical memory and can be DRAM, SRAM, non-volatile memory, or another type of storage device. Host 140 is external to and separate from memory device 101. In one embodiment, memory device 101 is embedded within host 140. In some implementations, the memory device 101 is not embedded in the host 140, but is connected to the host 140.

[0061] Host 140 is an instance of an entity external to memory device 101. Other instances of entities external to memory device 101 include other computing devices (e.g., computers, servers, smart devices, smartphones, cameras, etc.) connected to memory device 101 and other computing systems communicating with memory device 101 via any communication device (e.g., LAN, WAN, WiFi, wired connection, wireless connection, direct connection, indirect connection, etc.).

[0062] Figure 1B This is a block diagram of one implementation of the FEP circuit 141. Figure 1B An interface 150 communicating with a host 140 and a host processor 152 communicating with the interface 150 are shown. The interface 150 can be configured to communicate according to an interface protocol such as microSD, PCIe (e.g., in an interface according to the microSD Fast Standard), or UFS. The host processor 152 can be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network on-chip (NOC) 154. An NOC is a communication subsystem on an integrated circuit, typically between cores within a system-on-a-chip (SoC). NOCs can span synchronous and asynchronous clock domains or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and offers significant improvements compared to conventional bus and cross-switch interconnects. Compared to other designs, NOCs improve the scalability of SoCs and the power efficiency of complex SoCs. The wires and links of a NOC are shared by many signals. High parallelism is achieved because all links in a NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems continues to increase, the NOC offers enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and communicating with the NOC 154 are the memory processor 156, SRAM 160, and DRAM controller 162. The DRAM controller 162 is used to operate and communicate with the DRAM (e.g., local memory 106). The SRAM 160 is the local RAM memory used by the memory processor 156. The memory processor 156 is used to run FEP circuitry and perform various memory operations. Two PCIe interfaces, 164 and 166, also communicate with the NOC. Figure 1B In one implementation, the SSD controller will include two BEP circuits 142; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 142. In other implementations, there may be more or fewer than two BEP circuits 142; therefore, there may be more than two PCIe interfaces.

[0063] Figure 1C This is a block diagram of one implementation of the BEP circuit 142. Figure 1C This is shown for communicating with FEP circuit 141 (e.g., with...). Figure 2The PCIe interface 200 communicates with one of the PCIe interfaces 164 and 166. The PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs may be combined into a single large NOC. Each NOC (202 / 204) is connected to SRAM (230 / 260), buffers (232 / 262), a processor (220 / 250), and a data path controller (222 / 252) via an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engine 226 / 256 is used to perform error correction, as is known in the art (e.g., encoding data to be written and decoding data to be read). The XOR engine 224 / 254 is used to perform XOR on the data, enabling data to be reversibly combined (e.g., combining data) and stored in the event of a programming error. The data path controller 22 is connected to the interface module for communication with the memory package via four channels. Therefore, the top NOC 202 is associated with interface 228 for four channels of communication with the memory package, and the bottom NOC 204 is associated with interface 258 for four additional channels of communication with the memory package. Each interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers, and four schedulers. For each channel, there is one scheduler, one buffer, and one TM interface. The processor can be any standard processor known in the art. The data path controllers 222 / 252 can be a processor, an FPGA, a microprocessor, or other type of controller. The XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuits referred to as hardware accelerators. In other embodiments, the XOR engines 224 / 254 and ECC engines 226 / 256 can be implemented in software. The schedulers, buffers, and TM interfaces are hardware circuits.

[0064] Figure 1D This is a block diagram of one embodiment of a memory package 104 including multiple memory dies 300 connected to a memory bus 294 (command lines, data lines, and chip enable lines). The memory bus 294 is connected to a switching mode interface 296 for communication with the TM interface of the BEP circuit 142 (see, for example...). Figure 1C In some implementations, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory dies. In one implementation, each memory package includes eight or sixteen memory dies; however, other numbers of memory dies may also be implemented. The techniques described herein are not limited to any particular number of memory dies.

[0065] Figures 1A-1DAn exemplary architecture for a controller is provided. However, the techniques described herein are not limited to any particular form of controller. Therefore, other architectures can be used for controllers. For example, in other configurations, other implementations of the controller include microprocessors, microcontrollers, state machines, etc. In some cases, the controller can be internal to the host. In other cases, the controller can be implemented on a memory die. Other options / configurations are also possible. The controller can also be referred to as a processor, even though it includes multiple processing cores, because the controller operates as a processor for the memory device.

[0066] Figure 2 This is a perspective view of a memory device 500, which includes... Figure 1 The memory structure 126 comprises a set of blocks in an exemplary 3D configuration. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements), and peripheral regions having circuitry used by the blocks. Peripheral regions 504 extend along the edges of each block, while peripheral regions 505 are located at the ends of the set of blocks. The substrate 501 may also support circuitry beneath the blocks, and one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. These blocks are formed in a middle region 502 of the memory device. In an upper region 503 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals from the circuitry.

[0067] Figure 3 Depicting Figure 2 An exemplary cross-sectional view of a portion of a block. The block includes a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers include two SGD layers, one SGS layer, two source-side dummy word line layers (or word lines) WLS1 and WLS0, two drain-side dummy word line layers WLD1 and WLD0, and eleven data word line layers (or data word lines) WL0-WL10. WL0 is a source-side data word line, and WLS1 is a dummy word line layer adjacent to the source-side data word line. WLS0 is another dummy word line layer adjacent to WLS1. WL10 is a drain-side data word line, and WLD1 is a dummy word line layer adjacent to the drain-side data word line. WLD0 is another dummy word line layer adjacent to WLD1. The dielectric layers are labeled DL1-DL19. Furthermore, a region comprising the stack of NAND strings NS1 and NS2 is depicted. Each NAND string contains a memory hole 618 or a memory hole 619, which is filled with material forming memory cells adjacent to word lines.

[0068] The stack includes a substrate 611. In one approach, a portion of the source line SL includes an n-type source diffusion layer 611a in the substrate, which contacts the source terminals of each string of memory cells in the block. An erase voltage can be applied to this layer during an erase operation. In one possible embodiment, the n-type source diffusion layer 611a is formed in a p-type well region 611b, which in turn is formed in an n-type well region 611c, which in turn is formed in a p-type semiconductor substrate 611d. In one approach, the n-type source diffusion layer can be shared by all blocks in a plane.

[0069] NS1 has a source terminal 613 at the bottom 616b of the stack 616 and a drain terminal 615 at the top 616a of the stack. Metal-filled slots 617 and 620 may be provided periodically across the stack as interconnects extending through the stack, such as to connect source lines to lines above the stack. The slots may be used during word line formation and subsequently filled with metal. A portion of the bit line BL0 is also depicted. A conductive via 621 connects the drain terminal 615 to BL0.

[0070] In some embodiments, the memory device (e.g., memory device 100 or memory device 101) may be in the form of a memory card that is removably connected to the host rather than permanently connected. This allows the same memory device to be used with different hosts, the same memory card to be used at different times in cameras, telephones, music devices, laptops, or other hosts, and the same host to use different memory devices at different times. Various host interface standards exist to enable this interchangeability between memory cards and hosts.

[0071] The memory card can be inserted into a slot in the host computer, aligning and engaging the contacts on the host side with the pads on the memory card side, and establishing an electrical connection between the host contacts and the corresponding pads on the memory card. Aside from other aspects of the communication protocol and interface, the memory card interface standard defines the location of the host contacts and the corresponding location of the memory card pads, as well as the physical dimensions (form factor) of the host slot and the memory card.

[0072] Many memory cards are designed according to a single memory card standard, meaning they can only operate with hosts that have the corresponding memory card slot. Some memory cards are designed to operate with more than one version of a host interface standard, allowing newer cards that support newer host interface standards to also support older ones, providing backward compatibility. These memory cards may have the same form factor to allow them to be inserted into hosts that support either older or newer host interface standards. Therefore, some host interface standards include existing host interface standards for backward compatibility.

[0073] Figure 4An example of a microSD (μSD) fast memory card 402 is shown, including a first row of pads 404 (pads 1-8), which are positioned to connect to host contacts arranged in a microSD configuration (in such a conventional microSD host slot, host contacts are arranged in a single corresponding row). Row 404 includes a set of pads positioned to connect to corresponding host contacts arranged in a configuration according to the Secure Digital (SD) standard for communication (host contact pads are arranged in a single row). In addition to the first row 404, the memory card 402 includes a second row 406 (pads 9-17), which is positioned to connect to host contacts arranged in another configuration to support high-speed communication using a high-speed interface protocol (e.g., a protocol capable of transferring data faster than the SD protocol). Compared to the first row 404, the second row 406 is further from the leading edge of the memory card 402. Figure 4 The distance at the top is greater to connect with the host contacts in the corresponding row of the slot configured for high-speed communication. A microSD Fast Interface compliant memory card (e.g., memory card 402) is compatible with conventional microSD hosts having only host contacts corresponding to the first row 404, and also with μSD Fast hosts having host contacts corresponding to the second row 406 to enable high-speed communication based on the PCIe protocol. Table 1 shows the pad assignments for memory card 402 according to the microSD Fast standard, including conventional microSD pads and PCIe pads.

[0074]

[0075]

[0076] Table 1

[0077] As can be seen, some pads in row 404 are used for both microSD communication and high-speed communication (in this case, PCIe as the high-speed interface protocol). For example, when using the microSD protocol for communication, pads 7 and 8 are used for data (bits 0 and 1, respectively), while when using the PCIe protocol for communication, they are used for reference clock signals. The pads in row 406, combined with these pads in row 404, form a set of pads that are positioned to connect to the corresponding PCIe host contacts of the microSD high-speed host, which are arranged to communicate according to the PCIe protocol.

[0078] Figure 5Another example of a UFS memory card 510 with pad locations for communication with a host is shown. The UFS memory card 510 includes pad 512 for receiving a 3.3V power supply voltage and pad 514 for receiving a ground power supply voltage. Row 516 extends across the memory card 510 below pads 512 and 514 (at a greater distance from the leading edge 518 of the memory card 510 compared to pads 512 and 514). The pads in row 516 are numbered 90 to 99, and the pad assignments are given in Table 2 below (note that pads 91 and 92 in the UFS scheme correspond to pads 514 and 512 and are not included in Table 2).

[0079]

[0080]

[0081] Table 2

[0082] The form factor of memory card 510 differs from that of memory card 402. For example, memory card 510 includes an edge feature 520 that differs from the corresponding edge feature 408 of memory card 402. In some cases, the slot is capable of accommodating memory cards with microSD and UFS form factors.

[0083] Generally, memory cards designed for a given interface standard are only compatible with hosts configured according to the same standard, with some cards being backward compatible with earlier standards (e.g., microSD Fast is backward compatible with traditional microSD). This requires consumers to choose the correct memory card format compatible with one or more of their devices (e.g., choosing between microSD Fast or UFS). In some cases, consumers with multiple devices may have a memory card for one device that is incompatible with another (e.g., a microSD Fast memory card from a camera will not work in a phone or laptop with only a UFS slot), or may need an adapter.

[0084] This technology provides a memory card configured to operate with multiple host interface standards, enabling the same memory card to be used with hosts designed for different host interface standards (e.g., microSD Express and UFS Host). This allows consumers to use the same card with a wider range of devices without the need for adapters.

[0085] Figure 6A This shows the pad arrangement for memory cards compatible with microSD Fast (traditional microSD and PCIe) and UFS host. The first line, 404, includes the pads as previously referenced. Figure 4The pads in the second row, 630, are the conventional microSD pads described in Table 1, used for contacting the corresponding microSD host contacts. The second row of pads 630 typically corresponds to the second row 406 for high-speed communication (e.g., PCIe communication with the PCIe host contacts of the microSD fast slot), and the third row 632 typically corresponds to... Figure 5 Line 516 is used for UFS communication. The pads are numbered according to the corresponding scheme (i.e., microSD fast pads, such as...). Figure 4 Number them as shown in Table 1, while UFS pads are typically as follows: Figure 5 (and numbered as shown in Table 2).

[0086] Extending between the second row 630 and the third row 632 are common pads that extend along the y-direction (perpendicular to the row direction) so that they (at different locations) contact the host contacts of the microSD fast slot and the UFS slot. For example, common pads 624, 626, 628, and 629 extend through rows 630 and 632 such that when a microSD fast slot is inserted (at the location of row 630), they are each aligned with the corresponding microSD fast contact, and when a UFS slot is inserted (at the location of row 632), they are aligned with the corresponding UFS host contact. Figure 6A The pad assignments are shown in Table 3, with shaded rows representing shared pads 624, 626, 628, and 630.

[0087]

[0088] Table 3

[0089] Figure 6A Table 3 shows the pads including a first set of pads along row 404, which are positioned to connect to host contacts arranged according to a conventional microSD configuration for communication according to the microSD standard. A second set of pads (along rows 404 and 630) is positioned to connect to host contacts arranged according to a microSD quick configuration for communication according to the PCIe standard (e.g., as shown in Table 3). Figure 4 (As shown). Some pads in row 404 belong to the first and second groups (pads used for traditional microSD and PCIe communication, such as pads 1, 2, 4, and 6-8), while some are dedicated traditional microSD pads not used for PCIe communication (such as pads 3 and 5). Some pads in the second row 630 (such as pads 17, 11, 12, 14, and 15) are dedicated PCIe pads. The third group of pads is positioned to connect to host contacts arranged according to the UFS configuration for communication according to the UFS standard. The third group of pads includes pads 4 and 6 in row 404 (corresponding to...). Figure 5The common pads 624, 626, 628, and 629 extend between the second row 630 and the third row 632 (UFS pads 512 and 514), the third row 632 pads, and shared pads 624, 626, 628, and 629. These shared pads are shared by the second group (for PCIe communication) and the third group (for UFS communication). Shared pads 624, 626, 628, and 629 extend in the y-direction (perpendicular to the leading edge of the memory card) such that when the memory card is inserted into the microSD quick slot, they are aligned with the PCIe host contacts in the microSD quick configuration (along row 630), and when the memory card is inserted into the UFS slot, they are aligned with the UFS host contacts in the UFS configuration (along row 632). The positions of the corresponding PCIe and UFS pads are indicated by the corresponding reference numbers in the shared pads. For example, shared pad 626 is shown... Figure 4 The microSD fast pad 10 (and the corresponding microSD host contact) is located at position 630 along line 630 and Figure 5 The UFS pads 97 (and the corresponding UFS host contacts) are located along row 632, although these are not physically separate pads in this case. Common pads 624, 626, 628, and 629 are used to receive power supply voltages (e.g., VSS or ground) from the PCIe and UFS host contacts, as shown in Table 3. Additionally, the third row 632 includes dedicated UFS pads (e.g., pads 90, 98, 96, 95, 93, and 92).

[0090] Because conventional microSD host contacts are along row 404, there are no conventional microSD host contacts corresponding to pads in rows 630 and 632. Therefore, pads 1-8 form a first set of pads positioned along row 404 to connect with host contacts arranged in a corresponding first configuration for communication according to the microSD standard.

[0091] The microSD fast interface for communication according to the PCIe protocol includes pads along rows 404 and 630 and corresponding host contacts (a second set of pads positioned to connect to the host contacts arranged in a PCIe configuration along rows 404 and 630). Figure 6B The second set of pads is shown, with shaded areas indicating which pads are contacted by the corresponding host contacts when in a microSD fast slot. Some microSD fast pads used for PCIe communication can also be used for conventional microSD communication (e.g., some pads in line 404 are shared by the first set of pads used for microSD communication and the second set of pads used for PCIe communication).

[0092] In addition to pads 4 and 6 in row 404, the UFS interface for communication according to the UFS standard includes pads along row 632 and corresponding host contacts (positioned to connect to host contacts arranged in a third configuration, a third set of pads for communication according to the UFS standard). Figure 6C The third set of pads is shown, with shading indicating which pads are contacted by the corresponding UFS host contacts when in a UFS slot. Shared pads 624, 626, 628, and 629 are long enough to contact both the microSD host contacts (along line 630) and the UFS host contacts (along line 632), making them shared by the second and third sets.

[0093] like Figures 6A-6C The pads arranged as shown can be implemented in a variety of different memory cards, allowing the memory cards to operate with a variety of host interfaces (e.g., with traditional microSD, microSD Express, and UFS interfaces). Such cards can have different form factors. Figure 7A This is shown as implemented in memory card 750. Figures 6A-6C Lines 404, 630, and 632 indicate that the memory card has the form factor of a microSD fast card. Figure 7A Row 404 is shown at a first distance d1 from the leading edge 752 of the memory card 750, row 630 at a second distance d2 from the leading edge 752, and row 632 at a third distance d3 from the leading edge 752 (distances d1, d2, and d3 are shown as approximate midlines from the corresponding rows).

[0094] Figure 7B Examples of lines 404, 630, and 632 are shown in memory card 756, which has the form factor of a UFS card. Other form factors may also be used.

[0095] While the above arrangement includes four common pads (pads 624, 626, 628, and 629) shared by PCIe and UFS, other arrangements may use a different number of common pads.

[0096] Figure 8 An example including eight common pads is shown. Besides common pads 624, 626, 628, and 629 (for power supply voltage), Figure 8 Common pads 860, 862, 864, and 866 (for data) are shown. Table 4 shows... Figure 8 An example of pad-to-signal mapping in the arrangement, where rows corresponding to shared pads are indicated by shading.

[0097]

[0098]

[0099] Table 4

[0100] Although Figures 6A-6C The example uses a shared pad for the power supply voltage (e.g., a constant voltage such as VSS or ground), but Figure 8 Examples also include pads configured for data communication (data pads configured to transmit data). For example, a pair of shared pads 860 and 862 are used to transmit data in PCIe (PCIe TX+ and PCIe TX-) and UFS (DOUT_T and DOUT_C) using complementary signals. Similarly, another pair of shared pads 864 and 866 are used to receive data in PCIe (PCIe RX- and PCIe RX+) and UFS (DIN_T and DIN_C). These two pairs of data pads can be configured to contact the PCIe host data contacts for operation with the microSD fast host, and to contact the UFS host data contacts for operation with the UFS host. The circuitry connected to such pads can be configured according to the protocol used, such that appropriate voltages and timings are used for different protocols.

[0101] Although Figure 8 In one example, microSD pad 17 and UFS pad 98 are kept as separate pads; however, in another example, these pads are replaced by a common pad that extends to connect to corresponding host contacts, and the circuitry connected to this common pad receives either VDD3 (PCIe) or REFCLK (UFS) depending on the host. The interface circuitry can be configured for UFS communication to receive the clock signal (REFCLK) on the common pad, and configured for PCIe communication to receive the power supply voltage (VDD3) on the common pad. Figure 6A and Figure 8 In this context, the UFS card detection (C / D) pad 90 is only for UFS (it is not physically connected to any host contacts of the microSD fast slot). The number of shared pads can be selected according to this technology and is not limited to this. Figure 6A and Figure 8 Examples.

[0102] Figure 8 The pad arrangement can be implemented in memory cards with different form factors. Figure 9A The memory card 970 is shown, which has the form factor of a microSD card and has, for example, a form factor of 970. Figure 8 The rows 404, 630, and 632 are shown at distances d1, d2, and d3 from the leading edge 972 (where the common pad extends between the rows). Figure 9B The diagram shows a memory card 976, which has the form factor of a UFS memory card, and its implementation... Figure 8 The pad arrangement includes a shared pad extending between rows 630 and 632.

[0103] While the examples above refer to memory cards that use PCIe as the high-speed host protocol (e.g., microSD fast memory cards), some memory cards use other high-speed host protocols. This technology enables memory cards to operate with such high-speed protocols (e.g., memory cards using a different high-speed protocol than PCIe can also operate with UFS). An example of such a memory card is the microSD UHS-II card, which has the form factor of a microSD card and two rows of pads.

[0104] Figure 10 The microSD UHA-II memory card 1000 is shown, which includes two rows of pads. The first row 404 consists of pads 1-8 according to the conventional microSD standard (as described above). The second row 1002 includes pads 9-17, which have similar functions to pads 9-17 of the microSD interface (e.g., similar to Table 1) and are similarly numbered. Pads 9-17 are located in a different position than pads 9-17 of the microSD fast card (e.g., as shown in Table 1). Figure 4 (as shown), and are typically positioned so that their positions overlap with the positions of the UFS pads, making it challenging to manufacture memory cards compatible with microSD UHS-II or UFS slots using separate pads.

[0105] Figure 11 This illustrates an example of a memory card 1100 that can operate with various host interfaces, including conventional microSD, microSD UHS-II, and UFS. The first row 404 consists of pads 1-8 according to the conventional microSD standard. The second row 1102 includes, for example... Figure 10 Pads numbered 9-17 and 1104 are located in the middle. Pad 9-17 is located in the middle. Figure 10 In similar locations, some pads (e.g., pads 10, 13, and 16) have a certain elongation to ensure contact with the host contacts of the microSD UHS-II and UFS slots. Pad 1104 is added and is a card detection (C / D) pad for connection to the corresponding C / D host contacts of the UFS slot (pad 1104 corresponds to...). Figure 5 (C / D pad 90). Pad 1104 is used only for UFS and can be considered an example of a dedicated UFS pad. Although Figure 11 The example shows a memory card 1100 with the form factor of a microSD card, but it may alternatively have the form factor of a UFS card.

[0106] When a memory card compatible with different host interfaces is inserted into a slot (and the pads contact the corresponding host contacts), the memory card can perform certain detection operations to determine which host interface standard will be used (e.g., which pads will be active and which communication protocol will be used). Appropriate circuitry can be provided in the memory card to perform this detection operation (e.g., in response to the memory card receiving power for the first time). For example, a memory card compatible with UFS and other standards can first determine whether it is connected to a UFS interface and configure the interface circuitry accordingly (if so). If it is determined that it is not connected to a UFS interface, another interface standard can be selected, which may include detecting which other standard is being used (e.g., PCIe or traditional microSD).

[0107] Figure 12 An example of control circuitry 1220 is shown located in a memory card (e.g., memory cards 750, 756, 970, 976, 1100) and connected to pads 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229 (shown in cross-section along the outer surface 1230 of the memory card housing and the inner surface 1231 of the host slot). Control circuitry 1220 may be implemented by a controller (e.g., controller 102 or controller 122) and / or other circuitry. Some of pads 1222-1229 are in physical contact with corresponding host contacts, while others are not. For example, pad 1222 is in physical contact with host contact 1232, pad 1224 is in physical contact with host contact 1234, pad 1225 is in physical contact with host contact 1235, pad 1227 is in physical contact with host contact 1237, and pad 1229 is in physical contact with host contact 1239. The physical contact between the pads and their corresponding host contacts establishes an electrical connection between the control circuitry 1220 and the host circuitry, enabling the transfer of digital data between the host and the memory card. Some pads (e.g., pads 1223, 1226, 1228) do not contact any corresponding host contacts (e.g., pads for host interface standards different from those of the slot in this invention). Pads 1222-1229 include pads located in different positions to operate with different host interfaces by connecting to host contacts in different arrangements (e.g., UFS arrangement or microSD quick arrangement). When connected to a given set of host contacts (e.g., when powered on by receiving power supply voltage on one or more power supply pads), control circuitry 1220 can determine the interface standard for communicating with the host and configure the interface circuitry accordingly.

[0108] Control circuitry 1220 is connected to memory structure 1240 (e.g., memory structure 126) to enable a host to access data in memory structure 1240 (e.g., write data to and read data from memory structure 1240). Control circuitry 1220 can perform a conversion function so that different hosts using different interface standards can similarly access memory structure 1240. When using different host standards, communication between control circuitry 1220 and memory structure 1240 can use the same standard (e.g., using a TM interface). Therefore, data can be received from a first host using the UFS protocol, written to memory structure 1240, and subsequently read and sent to a second host using the microSD fast protocol.

[0109] Control circuitry 1220 includes detection circuitry 1242 configured to detect the type of host slot into which a memory card is inserted. For example, in response to the memory card initially receiving power, control circuitry 1220 can detect one or more voltages and / or currents at one or more pads (e.g., pads 1222-1229) to determine the type of host slot (e.g., UFS, microSD Fast / PCIe, or traditional microSD). Control circuitry 1220 also includes interface circuitry 1244 (e.g., host interface 122d, interface 150, and / or host processor 152) configured to communicate with a host using a different interface standard. Control circuitry 1220 also includes configuration circuitry 1246 connected to interface circuitry 1244 and configured to operate using the selected interface standard (e.g., configurable for UFS, PCIe, or microSD). When detection circuitry 1242 determines which type of host slot it is inserted into, it can indicate that type to configuration circuitry 1246. Then, configuration circuitry 1246 can configure interface circuitry 1244 according to type to enable communication with the host. For example, pad 1222 may correspond to C / D pad 90, and detection circuitry 1242 can use the voltage or current at pad 1222 to determine if the memory card is inserted into the UFS slot. Configuration circuitry 1246 can be considered as an example of a device for configuring interface circuitry connected to multiple pads to communicate with a UFS host according to the UFS interface standard, to communicate with a high-speed host according to a high-speed interface protocol (e.g., PCIe or microSD UHS-II), and to communicate with a microSD host according to the microSD protocol.

[0110] Generally, a UFS interface includes card detection (C / D) host contacts and corresponding C / D pads on the UFS-enabled memory card. This allows the UFS host to detect the presence of the UFS-enabled memory card. The UFS-enabled memory card can connect its C / D pads to ground, and the UFS host can detect the memory card by determining that the C / D pads are at or near ground (i.e., close to zero volts or below a certain low threshold voltage).

[0111] According to embodiments of this technology, the C / D pads can also be used by the memory card to detect the UFS host. When the memory card's C / D pads are physically and electrically connected to the corresponding C / D host contacts, the host contacts apply a voltage, which causes some current to flow to ground. This voltage or current can be detected on the memory card side. For example, a resistor can be provided between the C / D pads and ground, and the voltage drop across this resistor can indicate the current from the UFS host's C / D host contacts. The increased voltage at the C / D pads (above ground) can be used to identify when the UFS host applies voltage to the C / D pads.

[0112] Figure 13 An example of detection circuitry 1242 is shown, which can be implemented in any memory card described in the above embodiments. Detection circuitry 1242 is configured to detect when C / D pad 1222 is connected to the UFS host. When the corresponding host contact of the UFS host contacts C / D pad 1222, it applies a voltage VDD (e.g., 1.8 volts) detected by voltage detection circuitry 1340. Switch 1341 is initially open to isolate pad 1222 from ground, and when connected to VDD, it causes the voltage to rise, thereby detecting the voltage. After voltage detection circuitry 1340 detects a voltage (e.g., a voltage above a threshold) and detection circuitry 1242 determines that the memory card is connected to the UFS slot, switch 1341 closes to connect pad 1222 to ground, thereby enabling the host to detect the presence of the UFS card. Detection circuitry 1242 can be considered as an example of a device for detecting a connection to a UFS host.

[0113] Figure 14A An alternative arrangement for detecting the UFS host, which can be implemented in any of the aforementioned memory cards, is shown. In this embodiment, the current measurement circuit 1342 of the detection circuit 1242 measures the current from the pad 1222 to ground. In this embodiment, switching is not required (e.g., the current can flow and be detected by the current measurement circuit 1342 without affecting the detection of the UFS host).

[0114] Figure 14BThe implementation of the current measurement circuit 1342 in the detection circuit 1242 is shown, and a UFS host 1450 is also shown, which applies a voltage VDD to the C / D host contact 1454 via a resistor R1 and a switch 1452. A detection circuit 1456 is provided in the UFS host 1450 to detect the voltage drop at the C / D host contact 1454 when it is grounded through the C / D pad 1222. A resistor R2 is provided in the current measurement circuit 1342 between the pad 1222 and ground, and the current through R2 is measured (e.g., the voltage difference across R2 can be measured to obtain the current). Although the resistor R2 can cause some increase in the voltage at the pad 1222 (i.e., a voltage above zero volts), if R2 is sufficiently small compared to R1, the increased voltage can be small enough that the detection circuit 1456 is unaffected. For example, when VDD is 1.8 volts, R1 is 4.7 kΩ, and the detection circuit 1456 is configured to switch at 0.58 volts (detecting the UFS card when the voltage is below 0.58 volts), R2 can be less than about 2.23 kΩ.

[0115] When a memory card that can operate with multiple host interfaces is powered on, it can perform detection and configuration operations to detect the host interfaces and configure the interface circuitry accordingly for communication with the host. Figure 15 Show the detection (e.g., using) Figure 13-14B Examples of the method steps for configuring (one of the circuits or other such circuits) can be implemented using any of the memory cards described above that are capable of operating with multiple host interface standards.

[0116] At the start of operation 1560 (e.g., when the memory card is powered on due to insertion into a slot and having a power supply voltage supplied to the power pads), the method includes detecting whether a host connected to the memory card (which can operate with multiple host interface standards) is configured to use the Universal Flash Storage (UFS) interface standard 1562, and in response to determining that the host is configured to use the UFS interface standard, configuring the memory card's interface circuitry for UFS communication 1564. In response to determining that the host is not configured to use the UFS interface standard, the method includes determining whether the host is configured to use the Peripheral Component Interface Fast (PCIe) interface standard 1566. In response to determining that the host is configured to use the PCIe interface standard, the method includes configuring the memory card's interface circuitry for PCIe communication 1568, and in response to determining that the host is not configured to use the PCIe interface standard, configuring the memory card's interface circuitry for communication using the Secure Digital (SD) interface standard 1570.

[0117] One embodiment of the memory card includes a plurality of pads disposed on the surface of the memory card, such plurality of pads including: a first set of pads positioned for connection to host contacts arranged in a first configuration for communication according to the microSD standard; a second set of pads positioned for connection to host contacts arranged in a second configuration for communication according to the PCIe standard; and a third set of pads positioned for connection to host contacts arranged in a third configuration for communication according to the UFS standard, such plurality of pads including one or more shared pads shared by the second set of pads and the third set of pads.

[0118] In one embodiment, the first set of pads includes a plurality of microSD pads located at a first distance from the leading edge of the memory card, the second set of pads includes one or more dedicated PCIe pads located at a second distance from the leading edge of the memory card, and the third set of pads includes one or more dedicated UFS pads located at a third distance from the leading edge of the memory card. The shared pads extend in a direction perpendicular to the leading edge of the memory card and extend between the first distance and the second distance.

[0119] In one embodiment, a plurality of microSD pads are arranged in a first row to engage with corresponding microSD host contacts, one or more dedicated PCIe pads are arranged in a second row to engage with corresponding PCIe host contacts, one or more dedicated UFS pads are arranged in a third row to engage with corresponding UFS host contacts, and each shared pad extends from the second row to the third row to engage with a corresponding PCIe host contact at a first position and with a corresponding UFS host contact at a second position.

[0120] In one embodiment, the common pads include one or more common pads configured to receive a constant voltage from the PCIe host contacts and the UFS host contacts.

[0121] In one embodiment, the shared pads include two or more shared data pads configured to transfer data between the memory card and the PCIe host via PCIe host data contacts and between the memory card and the UFS host via UFS host data contacts.

[0122] In one embodiment, two or more shared data pads include a first pair of pads for receiving data via a PCIe host data contact or a UFS host data contact and a second pair of pads for sending data via a PCIe host data contact or a UFS host data contact.

[0123] In one embodiment, the first set of pads includes a plurality of microSD pads located at a first distance from the leading edge of the memory card; the second set of pads includes one or more dedicated PCIe pads located at a second distance from the leading edge of the memory card, the one or more dedicated PCIe pads including PCIe power voltage pads; the third set of pads includes one or more dedicated UFS pads located at a third distance from the leading edge of the memory card, the one or more dedicated UFS pads including UFS card detection pads; and the shared pads extend between the first and second distances and include three shared pads configured to receive a constant voltage and four shared pads for data communication.

[0124] In one embodiment, the memory card includes one or more circuits configured to detect a connection to a UFS host.

[0125] In one embodiment, the third set of pads includes UFS card detection pads, and one or more circuits are configured to detect the voltage supplied to the UFS card detection pads by the host and connect the UFS card detection pads to ground in response to the detection of a connection to the UFS host.

[0126] In one embodiment, the third set of pads includes UFS card detection pads, and one or more circuits are configured to detect current flowing from the card detection pads to ground.

[0127] In one embodiment, one or more circuits are configured to initiate communication using the UFS interface standard in response to the detection of a connection to a UFS host, including configuring two pairs of shared pads for UFS data communication.

[0128] In one embodiment, the memory card has the form factor of a microSD (μSD) card or a UFS card.

[0129] In one embodiment, the plurality of pads includes one or more power pads shared by a first group, a second group, and a third group of pads.

[0130] Embodiments of the method include: detecting whether a host connected to a memory card that can operate with multiple host interface standards is configured to use the Universal Flash Storage (UFS) interface standard; configuring the memory card's interface circuitry for UFS communication in response to determining that the host is configured to use the UFS interface standard; and determining whether the host is configured to use the Peripheral Component Fast Interface (PCIe) interface protocol in response to determining that the host is not configured to use the UFS interface standard. The method also includes configuring the memory card's interface circuitry for PCIe communication in response to determining that the host is configured to use the PCIe interface standard; and configuring the memory card's interface circuitry for communication using the Secure Digital (SD) interface standard in response to determining that the host is not configured to use the PCIe interface protocol.

[0131] In one embodiment, detecting whether the host is configured to use the UFS interface standard includes detecting the voltage on the UFS card detection pads and, in response to detecting a connection to the UFS host, connecting the card detection pads to ground.

[0132] In one embodiment, detecting whether the host is configured to use the UFS interface standard includes detecting the current flowing from the card's detection pads to ground.

[0133] In one embodiment, configuring the interface circuitry of the memory card for UFS communication includes configuring the interface circuitry to receive a clock signal on a common pad, and configuring the interface circuitry of the memory card for PCIe communication includes configuring the interface circuitry to receive a power supply voltage on a common pad.

[0134] One embodiment of the data storage system includes a plurality of pads disposed on a first surface of a memory card, the plurality of pads comprising a first set of pads positioned along a first row to connect to host contacts arranged in a first configuration for communication according to the Secure Digital (SD) standard; a second set of pads positioned along a second row to connect to host contacts arranged in a second configuration for communication according to a High Speed ​​Interface Protocol; a third set of pads positioned along a third row to connect to host contacts arranged in a third configuration for communication according to the Universal Flash Storage (UFS) standard, the third set of pads including a plurality of shared pads shared by the second set of pads and extending across the second and third rows to connect to host contacts arranged in the second or third configuration; and means for detecting a connection to a UFS host.

[0135] In one embodiment, the data storage system may further include means for configuring interface circuitry connected to a plurality of pads to communicate with a UFS host according to the UFS interface standard, to communicate with a high-speed host according to a high-speed interface protocol, and to communicate with a microSD host according to the microSD standard.

[0136] In one embodiment, the high-speed interface protocol is either the Peripheral Component Interface Fast (PCIe) protocol or the Ultra-High Speed-II (UHS-II) protocol.

[0137] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the intended particular use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A memory card, the memory card comprising: A plurality of pads disposed on the surface of a memory card, the plurality of pads comprising: a first set of pads positioned to connect to host contacts arranged in a first configuration for communication in accordance with the microSD standard; and a second set of pads positioned to connect to host contacts arranged in a second configuration for communication in accordance with the Peripheral Component Interconnect Fast PCIe protocol. A third set of pads, positioned to connect to host contacts arranged in a third configuration for communication according to the Universal Flash Storage (UFS) standard, includes one or more shared pads shared by the second and third sets of pads. One or more circuits configured to detect connections to a UFS host.

2. The memory card according to claim 1, wherein the first set of pads includes a plurality of microSD pads located at a first distance from the front edge of the memory card, the second set of pads includes one or more dedicated PCIe pads located at a second distance from the front edge of the memory card, the third set of pads includes one or more dedicated UFS pads located at a third distance from the front edge of the memory card, and the common pads extend in a direction perpendicular to the front edge of the memory card and extend between the first distance and the second distance.

3. The memory card of claim 2, wherein the plurality of microSD pads are arranged in a first row to engage with corresponding microSD host contacts, the one or more dedicated PCIe pads are arranged in a second row to engage with corresponding PCIe host contacts, the one or more dedicated UFS pads are arranged in a third row to engage with corresponding UFS host contacts, and each common pad extends from the second row to the third row to engage with a corresponding PCIe host contact at a first position and with a corresponding UFS host contact at a second position.

4. The memory card of claim 1, wherein the common pads include one or more common pads configured to receive a constant voltage from PCIe host contacts and UFS host contacts.

5. The memory card of claim 4, wherein the common pads comprise two or more common data pads configured to transfer data between the memory card and the PCIe host via PCIe host data contacts and between the memory card and the UFS host via UFS host data contacts.

6. The memory card of claim 5, wherein the two or more shared data pads include a first pair of pads for receiving data via a PCIe host data contact or a UFS host data contact and a second pair of pads for sending data via a PCIe host data contact or a UFS host data contact.

7. The memory card of claim 5, wherein the first set of pads includes a plurality of microSD pads located at a first distance from the leading edge of the memory card, the second set of pads includes one or more dedicated PCIe pads located at a second distance from the leading edge of the memory card, the one or more dedicated PCIe pads including PCIe power voltage pads, the third set of pads includes one or more dedicated UFS pads located at a third distance from the leading edge of the memory card, the one or more dedicated UFS pads including UFS card detection pads, the common pads extending between the first and second distances and including three common pads configured to receive a constant voltage and four common pads for data communication.

8. The memory card of claim 1, wherein one or more common pads include common pads configured to receive clock signals in a UFS configuration and power supply voltages in a PCIe configuration.

9. The memory card of claim 8, wherein the third set of pads includes UFS card detection pads, and the one or more circuits are further configured to detect the voltage supplied by the host to the UFS card detection pads and connect the UFS card detection pads to ground in response to detecting a connection with the UFS host.

10. The memory card of claim 8, wherein the third set of pads includes UFS card detection pads, and the one or more circuits are configured to detect current flowing from the card detection pads to ground.

11. The memory card of claim 1, wherein the one or more circuits are configured to initiate communication using the UFS interface standard in response to the detection of a connection to a UFS host, including configuring two pairs of shared pads for UFS data communication.

12. The memory card of claim 1, wherein the memory card has the form factor of a microSD card or a UFS card.

13. The memory card according to claim 1, wherein the plurality of pads includes one or more power pads shared by the first group, the second group and the third group of pads.

14. A method for configuring a memory card according to claim 1, the method comprising: Determine whether the host connected to a memory card that can operate with multiple host interface standards is configured to use the Universal Flash Storage (UFS) interface standard; In response to determining that the host is configured to use the UFS interface standard, the interface circuitry of the memory card is configured for UFS communication; and In response to determining that the host is not configured to use the UFS interface standard, determine whether the host is configured to use the Peripheral Component Interconnect Fast PCIe interface protocol; In response to determining that the host is configured to use the PCIe interface protocol, the interface circuitry of the memory card is configured for PCIe communication; as well as In response to determining that the host is not configured to use the PCIe interface protocol, the interface circuitry of the memory card is configured to communicate using the microSD interface standard.

15. The method of claim 14, wherein determining whether the host is configured to use the UFS interface standard includes detecting the voltage on the UFS card detection pads and, in response to detecting a connection to the UFS host, connecting the card detection pads to ground.

16. The method of claim 14, wherein determining whether the host is configured to use the UFS interface standard includes detecting current flowing from the card detection pads to ground.

17. The method of claim 14, wherein configuring the interface circuitry of the memory card for UFS communication includes configuring the interface circuitry to receive a clock signal on a common pad, and configuring the interface circuitry of the memory card for PCIe communication includes configuring the interface circuitry to receive a power supply voltage on a common pad.

18. A memory card, the memory card comprising: A first surface, configured to engage the host; A plurality of pads are disposed on the first surface, the plurality of pads including: The first set of pads is positioned along the first row to connect with host contacts arranged in a first configuration for communication in accordance with the microSD standard; The second set of pads, positioned along the second row to connect with the host contacts arranged in the second configuration for communication according to the high-speed interface protocol, and A third set of pads, positioned along the third row to connect with host contacts arranged in a third configuration for communication according to the Universal Flash Storage (UFS) standard, comprising multiple shared pads shared by the second set of pads and extending across the second and third rows to connect with host contacts arranged in a second or third configuration; and A means for detecting the connection of the memory card to the UFS host via the plurality of pads.

19. The memory card of claim 18, further comprising means for configuring interface circuitry connected to a plurality of pads to communicate with a UFS host according to the UFS interface standard, to communicate with a high-speed host according to a high-speed interface protocol, and to communicate with a microSD host according to the microSD standard.

20. The memory card of claim 18, wherein the high-speed interface protocol is one of the Peripheral Component Interconnect Fast (PCIe) protocol or the Ultra-High Speed-II (UHS-II) protocol.

Images