Determine the optical center in an image

Abstract

The optical center is determined column by column and row by row by identifying the brightest pixel in each column and row. The brightest pixel in each column is identified, and a line is fitted to these pixels. Similarly, the brightest pixel in each row is identified, and a second line is fitted to these pixels. The intersection of these two lines is the optical center.

Description

Background Art

[0001] Various applications can generate or receive input image data to perform one or more functions. Image data can be generated by a camera or other acquisition device including a lens. Typically, camera properties are calibrated prior to image acquisition. These images may experience an effect known as vignetting, where pixel intensity decreases from the center of the image toward the edges. This effect can be more pronounced based on various lens characteristics. Various methods can be used to correct vignetting, such as grid-based methods or rectangle fitting. However, these methods are often inadequate for correcting vignetting errors due to poor determination of the image's optical center. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0003] Figure 1A and 1B illustrates vignetting in an image according to at least one embodiment;

[0004] Figure 2 illustrates a pixel layout of an image according to at least one embodiment;

[0005] Figure 3A and 3B illustrates curve fitting over a range of pixel intensity values ​​in accordance with at least one embodiment;

[0006] Figure 4A and 4B shows a line fit to a set of brightest pixel values ​​in accordance with at least one embodiment;

[0007] Figure 4C and 4D illustrates optical center determination at intersections between fitted lines according to at least one embodiment;

[0008] Figure 5 An example process for determining the optical center of an image is shown in accordance with at least one embodiment;

[0009] Figure 6 An example process for determining the optical center of an image is shown in accordance with at least one embodiment;

[0010] Figure 7 An example data center system is shown in accordance with at least one embodiment;

[0011] Figure 8 A computer system according to at least one embodiment is shown;

[0012] Figure 9 A computer system according to at least one embodiment is shown;

[0013] Figure 10 illustrates at least a portion of a graphics processor according to one or more embodiments; and

[0014] Figure 11 At least a portion of a graphics processor is shown in accordance with one or more embodiments. DETAILED DESCRIPTION

[0015] Methods according to various embodiments provide for determining the optical center of an image, such as a flat-field image. Information corresponding to the optical center can then be provided as a calibration factor. Various applications can utilize the rendering, encoding, and / or transmission of image files, such as pictures, video frames, and the like (as examples and non-limiting examples). Vignetting is the effect of a gradual decrease or fall in pixel intensity from the center of an image toward the edges. Figure 1A and 1B An example of images 100, 102 experiencing vignetting is shown, where central regions 104A, 104B are brighter (e.g., have greater pixel intensity) than edge regions 106A, 106B. In various embodiments, images 100, 102 can be generated using one or more lenses. As an example, image 100 can be generated using a normal-length lens, while image 102 can be generated using a fisheye lens. It should be understood that these lenses are provided as examples, and any type of lens can be used by various devices to generate images 100, 102.

[0016] Optical vignetting can be a result of the lens used to acquire the image, with the vignetting centered at or approximately at the optical center of the image. While various correction algorithms are available, these methods either only approximate the optical center or utilize additional information, such as a calibration image, which can also be referred to as a flat-field image. A flat-field image can be an image with uniform illumination. For example, the illumination can be provided by scattered light from one or more directions. However, due to the illumination of this image, the area around the vignetting center can be so flat that noise dominates the pixel intensity variations. Consequently, identifying the image center can be challenging, and traditional methods are unable to accurately identify the center.

[0017] Figure 2 An example pixel layout 200 of an image 202 is shown, where the pixel layout 200 is represented by vertical lines 204 and horizontal lines 206 that divide the image 202 into individual pixels 208. It should be understood that Figure 2208 . The embodiment shown is for illustrative purposes only, and the image may include more pixels. In addition, lines 204, 206 are provided as illustrative markers to show the separation between adjacent pixels 208. In operation, each pixel 208 will have a value corresponding to the brightness or intensity of the pixel 208, for which, as described above, pixels near the center region 104 may be brighter than pixels near the edge region 106 due to vignetting. In one embodiment, the brightest or highest intensity pixel can be identified within each row 210 and each column 212 of the image 202. As will be described in detail below, the identification of the brightest pixel in each row 210 and / or column 212 may include fitting a curve to the data corresponding to the individual pixels forming the row or column and determining the maximum or peak of the curve to identify the brightest or substantially brightest pixel. It should also be understood that fractional pixels or floating point values ​​of pixels may also be used as the brightest or substantially brightest pixel.

[0018] Figure 3A A graphical representation 300 of a series of pixel intensity values ​​302 is shown. In this example, the x-axis 304 represents pixel position and the y-axis 306 represents pixel intensity. As described above, vignetting typically causes a gradual decrease in intensity at the edges, and therefore, the pixels 208 are arranged so that pixels 208 near the center region 104 have a greater intensity than the intensity at the edges. In this example, a fitting curve 308, shown as a 1D curve, is arranged (e.g., fitted) on the pixels 208 to identify the highest intensity pixels 310. As noted, the highest intensity pixels can include whole pixels, fractional pixels, floating point values, etc. It should be understood that the highest intensity pixels 310 can correspond to pixels with a maximum value and / or values ​​within a threshold amount of adjacent pixels. That is, embodiments of the present disclosure can identify pixel values ​​that are within a threshold amount of the maximum value. The highest intensity pixels 310 can be extracted from the series 302 for later use.

[0019] In at least one embodiment, the fitting curve 308 is mathematically derived using a curve fitting technique. The curve can be based on a moving average, a quartic polynomial, a cubic polynomial, a quadratic polynomial, or any other reasonable curve fitting technique. In embodiments, different curve fitting techniques can be applied and then compared to each other, for example, to determine the difference or range between the identified highest intensity pixels 310. Thus, in embodiments, the highest intensity pixel 310 can be determined by averaging the highest intensity pixels of the different curve fitting techniques. Furthermore, it should be understood that different curve fitting techniques can be used for different columns and / or rows. That is, the same technique may not be applied to every column and / or every row of an image. Various embodiments of the present disclosure may apply the curve fitting technique to each individual column and / or each individual row to determine a range of highest intensity pixels, as will be described below. It should be understood that the curve fitting technique can be selected to at least partially account for the noise of the image, as described above.

[0020] Figure 3B A graphical representation 312 of a series of pixel intensity values ​​314 is shown. In this example, the x-axis 304 represents pixel position and the y-axis 306 represents pixel intensity. As described above, vignetting typically results in a gradual decrease in intensity at the edges, and therefore, the pixels 208 are arranged so that the pixels 208 near the center region 104 have a greater intensity than the intensity at the edges. This effect may be more pronounced in cases where the image is produced by a fisheye lens, as is the case with representation 312. For images produced with a fisheye lens, the sides may be almost completely black (e.g., low intensity), as shown in FIG. Figure 3B , as shown in FIG. 3 . These regions 316 illustrate low-intensity pixels having substantially the same value, indicating a darkening or black edge of the image. Thus, in at least one embodiment, the flat regions 316 can be clipped or otherwise omitted from the curve fit described above to determine the highest intensity pixels.

[0021] In this example, portion 318 is cropped or otherwise isolated for curve fitting analysis. It should be understood that portion 318 can be determined using a variety of methods, such as a percentage of series 314, the slope of a curve formed by series 314, and so forth. By way of example only, portion 318 may have a starting position approximately 25% from an edge of the image and an ending position approximately 25% from an opposite edge of the image. In other words, portion 318 may span between approximately 25% and 75% of the length of series 314. Thereafter, fitting curve 320 is applied to pixels 208 within portion 318 to identify highest intensity pixels 322. As described above, various methods can be used to generate fitting curve 320. Due to portion 318, flat regions at the edges, which may be difficult to fit due to their significantly different shape from the rest of series 314, are omitted, thereby providing a more accurate fitting curve 320. It should be understood that highest intensity pixel 322 may correspond to a pixel with a maximum value and / or a value within a threshold amount of adjacent pixels, as described above. Furthermore, highest intensity pixel 322 may also correspond to a fractional pixel or floating point value. In one or more embodiments, at least a portion of one or more columns or one or more rows is removed. For example, one or more pixels along the top or bottom edge can be removed. Additionally, one or more pixels along the left or right edge can be removed. Thus, rather than removing an entire row or column from the evaluation, only certain pixels forming a row or column can be removed.

[0022] In at least one embodiment, each of the highest intensity pixels 310 , 322 from each row and / or each column may be identified and plotted together. Figure 4AA representation 400 of a set 402 of the brightest pixels from all image columns is shown. It should be understood that while embodiments may describe the use of all image columns, various embodiments may sample a subset of image columns within an image. For example, resource consumption may be reduced by evaluating every other column, every third column, and so on. Furthermore, the cropping or slicing applied above may also be used to focus on specific areas of the image to reduce the total number of rows and / or columns analyzed. As depicted, set 402 extends substantially horizontally across the image. However, as shown, some variations are possible based on the analysis previously performed to identify the brightest pixels. In at least one embodiment, a best-fit line 404 is applied to set 402. As shown, portions of set 402 may be positioned above or below best-fit line 404. It should be understood that best-fit line 404 may be a substantially straight line that can be fitted using one or more fitting algorithms. In at least one embodiment, best-fit line 404 may be applied to one or more different sets 402, each calculated using a different curve-fitting technique to determine best-fit line 404. For example, three different curve fitting techniques may be applied to generate different sets 402, and then three different best fit lines 404 may be generated, one for each of the different sets 402. These different best fit lines 404 may then be compared to identify the best fit line 404 that has the highest correlation with the sets 402, and the best fit line 404 with the highest correlation may be selected.

[0023] Figure 4BA representation 406 of a set 408 of the brightest pixels from all image rows is shown. It should be understood that while embodiments may describe using all image rows, various embodiments may sample a subset of image rows within an image. For example, resource consumption may be reduced by evaluating every other row, every third row, etc. Furthermore, the cropping or slicing applied above can also be used to focus on specific areas of the image to reduce the total number of rows and / or columns analyzed. This is an example, with set 408 extending substantially vertically across the image; however, as shown, some variation is possible based on the analysis previously performed to identify the brightest pixels. In at least one embodiment, a best-fit line 410 is applied to set 408. As shown, portions of set 408 may lie to the left or right of best-fit line 410. It should be understood that best-fit line 410 may be a substantially straight line that can be fitted using one or more fitting algorithms. As described above, best-fit line 410 may be applied to one or more different sets 408, each calculated using a different curve-fitting technique to determine best-fit line 408. For example, three different curve fitting techniques may be applied to generate different sets 408, and then three different best fit lines 410 may be generated, one for each of the different sets 408. These different best fit lines 410 may then be compared to identify the best fit line 410 that has the highest correlation with the sets 408, and the best fit line 410 with the highest correlation may be selected.

[0024] It should be understood that in some embodiments, dust or dirt may be present on the lens, which may distort or otherwise affect the pixel intensity of one or more columns or rows. For example, an outlier pixel may be located within set 408. An outlier pixel may correspond to a pixel located at a distance exceeding a threshold from other pixels. As an example, an outlier pixel of set 408 may correspond to a pixel whose intensity is greater than a certain percentage of one or more surrounding pixels. Furthermore, an outlier pixel may be determined based at least in part on the distance between a pixel within set 408 and a best fit line 410. In one or more embodiments, a pixel that is a threshold distance from the best fit line 410 may be considered an outlier pixel. As another example, an outlier pixel may be located within set 402, and embodiments of the present disclosure may determine the distance between a pixel within set 402 and the best fit line 404. If the distance between a pixel and the best fit line 404, 410 exceeds the threshold distance, the pixel may be discarded and the best fit lines 404, 410 may be recalculated without the outlier pixel.

[0025] Figure 4CA representation 412 of an optical center point 414 is shown, identified at the intersection between the best fit lines 404 and 410. The optical center point 414 takes into account the brightest point from each identified row and column, where the intersection corresponds to the brightest point for the horizontal row and vertical column. As described above, the optical center point 414 can correspond to a pixel location, a fractional pixel, or a floating point value, among other options. Thus, the pixel location corresponding to the optical center point 414 can be used for calibration of various imaging devices. As described above, these devices can be used in a variety of different applications, such as vehicles, user device cameras, robotics, video analytics, and the like. Furthermore, calibration can be used in conjunction with image signal processing, for example, with dedicated hardware components that can be pre-calibrated before the hardware is provided to the user. Furthermore, in various embodiments, calibration information for a set of hardware components can be provided to the user so that they can perform their own calibration.

[0026] Figure 4D A representation 416 is shown identifying an optical center point 418 where the lens used to obtain the calibration image is tilted relative to the sensor plane. As a result, the vignetting may be elliptical rather than substantially circular. As described above, the optical center point 418 may correspond to a pixel location, a fractional pixel, or a floating point value, among other options. As shown, the set 420 corresponding to the points associated with the rows and the set 422 corresponding to the columns each include a best fit line 424, 426. As described above, the intersection of the best fit lines 424, 426 corresponds to the optical center point 418. Thus, embodiments can be used to identify the optical center even when the lens is tilted or otherwise misaligned, thereby providing further improvement to complex algorithms that may require better alignment between components in order to produce reliable results.

[0027] Figure 5An example process 500 for determining the optical center of an image is shown. It should be understood that for this and other processes presented herein, unless otherwise specifically stated, additional, fewer, or alternative steps may be performed in a similar or alternative order, or at least partially in parallel, within the scope of various embodiments. In this example, a calibration image is acquired 502. The calibration image may be a flat-field image generated for the purpose of calibrating one or more hardware components corresponding to an imaging device, such as a camera. The brightest pixel for each column of the calibration image is determined 504. As described above, each column of pixels forming the image may be evaluated to determine the brightest pixel. In at least one embodiment, the brightest pixel is determined by establishing a brightness or intensity value for each pixel, fitting a curve to these values, and then determining the peak of the curve. The brightest pixel is also determined for each row of the calibration image 506. The brightest pixels from the rows and columns may be used to generate corresponding sets of pixels. A column fit line fits the brightest pixels in column 508, and a row fit line fits the brightest pixels in row 510. In various embodiments, the line is a straight line or a substantially straight line, but it should be understood that various embodiments may also include a curve. The fitted line is then placed along the image to determine the intersection point 512, which corresponds to the optical center of the image.

[0028] Figure 6 An example process 600 for determining an optical center in an image is shown. In this example, a plurality of pixel columns and pixel rows are determined 602. For example, an image, such as a flat-field image corresponding to a calibration image, can be evaluated to determine the rows and columns of pixels that form the image. The corresponding pixel rows and columns can then be evaluated. For example, a column brightest pixel can be determined from a column of pixels in the plurality of columns 604. Additionally, a row brightest pixel can be determined from one or more pixel rows in the plurality of rows 606. As described herein, the brightest pixel can be determined by evaluating the pixel intensity values ​​of each pixel forming the row and / or column, fitting a curve to these values, and then determining the peak of the curve. A subset of column pixels can be generated 608, wherein the subset includes the column brightest pixel at the corresponding column pixel position. Additionally, a subset of row pixels can be generated 610, wherein the subset includes the row brightest pixel at the corresponding row pixel position.

[0029] In at least one embodiment, a determination is made as to whether there are additional columns and / or pixels to evaluate 612. If so, the process can be repeated until a corresponding brightest column pixel and brightest row pixel are found for each column and / or row of the image. As a result, each subset can include multiple different column brightest pixels at different locations. In at least one embodiment, a column fit line is determined for a subset of column pixels 614. Additionally, a row fit line is determined for a subset of row pixels 616. These fit lines can then be evaluated to determine the optical center of the image 618, where the optical center can correspond to the intersection of the column fit line and the row fit line.

[0030] In various embodiments, the systems and methods of the present disclosure can be associated with hardware components that are calibrated prior to use. For example, a calibration image can be obtained using a hardware component or set of components. The optical center of the image can be determined to serve as calibration data. This calibration data can then be used with various other algorithms or processes associated with the hardware, such as radial lens shading, lens distortion, color, and the like. In this way, the optical center can be provided as calibration data to correct images obtained using the hardware component.

[0031] In some embodiments, the optical center can be reestablished or re-determined over time, for example if one or more characteristics of a hardware component degrade. Thus, the process can be repeated with a new or updated calibration image. Thereafter, the newly determined optical center can be provided to the image processing pipeline to update and refine the calibration data.

[0032] Data Center

[0033] Figure 7 An example data center 700 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0034] In at least one embodiment, Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources ("node CRs") 716(1)-716(N), where "N" represents any positive integer. In at least one embodiment, the node CRs 716(1)-716(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NWI / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 716(1)-716(N) may be servers having one or more of the above-mentioned computing resources.

[0035] In at least one embodiment, the grouped computing resources 714 can include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 714 can include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor can be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches, in any combination.

[0036] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may comprise a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 107 may comprise hardware, software, or some combination thereof.

[0037] In at least one embodiment, Figure 7 As shown, the framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, the framework layer 720 may include a framework that supports software 732 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 732 or the application 742 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 728 for large-scale data processing (e.g., "big data"). TM(hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be capable of configuring different layers, such as the software layer 730 and the framework layer 720 including Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 may be capable of managing the cluster or group computing resources mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the cluster or group computing resources may include the group computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0038] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. The one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0039] In at least one embodiment, the one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0040] In at least one embodiment, any of configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 700 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0041] In at least one embodiment, the data center 700 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 700. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to the data center 700.

[0042] In at least one embodiment, a data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0043] This type of component can be used to determine the optical center of a hardware component, such as a camera or imaging device with a lens.

[0044] Computer system

[0045] Figure 8 800 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, computer system 800 may include, but is not limited to, components such as processor 802, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 800 may include a processor such as the Intel® processor 802 available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , CoreTM or The computer system 800 may be based on a Nervana™ microprocessor, although other systems may also be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, the computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0046] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0047] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0048] In at least one embodiment, processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 802. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 806 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0049] In at least one embodiment, logic execution unit 808, including but not limited to performing integer and floating point operations, is also located in processor 802. In at least one embodiment, processor 802 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 808 may include logic for processing a packed instruction set 809. In at least one embodiment, by including the packed instruction set 809 in the instruction set of a general-purpose processor, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in processor 802. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0050] In at least one embodiment, execution unit 808 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals that may be executed by processor 802.

[0051] In at least one embodiment, the system logic chip can be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 can communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 can provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 can initiate data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 can be coupled to the memory 820 via the high-bandwidth memory path 818, and the graphics / video card 812 can be coupled to the MCH 816 via an Accelerated Graphics Port ("AGP") interconnect 814.

[0052] In at least one embodiment, the computer system 800 may use a system I / O 822, which is a proprietary hub interface bus, to couple the MCH 816 to an I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 may provide direct connections to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 820, chipset, and processor 802. Examples may include, but are not limited to, an audio controller 828, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, a data store 824, a legacy I / O controller 823 including a user input and keyboard interface, a serial expansion port 827 (e.g., a Universal Serial Bus (USB) port), and a network controller 834. The data store 824 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0053] In at least one embodiment, Figure 8 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 8An exemplary system on a chip (SoC) may be shown. In at least one embodiment, the devices may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 800 are interconnected using a Compute Express Link (CXL) interconnect.

[0054] This type of component can be used to determine the optical center of a hardware component, such as a camera or imaging device with a lens.

[0055] Figure 9 is a block diagram illustrating an electronic device 900 for utilizing a processor 910 in accordance with at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0056] In at least one embodiment, the system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 910 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 9 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 9 An exemplary system on a chip (SoC) may be shown. In at least one embodiment, Figure 9 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 9 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0057] In at least one embodiment, Figure 9The system may include a display 924, a touch screen 925, a touchpad 930, a near field communication unit ("NFC") 945, a sensor hub 940, a thermal sensor 946, a fast chipset ("EC") 935, a trusted platform module ("TPM") 938, a BIOS / firmware / flash memory ("BIOS, FWFlash") 922, a DSP 960, a drive 920 (e.g., a solid-state disk ("SSD") or a hard disk drive ("HDD")), a wireless local area network unit ("WLAN") 950, a Bluetooth unit 952, a wireless wide area network unit ("WWAN") 956, a global positioning system (GPS) 955, a camera ("USB 3.0 camera") 954 (e.g., a USB 3.0 camera), and / or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 915 implemented using, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0058] In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components described above. In at least one embodiment, an accelerometer 941, an ambient light sensor (“ALS”) 942, a compass 943, and a gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, a thermal sensor 939, a fan 937, a keyboard 936, and a touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, a speaker 963, an earpiece 964, and a microphone (“mic”) 965 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 962, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 962 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952 and the WWAN unit 956 may be implemented as a next generation form factor (NGFF).

[0059] This type of component can be used to determine the optical center of a hardware component, such as a camera or imaging device with a lens.

[0060] Figure 101000 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1002 or processor cores 1007. In at least one embodiment, system 1000 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0061] In at least one embodiment, the system 1000 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the system 1000 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 1000 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0062] In at least one embodiment, one or more processors 1002 each include one or more processor cores 1007 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a specific instruction set 1009. In at least one embodiment, the instruction set 1009 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or compute via very long instruction words (VLIW). In at least one embodiment, the processor cores 1007 can each process a different instruction set 1009, which can include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 1007 can also include other processing devices, such as a digital signal processor (DSP).

[0063] In at least one embodiment, processor 1002 includes cache memory 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 1002. In at least one embodiment, processor 1002 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among processor cores 1007 using known cache coherence techniques. In at least one embodiment, processor 1002 further includes a register file 1006. The processor may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, register file 1006 may include general purpose registers or other registers.

[0064] In at least one embodiment, one or more processors 1002 are coupled to one or more interface buses 1010 to transmit communication signals, such as address, data, or control signals, between the processors 1002 and other components in the system 1000. In at least one embodiment, the interface bus 1010 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1010 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1002 includes an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, the memory controller 1016 facilitates communication between memory devices and other components of the processing system 1000, while the platform controller hub (PCH) 1030 provides connections to I / O devices via a local I / O bus.

[0065] In at least one embodiment, memory device 1020 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other suitable memory device for use as processor memory. In at least one embodiment, memory device 1020 may be used as system memory for processing system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute applications or processes. In at least one embodiment, memory controller 1016 is also coupled to an optional external graphics processor 1012, which may communicate with one or more graphics processors 1008 in processor 1002 to perform graphics and media operations. In at least one embodiment, display device 1011 may be connected to processor 1002. In at least one embodiment, display device 1011 may include one or more internal display devices, such as in a mobile electronic device or laptop, or an external display device connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 1011 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0066] In at least one embodiment, the platform controller hub 1030 enables peripheral devices to connect to the storage device 1020 and the processor 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, and a data storage device 1024 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1024 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1025 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1026 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1028 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, a network controller 1034 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1010. In at least one embodiment, the audio controller 1046 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1000 includes an optional legacy I / O controller 1040 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 1000. In at least one embodiment, the platform controller hub 1030 can also be connected to one or more Universal Serial Bus (USB) controllers 1042, which connect input devices such as a keyboard and mouse 1043 combination, a camera 1044, or other USB input devices.

[0067] In at least one embodiment, instances of memory controller 1016 and platform controller hub 1030 may be integrated into a discrete external graphics processor, such as external graphics processor 1012. In at least one embodiment, platform controller hub 1030 and / or memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, system 1000 may include external memory controller 1016 and platform controller hub 1030, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 1002.

[0068] This type of component can be used to determine the optical center of a hardware component, such as a camera or imaging device with a lens.

[0069] Figure 11is a block diagram of a processor 1100 having one or more processor cores 1102A-1102N, an integrated memory controller 1114, and an integrated graphics processor 1108, in accordance with at least one embodiment. In at least one embodiment, processor 1100 may include additional cores, up to and including additional core 1102N, which is represented by a dashed box. In at least one embodiment, each processor core 1102A-1102N includes one or more internal cache units 1104A-1104N. In at least one embodiment, each processor core may also have access to one or more shared cache units 1106.

[0070] In at least one embodiment, the internal cache units 1104A-1104N and the shared cache unit 1106 represent a cache memory hierarchy within the processor 1100. In at least one embodiment, the cache memory units 1104A-1104N may include at least one level of instruction and data cache within each processor core and one or more levels of cache within a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is categorized as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 1106 and 1104A-1104N.

[0071] In at least one embodiment, processor 1100 may further include a set of one or more bus controller units 1116 and a system agent core 1110. In at least one embodiment, the one or more bus controller units 1116 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, system agent core 1110 provides management functions for various processor components. In at least one embodiment, system agent core 1110 includes one or more integrated memory controllers 1114 to manage access to various external memory devices (not shown).

[0072] In at least one embodiment, one or more processor cores 1102A-1102N include support for simultaneous multithreading. In at least one embodiment, system agent core 1110 includes components for coordinating and operating cores 1102A-1102N during multithreaded processing. In at least one embodiment, system agent core 1110 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 1102A-1102N and graphics processor 1108.

[0073] In at least one embodiment, processor 1100 also includes a graphics processor 1108 for performing graphics processing operations. In at least one embodiment, graphics processor 1108 is coupled to a shared cache unit 1106 and a system agent core 1110 including one or more integrated memory controllers 1114. In at least one embodiment, system agent core 1110 also includes a display controller 1111 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, display controller 1111 may also be a separate module coupled to graphics processor 1108 via at least one interconnect, or may be integrated within graphics processor 1108.

[0074] In at least one embodiment, a ring-based interconnect 1112 is used to couple the internal components of the processor 1100. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 1108 is coupled to the ring interconnect 1112 via an I / O link 1113.

[0075] In at least one embodiment, I / O link 1113 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1118 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 1102A-1102N and graphics processor 1108 uses embedded memory module 1118 as a shared last-level cache.

[0076] In at least one embodiment, the processor cores 1102A-1102N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 1102A-1102N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 1102A-1102N execute a common instruction set, while one or more other processor cores 1102A-1102N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 1102A-1102N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 1100 can be implemented on one or more chips or as a SoC integrated circuit.

[0077] This type of component can be used to determine the optical center of a hardware component, such as a camera or imaging device with a lens.

[0078] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0079] Unless otherwise noted or clearly contradicted by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include," "have," "include," and "contain" should be interpreted as open-ended terms (meaning "including but not limited to"). The term "connected" (when unmodified, refers to a physical connection) should be interpreted as partially or completely contained within, attached to, or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were separately recited herein. Unless otherwise noted or contradicted by the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0080] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" are understood in context to be generally used to refer to an item, clause, or the like, which may be A or B or C, or any non-empty subset of the set A, B, and C. For example, in the illustrative example of a set having three members, the conjunctions "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctions are not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to plurality (e.g., "a plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0081] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having executable instructions stored thereon, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0082] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system comprising multiple devices operating in different ways such that the distributed computer system performs the operations described herein and such that no single device performs all of the operations.

[0083] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illuminate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0084] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0085] In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0086] Unless expressly stated otherwise, it is understood that throughout this specification, terms such as “process,” “calculate,” “calculate,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers, or other such information storage, transmission, or display devices of the computing system.

[0087] In a similar manner, the term "processor" may refer to any device or portion of a memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As non-limiting examples, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process may refer to multiple processes to execute instructions continuously or intermittently, sequentially, or in parallel. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0088] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, a computer system, or a computer-implemented machine. Analog and digital data can be obtained, acquired, received, or input in a variety of ways, such as by receiving data as parameters of a function call or a call to an application programming interface (API). In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as input or output parameters of a function call, an application programming interface, or an interprocess communication mechanism.

[0089] Although the above discussion sets forth example implementations of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. In addition, although specific responsibilities are defined above for discussion purposes, the various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0090] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A computer-implemented method comprising: for each of a plurality of columns of pixels forming an image, determining a corresponding first pixel corresponding to a first brightest pixel; for each of a plurality of rows of pixels forming the image, determining a corresponding second pixel corresponding to a second brightest pixel; fitting a first fitted line to the corresponding first pixel; fitting a second fitted line to the corresponding second pixel; identifying an intersection point between the first fitted line and the second fitted line; as well as The identifier of the intersection point is provided to calibrate an imaging device used to generate the image.

2. The computer-implemented method of claim 1, wherein the intersection point corresponds to the optical center of the image.

3. The computer-implemented method of claim 1 , further comprising: determining the imaging device that generates the image using a fisheye lens; removing at least a portion of one or more of the plurality of columns, the portion of the one or more columns corresponding to one or more pixels along at least one of an upper edge or a lower edge of the image; as well as At least a portion of one or more rows of the plurality of rows is removed, the portion of the one or more rows corresponding to one or more pixels along at least one of a left edge or a right edge of the image.

4. The computer-implemented method of claim 1 , further comprising: determining a first fitting curve for each of the plurality of columns of pixels; as well as A maximum point along the first fitting curve is identified, the maximum point corresponding to the respective first pixel of each column.

5. The computer-implemented method of claim 1 , determining a second fitting curve for each of the plurality of rows of pixels; and A maximum point along the second fitting curve is identified, the maximum point corresponding to the respective second pixel of each row.

6. The computer-implemented method of claim 5, wherein: The second fitting curve is at least one of a moving average, a fourth-order polynomial, a third-order polynomial, and a second-order polynomial.

7. The computer-implemented method of claim 1 , further comprising: determining a distance between an outlier pixel and the first fitted line; determining that the distance exceeds a threshold; generating a subset of the corresponding first pixels, the subset omitting the outlier pixel; as well as A modified first fitted line is fitted to the subset of the corresponding first pixels.

8. The computer-implemented method of claim 7, further comprising: The intersection point between the modified first fitted line and the second fitted line is identified.

9. A system comprising: at least one processor; as well as A memory storing instructions that, when executed, cause the system to: Access flat-field images; determining a first line representing brightest pixels in a plurality of columns of pixels forming the flat-field image; determining a second line representing brightest pixels in a plurality of rows of pixels forming the flat-field image; as well as An intersection point between the first line and the second line is determined, the intersection point corresponding to an optical center of the flat-field image.

10. The system of claim 9, wherein: The instructions, when executed, further cause the system to: At least a portion of a calibration file is generated, the calibration file including position information of the optical center of the flat-field image.

11. The system of claim 9, wherein the instructions, when executed, further cause the system to: omitting at least a portion of one or more of the plurality of columns, the portion of the one or more columns corresponding to one or more pixels along at least one of an upper edge or a lower edge of the flat-field image; and At least a portion of one or more rows of the plurality of rows is omitted, the portion of the one or more rows corresponding to one or more pixels along at least one of a left edge or a right edge of the flat-field image.

12. The system of claim 9, wherein the plurality of columns corresponds to each column of pixels forming the flat-field image, and the plurality of rows corresponds to each row of pixels forming the flat-field image.

13. The system of claim 9, wherein: The instructions, when executed, further cause the system to: determining a corresponding column fit curve for each column in the plurality of columns; Determine the corresponding brightest column pixel for each corresponding column fitting curve; Extract each corresponding brightest column pixel; as well as A series of column pixels are generated from the extracted brightest column pixels.

14. The system of claim 9, wherein: The instructions, when executed, further cause the system to: determining a corresponding row fitting curve for each row in the plurality of rows; Determine the corresponding brightest row pixel for each corresponding row fitting curve; Extract each corresponding brightest row of pixels; as well as A series of row pixels are generated from the extracted brightest row pixels.

15. The system of claim 9, wherein the optical center is at least one of a pixel position, a fractional pixel, or a floating point value.

16. A computer-implemented method comprising: generating corresponding column fitting curves for a plurality of columns from the flat-field image; determining a plurality of first pixels for each of the plurality of columns from the corresponding column fit curve; generating a plurality of corresponding row fitting curves from the flat-field image; determining a plurality of second pixels for each of the plurality of rows from the corresponding row fitted curve; fitting a first line to the plurality of first pixels; fitting a second line to the plurality of second pixels; as well as An optical center of the flat-field image is determined based at least in part on the first line and the second line.

17. The computer-implemented method of claim 16, wherein: The optical center corresponds to an intersection point between the first line and the second line.

18. The computer-implemented method of claim 16, further comprising: determining a distance between an outlier pixel and the first line; determining that the distance exceeds a threshold; removing the outlier pixel from the plurality of first pixels to form a second plurality of first pixels; as well as The first line is refitted to the second plurality of first pixels.

19. The computer-implemented method of claim 16, wherein at least one of the row fit curve or the column fit curve is at least one of a moving average, a quartic polynomial, a cubic polynomial, or a quadratic polynomial.

20. The computer-implemented method of claim 19, further comprising: Determining position information of the optical center; as well as At least a portion of a calibration file is generated, the calibration file including the position information.

Images