Semiconductor memory device

Abstract

The nonvolatile memory (2) of the embodiment has a memory cell array (23) having a plurality of memory cell transistors (MT), a plurality of word lines (WL) connected to a plurality of gates of the plurality of memory cell transistors (MT) respectively, a VPGM monitor (34) connected to at least one of the plurality of word lines (WL), and a sequencer (27). The sequencer (27) detects a voltage of a selected word line WLs selected from among the plurality of word lines (WL) by the VPGM monitor (34) when a write voltage VPGM is applied to the selected word line WLs at the time of writing data to the memory cell array (23), and makes a determination as to whether or not a detected detection voltage DV reaches a prescribed value.

Description

[0001] Citation of relevant applications

[0002] This application is based on and claims the benefit of priority of the prior Japanese Patent Application No. 2021-024460, filed on February 18, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor memory devices. Background Technology

[0004] There are semiconductor memory devices that omit the verification process. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor memory device with improved write performance.

[0006] One embodiment of a semiconductor memory device includes: a memory cell array having a plurality of memory cell transistors; a plurality of word lines respectively connected to a plurality of gates of the plurality of memory cell transistors; a voltage detection circuit connected to at least one word line of the plurality of word lines; and a control circuit that, when writing data to the memory cell array, when a write voltage is applied to a selected word line selected from the plurality of word lines, detects the voltage of the selected word line by the voltage detection circuit and determines whether the detected voltage has reached a predetermined value.

[0007] Based on the above configuration, a semiconductor memory device with improved write performance can be provided. Attached Figure Description

[0008] Figure 1 This is a block diagram of the memory system in this embodiment.

[0009] Figure 2 This is a block diagram of the non-volatile memory in this embodiment.

[0010] Figure 3 This is a block diagram of the readout amplifier in this embodiment.

[0011] Figure 4 This is a circuit diagram of the non-volatile memory in this embodiment.

[0012] Figure 5 This is a flowchart illustrating the writing operation in this embodiment.

[0013] Figure 6 This is a graph showing the voltage of the select word line and the detection voltage in this embodiment.

[0014] Figure 7is a block diagram of a nonvolatile memory of another example of the present embodiment.

[0015] Figure 8 is a circuit diagram of a nonvolatile memory of another example of the present embodiment.

[0016] Figure 9 is a flowchart showing a write operation of a modification example 1 of the present embodiment.

[0017] Figure 10 is a flowchart showing a write operation of a modification example 2 of the present embodiment.

[0018] Figure 11 is a graph showing a voltage of a selected word line and a voltage detection timing of a modification example 3 of the present embodiment.

[0019] Figure 12 is a graph showing a voltage of a selected word line and a voltage detection timing of a modification example 4 of the present embodiment.

[0020] Figure 13 is a graph showing a setting method of a prescribed value of a modification example 5 of the present embodiment.

[0021] Figure 14 is a graph showing a setting method of a prescribed value of a modification example 6 of the present embodiment.

[0022] Figure 15 is a block diagram of a nonvolatile memory of a modification example 7 of the present embodiment.

[0023] Figure 16 is a flowchart showing an erase operation of a modification example 7 of the present embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, the embodiments will be described with reference to the drawings.

[0025] (Configuration of Memory System)

[0026] Figure 1 is a block diagram of a memory system. The memory system of the present embodiment is provided with a memory controller 1 and a nonvolatile memory 2. The memory system can be connected with a host. The host is, for example, an electronic device such as a personal computer, a portable terminal, and the like.

[0027] The nonvolatile memory 2 is a semiconductor storage device that stores data nonvolatilely, and is provided with, for example, a NAND type flash memory. In the present embodiment, a case where the nonvolatile memory 2 is a NAND memory having a memory cell transistor MT capable of storing 1 bit per memory cell transistor MT, that is, a 1 bit / Cell (SLC: Single Level Cell) NAND memory, is described, but is not limited thereto.

[0028] For example, the nonvolatile memory 2 can also be a NAND memory having a memory cell transistor MT capable of storing 2 bits or 3 bits per memory cell transistor MT, that is, a NAND memory of a multi-value cell such as 2 bits / cell (MLC: Multipler Level Cell) or 3 bits / cell (TLC: Triple Level Cell). The nonvolatile memory 2 is three-dimensionally formed.

[0029] The memory controller 1 is connected to the nonvolatile memory 2 via a NAND bus. The memory controller 1 controls writing of data to the nonvolatile memory 2 in accordance with a write request from a host. In addition, the memory controller 1 controls reading of data from the nonvolatile memory 2 in accordance with a read request from the host. The memory controller 1 is provided with a RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, the processor 12, the host interface 13, the ECC circuit 14, and the memory interface 15 are connected to each other by an internal bus 16.

[0030] The host interface 13 outputs a request received from the host, write data as user data, and the like to the internal bus 16. In addition, the host interface 13 transmits user data read from the nonvolatile memory 2, a response from the processor 12, and the like to the host.

[0031] The memory interface 15 controls a write process of writing user data and the like to the nonvolatile memory 2 and a read process of reading user data and the like from the nonvolatile memory 2 based on an instruction of the processor 12.

[0032] The RAM 11 temporarily stores user data received from the host before storing the user data to the nonvolatile memory 2. The RAM 11 temporarily stores data read from the nonvolatile memory 2 before transmitting the data to the host. The RAM 11 is, for example, a general-purpose memory such as an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), or the like.

[0033] The processor 12 collectively controls the memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. The processor 12 controls in accordance with a request received from a host via the host interface 13. For example, the processor 12 instructs the memory interface 15 to write user data to the non-volatile memory 2 in accordance with a request from the host. In addition, the processor 12 instructs the memory interface 15 to read out user data from the non-volatile memory 2 in accordance with a request from the host.

[0034] The processor 12 decides a storage area (hereinafter, referred to as a memory area) on the non-volatile memory 2 with respect to user data stored in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 performs the decision of the memory area with respect to data of a page unit, that is, page data, as a write unit. In the present specification, user data stored in one page of the non-volatile memory 2 is defined as unit data. The unit data is, for example, encoded by the ECC circuit 14 and stored in the non-volatile memory 2 as a codeword (Japanese: symbol word).

[0035] In addition, the encoding is not necessary. The memory controller 1 can also store the unit data in the non-volatile memory 2 without performing the encoding, but in the present embodiment, a configuration in which the encoding is performed is shown as one configuration example. In a case where the memory controller 1 does not perform the encoding, the page data coincides with the unit data. In addition, one codeword can be generated on the basis of one unit data, or one codeword can be generated on the basis of divided data obtained by dividing the unit data. In addition, one codeword can also be generated using a plurality of unit data. Figure 1

[0036] The processor 12 decides the memory area of the non-volatile memory 2 as a write destination for each unit data. The memory area of the non-volatile memory 2 is assigned a physical address. The processor 12 manages the memory area of the write destination of the unit data using the physical address. The processor 12 specifies the physical address of the decided memory area and instructs the memory interface 15 to write the user data to the non-volatile memory 2. The processor 12 manages the correspondence between the logical address (logical address managed by the host) of the user data and the physical address. The processor 12 determines the physical address corresponding to the logical address in a case where a read request including the logical address is received from the host, specifies the physical address, and instructs the memory interface 15 to read out the user data.

[0037] The ECC circuit 14 encodes the user data stored in the RAM 11 and generates a codeword. In addition, the ECC circuit 14 decodes the codeword read out from the non-volatile memory 2.

[0038] In​Figure 1 In the embodiment, a configuration example in which the memory controller 1 is provided with the ECC circuit 14 and the memory interface 15 is shown. However, the ECC circuit 14 can be built in the memory interface 15. In addition, the ECC circuit 14 can be built in the nonvolatile memory 2.

[0039] In a case where a write request is received from the host, the memory controller 1 acts as follows. The processor 12 temporarily stores the write data in the RAM 11. The processor 12 reads out the data stored in the RAM 11 and inputs to the ECC circuit 14. The ECC circuit 14 encodes the input data and supplies the codeword to the memory interface 15. The memory interface 15 writes the input codeword in the nonvolatile memory 2.

[0040] In a case where a read request is received from the host, the memory controller 1 acts as follows. The memory interface 15 supplies the codeword read out from the nonvolatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13.

[0041] (Configuration of Nonvolatile Memory)

[0042] Figure 2 is a block diagram of the nonvolatile memory 2. The nonvolatile memory 2 is provided with a logic control circuit 21, an input / output circuit 22, a memory cell array 23, a sense amplifier 24, a row decoder 25, a register 26, a sequencer 27, a voltage generation circuit 28, an address decoder 29, a driver 30, a pad group for input / output 31, a pad group for logic control 32, and a terminal group for power supply input 33.

[0043] The logic control circuit 21 and the input / output circuit 22 are connected with the memory controller 1 via a NAND bus. The input / output circuit 22 transmits / receives a signal DQ (for example, DQ0 to DQ7) between the memory controller 1 via the NAND bus.

[0044] The logic control circuit 21 receives external control signals (for example, a chip enable signal / CE, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal RE, / RE, and a write protect signal / WP) from the memory controller 1 via the NAND bus. In addition, the logic control circuit 21 transmits a ready / busy signal R / B to the memory controller 1 via the NAND bus.

[0045] The logic control circuit 21, when receiving the external control signals from the memory controller 1, outputs internal control signals to the input / output circuit 22 in accordance with the external control signals.

[0046] The input / output circuit 22 outputs data input from the input / output pad group 31 to the data latch circuit XDL in the sense amplifier 24 and the register 26 in accordance with an internal control signal from the logic control circuit 21. In addition, data from a plurality of data latch circuits XDL or the register 26 is output to the input / output pad group 31.

[0047] The memory cell array 23 has a plurality of memory cell transistors MT( Figure 4 ). The memory cell array 23 has a plurality of blocks (memory blocks) BLK as described later. The plurality of blocks BLK each has a plurality of memory cell transistors (memory cells) MT. In order to control voltages applied to the memory cell transistors MT, a plurality of bit lines, a plurality of word lines, a source line, and the like are provided in the memory cell array 23. The detailed configuration of each block BLK is described later.

[0048] The input / output pad group 31 has a plurality of terminals (pads) corresponding to the signals DQ<7:0> and the data strobe signals DQS, / DQS in order to transmit and receive each signal including data between the memory controller 1.

[0049] The logic control pad group 32 has a plurality of terminals (pads) corresponding to the chip enable signal / CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal / WE, the read enable signal RE, / RE, and the write protect signal / WP in order to transmit and receive each signal between the memory controller 1. The " / " attached to the signal name indicates active low.

[0050] The signal / CE enables selection of the non-volatile memory 2. The signal CLE enables latching of a command transmitted as the signal DQ in a command register. The signal ALE enables latching of an address transmitted as the signal DQ in an address register. The signal / WE enables writing. The signal RE enables reading. The signal / WP prohibits writing and erasing. The signal R / B indicates whether the non-volatile memory 2 is in a ready state (a state in which a command from the outside can be accepted) or a busy state (a state in which a command from the outside cannot be accepted). The memory controller 1 can recognize the state of the non-volatile memory 2 by receiving the signal R / B.

[0051] The terminal group 33 for power supply input has a plurality of terminals for inputting power supply voltages Vcc, VccQ, Vpp, and a ground voltage Vss, in order to supply various operation power supplies from the outside to the nonvolatile memory 2. The power supply voltage Vcc is a circuit power supply voltage that is generally supplied from the outside, and for example, a voltage of about 3.3 V is input. The power supply voltage VccQ is, for example, a voltage of 1.2 V is input. The power supply voltage VccQ is used when the memory controller 1 and the nonvolatile memory 2 transmit and receive signals. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, and for example, a voltage of 12 V is input.

[0052] The sense amplifier 24 receives the column address from the register 26, and decodes the column address. The sense amplifier 24 selects a certain bit line BL (k) based on the decoded column address. Figure 4 In addition, the sense amplifier 24 detects and amplifies the data read from the memory cell transistor MT to the bit line BL when reading the data. In addition, the sense amplifier 24 transmits the write data to the bit line BL when writing the data.

[0053] The sense amplifier 24 has a sense amplifier unit group 24A and a data register 24B. The sense amplifier unit group 24A has a plurality of sense amplifier units SAU corresponding to a plurality of bit lines BL.

[0054] Figure 3 is a block diagram of the sense amplifier 24. Figure 3 The case where the memory cell transistor MT is a TLC (Triple Level Cell) is shown. As illustrated, the sense amplifier 24 has a plurality of sense units SAU (SAU0 to SAU(K-1)) provided for each bit line BL.

[0055] The plurality of sense units SAU each have a sense amplifier section SA, two data latch circuits (hereinafter, also simply referred to as data latches) ADL and SDL. The data latch circuit ADL temporarily holds the write data. That is, the data latch circuit ADL is used for the writing of data from the memory controller 1 to the nonvolatile memory 2.

[0056] The data register 24B has a plurality of data latch circuits XDL.

[0057] These sense amplifier sections SA, data latch circuits ADL and SDL are connected by a bus so as to be able to transmit and receive data with each other. Also, the bus is connected with the data latch circuit XDL.

[0058] The sense amplifier 24 has a plurality of data latch circuits ADL, XDL, SDL that store 1 page amount of data, respectively.

[0059] In addition, in a case where the memory cell transistor MT is a multi-value cell such as a TLC (Triple Level Cell), the data latch circuit includes data latch circuits BDL, CDL in addition to the data latch circuit ADL as shown by dotted lines. In this case, the data latch circuits ADL, BDL, CDL are used for the multi-value operation of the memory cell transistor MT to hold data of 2 bits or more. That is, the data latch circuit ADL is used to hold a lower page. The data latch circuit BDL is used to hold an intermediate page. The data latch circuit CDL is used to hold an upper page. In addition, the number of data latch circuits included in the sense amplifier unit SAU can be arbitrarily changed according to the number of bits held by one memory cell transistor MT.

[0060] The sense amplifier unit SA detects data read out to the corresponding bit line BL and determines whether the data is "0" data or "1" data at the time of readout operation. In addition, the sense amplifier unit SA applies a voltage to the bit line BL based on the write data at the time of write operation.

[0061] The data register 24B temporarily holds data detected by the sense amplifier 24 at the time of readout of data and serially transfers the data to the input / output circuit 22. In addition, the data register 24B temporarily holds data serially transferred from the input / output circuit 22 at the time of write data and transfers the data to the sense amplifier 24. The data register 24B is constituted by an SRAM or the like.

[0062] The data register 24B includes a number of data latch circuits XDL corresponding to the number of sense amplifier units SAU. The data latch circuit XDL is connected to the input / output circuit 22. The data latch circuit XDL is a circuit for data transfer between the sense amplifier 24 and the outside, temporarily holds write data sent from the input / output circuit 22, and temporarily holds readout data sent from the sense amplifier unit SAU. More specifically, data transfer between the input / output circuit 22 and the plurality of sense amplifier units SAU is performed via a plurality of data latch circuits XDL of one page. Write data received by the input / output circuit 22 is transferred to the data latch circuit ADL via the data latch circuit XDL. Readout data read out by the sense amplifier unit SA is transferred to the input / output circuit 22 via the data latch circuit XDL.

[0063] The row decoder 25 receives a row address from the register 26 and decodes the row address. The row decoder 25 performs a selection operation of a word line based on the decoded row address. Then, the row decoder 25 transmits a plurality of voltages required for a write operation, a readout operation, and an erase operation to the selected block.

[0064] The register 26 has an instruction register, an address register, and a status register, etc. The instruction register temporarily holds an instruction. The address register temporarily holds an address. The status register temporarily holds data required for the operation of the nonvolatile memory 2. The register 26 is constituted by, for example, an SRAM.

[0065] The sequencer 27 as a control circuit receives the instruction from the register 26, and controls the nonvolatile memory 2 in accordance with a sequence based on the instruction.

[0066] The voltage generation circuit 28 receives a power supply voltage from the outside of the nonvolatile memory 2, and generates a plurality of voltages required for the write operation, the read operation, and the erase operation using the power supply voltage. The voltage generation circuit 28 supplies the generated voltages to the memory cell array 23, the sense amplifier 24, the row decoder 25, etc. via the driver 30.

[0067] The address decoder 29 decodes the address data of the register 26 in accordance with a control signal from the sequencer 27, and controls the states of a plurality of signal lines corresponding to the address data in sequence. Here, the address decoder 29 sets the voltage selection line corresponding to the address data to the "H" state, and sets the block selection line BSL (except for the block selection line BSL corresponding to the address data) and the voltage selection line VSL (except for the voltage selection line VSL corresponding to the address data) to the "L" state. Figure 4 ) to the "L" state. Figure 4

[0068] The driver 30 generates various voltage signals based on the block address BA and the page address PA in the register 26, and supplies the various voltages to the selected block BLK via the row decoder 25.

[0069] The driver 30 includes a plurality of VPGM monitors 34. Each VPGM monitor 34 is provided to a global word line. Each VPGM monitor 34 is a voltage detection circuit connected to each word line WL, and detects the voltage of each word line WL. The global word line is a word line that supplies a signal to a plurality of blocks BLK. Each VPGM monitor 34 is a detection circuit that detects the program voltage VPGM at the time of writing supplied to each word line WL in accordance with a control signal from the sequencer 27. Each VPGM monitor 34 can be a circuit that compares analog voltages with each other, or a circuit that converts the voltages to digital values and compares the digital values with each other. Each VPGM monitor 34 is able to output the detected voltage value to the sequencer 27 under the control of the sequencer 27.

[0070] Figure 4 is a circuit diagram of the nonvolatile memory 2.

[0071] As described above, the memory cell array 23 has a plurality of (three in the present embodiment) blocks BLK. Each block BLK of the memory cell array 23 has a plurality of (four in the present embodiment) memory cells MC. Figure 4 Figure 4 ​​The middle section contains three string units SU. In Figure 4 The diagram shows the structure of only one string unit SU, but other string units SU have the same structure. Each string unit SU has multiple memory strings MS (in... Figure 4 (There are four in total). Each memory string (MS) is a NAND string. One end of each memory string (MS) is connected to the peripheral circuitry (PC) via the bit line (BL). The other end of each memory string (MS) is connected to the peripheral circuitry (PC) via a common source line (SL). Additionally, in... Figure 4 The diagram shows the structure of only one block BLK, but other block BLKs have the same structure.

[0072] Each memory string (MS) has a drain selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cell transistors (MT), and a source selection transistor (STS). Hereinafter, the drain selection transistor (STD) and the source selection transistor (STS) will be simply referred to as selection transistors.

[0073] Each memory cell transistor (MT) is an electrolytic-effect transistor comprising a semiconductor layer functioning as a channel region, a gate insulating film containing a charge storage film, and a gate electrode. The threshold voltage of the memory cell transistor (MT) varies depending on the amount of charge in the charge storage film. Each memory cell transistor (MT) can store one bit or more bits of data. A word line (WL) is connected to the gate electrode of each memory cell transistor (MT). Within each block (BLK), each word line (WL) is shared among multiple string cells (SU). That is, each of the multiple word lines (WL) is connected to all string cells (SU) in a block (BLK).

[0074] Select transistors STD and STS are field-effect transistors that possess a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. The gate electrode of the drain select transistor STD is connected to a drain select gate line SGD. The gate electrode of the source select transistor STS is connected to a source select gate line SGS. Drain select gate lines SGD are provided for each string cell SU. All drain select gate lines SGD are connected to all memory strings MS in a string cell SU. Source select gate lines SGS are connected to all memory strings MS in a block BLK.

[0075] The peripheral circuitry PC includes a sense amplifier 24, a line decoder 25, and a register 26. Figure 2 ), sequencer 27, voltage generation circuit 28, address decoder 29, and driver 30.

[0076] The line decoder 25 includes multiple block selection circuits 41 corresponding to multiple blocks (BLK). Each block selection circuit 41 includes multiple block selection transistors 42. Additionally, in Figure 4In the present embodiment, only the configuration of the block selection circuit 41 corresponding to one block BLK is shown, but the other block selection circuits 41 also have the same circuit configuration. The plurality of block selection transistors 42 are provided corresponding to the plurality of drain selection gate lines SGD, the plurality of (five in the present embodiment) word lines WL, and the source selection gate line SGS. Figure 4

[0077] The block selection transistor 42 is a field effect type voltage resistant transistor. One end of each block selection transistor 42 is electrically connected to the corresponding drain selection gate line SGD, the corresponding word line WL, or the source selection gate line SGS. The other end of each block selection transistor 42 is electrically connected to the corresponding wiring CG. The gate electrodes of each block selection transistor 42 within one block selection circuit 41 are commonly connected to the corresponding block selection line BSL from the address decoder 29.

[0078] The driver 30 is provided with a plurality of voltage selection circuits 43, 43w. As shown in Figure 4 , the driver 30 is provided with a plurality of voltage selection circuits 43 corresponding to the plurality of selection gate lines SGD. In addition, the driver 30 is provided with a plurality of voltage selection circuits 43w corresponding to the plurality of word lines WL. Furthermore, the driver 30 is provided with a voltage selection circuit 43 corresponding to the selection gate line SGS.

[0079] Each voltage selection circuit 43, 43w has a plurality of (three in the present embodiment) voltage selection transistors 44. In addition, in the present embodiment, only the circuit configuration of two voltage selection circuits 43w is shown, but the circuit configuration of each voltage selection circuit 43, 43w is the same. Each voltage selection transistor 44 is a field effect type voltage resistant transistor. Figure 4

[0080] One end of each voltage selection transistor 44 of the voltage selection circuit 43 is connected to the wiring CG. One end of each voltage selection transistor 44 of the voltage selection circuit 43w is connected to the wiring CG via the VPGM monitor 34.

[0081] That is, one end of each voltage selection transistor 44 is electrically connected to the corresponding word line WL or selection gate line SGC, SGS via the corresponding wiring CG and the corresponding block selection transistor 42.

[0082] The other end of each voltage selection transistor 44 is connected to the corresponding operating voltage generation unit 45. As shown in Figure 4 , the other end of each voltage selection transistor 44 is electrically connected to the corresponding operating voltage output terminal 28a.

[0083] The gate electrode of each voltage selection transistor 44 is connected to the corresponding voltage selection line VSL.

[0084] ​​The voltage generation circuit 28 has a plurality of (three in this embodiment) operation voltage generation units 45. To each operation voltage generation unit 45, a supply terminal of a power supply voltage Vcc, Vss is connected, for example. Each operation voltage generation unit 45 is a circuit that generates, in accordance with a control signal from the sequencer 27, an operation voltage to be applied to the source line SL, each word line WL, and each select gate line SGD, SGS in order when a readout operation, a write operation, and an erase operation on the memory cell array 23 are performed, and outputs the operation voltage to a plurality of operation voltage output terminals 28a.

[0085] In addition, although not shown, each operation voltage generation unit 45 generates, in accordance with a control signal from the sequencer 27, an operation voltage to be applied to each bit line BL in order and outputs the operation voltage to each bit line BL.

[0086] The plurality of block selection lines BSL and the plurality of voltage selection lines VSL are connected to the address decoder 29. The address decoder 29 decodes the address data of the register 26 in accordance with a control signal from the sequencer 27, and causes a part of the plurality of block selection lines BSL and the plurality of voltage selection lines VSL corresponding to the address data to be in an "H" state and the other plurality of block selection lines BSL and the other plurality of voltage selection lines VSL to be in an "L" state.

[0087] The sequencer 27 decodes the instruction held in the register 26 in order and outputs an internal control signal to the sense amplifier 24, the row decoder 25, the driver 30, and the voltage generation circuit 28.

[0088] In addition, the sequencer 27 appropriately outputs state data indicating its own state to the register 26. For example, when a write sequence or an erase sequence is executed, information indicating whether the write sequence or the erase sequence has ended normally is output as the state data.

[0089] (Action)

[0090] Next, the operation of the memory system of the present embodiment will be described.

[0091] When data is written, each voltage selection transistor 44 of the driver 30 becomes an on or off state in accordance with a control signal from the sequencer 27. By the on and off of each voltage selection transistor 44, a prescribed voltage is applied to each word line WL and select gate line SGD, SGS.

[0092] For example, a prescribed program voltage VPGM is applied to a word line WL selected as a write target of data (hereinafter, a selected word line will be referred to as a WLs).

[0093] Figure 5 is a flowchart showing the processing of the write operation. Figure 6is a graph showing the voltage of the selected word line WLs at the time when the program voltage VPGM is applied and the detection voltage DVTl detected by the VPGM monitor 34.

[0094] In step S1, a prescribed program voltage VPGM is applied to the selected word line WLs. The actual voltage applied to the selected word line WLs is set as the voltage DV.

[0095] In step S2, the voltage of the selected word line WLs after the program voltage VPGM is applied is detected after a certain time has elapsed. The sequencer 27 controls the VPGM monitor 34 provided to the selected word line WLs via the control signal line LC to detect the voltage of the selected word line WLs after the program voltage VPGM is applied. As shown in FIG. 6, the sequencer 27 detects the voltage of the selected word line WLs as the detection voltage DVTl at the detection timing Tl after a prescribed time Tp has elapsed from the application timing TO of the program voltage VPGM. The prescribed time Tp is set in advance. In the present embodiment, the timing at which the voltage of the selected word line WLs is detected is only once. Figure 6

[0096] In step S3, it is determined whether the detection voltage DVTl detected by the VPGM monitor 34 exceeds a prescribed value TH. The prescribed value TH is set in advance and written to a prescribed storage region of the nonvolatile memory 2. The sequencer 27 reads out the prescribed value TH in advance.

[0097] The prescribed value TH is a voltage set in advance assuming that the desired amount of charge is stored in each memory cell transistor MT when a voltage exceeding the prescribed value TH is applied to the selected word line WLs.

[0098] In the case where the detection voltage DVTl exceeds the prescribed value TH (S3: Yes), the sequencer 27 ends the processing of Figure 5 .

[0099] In the case where the detection voltage DVTl does not exceed the prescribed value TH (S3: No), in step S4, a state defect is output to the memory controller 1. Specifically, the sequencer 27 writes state data indicating a program state defect into the register 26.

[0100] After step S3, in step S5, a defective block process is executed. The defective block process is a process of coping with the block including the selected word line WLs to which the program voltage VPGM is applied in step S1 as a defective block (i.e., a defective block) hereafter.

[0101] After step S5, the sequencer 27 ends the write processing of Figure 5 .

[0102] ​In addition, here, sequencer 27 performs the processing of S1 to S5, but it is also possible to perform all or part of the processing of S1 to S5 through a circuit different from sequencer 27.

[0103] use Figure 6 Step S3 will be explained in more detail below. Figure 6 In the case where the voltage DV of the selected word line WLs changes as shown by the solid line, the detection voltage DVT1 exceeds the specified value TH (S3: Yes), therefore the sequencer 27 ends. Figure 5 Write processing.

[0104] exist Figure 6 In the case where the voltage DV of the selected word line WLs changes as shown by the double-dotted line, and the detected voltage DVT1 does not exceed the specified value TH (S3: No), the sequencer 27 notifies the memory controller 1 of a bad condition (S4), performs bad block processing, and ends. Figure 5 The write process is shown.

[0105] Additionally, in the example above, each VPGM monitor 34 is located on a global word line within each word line WL, but it can also be located on a local word line within each word line WL. A local word line is a word line corresponding to each block BLK.

[0106] Figure 7 This is a block diagram of a non-volatile memory 2, which is another example of this embodiment. Figure 8 This is a circuit diagram of a non-volatile memory 2, which is another example of this embodiment. Figure 7 as well as Figure 8 In the middle, to and Figure 2 as well as Figure 4 The same constituent elements are labeled with the same reference numerals. Figure 7 as well as Figure 8 middle, Figure 4 Each VPGM monitor 34 is configured according to each local word line within each block BLK. Figure 7 In this configuration, multiple VPGM monitors 34 are disposed between the memory cell array 23 and the row decoder 25, and are referred to as VPGM monitor unit 35.

[0107] The VPGM monitor 34 is located between the line decoder 25 and the memory cell array 23, and on the local word line WL. That is, each VPGM monitor 34 is located on its respective local word line WL.

[0108] Each VPGM monitor 34 is controlled by the sequencer 27 via the control signal line LC, and outputs a detection voltage to the sequencer 27.

[0109] The sequencer 27 controls the VPGM monitor 34 corresponding to the selected word line WLs, and can obtain the detection voltage DVT1. The processing in the sequencer 27 is the same as Figure 5

[0110] Thus, according to the present embodiment, in the memory system, since the verify operation is not performed in the write operation, the write of data can be performed at high speed. Thus, according to the present embodiment, it is possible to provide a semiconductor memory device with improved write performance.

[0111] (Modified Example 1)

[0112] In the above embodiment, each memory cell transistor MT is an SLC capable of storing 1 bit of data, but can be a multi-value cell capable of storing 2 bits or more of data. In the case where each memory cell transistor MT is a multi-value cell, the prescribed value compared with the detection voltage DVT1 is plural.

[0113] Figure 9 is a flowchart showing the processing of the write operation of Modified Example 1.

[0114] Here, an example in which each memory cell transistor MT is an MLC capable of storing 2 bits of data will be described. Since each memory cell transistor MT is an MLC, each memory cell transistor MT can have four voltages. Thus, the prescribed value is three. The four voltages are Er, A, B, and C, and the prescribed value is the first to third prescribed values TH1 to TH3.

[0115] In step Sll, a prescribed program voltage VPGM(A-C) is applied to the selected word line WLs. The prescribed program voltage VPGM(A-C) is, for example, a voltage in which the threshold voltage of the memory cell transistor MT becomes a voltage VA or more between the levels Er and A.

[0116] In step S12, the voltage of the selected word line WLs after the application of the program voltage VPGM is detected. The sequencer 27 controls the VPGM monitor 34 provided to the selected word line WLs via the control signal line LC, and detects the voltage of the selected word line WLs after the application of the program voltage VPGM.

[0117] In step S13, it is determined whether the detection voltage DVT1 detected by the VPGM monitor 34 exceeds the prescribed value TH1. The prescribed value TH1 is a voltage preset assuming that, when a voltage exceeding the prescribed value TH1 is applied to the selected word line WLs, a prescribed amount of charge corresponding to the level A is stored in each memory cell transistor MT. TH1 is replaced with TH in Figure 6

[0118] ​​In a case where the detection voltage DVTl exceeds the prescribed value THl (S13: YES), a prescribed program voltage VPGM (B~C) is applied to the selected word line WLs in step S14. The prescribed program voltage VPGM (B~C) is, for example, a voltage at which the threshold voltage of the memory cell transistor MT becomes a voltage VB or more between the levels A and B.

[0119] In a case where the detection voltage DVTl does not exceed the prescribed value THl (S13: NO), a state defect is output to the memory controller 1 in step S4. After step S4, a defective block process is executed in step S5.

[0120] After S5, the sequencer 27 ends Figure 9 the write process.

[0121] After step S4, the voltage of the selected word line WLs after the application of the program voltage VPGM is detected in step S15. The sequencer 27 controls the VPGM monitor 34 provided to the selected word line WLs via the control signal line LC, and detects the voltage of the selected word line WLs after the application of the program voltage VPGM.

[0122] In step S16, it is determined whether the detection voltage DVTl detected by the VPGM monitor 34 exceeds a prescribed value TH2. The prescribed value TH2 is a voltage that is set in advance assuming that when a voltage exceeding the prescribed value TH2 is applied to the selected word line WLs, a prescribed amount of charge corresponding to the level B is stored in each memory cell transistor MT. TH2 is replaced with TH in Figure 6 .

[0123] In a case where the detection voltage DVTl exceeds the prescribed value TH2 (S16: YES), a prescribed program voltage VPGM (C) is applied to the selected word line WLs in step S17. The prescribed program voltage VPGM (C) is, for example, a voltage at which the threshold voltage of the memory cell transistor MT becomes a voltage VC or more between the levels B and C.

[0124] In a case where the detection voltage DVTl does not exceed the prescribed value TH2 (S16: NO), the sequencer 27 executes the processes of step S4 and step S5. After step S5, the sequencer 27 ends Figure 9 the write process.

[0125] After step S17, the voltage of the selected word line WLs after the application of the program voltage VPGM is detected in step S18. The sequencer 27 controls the VPGM monitor 34 provided to the selected word line WLs via the control signal line LC, and detects the voltage of the selected word line WLs after the application of the program voltage VPGM.

[0126] In step S19, it is determined whether the detection voltage DVT1 detected by the VPGM monitor 34 exceeds a prescribed value TH3. The prescribed value TH3 is a voltage that is set in advance assuming that a prescribed amount of charge corresponding to the level C is stored in each memory cell transistor MT when a voltage exceeding the prescribed value TH3 is applied to the selected word line WLs. TH3 is replaced with TH in the above. Figure 6

[0127] In the case where the detection voltage DV exceeds the prescribed value TH3 (S19: Yes), the sequencer 27 ends the processing of Figure 9 .

[0128] In the case where the detection voltage DVT1 does not exceed the prescribed value TH3 (S19: No), the sequencer 27 performs the processing of step S4 and step S5. After step S5, the sequencer 27 ends the write processing of Figure 9 .

[0129] As described above, in the case where each of the plurality of memory cell transistors MT is a multi-value cell capable of storing a plurality of bits of data, in order to distinguish the plurality of bits of data, the prescribed value is plural, and the sequencer 27 performs determination of whether the detection voltage DVT1 reaches each of the plural values.

[0130] The above example is an example in which each memory cell transistor MT is capable of storing 2 bits of data, but in the case of TLC, QLC, PLC, and the like in which each memory cell transistor MT is capable of storing 3 bits or more of data, the present embodiment can also be applied.

[0131] (Modified Example 2)

[0132] In the above embodiment, in the write operation, after the programming operation, the verify operation is not performed, and the voltage of the selected word line WLs is detected to determine success or failure of the write, but the write operation can also include the verify operation.

[0133] Figure 10 is a flowchart showing the write operation in the sequencer 27 of the present modified example 2.

[0134] In step S21, a prescribed program voltage VPGM is applied to the selected word line WLs.

[0135] In step S22, a verify operation is performed on the data to be written.

[0136] In step S23, it is determined whether the result of the verify operation, the selected memory cell transistor MT, reaches a verify level, that is, whether the verify is passed. The selected memory cell transistor MT reaching the verify level means that data is written in the selected memory cell transistor MT. ​

[0137] Thus, in the case where the verification is passed (S23: YES), the sequencer 27 ends the processing.

[0138] In the case where the verification is not passed (S23: NO), the step S24 applies the prescribed program voltage VPGM to the selected word line WLs again.

[0139] In the step S25, the voltage of the selected word line WLs after the application of the program voltage VPGM is detected. The sequencer 27 controls the VPGM monitor 34 (or 35) provided to the selected word line WLs to detect the voltage of the selected word line WLs after the application of the program voltage VPGM.

[0140] The sequencer 27 determines whether the detected voltage DVT1 detected by the VPGM monitor 34 exceeds the prescribed value TH (S26).

[0141] In the case where the detected voltage DVT1 exceeds the prescribed value TH (S26: YES), the sequencer 27 ends the write processing. Figure 10

[0142] In the case where the detected voltage DVT1 does not exceed the prescribed value TH (S26: NO), in the step S4, the state of failure is output to the memory controller 1, and in the step S5, the failure block processing is executed.

[0143] That is, according to the present modified example 2, in the write operation, the verification operation is performed for the initial VPGM application, and in the case where the verification is not passed, the write state is determined based on the detected voltage DVT1 of the VPGM monitor 34. Even if the verification is not passed, if the detected voltage DVT1 exceeds the prescribed value TH, it can be considered that the write is successful.

[0144] In addition, in the case where the VPGM application is performed multiple times in the program sequence, the verification operation can be performed at the initial VPGM application, and the write state can be determined based on the detected voltage DV of the VPGM monitor 34 at the final VPGM application.

[0145] (Modified Example 3)

[0146] The detection timing of the voltage of the selected word line WLs can also be capable of being set changed.

[0147] Figure 11 is a graph showing the change of the voltage of the selected word line WLs according to the present modified example 3.

[0148] In Figure 11 , as shown by the double-dot chain line, there is also a case where the change of the voltage DV of the selected word line WLs after the application of the program voltage VPGM is slow. In such a case, in Figure 11 ​the detection timing T2, the detection voltage DVT2 of the selected word line WLs does not reach the prescribed value TH. In this modification example 3, the timing at which the voltage DV of the selected word line WLs is detected by the VPGM monitor 34 can be set to be changed. Thus, the voltage detection timing can be delayed, and in Figure 11 the detection timing T2a, the detection voltage DVT2a of the selected word line WLs can be detected. The voltage detection timing is set according to the characteristics of the semiconductor storage device.

[0149] (Modification Example 4)

[0150] In the above-described embodiment and modification example 3, the detection timing of the voltage DV of the selected word line WLs is once, but can be performed multiple times.

[0151] Figure 12 is a graph showing the change in the voltage of the selected word line WLs and the voltage detection timing in this modification example 4.

[0152] In Figure 12 , the voltage detection timing is set twice. As shown by the double-dot chain line, there is a case in which the voltage DV of the selected word line WLs temporarily rises but then falls. In Figure 12 , the detection voltage DVT11 and the detection voltage DVT12 of the selected word line WLs are detected at the first detection timing T11 and the detection timing T12 thereafter. The two detection timings are set according to the characteristics of the selected word line WLs. In this modification example 4, the timing at which the voltage DV of the selected word line WLs is detected by the VPGM monitor 34 is twice by the sequencer 27, and the sequencer 27 determines whether the writing is successful or not according to the determination result regarding the detection voltages DVT11 and DVT12. In this modification example, the voltage detection timing is twice, but can be more.

[0153] By setting the voltage detection timing multiple times, it is possible to more accurately determine whether the data writing is successful or not.

[0154] For example, at the first detection timing T11, the detection voltage DVT11 exceeds the prescribed value TH, but at the second detection timing T12, the detection voltage DVT12 is lower than the prescribed value TH. In this case, since the detection voltage DVT11 exceeds the prescribed value TH, the sequencer 27 can determine that the writing is successful.

[0155] In a case in which the detection voltage DVT11 is lower than the prescribed value TH at the first detection timing T11 but the detection voltage DVT12 exceeds the prescribed value TH at the second detection timing T12, the sequencer 27 can determine that the writing is successful.

[0156] Alternatively, it can also be determined that the writing is unsuccessful if both the voltage detected at the first detection timing T11 and the voltage detected at the second detection timing T12 do not exceed the prescribed value TH. Further, the prescribed value can be changed at the first detection timing T11 and the second detection timing T12 as TH1, TH2. The prescribed value TH1 at the first detection timing T11 can be larger than the prescribed value TH2 at the second detection timing T12, or can be smaller than the prescribed value TH2 at the second detection timing T12. That is, the prescribed value can be set to different values at the plurality of detection timings.

[0157] (Modified example 5)

[0158] In the above-described embodiments and each modified example, the prescribed value TH is arbitrarily set in advance, but can also be set based on a set voltage at the time of writing (so-called trimming voltage). The set voltage at the time of writing (so-called trimming voltage) is set and stored in each nonvolatile memory 2 based on individual differences of the nonvolatile memories 2 at the time of manufacturing of the nonvolatile memories 2.

[0159] Figure 13 is a view showing a setting method of the prescribed value TH of the present modified example 5. In Figure 13 , the prescribed value TH is set from a bias voltage value Voff from a trimming voltage Vtr. That is, the prescribed value TH is set based on the trimming voltage set according to individual differences of the nonvolatile memories 2.

[0160] The bias voltage value Voff can be set to be changed. Thereby, by changing the bias voltage value Voff according to the characteristics of each semiconductor memory device, the voltage of the selection word line WLs can be reliably detected.

[0161] (Modified example 6)

[0162] In the above-described modified example 5, the prescribed value TH is set based on a bias voltage value Voff with respect to a set voltage at the time of writing (so-called trimming voltage), but can also be set based on a ratio with respect to a set voltage at the time of writing (so-called trimming voltage).

[0163] Figure 14 is a view showing a setting method of the prescribed value TH of the present modified example 6. In Figure 14 , the prescribed value TH (V) is set using a ratio k with respect to a trimming voltage Vtr (V0). The ratio k is (V / V0). That is, the prescribed value TH is set based on the trimming voltage set according to individual differences of the nonvolatile memories 2.

[0164] The ratio k can be set to be changed. Thereby, by changing the ratio k according to the characteristics of each semiconductor memory device, the voltage of the selection word line WLs can be reliably detected.

[0165] (Modified example 7)

[0166] As to the above embodiment and each modified example, in the write operation, the verify operation is omitted, and it is confirmed whether the threshold voltage of each memory cell transistor MT becomes the desired threshold voltage, but the verify operation can be omitted in the data erase operation, and the erase voltage is detected, and it is confirmed whether the data of each memory cell transistor is erased.

[0167] Figure 15 is a block diagram of the nonvolatile memory 2 of the present modified example 7. In Figure 15 , the same components as Figure 2 are denoted by the same reference numerals, and the description is omitted, and the different components are described.

[0168] The erase voltage VERA is applied to the source line SL. The source line SL is commonly connected to the source side of a plurality of memory cell transistors MT. The voltage applied to the source line SL is detected by the VERA monitor 36 provided to the source line SL of the driver 30. That is, the VERA monitor 36 is a voltage detection circuit connected to the source line SL and detects the voltage of the source line SL.

[0169] Figure 16 is a flowchart showing the erase operation of the present modified example 7.

[0170] In step S41, the prescribed erase voltage VERA is applied to the source line SL.

[0171] In step S42, the voltage of the source line SL after the application of the erase voltage VERA is detected. The sequencer 27 controls the VERA monitor 36 provided to the source line SL via the control signal line LC, and detects the voltage of the source line SL after the application of the erase voltage VERA. The detection timing is as shown in Figure 6 , the voltage of the source line SL is detected at the detection timing Tl after the prescribed time Tp elapses from the application timing TO of the erase voltage VERA. The prescribed time Tp is set in advance.

[0172] Further, in Figure 6 , 11 , 12, the voltage DV is replaced with the voltage of the source line SL.

[0173] In step S43, it is determined whether the detected voltage DVTl of the source line SL detected by the VERA monitor 36 exceeds the prescribed value THe. Further, in Figure 6 , 11 , 12, 13, 14, the prescribed value TH is replaced with the prescribed value THe.

[0174] The is a voltage set in advance assuming that the data of each memory cell transistor MT is erased when a voltage exceeding the prescribed value THe is applied to the source line SL.

[0175] In a case where the detection voltage DV exceeds the prescribed value THe (S43: YES), the sequencer 27 ends the processing. At this time, the voltage DV changes as the solid line. Figure 16

[0176] In a case where the detection voltage DV does not exceed the prescribed value THe (S43: NO), in step S4, a state defect is output to the memory controller 1, and in step S5, a defective block processing is executed. At this time, the voltage DV changes as the double-dot chain line.

[0177] As described above, the sequencer 27, at the time of erasing the data of the memory cell array 23, detects the voltage of the source line SL by the VERA monitor 36 when the erasing voltage VERA is applied to the source line SL, and performs a determination of whether the detected detection voltage DVT1 reaches the prescribed value.

[0178] In the present modified example, as with the modified example 3 shown in Figure 11 , the detection timing can be set to be changed.

[0179] In the present modified example, as with the modified example 4 shown in Figure 12 , the number of times of the detection timing is plural.

[0180] In the present modified example, as with the modified example 5 shown in Figure 13 , the prescribed value THe is set based on a bias voltage from a set voltage at the time of erasing (so-called trimming voltage Vtr). In addition, in the Figure 14 , ​ , Vtr is replaced with the set voltage Vtr applied to the source line SL at the time of erasing.

[0181] In the present modified example, as with the modified example 6, the prescribed value THe is set based on a ratio with respect to a set voltage at the time of erasing (so-called trimming voltage Vtr).

[0182] As described above, according to the above-described embodiments and each modified example, in the memory system, the verification operation is not executed in the write operation or the erase operation, and thus the write or erase of the data can be performed at high speed.

[0183] Accordingly, according to the present embodiment, it is possible to provide a semiconductor storage device with improved write performance.

[0184] ​Several embodiments of the present application are described, but these embodiments are illustrative only and are not intended to limit the scope of the present application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the scope of the present application. These embodiments and their modifications are included in the scope, spirit of the present application, and are included in the scope of the present application and equivalents thereof recited in the claims.

Claims

1. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cell transistors; Multiple word lines are respectively connected to multiple gates of the multiple memory cell transistors; A voltage detection circuit is connected to at least one word line of the plurality of word lines; as well as When writing data to the memory cell array, the control circuit, upon applying a write voltage to a selected word line chosen from the plurality of word lines, detects the voltage of the selected word line using a voltage detection circuit and determines whether the detected voltage has reached a predetermined value. The control circuit can set and change the number of times it detects the voltage of the selection word line through the voltage detection circuit.

2. The semiconductor memory device as claimed in claim 1, wherein, The number of times mentioned is only once.

3. The semiconductor memory device as claimed in claim 1, wherein, Each of the plurality of memory cell transistors is capable of storing 1 bit of data.

4. The semiconductor memory device as claimed in claim 1, wherein, Each of the plurality of memory cell transistors is a multi-valued unit capable of storing multiple bits of data. In order to distinguish between the plurality of bit data, the specified value is multiple. The control circuit determines whether the detection voltage has reached each of the multiple values.

5. The semiconductor memory device as claimed in claim 1, wherein, The specified value is set based on a trimming voltage, which is set according to the characteristics of the semiconductor memory device.

6. The semiconductor memory device of claim 1, wherein, The plurality of memory cell transistors are divided into multiple blocks within the memory cell array. The voltage detection circuit is connected to a global word line, which supplies multiple signals containing the write voltage to the multiple blocks.

7. The semiconductor memory device of claim 1, wherein, The plurality of memory cell transistors are divided into multiple blocks within the memory cell array. The voltage detection circuit is connected to the local word lines within each block.

8. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cell transistors; Multiple word lines are respectively connected to multiple gates of the multiple memory cell transistors; A voltage detection circuit is connected to at least one word line of the plurality of word lines; as well as When writing data to the memory cell array, the control circuit, upon applying a write voltage to a selected word line chosen from the plurality of word lines, detects the voltage of the selected word line using a voltage detection circuit and determines whether the detected voltage has reached a predetermined value. In each of the multiple operations, the control circuit detects the voltage of the select word line through the voltage detection circuit. The control circuit makes the determination based on the determination results regarding the plurality of detected voltages.

9. The semiconductor memory device of claim 8, wherein, The specified value is set based on a trimming voltage, which is set according to the characteristics of the semiconductor memory device.

10. The semiconductor memory device of claim 8, wherein, The plurality of memory cell transistors are divided into multiple blocks within the memory cell array. The voltage detection circuit is connected to a global word line, which supplies multiple signals containing the write voltage to the multiple blocks.

11. The semiconductor memory device of claim 8, wherein, The plurality of memory cell transistors are divided into multiple blocks within the memory cell array. The voltage detection circuit is connected to the local word lines within each block.

12. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cell transistors; Multiple word lines are respectively connected to multiple gates of the multiple memory cell transistors; A voltage detection circuit is connected to at least one word line of the plurality of word lines; as well as When writing data to the memory cell array, the control circuit, upon applying a write voltage to a selected word line chosen from the plurality of word lines, detects the voltage of the selected word line using a voltage detection circuit and determines whether the detected voltage has reached a predetermined value. The control circuit performs a verification operation on the writing of the data to the memory cell array, and makes the determination in response to the verification failing.

13. The semiconductor memory device of claim 12, wherein, The specified value is set based on a trimming voltage, which is set according to the characteristics of the semiconductor memory device.

14. The semiconductor memory device of claim 12, wherein, The plurality of memory cell transistors are divided into multiple blocks within the memory cell array. The voltage detection circuit is connected to a global word line, which supplies multiple signals containing the write voltage to the multiple blocks.

15. The semiconductor memory device of claim 12, wherein, The plurality of memory cell transistors are divided into multiple blocks within the memory cell array. The voltage detection circuit is connected to the local word lines within each block.

16. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cell transistors; Multiple word lines are respectively connected to multiple gates of the multiple memory cell transistors; A voltage detection circuit is connected to at least one word line of the plurality of word lines; as well as When writing data to the memory cell array, the control circuit, upon applying a write voltage to a selected word line chosen from the plurality of word lines, detects the voltage of the selected word line using a voltage detection circuit and determines whether the detected voltage has reached a predetermined value. The plurality of memory cell transistors are divided into multiple blocks within the memory cell array. The control circuit processes the block containing the select word line whose detection voltage has not reached the specified value as a defective block.

17. The semiconductor memory device of claim 16, wherein, Each of the plurality of memory cell transistors is capable of storing 1 bit of data.

18. The semiconductor memory device of claim 16, wherein, Each of the plurality of memory cell transistors is a multi-valued unit capable of storing multiple bits of data. In order to distinguish between the plurality of bit data, the specified value is multiple. The control circuit determines whether the detection voltage has reached each of the multiple values.

19. The semiconductor memory device of claim 16, wherein, The plurality of memory cell transistors are divided into multiple blocks within the memory cell array. The voltage detection circuit is connected to the local word lines within each block.

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