Memory, system, and operating method of the memory

Abstract

This application discloses a memory, a system, and a method for operating the memory, belonging to the field of memory technology. After the programming stage of the first stack in a memory string, the memory applies a first voltage to one end of the memory string, and applies a second voltage and a third voltage to the first and second selection transistors of the memory string, respectively, turning them on. A fourth voltage is applied to the memory cells of the first stack, turning them on, and a fifth voltage is applied to the memory cells of the second stack, turning them off. This discharges the channel of the memory string. During the discharge process, since some memory cells in the memory string are in a conducting state while others are in a non-conducting state, the current in the channel during the discharge process can be reduced, reducing hot carrier injection into the memory cells of the second stack and decreasing interference to the memory cells of the second stack.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a system, and a method of operating the memory. Background Technology

[0002] Three-dimensional (3D) memory is widely used in computer equipment, mobile phones, personal computers and other types of electronic devices due to its small size, high storage capacity and non-transferability of stored data.

[0003] The storage strings in a 3D memory are composed of multiple stacks, each stack consisting of multiple levels of cascaded storage units. During the programming phase, the 3D memory programs storage units, page by page, to store data.

[0004] However, after the programming phase is completed, the channel of the memory string containing the memory cell being programmed will be rapidly discharged. Since multiple stacks in the memory string share the same channel, during the discharge process, the channel is prone to hot carrier injection (HCI) effect in memory cells in other stacks, causing the threshold voltage of memory cells in other stacks to drift, thereby interfering with memory cells in other stacks. Summary of the Invention

[0005] This application provides a memory, a system, and a method for operating the memory, which reduces interference with storage units of other stacks in the memory string when programming a storage unit of a certain stack in the memory string. The technical solution is as follows:

[0006] In a first aspect, a memory is provided, the memory including a storage array and peripheral circuitry;

[0007] The storage array includes a storage string, a first select line, a second select line, and multiple word lines. The storage string includes a first stack, a second stack, a first select transistor, and a second select transistor. The first stack and the second stack each include multiple storage cells.

[0008] The first selection line is coupled to the first selection tube, and the second selection line is coupled to the second selection tube;

[0009] The plurality of word lines are respectively coupled to the plurality of storage cells of the storage string;

[0010] The peripheral circuitry is coupled to the first select line, the second select line, and the plurality of word lines, and the peripheral circuitry is configured to:

[0011] After the programming phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to the first select line coupled to the first select transistor, a third voltage is applied to the second select line coupled to the second select transistor, a fourth voltage is applied to the word line coupled to each memory cell of the first stack, and a fifth voltage is applied to the word line coupled to each memory cell of the second stack to discharge the channel of the memory string.

[0012] Wherein, the second voltage is used to turn on the first selection transistor, the third voltage is used to turn on the second selection transistor, the fourth voltage applied to each memory cell of the first stack is used to turn on the corresponding memory cell, and the fifth voltage applied to each memory cell of the second stack is used to turn off the corresponding memory cell.

[0013] In one possible implementation, the verification phase of the first stack follows the programming phase, and the peripheral circuitry is further configured as follows:

[0014] After the programming phase and before the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

[0015] In one possible implementation, the peripheral circuit is further configured as follows:

[0016] Immediately after the programming phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are executed.

[0017] In one possible implementation, the peripheral circuit is further configured as follows:

[0018] After the programming phase ends, after a first preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0019] In one possible implementation, the verification phase of the first stack follows the programming phase, and the peripheral circuitry is further configured as follows:

[0020] After the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

[0021] In one possible implementation, the peripheral circuit is further configured as follows:

[0022] Immediately after the verification phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are executed.

[0023] In one possible implementation, the peripheral circuit is further configured as follows:

[0024] After the verification phase ends, after a second preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0025] In one possible implementation, the fifth voltage applied to each memory cell of the second stack is less than the minimum on-state voltage of each memory cell of the second stack.

[0026] In one possible implementation, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage applied to the word line coupled to each memory cell of the second stack during the programming phase.

[0027] Alternatively, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage of the word line coupled to each memory cell of the second stack applied during the verification phase.

[0028] In a second aspect, a system is provided, the system including a memory configured to store data, the memory including a storage array and peripheral circuitry;

[0029] The storage array includes a storage string, a first select line, a second select line, and multiple word lines. The storage string includes a first stack, a second stack, a first select transistor, and a second select transistor. The first stack and the second stack each include multiple storage cells.

[0030] The first selection line is coupled to the first selection tube, and the second selection line is coupled to the second selection tube;

[0031] The plurality of word lines are respectively coupled to the plurality of storage cells of the storage string;

[0032] The peripheral circuitry is coupled to the first select line, the second select line, and the plurality of word lines, and the peripheral circuitry is configured to:

[0033] After the programming phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to the first select line coupled to the first select transistor, a third voltage is applied to the second select line coupled to the second select transistor, a fourth voltage is applied to the word line coupled to each memory cell of the first stack, and a fifth voltage is applied to the word line coupled to each memory cell of the second stack to discharge the channel of the memory string.

[0034] Wherein, the second voltage is used to turn on the first selection transistor, the third voltage is used to turn on the second selection transistor, the fourth voltage applied to each memory cell of the first stack is used to turn on the corresponding memory cell, and the fifth voltage applied to each memory cell of the second stack is used to turn off the corresponding memory cell.

[0035] In one possible implementation, the verification phase of the first stack follows the programming phase, and the peripheral circuitry is further configured as follows:

[0036] After the programming phase and before the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

[0037] In one possible implementation, the peripheral circuit is further configured as follows:

[0038] Immediately after the programming phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are executed.

[0039] In one possible implementation, the peripheral circuit is further configured as follows:

[0040] After the programming phase ends, after a first preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0041] In one possible implementation, the verification phase of the first stack follows the programming phase, and the peripheral circuitry is further configured as follows:

[0042] After the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

[0043] In one possible implementation, the peripheral circuit is further configured as follows:

[0044] Immediately after the verification phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are executed.

[0045] In one possible implementation, the peripheral circuit is further configured as follows:

[0046] After the verification phase ends, after a second preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0047] In one possible implementation, the fifth voltage applied to each memory cell of the second stack is less than the minimum on-state voltage of each memory cell of the second stack.

[0048] In one possible implementation, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage applied to the word line coupled to each memory cell of the second stack during the programming phase.

[0049] Alternatively, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage of the word line coupled to each memory cell of the second stack applied during the verification phase.

[0050] In one possible implementation, the system further includes a host and a memory controller;

[0051] The host is configured to send data to or receive data from the memory;

[0052] The memory controller is coupled to the host and the memory, and is configured to control the memory.

[0053] Thirdly, a method for operating a memory is provided, the memory including a memory array, the memory array including a memory string, a first select line, a second select line and a plurality of word lines, the memory string including a first stack, a second stack, a first select transistor and a second select transistor, the first stack and the second stack each including a plurality of memory cells;

[0054] The first selection line is coupled to the first selection tube, and the second selection line is coupled to the second selection tube;

[0055] The plurality of word lines are respectively coupled to a plurality of storage cells of the storage string, and the method includes:

[0056] After the programming phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to the first select line coupled to the first select transistor, a third voltage is applied to the second select line coupled to the second select transistor, a fourth voltage is applied to the word line coupled to each memory cell of the first stack, and a fifth voltage is applied to the word line coupled to each memory cell of the second stack to discharge the channel of the memory string.

[0057] Wherein, the second voltage is used to turn on the first selection transistor, the third voltage is used to turn on the second selection transistor, the fourth voltage applied to each memory cell of the first stack is used to turn on the corresponding memory cell, and the fifth voltage applied to each memory cell of the second stack is used to turn off the corresponding memory cell.

[0058] In one possible implementation, the verification phase of the first stack occurs after the programming phase, and the method further includes:

[0059] After the programming phase and before the verification phase, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0060] In one possible implementation, the method further includes:

[0061] Immediately after the programming phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are executed.

[0062] In one possible implementation, the method further includes:

[0063] After the programming phase ends, after a first preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0064] In one possible implementation, the verification phase of the first stack occurs after the programming phase, and the method further includes:

[0065] After the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

[0066] In one possible implementation, the method further includes:

[0067] Immediately after the verification phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are executed.

[0068] In one possible implementation, the method further includes:

[0069] After the verification phase ends, after a second preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0070] In one possible implementation, the fifth voltage applied to each memory cell of the second stack is less than the minimum on-state voltage of each memory cell of the second stack.

[0071] In one possible implementation, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage applied to the word line coupled to each memory cell of the second stack during the programming phase.

[0072] Alternatively, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage of the word line coupled to each memory cell of the second stack applied during the verification phase.

[0073] The technical solution provided in this application, after the programming stage of the first stack in the memory string, applies a first voltage to one end of the memory string, applies a second voltage and a third voltage to the selection line coupled to the first selection transistor and the selection line coupled to the second selection transistor, respectively, so that the first selection transistor and the second selection transistor are turned on. A fourth voltage is applied to the word line coupled to the memory cell of the first stack, so that the memory cell of the first stack is turned on. A fifth voltage is applied to the word line coupled to the memory cell of the second stack in the memory string, so that the memory cell of the second stack is not turned on, so as to discharge the channel of the memory string. During the discharge process, since some memory cells in the memory string are in the on state and other memory cells are in the off state, the current in the channel during the discharge process can be reduced, the hot carrier injection of the memory cells in the second stack can be reduced, and the interference to the memory cells of the second stack can be reduced. Attached Figure Description

[0074] Figure 1 This is a schematic diagram of a system according to an exemplary embodiment;

[0075] Figure 2 This is a schematic diagram illustrating a memory card according to an exemplary embodiment;

[0076] Figure 3 This is a schematic diagram illustrating a solid-state driver according to an exemplary embodiment;

[0077] Figure 4 This is a schematic diagram illustrating a memory according to an exemplary embodiment;

[0078] Figure 5 This is a schematic diagram illustrating the structure of a storage string according to an exemplary embodiment;

[0079] Figure 6 This is a schematic diagram of the structure of a peripheral circuit according to an exemplary embodiment;

[0080] Figure 7 This is a schematic diagram illustrating the principle of HCI effect occurrence according to an exemplary embodiment;

[0081] Figure 8 This is a flowchart illustrating a method of operating a memory according to an exemplary embodiment;

[0082] Figure 9 This is a flowchart illustrating an operation method performed after the programming phase and before the verification phase, according to an exemplary embodiment.

[0083] Figure 10 This is a voltage waveform diagram illustrating channel discharge immediately after the end of a programming phase, according to an exemplary embodiment.

[0084] Figure 11 This is a voltage waveform diagram illustrating channel discharge after a first preset time, according to an exemplary embodiment.

[0085] Figure 12 This is a flowchart illustrating an operation method performed after the verification phase, according to an exemplary embodiment.

[0086] Figure 13 This is a voltage waveform diagram illustrating channel discharge immediately after the completion of a verification phase, according to an exemplary embodiment.

[0087] Figure 14 This is a voltage waveform diagram illustrating channel discharge after a second preset time, according to an exemplary embodiment.

[0088] Figure 15 This is a comparison diagram of the threshold voltage drift of a storage cell in a second stack according to an exemplary embodiment. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0090] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms.

[0091] These terms are simply used to distinguish one element from another. For example, without departing from the various examples, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. Both the first and second elements can be elements, and in some cases, they can be separate and distinct elements.

[0092] "At least one" means one or more elements. For example, at least one element can be one element, two elements, three elements, or any integer number of elements greater than or equal to one. "At least two" means two or more elements. For example, at least two elements can be two elements, three elements, or any integer number of elements greater than or equal to two.

[0093] Figure 1This is a schematic diagram of a system according to an exemplary embodiment. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0094] like Figure 1 As shown, system 100 includes a host 101 and a storage subsystem 102. The host 101 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 101 may be configured to send data to memory 103. Alternatively, the host 101 may be configured to receive data from memory 103.

[0095] The storage subsystem 102 includes one or more memories 103 and a memory controller 104. The memory 103 is configured to store the memory controller 104 coupled to it. The memory 103 can be any memory disclosed herein. Optionally, the memory 103 is a NAND flash memory device. NAND flash memory devices, such as 3D NAND flash memory devices, are also possible.

[0096] According to some implementations, the memory controller 104 is also coupled to the host 101. The memory controller 104 can manage data stored in the memory 10 and communicate with the host 101.

[0097] In one possible implementation, the memory controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0098] In one possible implementation, the memory controller 104 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0099] The memory controller 104 can be configured to control operations of the memory 103, such as read, erase, and program operations. The memory controller 104 can also be configured to manage various functions relating to data stored or to be stored in the memory 103, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In one possible implementation, the memory controller 104 is also configured to handle error correction codes (ECC) relating to data read from or written to the memory 103.

[0100] The memory controller 104 can also perform any other suitable functions, such as formatting the memory 103. The memory controller 104 can communicate with external devices (e.g., the host 101) according to a specific communication protocol. For example, the memory controller 104 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0101] The memory controller 104 and one or more memories 103 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the system 100 can be implemented and packaged into different types of end electronic products.

[0102] Figure 2 This is a schematic diagram of a memory card according to an exemplary embodiment, such as... Figure 2 As shown, the memory controller 104 and a single memory 103 can be integrated into the memory card 200. The memory card 200 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 200 may also include a connection between the memory card 200 and a host computer (e.g., Figure 1 The memory card connector 201 is coupled to the host 101.

[0103] Figure 3 This is a schematic diagram illustrating a solid-state drive according to an exemplary embodiment, such as... Figure 3As shown, the memory controller 104 and multiple memories 103 can be integrated into a solid-state drive (SSD) 300. The solid-state drive 300 may also include a connection between the solid-state drive 300 and a host computer (e.g., ...). Figure 1 The solid-state drive connector 301 is coupled to the host 101. In one possible implementation, the storage capacity and / or operating speed of the solid-state drive 300 is greater than the storage capacity and / or operating speed of the memory card 200.

[0104] Figure 4 This is a schematic diagram illustrating a memory according to an exemplary embodiment. Figure 4 As shown, the memory 103 includes a memory array 310, multiple bit lines (BL) 320, multiple word lines (WL) 330, and peripheral circuitry 340.

[0105] The memory array 310 includes a plurality of memory strings 311 arranged in an array above a memory array substrate (not shown), with each memory string 311 extending vertically above the substrate.

[0106] Each memory string 311 includes multiple memory cells 312, which are vertically stacked above the substrate of the memory array 310. Each memory cell 312 stores data, the amount of data stored being determined by the number of electrons stored in the cell. The number of electrons stored in a cell determines its threshold voltage, thus indicating the amount of data stored. The memory cell 312 is either a floating-gate field-effect transistor (FET) or a charge-trap FET.

[0107] Each memory string 311 also includes an upper select transistor 313 and a lower select transistor 314. Upper select transistors 313 in different memory strings 311, at the same or similar height from the substrate support surface, are coupled to the same drain select line (DSL) 350. Lower select transistors 314 in different memory strings 311, at the same or similar height from the substrate support surface, are coupled to the same source select line (SSL) 360. The upper select transistors 313 and 314 are used to activate the selected memory string during erase, programming, or erasing of memory cells. The upper select transistor 313 is also called the top select gate (TSG), and the lower select transistor 314 is also called the bottom select gate (BSG).

[0108] One end of the storage string 311 is coupled to the bit line 320, and the other end of the storage string 311 is coupled to the source line (SL) 370.

[0109] Memory cells 312 in different memory strings 311 that are at the same or similar height from the substrate bearing surface are located on the same layer. Multiple memory cells 312 on the same layer form a memory cell row 31a. That is, the memory array 310 includes multiple memory cell rows, and multiple word lines 330 are coupled to multiple memory cell rows respectively. All memory strings 311 in the memory array 310 that share the same set of word lines form a memory block 31b. The source terminals of each memory string 311 in the same memory block 31b are coupled to the same source line 370.

[0110] As the number of storage string 311 layers increases, multiple stacked storage strings 311 need to be formed through multiple etches. For example, Figure 5 A schematic diagram of a storage string structure is shown according to an exemplary embodiment. See also: Figure 5 The memory string 500 includes multiple memory cells, which are sequentially connected to word lines 330. Each sequentially arranged memory cell includes a channel, and the channels of each memory cell in each stack can be connected sequentially to form the channel 315 of the memory string 311. When two stacks are stacked to form the memory string 311 through an etching process, at least one virtual memory cell is provided between the two stacks so that the peripheral circuit 340 can control different stacks in the same memory string based on the virtual memory cell.

[0111] Return to reference Figure 4 The peripheral circuit 340 is coupled to multiple word lines 330. The peripheral circuit 340 controls the voltage V of the word lines 330 coupled to the selected memory string. WL and the voltage V of the bit line coupled to the selected memory string. BL The following operation method is implemented by controlling the storage cells in the selected storage string.

[0112] Peripheral circuitry 340 includes various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 A schematic diagram of a peripheral circuit is shown according to an exemplary embodiment. For example... Figure 6 The peripheral circuitry 340 shown includes a page buffer / sensor amplifier 604, a column decoder / bit line (BL) driver 606, a row decoder / word line (WL) driver 608, a voltage generator 610, a control logic unit 612, a register 614, an interface 616, and a data bus 618. In some examples, it also includes... Figure 6Additional peripheral circuitry is not shown. The page buffer / sensor amplifier 604 can be configured to read data from and program (write) data to the memory array 310 according to control signals from the control logic unit 612. In one example, the page buffer / sensor amplifier 604 can store one page of programming data (write data) to be programmed into a page of the memory array 310. In another example, the page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell 312 coupled to the selected word line. In yet another example, the page buffer / sensor amplifier 604 can also sense a low-power signal from the bit line representing a data bit stored in the memory cell 312 and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 606 can be configured to be controlled by the control logic unit 612 and select one or more memory strings 311 by applying a bit line voltage generated from the voltage generator 610.

[0113] The line decoder / word line driver 608 can be configured to be controlled by the control logic unit 612 and to select / deselect word lines 330 of memory blocks 31b of the memory array 310. The line decoder / word line driver 608 can also be configured to drive word lines using word line voltages generated from the voltage generator 610. In some embodiments, the line decoder / word line driver 608 can also select / deselect and drive DSL and SSL. As described in detail below, the line decoder / word line driver 608 is configured to perform erase operations on memory cells 312 coupled to one or more selected word lines. The voltage generator 610 can be configured to be controlled by the control logic unit 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 310.

[0114] Control logic unit 612 can be coupled to each of the peripheral circuits 340 described above and is configured to control the operation of each peripheral circuit 340. Register 614 can be coupled to control logic unit 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 340. Interface 616 can be coupled to control logic unit 612 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 612, as well as to buffer status information received from control logic unit 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bitline driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 310.

[0115] Continue to refer to Figure 5 ,by Figure 5 In this context, memory string 500 is the selected memory string. The lower stack (lowerduck) of the selected memory string is the unselected (unsel) stack, and the upper stack (upper duck) is the selected (sel) stack. Taking a specific memory cell in the selected stack as an example, the HCI effect occurring in the unselected stack within the selected memory string is described as follows:

[0116] The programming process for the selected memory cell includes a precharge phase, a programming (PGM) phase, and a verification phase. In the precharge phase, gate-induced drain leakage (GIDL) is used to precharge the channel of the selected memory string to increase the channel potential. Afterward, the voltage of the BL or SL corresponding to the selected memory string drops to 0V. During the programming phase, both BL and SL voltages remain at 0V. When the voltage of BL or SL drops to 0V, it is lower than the channel voltage of the selected memory string. Since the channel of the selected memory string and BL or SL constitute a PN junction, when the voltage of BL or SL is lower than the channel voltage, a forward-conducting PN junction is formed between the channel and BL or SL, and the channel potential begins to discharge. Simultaneously, the different threshold voltages of each memory cell in the selected memory string result in a PNP junction-like channel voltage forming in the channel. If the voltage of BL is 0V, and any P-region of the PNP-like junction is close to the upper select transistor, since the channel voltage of the memory cell in any P-region is higher than the voltage of BL, holes in the channel of the memory cell in any P-region will propagate towards BL, causing the channel voltage of the memory cell in any P-region to decrease, thus achieving discharge towards BL. If the voltage of SL is 0V, and any P-region of the PNP-like junction is close to the lower select transistor, since the channel voltage of the memory cell in any P-region is higher than the voltage of SL, holes in the channel of the memory cell in any P-region will propagate towards SL, causing the channel potential of the memory cell in any P-region to decrease, thus achieving discharge towards SL.

[0117] For a period during the verification phase, the voltages of BL and SL remained at 0V, causing the PNP-like junction structure to slow down the channel voltage discharge. Specifically, due to the unidirectional conductivity of the PN junction, during discharge, holes in the channel of the N-region memory cell cannot propagate towards the P-region, causing them to remain trapped in the N-region channel, thus delaying the discharge. Furthermore, the trapped holes cause the potential of the N-region channel to be higher than that of the P-region channel, creating a potential difference between the two channels. When charge carriers flow through the channel, this potential difference triggers the HCI effect.

[0118] by Figure 7 Taking a schematic diagram illustrating the principle of HCI effect as an example from an exemplary embodiment, such as... Figure 7The selected memory cells a and b within the selected memory string are shown. If at least one memory cell c is stacked between selected memory cells a and b, and the threshold voltage of the at least one memory cell c is 0V, and the threshold voltages of memory cells a and b are both greater than the threshold voltage of at least one memory cell c, then due to the different threshold voltages of memory cells a, at least one memory cell c, and memory cell b, memory cells a, at least one memory cell c, and memory cell b form a PNP-like junction. Memory cells a and b are located in the P-region of the PNP-like junction, and at least one memory cell c is located in the N-region of the PNP-like junction. If the voltages BL and SL are both 0V, and memory cell a is close to TSG, holes in the channel of memory cell a propagate towards BL. Taking the discharge of at least one memory cell c towards SL as an example, if memory cell b is close to BSG, then memory cell b is located in the SL direction of at least one memory cell c. Under the influence of the low voltage SL, holes in the channel of at least one memory cell c propagate towards memory cell b. However, due to the unidirectional conductivity of the PN junction, the holes in the channel of at least one memory cell c cannot cross the channel of memory cell b, thus retaining the holes in their original positions and maintaining the high voltage of the channel of at least one memory cell c. Under the influence of the low voltage SL, holes in the channel of memory cell b propagate towards SL, reducing the voltage of the channel of memory cell b, thereby creating a potential difference between the channels of at least one memory cell c and memory cell b. When charge carriers flow through the channel, the potential difference between the channels of at least one memory cell c and memory cell b causes the HCI effect to occur between memory cell b and at least one memory cell c, with hot electrons from the HCI effect entering at least one memory cell c.

[0119] If data is stored in a cell within a non-selected stack, and this stored data is maintained, the threshold voltages of these cells may differ. During the discharge of the selected memory string, a PNP-like junction may form between the cells in the non-selected stack. When reading data from the selected memory string or during the programming phase, carriers are generated in the channel of the selected memory string. This can lead to the HCI effect at the N-region of the PNP-like junction in the non-selected stack. With each read or programming cycle, multiple HCI effects may occur in cells with low threshold voltages in the non-selected stack. The hot electrons from these multiple HCI effects accumulate in the storage layer of these cells, causing the threshold voltage to drift and interfering with the memory.

[0120] As described above, the memory includes a memory array and peripheral circuitry. The memory array includes multiple memory strings, a first select line, a second select line, and multiple word lines. The first select line is either DSL or SSL, while the second select line is the other of DSL and SSL. For example, the first select line may be DSL, and the second select line may be SSL; or, for another example, the first select line may be SSL, and the second select line may be DSL.

[0121] In one possible implementation, each memory string includes a first stack, a second stack, a first selector, and a second selector. The first stack and the second stack each include multiple memory cells. If the first selector is a DSL and the second selector is an SSL, then the first selector is a TSG and the second selector is a BSG; if the first selector is an SSL and the second selector is a DSL, then the first selector is a BSG and the second selector is a TSG.

[0122] The peripheral circuitry in this memory is configured to discharge the channel of a selected memory string among the plurality of memory strings. For further illustration of the process of discharging the channel of a selected memory string, see [link to relevant documentation]. Figure 8 A flowchart illustrating a memory operation method according to an exemplary embodiment is provided, the method comprising:

[0123] 801. After the programming phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to the first select line coupled to the first select transistor, and a third voltage is applied to the second select line coupled to the second select transistor.

[0124] Here, the storage string is the selected storage string for this programming process, and the first stack is the selected stack for this programming process, that is, the stack containing the selected storage unit for this programming process. Still using... Figure 5 Taking the storage string 500 as an example, if the first stack is the upper stack of the storage string 500, the selected storage unit is any storage unit in the upper stack; if the first stack is the lower stack of the storage string 500, the selected storage unit is any storage unit in the lower stack.

[0125] The first voltage is a voltage that enables the channel of the memory string to discharge. The value of the first voltage ranges from 0V to 1V. The second voltage is used to turn on the first select transistor; for example, the second voltage is the turn-on voltage of the first select transistor. The third voltage is used to turn on the second select transistor; for example, the third voltage is the turn-on voltage of the second select transistor.

[0126] Taking the memory string as an example, with one end as the drain terminal, the first selection transistor as TSG, the second selection transistor as BSG, the second voltage as the turn-on voltage of TSG, and the third voltage as the turn-on voltage of BSG, step 801 is described as follows:

[0127] The drain terminal is coupled to the bit line. After the programming phase of the first stack, a first voltage is applied to the bit line of the memory string, such that the first voltage acts on the drain terminal of the memory string. The source line of the memory string is grounded, such that a 0V voltage on the source line acts on the source terminal of the memory string.

[0128] After the programming phase of the first stack, a turn-on voltage of the TSG is applied to the drain select line coupled to the TSG of the memory string, causing the TSG to turn on. A turn-on voltage of the BSG is applied to the source select line coupled to the BSG of the memory string, causing the BSG to turn on.

[0129] 802. After the programming phase of the first stack, a fourth voltage is applied to the word line coupled to each memory cell of the first stack, and the fourth voltage applied to each memory cell of the first stack is used to turn on the corresponding memory cell.

[0130] In this design, the value of the fourth voltage applied to each memory cell in the first stack can be the same or different, as long as it is sufficient to turn on the corresponding memory cell. The value of the fourth voltage for each memory cell in the first stack ranges from 5V to 7V. Since a fourth voltage can turn on a corresponding memory cell, by applying the fourth voltage to the word lines coupled to the memory cells of the first stack, all memory cells in the first stack can be turned on.

[0131] It should be noted that when the storage string includes virtual storage cells, a virtual storage cell conduction unit is also applied to the pseudo-word line coupled to the virtual storage cell, so that the virtual storage cell is turned on.

[0132] 803. After the programming phase of the first stack, a fifth voltage, which is less than the fourth voltage, is applied to the word line coupled to each memory cell of the second stack.

[0133] The second stack is the stack in the memory string other than the first stack, and this second stack is a non-selected stack. Still using... Figure 5 Taking the storage string 500 as an example, if the first stack is the upper stack in the storage string 500, then the second stack is the lower stack in the storage string 500; if the first stack is the lower stack in the storage string 500, then the second stack is the upper stack in the storage string 500. Figure 5 The example given is that storage string 500 includes two stacks. In other embodiments, the storage string contains more than two stacks. In this programming process, the storage string contains one first stack, and all stacks in the storage string other than the first stack are second stacks. In this case, the storage string contains at least two second stacks.

[0134] The value of the fifth voltage applied to each memory cell in the second stack can be the same or different, as long as it does not turn on the corresponding memory cell. In one possible implementation, the fifth voltage applied to each memory cell in the second stack is less than the minimum turn-on voltage of each memory cell in the second stack. The value of the fifth voltage ranges from 0V to 4V or from 0V to 3V. In one possible implementation, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell in the second stack, and less than the voltage applied to the word line coupled to each memory cell in the second stack during the programming phase; or, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell in the second stack, and less than the voltage applied to the word line coupled to each memory cell in the second stack during the verification phase. Wherein, the initial voltage of the word line coupled to each memory cell is greater than or equal to 0V, the voltage applied to the word line coupled to each memory cell in the second stack during the programming phase is greater than the initial voltage of the corresponding word line, and the voltage applied to the word line coupled to each memory cell in the second stack during the verification phase is greater than the initial voltage of the corresponding word line. The voltage applied to the word line coupled to each memory cell in the second stack during the programming phase may be the same as or different from the voltage applied to the word line coupled to each memory cell in the second stack during the verification phase.

[0135] Since the fifth voltage can prevent the corresponding memory cell from conducting, by applying the fifth voltage to the word line coupled to each memory cell in the second stack, each memory cell in the second stack is prevented from conducting.

[0136] Through the above operations, the memory cells, TSG, and BSG of the first stack in the memory string are all turned on, while the memory cells of the second stack are all turned off. Although the memory cells of the second stack are not turned on and are in a non-conductive state (i.e., off state), they can still transmit leakage current. Therefore, under the action of the first voltage, the channel of the memory string is discharged. During the discharge process, since each memory cell of the second stack is in a off state, a small amount of current in the channel of the memory string can still be transmitted through the non-conductive memory cells, thereby achieving slow discharge. Because the current in the channel is small, under the action of the first voltage at one end of the memory string, the number of electrons in the current becoming hot electrons is reduced, and correspondingly, the number of hot electrons tunneling to the memory cells of the second stack is also reduced, slowing down the drift of the threshold voltage of the memory cells of the second stack. Thus, during the programming of the first stack, interference to the memory cells in the second stack can be reduced.

[0137] It should be noted that the peripheral circuit can execute steps 801-803 simultaneously or at different times. In this embodiment, the execution order of steps 801-803 is not limited.

[0138] The method provided in this application embodiment applies a first voltage to one end of the memory string after the programming stage of the first stack in the memory string, applies a second voltage and a third voltage to the select line coupled to the first select transistor and the select line coupled to the second select transistor, respectively, so that the first select transistor and the second select transistor are turned on, applies a fourth voltage to the word line coupled to the memory cell of the first stack, respectively, so that the memory cell of the first stack is turned on, and applies a fifth voltage to the word line coupled to the memory cell of the second stack in the memory string, respectively, so that the memory cell of the second stack is not turned on, thereby discharging the channel of the memory string. During the discharge process, since some memory cells in the memory string are turned on and others are not turned on, the current in the channel during the discharge process can be reduced, the hot carrier injection of the memory cells in the second stack can be reduced, and the interference to the memory cells of the second stack can be reduced.

[0139] The above-mentioned operation of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack is an operation of discharging the channel of the memory string. For ease of description, this operation is referred to as a discharge operation.

[0140] There are two possible implementations for performing the discharge operation after the programming phase. The first implementation is to perform the discharge operation after the programming phase of the first stack and before the verification phase of the first stack. The second implementation is to perform the discharge operation after the verification phase of the first stack. For further explanation of these two implementations, please refer to [link to relevant documentation]. Figure 9 and 11 .

[0141] Figure 9 This is a flowchart illustrating an operational method performed after the programming phase and before the verification phase, according to an exemplary embodiment. Figure 9 As shown.

[0142] 901. After the programming phase of the first stack and before the verification phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to the first select line coupled to the first select transistor, and a third voltage is applied to the second select line coupled to the second select transistor.

[0143] In this scenario, the verification phase of the first stack follows the programming phase, and both the verification and programming phases constitute the current programming process of the first stack. In this case, according to the execution sequence, the stages of the current programming process of the first stack are, in order: pre-charge phase, programming phase, discharging phase, and verification phase.

[0144] The process of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, and applying a third voltage to the second select line coupled to the second select transistor is described in step 801 and will not be repeated here.

[0145] 902. After the programming phase and before the verification phase, a fourth voltage is applied to the word line coupled to each memory cell of the first stack.

[0146] The process of applying a fourth voltage to the word lines coupled to each memory cell of the first stack is described in step 802 and will not be repeated here.

[0147] 903. After the programming phase and before the verification phase, a fifth voltage is applied to the word line coupled to each memory cell of the second stack.

[0148] The process of applying a fifth voltage to the word lines coupled to each memory cell of the second stack is described in step 803 and will not be repeated here.

[0149] It should be noted that the peripheral circuit can execute steps 901-903 simultaneously or at different times. In this embodiment, the execution order of steps 901-903 is not limited.

[0150] The method provided in this application embodiment applies a first voltage to one end of the memory string after the programming stage and before the verification stage of the first stack, applies a second voltage and a third voltage to the selection lines coupled to the first and second selection transistors of the memory string, respectively, so that the first and second selection transistors are turned on, applies a fourth voltage to the word lines coupled to the memory cells of the first stack, respectively, so that the memory cells of the first stack are turned on, and applies a fifth voltage to the word lines coupled to the memory cells of the second stack in the memory string, respectively, so that the memory cells of the second stack are not turned on, thereby discharging the channel of the memory string. During the discharge process, since some memory cells in the memory string are in a conducting state and other memory cells are in a non-conducting state, the current in the channel during the discharge process can be reduced, the hot carrier injection of the memory cells in the second stack can be reduced, and the interference to the memory cells of the second stack can be reduced.

[0151] Figure 9 The process shown is the process of performing a discharge operation on the memory string containing the first stack after the programming phase and before the verification phase. The method of performing the discharge operation on the memory string after the programming phase and before the verification phase includes either method A1 or method A2.

[0152] Method A1: After the programming phase ends, immediately execute the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0153] Taking the first selection transistor as TSG, the second selection transistor as BSG, the second voltage as the turn-on voltage of TSG, and the third voltage as the turn-on voltage of BSG as an example, see [reference needed]. Figure 10 A voltage waveform diagram illustrating channel discharge immediately after the programming phase, according to an exemplary embodiment, is shown. The memory string is a selected memory string within the memory block to be programmed. The bit lines of the selected memory string are selected bit lines (sel-BL), the TSGs within the selected memory string are selected TSGs (sel-TSG), and the BSGs within the selected memory string are selected BSGs (sel-BSG). A first stack within the selected memory string is a selected stack. The word lines coupled to selected memory cells in the first stack are selected word lines (sel-WL), and the word lines coupled to memory cells other than the selected memory cells in the first stack are denoted as word lines of the selected stack (sel-deck-WL). A second stack within the selected memory string is a non-selected stack. The memory cells in the second stack are non-selected memory cells, and the word lines of the memory cells in the second stack are word lines of the non-selected stack (unsel-deck-WL).

[0154] like Figure 10 As shown, the time period t0-t6 corresponds to the current programming process of the selected memory cell in the first stack, and the time period after t6 corresponds to the next programming process. The current programming process includes a discharge phase (i.e., the phase of performing a discharge operation), while the next programming process does not include a discharge phase. However, in some other embodiments, the next programming process may also include a discharge phase. This application's embodiments limit whether the next programming process includes a discharge phase. It can be understood that yes. In multiple programming processes of the first stack, the discharge phase involved in this application occurs in at least one programming process. Here, this application does not limit the at least one programming process in which the discharge phase occurs.

[0155] The time period t0-t1 corresponds to the pre-charging phase in this programming process, the time period t1-t3 corresponds to the programming phase in this programming process, the time period t3-t4 corresponds to the discharging phase in this programming process, during which the discharging operation is performed, and t5-t6 corresponds to the verification phase in this programming process.

[0156] During t1-t3, the initial voltage of the bit line is maintained on sel-BL, and SL is kept grounded, where the initial voltage of the bit line is the initial voltage of the bit line. Starting from t0, the voltage of the DSL coupled to sel-TSG gradually increases from the initial voltage of the DSL. When it increases to a certain voltage, it is maintained on the DSL, where this voltage is less than the second voltage. The initial voltage of the DSL is maintained on the DSL coupled to sel-TSG. During a certain period of t1-t3, the voltage of sel-WL is maintained at a certain high voltage, and then during t2-t3, the voltage of sel-WL gradually decreases from this high voltage. During a certain period of t1-t3, the voltage of sel-deck-WL is maintained at the fourth voltage until the end of the programming phase. During a certain period of t1-t3, the voltage of unsel-deck-WL is maintained at a high voltage, and then gradually decreases from the high voltage until it decreases to the fifth voltage at t3.

[0157] During the period t3-t4, the discharge phase begins. SL remains grounded. Starting at t3, the voltage of sel-BL gradually increases from the initial voltage of the bit line until it reaches the first voltage, and maintains this first voltage for a certain period. Then, it gradually decreases until it returns to the initial voltage of the bit line. Starting at t3, the voltage of DSL gradually increases until it reaches the second voltage, and maintains this second voltage for a certain period, keeping TSG on. Then, it gradually decreases until it returns to the initial voltage of DSL. Starting at t3, the voltage of SSL gradually increases from its initial voltage until it reaches the third voltage, and maintains this third voltage for a certain period, keeping BSG on. Then, it gradually decreases until it returns to the initial voltage of SSL. Starting at t3, the voltage of sel-WL gradually increases, and when it reaches the fourth voltage, it remains at the fourth voltage, keeping the selected memory cell on. Afterward, the voltage of sel-WL gradually decreases from the fourth voltage until t4, when it returns to the initial voltage of the bit line. For a certain period after t3, the fourth voltage is maintained on the sel-deck-WL, keeping the unselected memory cells in the first stack on. Then, the voltage of the sel-deck-WL gradually decreases from the fourth voltage until t4, when it drops to the initial word line voltage, which is the initial voltage of the word line coupled to the memory cell. For a certain period after t3, the voltage of the unsel-deck-WL gradually decreases from the fifth voltage until t4, when it drops to the initial word line voltage. While the voltage of the unsel-deck-WL remains at the fifth voltage, the memory cells in the second stack are not on. Under the action of the first voltage on the bit line, the channel of the selected memory string slowly discharges.

[0158] Furthermore, memory strings other than the selected memory string in the memory block to be programmed are considered as unselected memory strings. The bit lines coupled to the unselected memory strings are unselected bit lines, i.e., unsel-BL, and the TSGs in the unselected memory strings are unselected TSGs, i.e., unsel-TSGs. Since the unselected memory strings are not programmed, during the discharge phase, a sixth voltage is applied to the unsel-BL. This sixth voltage can be the same as or different from the first voltage, but the gate of the unsel-TSG maintains the initial voltage of the TSG to prevent the unselected memory strings from being turned on.

[0159] Method A2: After the programming phase ends, after a first preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0160] Wherein, the first preset duration is greater than 0, and the first preset duration can be set according to the specific implementation scenario. Here, the embodiment of this application does not limit the range of values ​​for the first preset duration.

[0161] Taking the first selection transistor as TSG, the second selection transistor as BSG, the second voltage as the turn-on voltage of TSG, and the third voltage as the turn-on voltage of BSG as an example, see [reference needed]. Figure 11 A voltage waveform diagram of channel discharge after a first preset time period is shown according to an exemplary embodiment.

[0162] like Figure 11 As shown, the time period t0-t5 corresponds to the current programming process of the selected memory cell in the first stack, and the time period after t5 corresponds to the next programming process. The time period t0-t1 corresponds to the pre-charging phase of the current programming process, the time period t1-t2 corresponds to the programming phase of the current process, and the duration of the time period t2-t3 is the first preset duration. The time period t3-t4 corresponds to the discharging phase of the current programming process, and the time period t4-t5 corresponds to the verification phase of the current programming process.

[0163] During the period t1-t2, the voltages on the SSL coupled to sel-BL and sel-BSG remain at their respective initial voltages. However, the voltages on the DSL coupled to sel-WL, sel-deck-WL, unsel-deck-WL, and sel-TSG gradually decrease after maintaining a high voltage for a certain period of time, and at t2, they decrease to their respective initial voltages.

[0164] During the period t2-t3, sel-BL, SSL, sel-WL, sel-deck-WL, unsel-deck-WL, and SSL maintain their respective initial voltages.

[0165] During the period t3-t4, starting at t3, the voltage of sel-BL gradually increases from the initial voltage of the bit line until it reaches the first voltage, and maintains the first voltage for a certain period of time. Then, it gradually decreases until it drops back to the initial voltage of the bit line at t4. Starting at t3, the voltage of DSL gradually increases from the initial voltage until it reaches the second voltage, and maintains the second voltage for a certain period of time, keeping TSG on. Then, it gradually decreases until it drops back to the initial voltage at t4. Starting at t3, the voltage of SSL gradually increases from the initial voltage until it reaches the third voltage, and maintains the third voltage for a certain period of time, keeping BSG on. Then, it gradually decreases until it drops back to the initial voltage at t4. Starting at time t3, the voltages of sel-WL and sel-deck-WL gradually increase from their initial voltages until they reach their corresponding fourth voltage, and remain at the fourth voltage for a certain period, keeping the memory cells in the first stack conducting. Afterward, the voltages of sel-WL and sel-deck-WL gradually decrease until they drop back to their initial voltages at time t4. Starting at time t3, the voltage of unsel-deck-WL gradually increases from the initial word line voltage until it reaches the fifth voltage, and remains at the fifth voltage for a certain period, keeping the memory cells in the second stack non-conductive. Afterward, the voltage of unsel-deck-WL gradually decreases until it drops back to the initial word line voltage at time t4.

[0166] During t1-t4, SL remains grounded. During the discharge phase, during t3-t4, when sel-TSG and sel-BSG are turned on, the channel of the memory string is turned on. If the memory cells of the first stack are turned on, and the voltage of unsel-deck-WL is maintained at the fifth voltage, the memory cells of the second stack are not turned on. Under the action of the first voltage of the bit line, the channel of the selected memory string is slowly discharged.

[0167] Additionally, since non-selected memory strings are not programmed, the same sixth voltage is applied to unsel-BL during the discharge phase, but the gate of unsel-TSG maintains the initial voltage of TSG to prevent non-selected memory strings from turning on.

[0168] Figure 12 This is a flowchart illustrating an operational method performed after the verification phase, according to an exemplary embodiment, such as... Figure 12 As shown.

[0169] 1201. After the verification phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to the first select line coupled to the first select transistor, and a third voltage is applied to the second select line coupled to the second select transistor.

[0170] In this scenario, the verification phase of the first stack follows the programming phase of the first stack, and both the verification and programming phases constitute the current programming process of the first stack. In this case, according to the execution sequence, the stages of the current programming process of the first stack are, in order: pre-charge phase, programming phase, verification phase, and discharge phase.

[0171] The process of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, and applying a third voltage to the second select line coupled to the second select transistor is described in step 801 and will not be repeated here.

[0172] 1202. After the verification phase of the first stack, a fourth voltage is applied to the word line coupled to each memory cell of the first stack.

[0173] The process of applying a fourth voltage to the word lines coupled to each memory cell of the first stack is described in step 802 and will not be repeated here.

[0174] 1203. After the verification phase of the first stack, a fifth voltage is applied to the word line coupled to each memory cell of the second stack.

[0175] The process of applying a fifth voltage to the word lines coupled to each memory cell of the second stack is described in step 803 and will not be repeated here.

[0176] It should be noted that the peripheral circuit can execute steps 1201-1203 simultaneously or at different times. In this embodiment, the execution order of steps 1201-1203 is not limited.

[0177] The method provided in this application embodiment applies a first voltage to one end of the memory string after the verification stage of the first stack, applies a second voltage and a third voltage to the selection lines coupled to the first and second selection transistors of the memory string, respectively, so that the first and second selection transistors are turned on, applies a fourth voltage to the word lines coupled to the memory cells of the first stack, so that the memory cells of the first stack are turned on, and applies a fifth voltage to the word lines coupled to the memory cells of the second stack in the memory string, so that the memory cells of the second stack are not turned on, thereby discharging the channel of the memory string. During the discharge process, since some memory cells in the memory string are in a conducting state and other memory cells are in a non-conducting state, the current in the channel during the discharge process can be reduced, the hot carrier injection of the memory cells in the second stack can be reduced, and the interference to the memory cells of the second stack can be reduced.

[0178] Figure 12 The process shown is the process of performing a discharge operation on the memory string containing the first stack after the verification phase. The method for performing the discharge operation on the memory string after the verification phase includes either method B1 or method B2.

[0179] Method B1: After the verification phase of the first stack ends, immediately execute the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0180] Taking the first selection transistor as TSG, the second selection transistor as BSG, the second voltage as the turn-on voltage of TSG, and the third voltage as the turn-on voltage of BSG as an example, see [reference needed]. Figure 13 A voltage waveform diagram of channel discharge immediately after the completion of a verification phase is shown according to an exemplary embodiment.

[0181] like Figure 13 As shown, the time period t0-t4 corresponds to the current programming process of the selected memory cell in the first stack, and the time period after t4 corresponds to the next programming process. The time period t0-t1 corresponds to the pre-charging phase of the current programming process, the time period t1-t2 corresponds to the programming phase of the current programming process, the time period t2-t3 corresponds to the verification phase of the current programming process, and the total duration of t2-t3 is also the preset duration. The time period t3-t4 corresponds to the discharging phase of the current programming process, during which a discharging operation is performed.

[0182] During the period t2-t3 after programming ends, starting from t2, the voltage of sel-BL gradually increases from the initial bit line voltage, and remains at the first voltage after reaching it. At t3, for a certain period after entering the discharge phase, the voltage of sel-BL continues to maintain the first voltage, and then gradually decreases until it decreases to the initial bit line voltage at t4.

[0183] During the period t2-t3 after programming, starting from t2, the voltage of the DSL coupled to the sel-TSG gradually increases from its initial voltage, and remains at the second voltage after reaching it. Starting from t2, the voltage of the SSL coupled to the sel-BSG gradually increases from its initial voltage, and remains at the third voltage after reaching it.

[0184] At time t3, for a certain period after entering the discharge phase, the DSL voltage continues to maintain the second voltage, causing the TSG to conduct. The SSL voltage continues to maintain the third voltage, causing the BSG to conduct. Afterward, the voltages of both the DSL and SSL gradually decrease until they drop to their respective initial voltages at time t4.

[0185] During the period t2-t3 after programming, starting from t2, the voltages of sel-WL and sel-deck-WL gradually increase, maintaining the fourth voltage thereafter. At t3, for a certain duration after entering the discharge phase, sel-WL and sel-deck-WL continue to maintain the fourth voltage, turning on the memory cells of the first stack. Afterward, the voltages of sel-WL and sel-deck-WL gradually decrease until t4, when they drop back to the initial word line voltage.

[0186] During a certain period between t2 and t3, the voltage of the unsel-deck-WL remains at the fifth voltage. Afterward, it gradually decreases from the fourth voltage until it reaches the fifth voltage at t3. At t3, the discharge phase begins, and for a certain period after t3, the voltage of the unsel-deck-WL continues to remain at the fifth voltage, keeping the memory cells of the second stack non-conductive. Then, the voltage of the unsel-deck-WL gradually decreases from the fifth voltage until it reaches the initial word line voltage at t4.

[0187] During t1-t4, SL remains grounded. During the discharge phase, during t3-t4, when sel-TSG and sel-BSG are turned on, the channel of the memory string is turned on. If the memory cells of the first stack are turned on, and the voltage of unsel-deck-WL is maintained at the fifth voltage, the memory cells of the second stack are not turned on. Under the action of the first voltage of the bit line, the channel of the selected memory string is slowly discharged.

[0188] Additionally, since non-selected memory strings are not programmed, a sixth voltage is applied to unsel-BL during the discharge phase, but the gate of unsel-TSG maintains the initial voltage of TSG to prevent non-selected memory strings from turning on.

[0189] Method B2: After the verification phase of the first stack ends, after a second preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

[0190] Wherein, the second preset duration is greater than 0, and the second preset duration may be equal to or not equal to the first preset duration. The second preset duration can be set according to the specific implementation scenario. Here, the embodiment of this application does not limit the range of values ​​for the second preset duration.

[0191] Taking the first selection transistor as TSG, the second selection transistor as BSG, the second voltage as the turn-on voltage of TSG, and the third voltage as the turn-on voltage of BSG as an example, see [reference needed]. Figure 14 A voltage waveform diagram of channel discharge after a second preset time period is shown according to an exemplary embodiment.

[0192] like Figure 14 As shown, the time period t0-t5 corresponds to the current programming process of the selected memory cell in the first stack, and the time period after t5 corresponds to the next programming process. The time period t0-t1 corresponds to the pre-charging phase of the current programming process, the time period t1-t2 corresponds to the programming phase of the current process, the time period t2-t3 corresponds to the verification phase of the current programming process, and the duration of the time period t3-t4 is the second preset duration. The time period t4-t5 corresponds to the discharging phase of the current programming process.

[0193] During the period t2-t3, the voltages on the DSL coupled to sel-BL and sel-TSG, sel-WL, sel-deck-WL, unsel-deck-WL, and SSL coupled to sel-BSG, after maintaining a high voltage for a certain period of time, gradually decreased, and at t3, they decreased to their respective initial voltages.

[0194] During the period t3-t4, sel-BL, DSL, sel-WL, sel-deck-WL, unsel-deck-WL, and SSL maintain their respective initial voltages.

[0195] During the period t4-t5, starting at t4, the voltage of sel-BL gradually increases from its initial bit line voltage until it reaches a first voltage, which is maintained for a certain period. Then, it gradually decreases until it returns to the initial bit line voltage at t5. Starting at t4, the voltage of the DSL coupled to sel-TSG gradually increases from its initial voltage until it reaches a second voltage, which is maintained for a certain period. Then, the DSL voltage gradually decreases until it returns to its initial voltage at t5. The voltage of the SSL coupled to sel-BSG gradually increases from its initial voltage until it reaches a third voltage, which is maintained for a certain period. Then, the SSL voltage gradually decreases until it returns to its initial voltage at t5. Starting at time t4, the voltages of sel-WL and sel-deck-WL gradually increase from their initial voltages until they reach a fourth voltage, which is maintained for a certain period, keeping the memory cells in the first stack conducting. Afterward, the voltages of sel-WL and sel-deck-WL gradually decrease until they return to their initial voltages at time t5. Starting at time t4, the voltage of unsel-deck-WL gradually increases from the initial word line voltage until it reaches a fifth voltage, which is maintained for a certain period, keeping the memory cells in the second stack non-conductive. Afterward, the voltage of unsel-deck-WL gradually decreases until it returns to the initial word line voltage at time t5.

[0196] During t1-t5, SL remains grounded. During the discharge phase, during t4-t5, when sel-TSG and sel-BSG are turned on, the channel of the memory string is turned on. If the memory cells of the first stack are turned on, and the voltage of unsel-deck-WL is maintained at the fifth voltage, the memory cells of the second stack are not turned on. Under the action of the first voltage of the bit line, the channel of the selected memory string is slowly discharged.

[0197] Additionally, since non-selected memory strings are not programmed, a sixth voltage is applied to unsel-BL during the discharge phase, but the gate of unsel-TSG maintains the initial voltage of TSG to prevent non-selected memory strings from turning on.

[0198] Figure 15 This is a comparison diagram of the threshold voltage drift of memory cells in a second stack according to an exemplary embodiment. Without including the discharge phase proposed in this disclosure during the programming process, the memory cells in the second stack of the memory string are not programmed, but the memory cells in the first stack of the memory string are programmed multiple times. Afterwards, the offset of the threshold voltage of the memory cells in the second stack is statistically analyzed, and the offset of the threshold voltage of the memory cells in the second stack is distributed as follows: Figure 15The quantile diagram shown on the left is as follows. In cases where the programming process includes the discharge stage proposed in this application, the memory cells in the second stack of the memory string are not programmed, but the memory cells in the first stack of the memory string are programmed multiple times. Afterwards, the offset of the threshold voltage of the memory cells in the second stack is statistically analyzed, and the offset of the threshold voltage of the memory cells in the second stack is distributed as follows: Figure 15 The quantile diagram shown on the right side of the middle section. From... Figure 15 As can be seen from the two quantile diagrams, the threshold voltage offset in the left quantile diagram is generally higher than that in the right quantile diagram. Therefore, adding a discharge stage after the verification stage of the memory cell can reduce the interference of HCI to memory cells in other stacks.

[0199] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory, characterized in that, The memory includes a storage array and peripheral circuitry; The storage array includes a storage string, a first select line, a second select line, a bit line, and multiple word lines. The storage string includes a first stack, a second stack, a first select transistor, and a second select transistor. The first stack and the second stack each include multiple storage cells. One end of the storage string is coupled to a bit line, the first selection line is coupled to the first selection transistor, and the second selection line is coupled to the second selection transistor. The plurality of word lines are respectively coupled to the plurality of storage cells of the storage string; The peripheral circuitry is coupled to the first select line, the second select line, the bit line, and the plurality of word lines, and the peripheral circuitry is configured to: After the programming phase of the first stack, a first voltage is applied to the bit line coupled to the memory string, a second voltage is applied to the first select line coupled to the first select transistor, a third voltage is applied to the second select line coupled to the second select transistor, a fourth voltage is applied to the word line coupled to each memory cell of the first stack, and a fifth voltage is applied to the word line coupled to each memory cell of the second stack to discharge the channel of the memory string. Wherein, the second voltage is used to turn on the first selection transistor, the third voltage is used to turn on the second selection transistor, the fourth voltage applied to each memory cell of the first stack is used to turn on the corresponding memory cell, and the fifth voltage applied to each memory cell of the second stack is used to turn off the corresponding memory cell.

2. The memory according to claim 1, characterized in that, The verification phase of the first stack occurs after the programming phase, and the peripheral circuitry is further configured as follows: After the programming phase and before the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

3. The memory according to claim 2, characterized in that, The peripheral circuit is also configured to: Immediately after the programming phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are executed.

4. The memory according to claim 2, characterized in that, The peripheral circuit is also configured to: After the programming phase ends, after a first preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

5. The memory according to claim 1, characterized in that, The verification phase of the first stack occurs after the programming phase, and the peripheral circuitry is further configured as follows: After the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

6. The memory according to claim 5, characterized in that, The peripheral circuit is also configured to: Immediately after the verification phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are executed.

7. The memory according to claim 5, characterized in that, The peripheral circuit is also configured to: After the verification phase ends, after a second preset time, the following steps are performed: applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

8. The memory according to any one of claims 1-7, characterized in that, The fifth voltage is less than the minimum on-state voltage of each memory cell in the second stack.

9. The memory according to any one of claims 1-7, characterized in that, The fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage applied to the word line coupled to each memory cell of the second stack during the programming phase. Alternatively, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, but less than the voltage applied to the word line coupled to each memory cell of the second stack during the verification phase.

10. A storage system, characterized in that, The system includes a memory configured to store data, the memory including a storage array and peripheral circuitry; The storage array includes a storage string, a first select line, a second select line, a bit line, and multiple word lines. The storage string includes a first stack, a second stack, a first select transistor, and a second select transistor. The first stack and the second stack each include multiple storage cells. One end of the storage string is coupled to a bit line, the first selection line is coupled to the first selection transistor, and the second selection line is coupled to the second selection transistor. The plurality of word lines are respectively coupled to the plurality of storage cells of the storage string; The peripheral circuitry is coupled to the first select line, the second select line, the bit line, and the plurality of word lines, and the peripheral circuitry is configured to: After the programming phase of the first stack, a first voltage is applied to the bit line coupled to the memory string, a second voltage is applied to the first select line coupled to the first select transistor, a third voltage is applied to the second select line coupled to the second select transistor, a fourth voltage is applied to the word line coupled to each memory cell of the first stack, and a fifth voltage is applied to the word line coupled to each memory cell of the second stack to discharge the channel of the memory string. Wherein, the second voltage is used to turn on the first selection transistor, the third voltage is used to turn on the second selection transistor, the fourth voltage applied to each memory cell of the first stack is used to turn on the corresponding memory cell, and the fifth voltage applied to each memory cell of the second stack is used to turn off the corresponding memory cell.

11. The system according to claim 10, characterized in that, The verification phase of the first stack occurs after the programming phase, and the peripheral circuitry is further configured as follows: After the programming phase and before the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

12. The system according to claim 10, characterized in that, The verification phase of the first stack occurs after the programming phase, and the peripheral circuitry is further configured as follows: After the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

13. The system according to any one of claims 10-12, characterized in that, The fifth voltage applied to each memory cell of the second stack is less than the minimum on-state voltage of each memory cell of the second stack.

14. The system according to any one of claims 10-12, characterized in that, The fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage applied to the word line coupled to each memory cell of the second stack during the programming phase. Alternatively, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, but less than the voltage applied to the word line coupled to each memory cell of the second stack during the verification phase.

15. The system according to any one of claims 10-12, characterized in that, The system also includes a host and a memory controller; The host is configured to send data to or receive data from the memory; The memory controller is coupled to the host and the memory, and is configured to control the memory.

16. A method for operating a memory, characterized in that, The memory includes a memory array, which includes a memory string, a first select line, a second select line, and multiple word lines such as bit lines. The memory string includes a first stack, a second stack, a first select transistor, and a second select transistor. The first stack and the second stack each include multiple memory cells. One end of the storage string is coupled to a bit line, the first selection line is coupled to the first selection transistor, and the second selection line is coupled to the second selection transistor. The plurality of word lines are respectively coupled to a plurality of storage cells of the storage string, and the method includes: After the programming phase of the first stack, a first voltage is applied to the bit line coupled to the memory string, a second voltage is applied to the first select line coupled to the first select transistor, a third voltage is applied to the second select line coupled to the second select transistor, a fourth voltage is applied to the word line coupled to each memory cell of the first stack, and a fifth voltage is applied to the word line coupled to each memory cell of the second stack to discharge the channel of the memory string. Wherein, the second voltage is used to turn on the first selection transistor, the third voltage is used to turn on the second selection transistor, the fourth voltage applied to each memory cell of the first stack is used to turn on the corresponding memory cell, and the fifth voltage applied to each memory cell of the second stack is used to turn off the corresponding memory cell.

17. The method according to claim 16, characterized in that, The verification phase of the first stack occurs after the programming phase, and the method further includes: After the programming phase and before the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

18. The method according to claim 16, characterized in that, The verification phase of the first stack occurs after the programming phase, and the method further includes: After the verification phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select transistor, applying a third voltage to the second select line coupled to the second select transistor, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

19. The method according to any one of claims 16-18, characterized in that, The fifth voltage is less than the minimum on-state voltage of each memory cell in the second stack.

20. The method according to any one of claims 16-18, characterized in that, The fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, and less than the voltage applied to the word line coupled to each memory cell of the second stack during the programming phase. Alternatively, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack, but less than the voltage applied to the word line coupled to each memory cell of the second stack during the verification phase.

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