A semiconductor device having an asymmetric work function metal layer

Abstract

A semiconductor device with asymmetric work function metal layer is disclosed. The semiconductor device mainly comprises a metal gate disposed on a substrate. The metal gate comprises a first work function metal layer. The first work function metal layer comprises a first vertical portion, a second vertical portion, and a first horizontal portion connecting the first vertical portion and the second vertical portion. In the embodiment, the first vertical portion and the second vertical portion preferably comprise different heights.

Description

[0001] This application is a divisional application of a Chinese patent application with the application number 201810896433.8 and the application date 08 / 08 / 2018 for a semiconductor device with asymmetric work function metal layer. TECHNICAL FIELD

[0002] The present application relates to a semiconductor device, in particular, to a semiconductor device with asymmetric work function metal layer. BACKGROUND

[0003] In the existing semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as the standard gate filling material. However, as the size of MOS transistors continues to shrink, the traditional polysilicon gate causes the device performance to decrease due to boron penetration effect and its inevitable depletion effect, which increases the equivalent gate dielectric layer thickness, reduces the gate capacitance, and further leads to the decline of device driving ability. Therefore, the semiconductor industry tries to use new gate filling materials, such as using work function metal to replace the traditional polysilicon gate, as the control electrode for matching the high dielectric constant (High-K) gate dielectric layer.

[0004] However, in the current process of manufacturing metal gate transistors, especially when manufacturing metal gate transistors with different sizes, as the line width decreases, the multi-layer work function metal layer and other metal materials often cannot be successfully filled into the smaller size groove to form a metal gate and affect the device performance. Therefore, how to improve the current manufacturing process to solve the above problems is an important issue today. SUMMARY

[0005] One embodiment of the present application discloses a semiconductor device, which mainly comprises a metal gate disposed on a substrate, the metal gate comprising a first work function metal layer, wherein the first work function metal layer comprises a first vertical portion, a second vertical portion, and a first horizontal portion connecting the first vertical portion and the second vertical portion. In this embodiment, the first vertical portion and the second vertical portion preferably comprise different heights.

[0006] Another embodiment of the present application discloses a semiconductor device, which includes a metal gate disposed on a substrate, the metal gate including a first work function metal layer and a second work function metal layer disposed on the first work function metal layer. The first work function metal layer includes a first U-shape, and the first U-shape includes a first end and a second end. The second work function metal layer includes a second U-shape, and the second U-shape includes a third end and a fourth end. The first end upper surface is flush with the third end upper surface, the second end upper surface is flush with the fourth end upper surface, and the first end is lower than the second end. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1 to 3 A schematic diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;

[0008] Figures 4 to 5 A schematic diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;

[0009] Figures 6 to 8 A schematic diagram of a method of fabricating a semiconductor device according to an embodiment of the present application.

[0010] LIST OF ELEMENTS

[0011] 12 substrate 14 fin structure

[0012] 16 gate structure 18 gate structure

[0013] 20 gate dielectric layer 22 gate material layer

[0014] 24 spacer 26 source / drain region

[0015] 28 offset spacer 30 main spacer

[0016] 32 contact hole etch stop layer 34 interlayer dielectric layer

[0017] 36 dielectric layer 38 high-k dielectric layer

[0018] 40 work function metal layer 42 recess

[0019] 44 patterned mask 46 vertical portion

[0020] 48 vertical portion 50 horizontal portion

[0021] 52 work function metal layer 54 low impedance metal layer

[0022] 56 metal gate 58 metal gate

[0023] 60 hard mask 62 first end

[0024] 64 Second end 66 Third end

[0025] 68 Fourth end 70 Vertical part

[0026] 72 Vertical section 74 Horizontal section

[0027] 76 Patterned Masks

[0028] 102 First Area 104 Second Area Detailed Implementation

[0029] Please refer to Figures 1 to 3 , Figures 1 to 3 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, is first provided. A first region 102 and a second region 104 can be defined on the substrate. The first region 102 is preferably used to fabricate larger-sized metal-oxide-semiconductor (MOS) transistors, while the second region 104 is used to fabricate smaller-sized MOS transistors. Therefore, the gate structure or metal gate width of the second region 104 in subsequent fabrication processes is preferably smaller than the gate structure or metal gate width of the first region 102. Furthermore, in this embodiment, the first region 102 and the second region 104 are preferably transistor regions of the same conductivity type, such as both being PMOS or NMOS regions. These variations are all within the scope of this invention. The substrate 12 has at least one fin structure 14, wherein the bottom of the fin structure 14 is covered by an insulating layer, such as silicon oxide, to form a shallow trench isolation. It should be noted that although this embodiment uses the fabrication of a non-planar field-effect transistor, such as a fin structure field-effect transistor, it is not limited to this. The present invention can also be applied to general planar field-effect transistors, and this embodiment is also within the scope of the present invention.

[0030] According to one embodiment of the present invention, the fin structure 14 is preferably fabricated using sidewall image transfer (SIT) technology. The procedure generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0031] In addition, the fin structure 14 can be formed by first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure. Alternatively, the fin structure can be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then performing an epitaxial growth process to grow a semiconductor layer, such as a silicon germanium layer, on the substrate 12 exposed by the patterned hard mask layer, which can serve as the corresponding fin structure. These embodiments of forming the fin structure are all within the scope of the present disclosure.

[0032] Next, at least one gate structure 16, 18 or dummy gate can be formed on the substrate 12 in the first region 102 and the second region 104. In this embodiment, the gate structure 16, 18 can be formed by a gate first process, a gate last process, a high-k first process, or a high-k last process, depending on the process requirements. For example, in the high-k last process, a gate dielectric layer 20 or a dielectric layer, a gate material layer 22 composed of polysilicon, and a selective hard mask (not shown) can be sequentially formed on the substrate 12, and then a pattern transfer process can be performed using a patterned photoresist (not shown) as a mask to remove part of the gate material layer 22 and part of the gate dielectric layer 20 by a single etching or a step-by-step etching process, and then the patterned photoresist can be removed to form a gate electrode or a gate structure 16, 18 composed of the patterned gate dielectric layer 20 and the patterned gate material layer 22 on the substrate 12. In this embodiment, the width of the gate structure 18 in the second region 104 is preferably smaller than the width of the gate structure 16 in the first region 102.

[0033] Then, at least one spacer 24 can be formed on the sidewall of the gate structure 16, 18, and then a source / drain region 26 and / or an epitaxial layer (not shown) can be formed in the fin structure 14 and / or the substrate 12 on both sides of the spacer 24, and a metal silicide (not shown) can be selectively formed on the surface of the source / drain region 24 and / or the epitaxial layer. In this embodiment, the spacer 26 can be a single spacer or a composite spacer, such as a bias spacer 28 and a main spacer 30. The bias spacer 28 and the main spacer 30 can include the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride. The source / drain region 26 can include different dopants depending on the type of transistor to be provided, such as P-type dopants or N-type dopants.

[0034] Next, a contact hole etch stop layer 32 is formed on the surface of the substrate 12 and the gate structures 16 and 18, and then an interlayer dielectric layer 34 is formed on the contact hole etch stop layer 32. Then, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 34 and part of the contact hole etch stop layer 32 and expose the gate material layer 22 made of polysilicon, so that the upper surface of each gate material layer 22 is flush with the upper surface of the interlayer dielectric layer 34.

[0035] like Figure 2 As shown, a metal gate replacement fabrication process is then performed to convert the gate structures 16 and 18 into metal gates. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 22 and even the gate dielectric layer 20 in the gate structures 16 and 18, so as to form grooves 42 in the interlayer dielectric layer 34 of the first region 102 and the second region 104, respectively.

[0036] Subsequently, a selective dielectric layer 36 or a gate dielectric layer, a high dielectric constant dielectric layer 38, and a work function metal layer 40 are sequentially formed in the grooves of the first region 102 and the second region 104. A patterned mask 44 is formed to cover the first region 102 and expose the work function metal layer 40 of the second region 104. An etching process is then performed using the patterned mask 44 as a mask to remove part of the work function metal layer 40 located on top of the interlayer dielectric layer 34 in the second region 102, so that the remaining work function metal layer 40 is slightly lower than the interlayer dielectric layer 34 or the top of the groove.

[0037] In this embodiment, the etching process for removing part of the work function metal layer 40 preferably includes a wet etching process, wherein the etchant used in the etching process preferably includes chlorine, or more specifically, a group consisting of hydrochloric acid and hydrogen peroxide. It is worth noting that in this embodiment, during the aforementioned wet etching process, a rotation step is preferably performed simultaneously on the substrate 12 or the semiconductor wafer, wherein the rotation step preferably rotates only a single semiconductor wafer or substrate 12 rather than simultaneously rotating multiple wafers or a batch of wafers. Since the semiconductor wafer or substrate 12 is subjected to the wet etching process while rotating, the work function metal layer 40 preferably exhibits an asymmetrical structure due to the centrifugal force of the rotation step. In detail, the etched work function metal layer 40 preferably includes a vertical portion 46 on one side of the groove 42, a vertical portion 48 on the other side of the groove 42, and a horizontal portion 50 connecting the vertical portions 46 and 48, wherein the vertical portions 46 and 48 have different heights, with the lower vertical portion 46 being closer to the wafer center and the higher vertical portion 48 being closer to the wafer edge.

[0038] Then as Figure 3 As shown, the patterned mask 44 of the first region 102 is first removed, and then another work function metal layer 52 and a low impedance metal layer 54 are sequentially formed and filled in the grooves 42 of the first region 102 and the second region 104. Then, a planarization process is performed, for example, CMP is used to remove part of the low impedance metal layer 54, part of the work function metal layer 52, part of the work function metal layer 40, and part of the high dielectric constant dielectric layer 38 of the first region 102, and part of the low impedance metal layer 54, part of the work function metal layer 52, and part of the high dielectric constant dielectric layer 38 of the second region 104, so as to form metal gates 56 and 58 in the first region 102 and the second region 104, respectively. Similar to the gate structure before the metal gate replacement process, the width of the metal gate 58 in the second region 104 is preferably smaller than the width of the metal gate 56 in the first region 102. Next, another etching process is performed to remove a portion of the metal gates 56 and 58 in the first region 102 and the second region 104 to form grooves (not shown). Then, a hard mask 60 made of, for example, silicon nitride is filled onto each metal gate 56 and 58. Then, a planarization process is performed, for example, by using CMP to remove part of the hard mask 60 so that the remaining hard mask 60 is aligned with the surface of the interlayer dielectric layer 34. Subsequently, contact plugs can be formed on both sides of each metal gate 56 and 58 to electrically connect the source / drain regions 26, according to the fabrication process requirements. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0039] Please continue to refer to Figures 4 to 5 , Figures 4 to 5 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.Figure 4 As shown, the present invention can be used in Figure 2 After the groove 42 is formed, a selective dielectric layer 36 or a gate dielectric layer, a high dielectric constant dielectric layer 38, a work function metal layer 40, and another work function metal layer 52 are sequentially formed in the groove 42 of the first region 102 and the second region 104. Then, a patterned mask 44 is formed to cover the first region 102 and expose the work function metal layer 52 of the second region 104. Using the patterned mask 44 as a mask, an etching process is performed to remove part of the work function metal layer 52 and part of the work function metal layer 40 located on top of the interlayer dielectric layer 34 in the second region 102, so that the remaining work function metal layer 52 and work function metal layer 40 are slightly lower than the top of the interlayer dielectric layer 34 or the groove 42.

[0040] as Figure 3 In this embodiment, the etching process used to remove part of the work function metal layers 40 and 52 preferably includes a wet etching process, wherein the etchant used in the etching process preferably includes chlorine, or more specifically, may be a group consisting of hydrochloric acid and hydrogen peroxide. Furthermore, since the semiconductor wafer or substrate 12 in this embodiment is subjected to a wet etching process while rotating, the work function metal layers 40 and 52 preferably develop an asymmetric structure due to the centrifugal force of the rotation step.

[0041] Overall, the work function metal layer 40 after etching includes a first U-shape and the first U-shape includes a first end 62 and a second end 64. The work function metal layer 52 disposed on the work function metal layer 40 includes a second U-shape and the second U-shape includes a third end 66 and a fourth end 68. The upper surface of the first end 62 is flush with the upper surface of the third end 66, the upper surface of the second end 64 is flush with the upper surface of the fourth end 68, and the first end 62 and the third end 66 are both lower than the second end 64 and the fourth end 68.

[0042] In detail, the work function metal layer 40 preferably includes a vertical portion 46 disposed on one side of the groove 42, a vertical portion 48 disposed on the other side of the groove 42, and a horizontal portion 50 connecting the vertical portion 46 and the vertical portion 48. The work function metal layer 52 preferably includes a vertical portion 70 disposed on one side of the groove 42, a vertical portion 72 disposed on the other side of the groove 42, and a horizontal portion 74 connecting the vertical portion 70 and the vertical portion 72. The upper surface of the vertical portion 46 is flush with the upper surface of the vertical portion 70, and the upper surface of the vertical portion 48 is flush with the upper surface of the vertical portion 72. The vertical portions 46, 70, 48, and 72 preferably have different heights. For example, the height of the vertical portion 46 is preferably lower than the height of the vertical portion 48, and the height of the vertical portion 70 is lower than the height of the vertical portion 72.

[0043] Then as Figure 5As shown, the patterned mask 44 of the first region 102 is first removed, and then a low-impedance metal layer 54 is sequentially formed in the grooves 42 of the first region 102 and the second region 104 and the grooves 42 are filled. Then a planarization process is performed, for example, CMP is used to remove part of the low-impedance metal layer 54, part of the work function metal layers 40 and 52, part of the high dielectric constant dielectric layer 38 of the first region 102, and part of the low-impedance metal layer 54 and part of the high dielectric constant dielectric layer 38 of the second region 104, so as to form metal gates 56 and 58 in the first region 102 and the second region 104 respectively. Next, another etching process is performed to remove a portion of the metal gates 56 and 58 in the first region 102 and the second region 104 to form grooves (not shown). A hard mask 60, made of, for example, silicon nitride, is then inserted onto each metal gate 56 and 58. A planarization process is then performed, for example, using CMP to remove a portion of the hard mask 60 so that the remaining hard mask 60 is aligned with the surface of the interlayer dielectric layer 34. Subsequently, contact plugs can be formed on both sides of the metal gates 56 and 58 to electrically connect the source / drain regions 26, thus completing the fabrication of a semiconductor device according to an embodiment of the present invention.

[0044] Please continue to refer to Figures 6 to 8 , Figures 6 to 8 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 6 As shown, the present invention can be used in Figure 2 After the groove 42 is formed, a selective dielectric layer 36 or a gate dielectric layer, a high dielectric constant dielectric layer 38, and a work function metal layer 40 are sequentially formed in the groove 42 of the first region 102 and the second region 104. Then, a patterned mask 44 is formed to cover the first region 102 and expose the work function metal layer 40 of the second region 104. Using the patterned mask 44 as a mask, an etching process is performed to remove part of the work function metal layer 40 located on top of the interlayer dielectric layer 34 in the second region 104, so that the remaining work function metal layer 40 is slightly lower than the top of the interlayer dielectric layer 34 or the groove 42.

[0045] like Figure 7 As shown, the patterned mask 44 of the first region 102 can then be removed to form another work function metal layer 52 within the groove 42 between the first region 102 and the second region 104. Then, another patterned mask 76 is formed to cover the first region 102 and expose the work function metal layer 52 of the second region 104. An etching process is then performed using the patterned mask 76 as a mask to remove a portion of the work function metal layer 52 located on top of the interlayer dielectric layer 34 in the second region 104, leaving the remaining work function metal layer 52 slightly below the top of the interlayer dielectric layer 34 or the groove 42. Compared to... Figures 4 to 5In one embodiment, two work function metal layers 40 and 52 are removed simultaneously in a single etching process. Preferably, a segmented etching method is used to remove portions of the work function metal layers 40 and 52. Since the etching gas and methods used are the same as in the aforementioned embodiment, the remaining work function metal layers 40 and 52 each have asymmetrical heights.

[0046] as Figure 3 In this embodiment, the etching process for removing a portion of the work function metal layer preferably includes a wet etching process, wherein the etchant used in the etching process preferably includes chlorine, or more specifically, may be a group consisting of hydrochloric acid and hydrogen peroxide. Furthermore, since the semiconductor wafer or substrate 12 in this embodiment is subjected to a wet etching process while rotating, the work function metal layers 40 and 52 preferably develop an asymmetric structure due to the centrifugal force of the rotation step. In detail, the work function metal layer 40 after etching preferably includes a vertical portion 46 disposed on one side of the groove 42, a vertical portion 48 disposed on the other side of the groove 42, and a horizontal portion 50 connecting the vertical portion 46 and the vertical portion 48. The work function metal layer 52 preferably includes a vertical portion 70 disposed on one side of the groove 42, a vertical portion 72 disposed on the other side of the groove 42, and a horizontal portion 74 connecting the vertical portion 70 and the vertical portion 72. The vertical portions 46 and 48 of the work function metal layer 40 preferably have different heights, and the vertical portions 70 and 72 of the work function metal layer 52 also have different heights. For example, the height of the vertical portion 46 is preferably lower than the height of the vertical portion 48, and the height of the vertical portion 70 is also lower than the height of the vertical portion 72.

[0047] Then as Figure 8As shown, the patterned mask 76 of the first region 102 is first removed, and then a low-impedance metal layer 54 is formed and filled in the grooves 42 of the first region 102 and the second region 104. Then, a planarization process is performed, for example, using CMP to remove part of the low-impedance metal layer 54, part of the work function metal layers 40 and 52, part of the high dielectric constant dielectric layer 38 of the first region 102, and part of the low-impedance metal layer 54 and part of the high dielectric constant dielectric layer 38 of the second region 102, so as to form metal gates 56 and 58 in the first region 102 and the second region 104, respectively. After that, another etching process is performed to remove part of the metal gates 56 and 58 of the first region 102 and the second region 104 to form grooves (not shown), and a hard mask 60 made of, for example, silicon nitride is filled on each metal gate 56 and 58. Then, a planarization process is performed again, for example, using CMP to remove part of the hard mask 60 so that the remaining hard mask 60 is aligned with the surface of the interlayer dielectric layer 34. Subsequently, contact plugs can be formed on both sides of the metal gates 56 and 58 to electrically connect the source / drain regions 26, thereby completing the fabrication of a semiconductor element according to an embodiment of the present invention.

[0048] In this embodiment, the high dielectric constant dielectric layer 38 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- xGroups consisting of TiO3, BST, or combinations thereof.

[0049] Furthermore, the work function metal layer 40 is preferably a P-type work function metal layer, which may be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. The work function metal layer 52 is preferably an N-type work function metal layer, which may be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminum nitride (TiAl), zirconium aluminum nitride (ZrAl), tungsten aluminum nitride (WAl), tantalum aluminum nitride (TaAl), hafnium aluminum nitride (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 52 and the low impedance metal layer 54, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low-resistivity metal layer 54 can be selected from low-resistivity materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof.

[0050] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base with grooves; A first work function metal layer is formed in the groove of the substrate; The first work function metal layer is fabricated using a first etching process, such that the remaining portion of the first work function metal layer located in the groove includes: First vertical section; The second vertical portion, wherein the first vertical portion and the second vertical portion comprise different heights; and The first horizontal portion connects the first vertical portion and the second vertical portion. The first etching process is a wet etching process, and while the first work function metal layer is being etched, the substrate is being rotated.

2. The method as described in claim 1, wherein, Performing this first rotation step on the substrate involves rotating the substrate individually.

3. The method as described in claim 1, wherein, The etchant used in this first etching process includes hydrochloric acid and hydrogen peroxide.

4. The method of claim 1, further comprising: A second work function metal layer is formed in the groove of the substrate, and the second work function metal layer covers the remaining portion of the first work function metal layer; A second etching process is performed on the second work function metal layer, such that the remaining portion of the second work function metal layer in the groove includes: The third vertical section; The fourth vertical portion, wherein the third vertical portion and the fourth vertical portion comprise different heights; and The second horizontal section connects the third vertical section and the fourth vertical section.

5. The method of claim 4, wherein, The second etching process is a wet etching process, and while performing the second etching process on the second work function metal layer, the substrate is subjected to a second rotation step.

6. The method of claim 5, wherein, The second rotation step of the substrate includes rotating the substrate separately.

7. The method of claim 4, wherein, The third vertical portion covers the side and top surfaces of the first vertical portion, and the fourth vertical portion covers the side and top surfaces of the second vertical portion.

8. The method of claim 4, further comprising: A low-impedance metal layer is formed in the groove of the substrate, wherein the remaining portion of the first work function metal layer and the remaining portion of the second work function metal layer are both located directly below the flat surface of the low-impedance metal layer.

9. The method of claim 1, wherein, The substrate also includes two source / drain regions, respectively located on opposite sides of the groove, wherein the first vertical portion is closer to one of the two source / drain regions than the second vertical portion.

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