A method for opening PI layer with ultra-narrow pitch and a semiconductor packaging structure

Abstract

The present invention discloses a method for opening an ultra-narrow pitch PI layer and a semiconductor packaging structure. The method includes: providing a substrate, fabricating an ultra-thin PI layer on the substrate by using an ultra-high speed spin coating method, where the ultra-thin PI layer is formed with an ultra-narrow opening one having an opening width dimension less than or equal to 5 μm, fabricating a dielectric layer on the ultra-thin PI layer, the dielectric layer being a PI layer with a glue thickness of 5 - 10 μm, and forming an opening two, and the opening one and the opening two form a space for fabricating a redistribution layer; a semiconductor packaging structure with multiple redistribution layers can be fabricated by this method, and this method can be adopted when each redistribution layer grows. The present invention combines a conventional PI layer into an ultra-thin PI layer and a PI dielectric layer, provides an ultra-narrow PI opening size without changing the thickness of the original conventional PI layer, solves the problem that the conventional PI layer cannot achieve an ultra-narrow pitch opening, the two PI layers better provide circuit connection and mechanical properties, achieve a better electromagnetic shielding effect, and at the same time improve the problem of relatively large surface undulations of the conventional PI layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a method for opening a PI layer with an ultra-narrow pitch and a semiconductor packaging structure. Background Art

[0002] During the semiconductor packaging lithography process, for a conventional PI layer, due to the limitation of the aspect ratio (resist thickness: opening size), while ensuring the PI resist thickness, it is impossible to take into account the size of the PI opening.

[0003] As Figure 1 shown, in this figure, 101 is a substrate, and 102 is a conventional PI layer. The commonly used PI layer forms a PI protection layer with a resist thickness of 5-10 μm through conventional coating, exposure, development, and curing process flows. In the case of the conventional resist thickness, due to the characteristics of the PI resist material, there will be its limit opening size. For different PI resist materials, their limit capabilities will have some differences. Taking BL301 as an example, the aspect ratio limit is 1:2. When the conventional PI layer is 5 μm, the minimum opening size is 10 μm; if the designed encapsulation opening size is smaller than its opening ability, abnormal defects such as residual glue, overdevelopment, and deformation will occur inside the opening after the lithography process, and its process requirements cannot be achieved.

[0004] At the same time, as Figure 2 shown, in this figure, 101 is a substrate, 102 is a conventional PI layer, and 103 is a redistribution layer. In the fan-out packaging process, due to multiple redistribution layers (RDL) and multiple PI layers, the surface lines of the substrate are complex and the surface undulation changes greatly. The conventional PI layer coating cannot fill the places with large undulations, and the uniformity of the PI resist thickness is poor, which has a significant impact on the stability and reliability of the entire package. Summary of the Invention

[0005] In order to solve the above problems, the present invention provides a method for opening a PI layer with an ultra-narrow pitch and a semiconductor packaging structure, providing an ultra-narrow PI opening size, solving the problem that the conventional PI layer cannot achieve an ultra-narrow pitch opening, and the two PI layers better provide circuit connection and mechanical properties, achieving a better electromagnetic shielding effect, and at the same time improving the problem of large surface undulations of the conventional PI layer.

[0006] According to one aspect of the present invention, there is provided a method for opening a PI layer with an ultra-narrow pitch, including:

[0007] Providing a substrate, the substrate including a passivation layer on the surface and a semiconductor device structure under the passivation layer, the semiconductor device structure at least including a top metal layer adjacent to the passivation layer and a substrate under the top metal layer;

[0008] Apply glue on the substrate to form the first ultra-thin PI layer. Perform low-energy exposure on the first ultra-thin PI layer, dissolve and remove the photoresist in the unexposed area through development to form an ultra-narrow opening 1, and then cure it to form the first ultra-thin PI layer with a glue thickness less than or equal to 3 μm. The opening width dimension of opening 1 is less than or equal to 5 μm;

[0009] Apply glue on the first ultra-thin PI layer to form the first dielectric layer. The first dielectric layer is a PI layer. Through exposure, development, and curing of the first dielectric layer, a first dielectric layer with a glue thickness of 5 - 10 μm is formed, and an opening 2 with an opening width dimension greater than 8 μm is formed. Opening 2 is located above opening 1;

[0010] Opening 1 and opening 2 form a space for manufacturing the redistribution layer.

[0011] In some embodiments, the spin coating method is used to manufacture the first ultra-thin PI layer and the first dielectric layer.

[0012] In some embodiments, an ultra-high rotation speed is used when manufacturing the first ultra-thin PI layer, and the rotation speed is greater than 5000 rpm / min.

[0013] In some embodiments, after opening 1 and opening 2 are formed and the first layer of redistribution layer is manufactured, a second ultra-thin PI layer is manufactured on the first dielectric layer, and through low-energy exposure, development, and curing, a second ultra-thin PI layer with opening 3 is formed. The glue thickness of the second ultra-thin PI layer is less than or equal to 3 μm, and the opening width dimension of opening 3 is less than or equal to 5 μm;

[0014] A second dielectric layer is manufactured on the second ultra-thin PI layer. The second dielectric layer is a PI layer. The second dielectric layer is formed into a second dielectric layer with opening 4 through exposure, development, and curing. The glue thickness of the second dielectric layer is 5 - 10 μm, the opening width dimension of opening 4 is greater than 8 μm, and opening 4 is located above opening 3;

[0015] Opening 3 and opening 4 form a space for manufacturing the second layer of redistribution layer, and the surface of the second dielectric layer is flat.

[0016] According to another aspect of the present invention, there is provided a semiconductor package structure manufactured by using the above-mentioned ultra-narrow pitch PI layer opening method, including:

[0017] A substrate, the substrate includes a passivation layer on the surface and a semiconductor device structure under the passivation layer. The semiconductor device structure at least includes a top metal layer adjacent to the passivation layer and a substrate under the top metal layer;

[0018] A first ultra-thin PI layer provided on the passivation layer, and the first ultra-thin PI layer is provided with an opening 1 with an opening width dimension less than or equal to 5 μm;

[0019] The first dielectric layer disposed on the first ultra-thin PI layer, the first dielectric layer is provided with an opening two with an opening width dimension greater than 8 μm, and the opening two is located above the opening one, forming a space for manufacturing the redistribution layer;

[0020] The redistribution layer, the lower part of the redistribution layer is filled in the space formed by the opening one and the opening two, and the bottom of the redistribution layer has a seed layer.

[0021] In some embodiments, a second ultra-thin PI layer is covered on the redistribution layer and the first dielectric layer, and the second ultra-thin PI layer is provided with an opening three with an opening width dimension less than or equal to 5 μm;

[0022] A second dielectric layer is provided on the second ultra-thin PI layer, the second dielectric layer is provided with an opening four with an opening width dimension greater than 8 μm, and the opening four is located above the opening three, forming a space for manufacturing the redistribution layer;

[0023] The opening three and the opening four are filled with the redistribution layer, and the bottom of the redistribution layer has a seed layer.

[0024] In some embodiments, the thickness of the first ultra-thin PI layer is less than or equal to 3 μm, and the thickness of the first dielectric layer is 5-10 μm.

[0025] In some embodiments, the thickness of the second ultra-thin PI layer is less than or equal to 3 μm, and the thickness of the second dielectric layer is 5-10 μm.

[0026] In some embodiments, a downwardly concave recess is provided at the top of the redistribution layer.

[0027] Compared with the prior art, the beneficial effects of the present invention are:

[0028] (1) Solve the problem of ultra-narrow pitch PI opening: Replace the conventional PI layer with a combination of an ultra-thin PI layer and a PI dielectric layer, and the combined thickness of the improved PI dielectric layer and the ultra-thin PI layer can be equal to the original conventional PI layer. In this way, without changing the thickness of the original conventional PI layer, it can provide a growth space for the redistribution layer with an ultra-narrow opening width to reduce the width dimension of the bottom of the redistribution layer.

[0029] (2) Solve the electromagnetic shielding problem of high-frequency circuits: By combining the bottom ultra-thin PI layer and the PI dielectric layer as an insulating and protective layer, the two PI layers can also better provide circuit connection and mechanical properties, achieving a better electromagnetic shielding effect. And by forming the ultra-narrow opening, the bottom width dimension of the formed redistribution layer is reduced, which can also increase the distance between adjacent redistribution layers, effectively increasing the path length of electron migration between adjacent redistribution layers.

[0030] (3) Improving the surface undulation problem of the PI layer: In the case of a multi-layer redistribution layer (RDL), the surface flatness can be improved through the PI dielectric layer on the ultra-thin PI layer, and the problem of large surface undulation of the conventional PI layer can be improved. In addition, the top of the redistribution layer has a recess, which can increase the adhesion between the redistribution layer and the ultra-thin PI layer and improve the yield rate of semiconductor packaging. Description of the Drawings

[0031] Figure 1 is a schematic structural diagram of a conventional PI layer in the prior art;

[0032] Figure 2 is a semiconductor packaging structure fabricated by using the conventional PI layer structure and the existing packaging method in the prior art, and there are problem defects of undulation on the surface of its PI layer;

[0033] Figure 3 is a schematic structural diagram of a structure with ultra-narrow pitch openings obtained by using a method for forming ultra-narrow pitch openings of a PI layer according to the present invention;

[0034] Figure 4 is a schematic structural diagram of a semiconductor packaging structure obtained by using the method for forming ultra-narrow pitch openings of a PI layer provided by the present invention. Detailed Embodiments

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] As Figure 3 and 4 shown, the embodiments of the present invention provide a method for forming ultra-narrow pitch openings of a PI layer, including:

[0038] S1. Provide a substrate 1, where the substrate 1 includes a passivation layer 13 on the surface and a semiconductor device structure under the passivation layer 13. The semiconductor device structure at least includes a top metal layer 12 adjacent to the passivation layer 13 and a substrate 11 under the top metal layer 12. In this embodiment, the top metal layer 12 is a chip bonding pad. In practical applications, the semiconductor device may have a more complex metal layer structure.

[0039] Next, the space for growing the redistribution layer needs two photolithography processes:

[0040] S2. Photolithography process of the ultra-thin PI layer: Coating glue on the substrate 1, using the spin coating method, through ultra-high rotation speed, the rotation speed needs to be greater than 5000 rpm / min, to form the ultra-thin PI layer, that is, the first ultra-thin PI layer 2; through low-energy exposure, the exposure energy is 50% - 80% of the exposure energy of the conventional PI layer, transfer the pattern of the mask to the upper part of the first ultra-thin PI layer 2, dissolve and remove the photoresist in the unexposed area through development, exposing the ultra-narrow PI opening, that is, forming the first opening 21, and the development time is 50% - 80% of the development time of the conventional PI layer; through curing, evaporate the solvent in the photoresist to form the first ultra-thin PI layer 2 with a glue thickness less than or equal to 3μm, and the opening width a dimension of the first opening 21 is less than or equal to 5μm. Here, it is introduced that in the prior art, the conventional exposure energy of the conventional PI layer is 300 - 600 mg / cm 2 , and the conventional development time is 50 - 100 s.

[0041] S3. Photolithography process of the PI dielectric layer: Coating glue on the ultra-thin PI layer (that is, the first ultra-thin PI layer 2), also using the spin coating method, through the normal rotation speed of 1000 - 3000 rpm / min, to form the dielectric layer of PI material, that is, the first dielectric layer 3, and the thickness of this PI dielectric layer is slightly thinner than that of the conventional PI layer; through conventional exposure, development, and curing, the formed first dielectric layer 3 has a glue thickness of 5 - 10μm, and forms the second opening 31 with an opening width b dimension greater than 8μm, and the second opening 31 is located above the first opening 21, and the first opening 21 and the second opening 31 form the space for making the redistribution layer. The combined thickness of the ultra-thin PI layer and the PI dielectric layer can be equal to the thickness of the required conventional PI layer, so that the thickness of the original conventional PI layer will not be changed.

[0042] Due to the complex structure of the semiconductor package, in some embodiments, there can be multiple layers of redistribution layers (RDL), and each layer of the redistribution layer will be patterned to form multiple RDL segments (not shown in the figure). When making the space for growing each layer of the redistribution layer, the double-layer PI layer structure combined with the above-mentioned ultra-thin PI layer and PI dielectric layer is used, and the above-mentioned opening method is adopted at the growth position of each RDL segment to form the upper and lower two openings required for its growth, and the structure with an ultra-narrow lower opening width.

[0043] After forming and fabricating the first redistribution layer 601 at the opening one 21 and the opening two 31, the second ultra-thin PI layer 4 is fabricated on the first dielectric layer 3. The process method of the second ultra-thin PI layer 4 is the same as that of the above-mentioned first ultra-thin PI layer 2. Through low-energy exposure, development, and curing, the second ultra-thin PI layer 4 with an opening three 41 is formed. The thickness of the glue of the second ultra-thin PI layer 4 is less than or equal to 3μm, and the opening width dimension of the opening three 41 is less than or equal to 5μm. Then, the second dielectric layer 5 is fabricated on the second ultra-thin PI layer 4, and the second dielectric layer 5 is a PI layer. The process method of the second dielectric layer 5 is the same as that of the above-mentioned first dielectric layer 3. Through exposure, development, and curing, the second dielectric layer 5 with an opening four 51 is formed. The thickness of the glue of the second dielectric layer 5 is 5 - 10μm, the opening width dimension of the opening four 51 is greater than 8μm, and the opening four 51 is located above the opening three 41. The opening three 41 and the opening four 51 form a space for fabricating the second redistribution layer 603. By adopting the process method provided by the present invention, the surface of the second dielectric layer 5 can be made flat.

[0044] As Figure 3 and 4 shown, another aspect of the embodiment of the present invention provides a semiconductor package structure fabricated by using the above-mentioned ultra-narrow pitch PI layer opening method, including:

[0045] A substrate 1, the substrate 1 includes a passivation layer 13 on the surface and a semiconductor device structure under the passivation layer 13. The semiconductor device structure at least includes a top metal layer 12 adjacent to the passivation layer 13 and a substrate 11 under the top metal layer 12;

[0046] The first ultra-thin PI layer 2 disposed on the passivation layer 13, and the first ultra-thin PI layer 2 is provided with an opening one 21 with an opening width dimension less than or equal to 5μm;

[0047] The first dielectric layer 3 disposed on the first ultra-thin PI layer 2, and the first dielectric layer 3 is provided with an opening two 31 with an opening width dimension greater than 8μm. The opening two 31 is located above the opening one 21, forming a space for fabricating the redistribution layer 601;

[0048] The redistribution layer 601, the lower part of the redistribution layer 601 is filled in the space formed by the opening one 21 and the opening two 31, and the bottom of the redistribution layer 601 has a seed layer 602. The redistribution layer 601 will be patterned to form multiple RDL segments. At each position of the RDL segment, the ultra-thin PI layer and the IP dielectric layer both form upper and lower two-layer openings such as the opening one 21 and the opening two 31, and the lower opening has an ultra-narrow structure.

[0049] In practical applications, the semiconductor package structure is complex and there may be multiple redistribution layers. After the first redistribution layer 601 is formed, the second ultra-thin PI layer 4 can be covered on the first dielectric layer 3 by the process method of the above-mentioned first ultra-thin PI layer 2. The second ultra-thin PI layer 4 is provided with an opening three 41 whose opening width dimension is less than or equal to 5 μm. The second dielectric layer 5 is fabricated on the second ultra-thin PI layer 4 by the process method of the above-mentioned first dielectric layer 3. The second dielectric layer 5 is provided with an opening four 51 whose opening width dimension is greater than 8 μm. The opening four 51 is located above the opening three 41 to form a space for fabricating the second redistribution layer 603. The opening three 41 and the opening four 51 are filled with the redistribution layer 603, and the bottom of the redistribution layer 603 has a seed layer 604.

[0050] The adhesive thicknesses of both the first ultra-thin PI layer 2 and the second ultra-thin PI layer 4 are less than or equal to 3 μm, and the adhesive thicknesses of the first dielectric layer 3 and the second dielectric layer 5 are 5 - 10 μm. The adhesive thicknesses of the first dielectric layer 3 and the second dielectric layer 5 are slightly thinner than those of the conventional PI layer. In this embodiment, the top of the redistribution layer is provided with a downward concave recess, so that the adhesion between the redistribution layer and the ultra-thin PI layer can be increased.

[0051] The ultra-narrow pitch PI layer opening method and the semiconductor package structure provided by the present invention break the structure of the conventional PI layer, change the conventional PI layer into a combination of an ultra-thin PI layer and a PI dielectric layer, and the combined thickness of the improved PI dielectric layer and the ultra-thin PI layer can be equal to the original conventional PI layer. In this way, without changing the thickness of the original conventional PI layer, it can provide a growth space for the redistribution layer with an ultra-narrow opening width, solve the problem of ultra-narrow pitch PI opening, and reduce the width dimension of the bottom of the redistribution layer. Through the combination of the bottom ultra-thin PI layer and the PI dielectric layer as an insulating and protective layer, the two PI layers can also better provide circuit connection and mechanical properties, achieving a better electromagnetic shielding effect. And due to the formation of the ultra-narrow opening, the width dimension of the bottom of the formed redistribution layer becomes smaller, which can also increase the distance between adjacent redistribution layers, effectively increasing the path length of electron migration between adjacent redistribution layers. In the case of multiple redistribution layers (RDL), through the PI dielectric layer on the ultra-thin PI layer, the surface flatness can be improved, and the problem of large surface undulation of the conventional PI layer can be improved. In addition, the top of the redistribution layer has a recess, which can increase the adhesion between the redistribution layer and the ultra-thin PI layer, improving the yield of the semiconductor package.

[0052] The above are only some embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the creative concept of the present invention, other deformations and improvements can be made, and these all belong to the protection scope of the present invention.

Claims

1. A method for opening the PI layer with ultra-narrow pitch, characterized in that: Provide a substrate, the substrate includes a passivation layer on the surface and a semiconductor device structure under the passivation layer, and the semiconductor device structure at least includes a top metal layer adjacent to the passivation layer and a substrate under the top metal layer; Coat a first ultra-thin PI layer on the substrate, perform low-energy exposure on the first ultra-thin PI layer, dissolve and remove the photoresist in the unexposed area through development, form an ultra-narrow opening one, and perform curing to form a first ultra-thin PI layer with a glue thickness less than or equal to 3μm, and the opening width dimension of the opening one is less than or equal to 5μm; Coat a first dielectric layer on the first ultra-thin PI layer, the first dielectric layer is a PI layer, perform exposure, development, and curing on the first dielectric layer to form a first dielectric layer with a glue thickness of 5-10μm, and form an opening two with an opening width dimension greater than 8μm, and the opening two is located above the opening one; The opening one and the opening two form a space for manufacturing the redistribution layer; the lower part of the manufactured redistribution layer is filled in the space formed by the opening one and the opening two, the top of the redistribution layer is provided with a downward concave portion, and the bottom of the redistribution layer has a seed layer.

2. The ultra-narrow pitch PI layer opening method according to claim 1, characterized in that The first ultra-thin PI layer and the first dielectric layer are both manufactured by the spin coating method.

3. The ultra-narrow pitch PI layer opening method according to claim 2, wherein When manufacturing the first ultra-thin PI layer, an ultra-high rotation speed is adopted, and the rotation speed is greater than 5000rpm / min.

4. The ultra-narrow pitch PI layer opening method according to claim 3, characterized in that, After the opening one and the opening two are formed and the first layer of redistribution layer is manufactured, a second ultra-thin PI layer is manufactured on the first dielectric layer, and through low-energy exposure, development, and curing, a second ultra-thin PI layer with an opening three is formed, the glue thickness of the second ultra-thin PI layer is less than or equal to 3μm, and the opening width dimension of the opening three is less than or equal to 5μm; Manufacture a second dielectric layer on the second ultra-thin PI layer, the second dielectric layer is a PI layer, the second dielectric layer is formed with an opening four through exposure, development, and curing, the glue thickness of the second dielectric layer is 5-10μm, the opening width dimension of the opening four is greater than 8μm, and the opening four is located above the opening three; The opening three and the opening four form a space for manufacturing the second layer of redistribution layer, and the surface of the second dielectric layer is flat.

5. A semiconductor package structure fabricated by using the ultra-narrow pitch PI layer opening method according to any one of claims 1 to 4, characterized in that, Including: A substrate, the substrate includes a passivation layer on the surface and a semiconductor device structure under the passivation layer, and the semiconductor device structure at least includes a top metal layer adjacent to the passivation layer and a substrate under the top metal layer; A first ultra-thin PI layer provided on the passivation layer, the glue thickness of the first ultra-thin PI layer is less than or equal to 3μm, and the first ultra-thin PI layer is provided with an opening one with an opening width dimension less than or equal to 5μm; A first dielectric layer provided on the first ultra-thin PI layer, the glue thickness of the first dielectric layer is 5-10μm, the first dielectric layer is provided with an opening two with an opening width dimension greater than 8μm, and the opening two is located above the opening one, forming a space for manufacturing the redistribution layer; A redistribution layer, the lower part of the redistribution layer is filled in the space formed by the first opening and the second opening, the bottom of the redistribution layer has a seed layer, and the top of the redistribution layer is provided with a downwardly concave recess.

6. The semiconductor package structure according to claim 5, wherein, The redistribution layer and the first dielectric layer are covered with a second ultra-thin PI layer, the thickness of the glue of the second ultra-thin PI layer is less than or equal to 3 μm, and the second ultra-thin PI layer is provided with a third opening with an opening width dimension less than or equal to 5 μm; A second dielectric layer is provided on the second ultra-thin PI layer, the thickness of the glue of the second dielectric layer is 5-10 μm, the second dielectric layer is provided with a fourth opening with an opening width dimension greater than 8 μm, and the fourth opening is located above the third opening to form a space for manufacturing the redistribution layer; The third opening and the fourth opening are filled with a redistribution layer, the bottom of the redistribution layer has a seed layer, and the top of the redistribution layer is provided with a downwardly concave recess.

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