Communication interface structure between processing die and memory die

Abstract

The present invention provides a communication interface structure for connecting a processing die and a memory die, comprising a memory die, a processing die, and an interconnection router. The memory die comprises a first interface edge, wherein the first interface edge is divided into a plurality of interface groups. Each of the processing dies comprises a second interface edge. The interconnection router connects the second interface edge of the processing die to the interface groups of the memory die.

Description

Technical Field

[0001] The present invention relates to an interface between two integrated circuit (IC) dies for data communication, and more particularly, to a communication interface structure and method between a processing die and a memory die. Background Art

[0002] Digital electronic devices based on semiconductor integrated circuits (e.g., mobile phones, digital cameras, personal digital assistants (PDAs), etc.) are designed to have increasingly powerful functionality to accommodate the diverse applications of the modern digital world. However, as a trend in semiconductor manufacturing, digital electronic devices are expected to become smaller and lighter while offering improved functionality and higher performance. Semiconductor devices can be packaged into 2.5D semiconductor devices, in which multiple circuit chips are integrated into a larger integrated circuit, with contact elements, interposers, or RDL layers used to connect between the chips.

[0003] Integrated Fan-Out (InFO) and chip-on-wafer-on-substrate (CoWoS) packaging technologies have been proposed to package multiple chips assembled side by side.

[0004] Regarding the entire electronic circuit, a main circuit manufactured as a main die in an example may need to be connected to multiple slave dies as an example. The main die may be a processing die such as an application specific integrated circuit (ASIC) die, and the slave die may be a memory die such as a high bandwidth memory (HBM). In operation, the HBM die can be shared by multiple ASIC dies. Based on 2.5D packaging technology, the ASIC die and the HBM die are connected through an interposer or a redistribution layer (RDL). In other words, the interfaces in the ASIC die and the HBM die respectively include contact elements such as bonding pads or through-holes. The contact elements are then connected through an interposer or RDL.

[0005] The HBM die typically has a relatively large number of communication channels that can be accessed by the ASIC die. Each of the various ASIC dies may have different functionality and may only need access to portions of the HBM die rather than the entire HBM die.

[0006] In order to enable the HBM die to communicate with various ASIC dies more efficiently, the communication interface structure of the interface between the memory die and the processing die needs to be properly designed. Summary of the Invention

[0007] The present invention provides a communication interface for connecting between tube cores so as to be packaged and connected through an interposer or RDL. For example, the interface edge of the memory tube core of the HBM tube core is split into 2 or 2 n The ASIC die can have the same functionality or different functionality. In addition, the ASIC die can have different manufacturing qualities.

[0008] In one embodiment, the present invention provides a communication interface structure for connecting dies, comprising a memory die, a processing die, and an interconnection router. The memory die comprises a first interface edge, wherein the first interface edge is divided into a plurality of interface groups. Each of the processing dies comprises a second interface edge. The interconnection router connects the second interface edge of the processing die to the interface groups of the memory die.

[0009] In one embodiment, the present invention provides a communication interface structure for connecting dies. The communication interface structure includes a first memory die having a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Additionally, the communication interface structure includes at least one second memory die having a second interface edge. Furthermore, the communication interface structure includes a plurality of processing dies, wherein each of the processing dies includes a third interface edge and at least one fourth interface edge. A plurality of interconnect routes are connected between the processing dies and the first memory die and the second memory die. The interconnect routes connect each of the interface groups of the first memory die to the third interface edge of one of the processing dies, wherein the interconnect routes also connect the second interface edge of the second memory die to the fourth interface edge of one of the processing dies.

[0010] In order to make the foregoing content more understandable, several embodiments are described in detail below with accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 is a diagram schematically illustrating a cross-sectional stacking structure of a 2.5D semiconductor device having an interface according to an embodiment of the present invention;

[0013] Figure 2 is a diagram schematically illustrating a routing structure between dies as viewed according to an embodiment of the present invention;

[0014] Figure 3 is a diagram schematically illustrating a routing structure between dies as viewed according to an embodiment of the present invention;

[0015] Figure 4 FIG. 1 is a diagram schematically illustrating a routing structure between dies according to an embodiment of the present invention.

[0016] Explanation of Figure Numbers

[0017] 50: platform;

[0018] 100: substrate;

[0019] 102: through hole;

[0020] 104: bottom solder ball;

[0021] 106, 116: contact elements;

[0022] 110: conductor layer;

[0023] 112: silicon via;

[0024] 114, 170: interconnection routing;

[0025] 120, 150, 150a, 150b, 150c, 150d, 150e: memory die;

[0026] 130, 180a, 180b: processing die;

[0027] 140: routing structure;

[0028] 152, 162a, 162b, 182a_1, 182a_2, 182a_3, 182a_4, 182a_5, 182b_1, 182b_2, 182b_3, 182b_4, 182b_5: interface edge;

[0029] 152': second interface edge;

[0030] 152a, 152b: interface group;

[0031] 160a, 160b: ASIC die. DETAILED DESCRIPTION

[0032] The present invention is directed to an interface between two integrated circuit (IC) dies for data communication, wherein a communication interface structure is configured between a processing die, such as an ASIC die, and a memory die, such as an HBM die. The HBM die has a high bandwidth and, in an embodiment, includes 1024 communication channels or even more. The contact elements of the interface of the HBM die can be configured as contact patterns into a plurality of groups that communicate with the ASIC die respectively. In an embodiment, the number of groups can be 2, 4, 8, ..., 2 n , n is an integer.

[0033] Depending on the packaging process used, the contact elements of the two dies are connected correspondingly via a connection interface such as an interposer or a redistribution layer (RDL). The routing structure is embedded in the interposer or RDL layer. In an example, the contact elements can be contact pads or bump pads.

[0034] Several embodiments are provided for describing the present invention, but the present invention is not limited to the embodiments.

[0035] The entire integrated circuit can be manufactured as a semiconductor device through a semiconductor manufacturing process, and the semiconductor device can be manufactured based on the stacked structure of a 2.5D semiconductor device. In an embodiment, the interface of the die for receiving data may include a frame decoding circuit associated with a deserialization circuit. In an embodiment, the interface in the semiconductor structure is integrated into the circuit of the entire die. In an embodiment, the die in communication may be a main die of a processing circuit and a slave die of a memory die. In other words, the type of die is not limited to a specific type. However, the die communicates with a routing structure including multiple routing paths through an interface.

[0036] First, general semiconductor manufacturing is described. Figure 1 FIG2 is a diagram schematically showing a cross-sectional stacking structure of a 2.5D semiconductor device with an interface according to an embodiment of the present invention. Figure 1In another application, a CoWoS or InFO platform 50 having a desired IC structure is formed based on 2.5D packaging technology. The CoWoS or InFO platform 50 may include a package substrate 100 having a bottom solder ball 104 and a top contact element 106. A through-hole 102 may be used to connect from the bottom solder ball 104 to the top contact element 106. In addition, a wire layer 110 such as an interposer or RDL may be further formed on the substrate 100 using the connection of the contact element 106. The wire layer 110 is embedded with a routing structure 140, wherein the routing structure 140 has a routing path for connection purposes. The wire layer 110 may also include a through silicon via (TSV) 112, an interconnect routing 114, and a contact element 116. Here, depending on the manufacturing process used, the contact element 116 may be a through hole or a contact element or any suitable connection structure for terminal-to-terminal contact. The present invention does not limit the contact elements 106, 116 to a specific type.

[0037] In practical applications, the CoWoS or InFO platform 50 may also be implemented with additional dies such as a processing die 130 and a memory die 120 or other types of dies, without limitation. The processing die 130 and the memory die 120 are connected via a routing structure 140 embedded in the conductive layer 110 .

[0038] Figure 2 FIG is a diagram schematically illustrating a routing structure between dies as viewed according to an embodiment of the present invention. Figure 2 In an embodiment, the memory die 150 and the processing die such as the ASIC die 160a and the ASIC die 160b are connected via an interconnect routing 170. The memory die 150 can be shared by multiple ASIC dies 160a and ASIC dies 160b of smaller interface size. The memory die 150 generally includes an interface as a physical layer (PHY). The contact elements of the interface form an interface edge 152, wherein each contact element corresponds to a communication channel, and the communication channel is represented by a DQ. In the example, the number of contact elements is 1024, but the present invention is not limited to this number. In the example, 1024 channels can be used, or 512 channels can be used. In the example, the memory die 150 can be an HBM die with a specific large number of communication channels.

[0039] In an embodiment, the interface edge 152 of the memory die can be divided into a plurality of interface groups 152a and 152b, and the number of the interface groups is 2, 4, 8, ..., 2. n, where n is a positive integer. As mentioned above, two interface groups 152a and 152b are used as an example. Here, interface groups 152a and 152b are equally divided in the communication channel. In an embodiment, two ASIC dies 160a and 160b are respectively connected to interface groups 152a and 152b of the same memory die 150. In addition, as described above, the number of ASIC dies 160a and 160b is not limited to two.

[0040] Taking a total of 1024 channels as an example, ASIC die 160a and ASIC die 160b have interface edge 162a and interface edge 162b of 512 channels (DQ), which is half of the 1024 channels in the example.

[0041] In one embodiment, two ASIC dies 160a and 160b are connected to interface groups 152a and 152b, respectively, of memory die 150 via interconnect routing 170. In this scenario, ASIC dies 160a and 160b may have identical functionality and are formed as a single, larger ASIC die to communicate with memory die 150. From a packaging perspective, the two ASIC dies 160a and 160b have more freedom in position relative to memory die 150. During manufacturing, ASIC dies 160a and 160b with fewer channels have relatively lower manufacturing costs. In other words, device components do not require high-precision control of the compressed circuit elements during manufacturing. In this example, larger photomasks are more expensive than smaller photomasks.

[0042] In one embodiment, the two ASIC dies 160a and 160b may have different functionalities or different manufacturing qualities. In this scenario, one of the ASIC dies 160a and 160b may be a relatively simple ASIC die. During manufacturing, this relatively simple ASIC die can be manufactured under relaxed manufacturing control conditions, resulting in lower costs.

[0043] In other words, the design methodology of memory die 150 can be retained. However, depending on the number of interface groups 152a and 152b into which memory die 150 is split, ASIC dies 160a and 160b can have more flexible conditions in terms of manufacturing and packaging. In this example, the minimum number of channels in the split interface groups is 256.

[0044] based on Figure 2 The same aspects and mechanisms in

[0045] can be further applied to other arrangements. Figure 3In the embodiment, multiple memory tube cores 150a, 150b, 150c, 150d, and 150e are involved. Among them, the memory tube core 150c can be regarded as Figure 2 The memory die 150 depicted in FIG has two separate interface groups at its interface edge 152 for connecting to the two processing dies 180a and 180b, respectively. The other memory dies 150a, 150b, 150d, and 150e can be considered common memory dies, each correspondingly connected to the interface edges of the same processing die 180a and 180b.

[0045] In one embodiment, a processing die 180a may include multiple interface edges 182a_1, 182a_2, 182a_3, 182a_4, and 182a_5, each of which is implemented in a physical layer (PHY) and has 512 DQ channels. Taking a memory die 150c having 1024 DQ channels as an example, the 512 DQ channels on the interface edge represent half of the channels on memory die 150c. Similarly, a processing die 180b may include multiple interface edges 182b_1, 182b_2, 182b_3, 182b_4, and 182b_5, each of which has 512 DQ channels. As an example, the 512 DQ channels on these interface edges represent half of the 1024 DQ channels. However, as previously described, depending on the configuration of the memory die 150c in an actual application, the number of processing dies 180a and 180b associated with the interface edge 182a_5 and the interface edge 182b_1 may be 2. n , where n is a positive integer.

[0046] Interface edges 182a_1, 182a_2, 182a_3, and 182a_4 of processing die 180a can be connected to the interface groups of memory die 150a and memory die 150b via interconnect routing 170. For processing die 180b, interface edges 182b_2, 182b_3, 182b_4, and 182b_5 of processing die 180b can be connected to the interface groups of memory die 150d and memory die 150e via interconnect routing 170.

[0047] However, the channel sizes of interface edges 182a_1, 182a_2, 182a_3, and 182a_4 of the processing die 180a and the channel sizes of interface edges 182b_2, 182b_3, 182b_4, and 182b_5 of the processing die 180b may not necessarily be split into 512DQ.

[0048] Figure 4 FIG is a diagram schematically showing a routing structure between dies according to an embodiment of the present invention. Figure 4 , with the exception of memory die 150c, which is split and connected to both processing dies 180a and 180b, the interface edges of memory dies 150a, 150b, 150d, and 150e are not split. On the sides of processing dies 180a and 180b, interface edges 182a_1 and 182a_2 of processing die 180a and interface edges 182b_2 and 182b_3 of processing die 180b retain a full 1024 DQ channels. However, based on the mechanism described above, memory die 150c is connected to both processing dies 180a and 180b.

[0049] As mentioned again, the present invention is limited to splitting and connecting the memory die 150c to two processing dies 180a, 180b. Figure 2 As described in , the memory die 150c can be split into more interface groups. The processing die 180a, 180b can have more functionality and additional interface edges can be connected to the memory die 150c. Figure 3 The interface edge 182a_5 and the interface edge 182b_1 or Figure 4 The interface edge 182a_3 and the interface edge 182b_1 in are implemented together.

[0050] Generally speaking, in one embodiment, the present invention provides a communication interface structure for inter-die connections, including a memory die 150, a processing die 160a, a processing die 160b, and an interconnect routing 170. Memory die 150 includes a first interface edge 152 divided into a plurality of interface groups, such as two interface groups 152a and 152b. Each of processing die 160a and processing die 160b includes a second interface edge 162a and a second interface edge 162b. Interconnect routing 170 connects the second interface edge 162a and the second interface edge 162b of processing die 160a and processing die 160b, respectively, to the interface groups 152a and 152b of memory die 150.

[0051] In an embodiment, the present invention further provides a communication interface structure for connecting dies. The communication interface structure includes a first memory die 150c, wherein the first memory die 150c includes an interface edge 152 that can be referred to as a first interface edge, and the first interface edge is divided into a plurality of interface groups 152a, 152b. In addition, it includes at least one second memory die 150a, a second memory die 150b, a second memory die 150d, and a second memory die 150e, which have an interface edge that can be referred to as a second interface edge 152'. It also includes a plurality of processing dies 182a, 182b, wherein each of the processing dies 182a, 182b includes a third interface edge 182a_5, a third interface edge 182b_1 (see Figure 3 ) and at least one fourth interface edge 182a_1, fourth interface edge 182a_2, fourth interface edge 182a_3, fourth interface edge 182a_4, fourth interface edge 182b_2, fourth interface edge 182b_3, fourth interface edge 182b_4, and fourth interface edge 182b_5. A plurality of interconnect routes 170 connect the processing dies 180a and 180b with the first memory die 150c and the second memory dies 150a, 150b, 150d, and 150e. Interconnect routes 170 connect each of the interface groups 152a and 152b of the first memory die 150c to a third interface edge 182a_5 or third interface edge 182b_1 of one of the processing dies 180a and 180b. The interconnect routing 170 also connects an interface edge, referred to as a second interface edge 152' of the second memory die 150a, the second memory die 150b, the second memory die 150d, the second memory die 150e, to a fourth interface edge 182a_1, interface edge 182a_2, interface edge 182a_3, interface edge 182a_4, interface edge 182b_2, edge 182b_3, interface edge 182b_4, interface edge 182b_5 of one of the processing dies 180a, 180b.

[0052] In an embodiment, with respect to the communication interface structure, the first interface edge is split into two interface groups and the number of processing dies connected to the two interface groups through the interconnect routing is two.

[0053] In an embodiment, regarding the communication interface structure, each of the interface groups or each of the second interface edges has half the number of communication channels of the total communication channels of the first interface edge.

[0054] In an embodiment, regarding the communication interface structure, the number of interface groups is an even number.

[0055] In the embodiment, regarding the communication interface structure, the number of interface groups is 2 n , where n is a positive integer.

[0056] In an embodiment, the processing dies are manufactured with the same functionality and the same quality with respect to the communication interface structure.

[0057] In an embodiment, with respect to the communication interface structure, the processing die includes at least one processing die having different functionality than another processing die.

[0058] In an embodiment, with respect to the communication interface structure, the processing die includes at least one processing die having a different manufacturing quality than another processing die.

[0059] In an embodiment, with respect to the communication interface structure, the first interface edge includes 1024 communication channels or a multiple of 1024 communication channels.

[0060] In an embodiment, with respect to the communication interface structure, the first interface edge and the second interface edge comprise contact elements arranged in a contact pattern, said contact elements being connected by a corresponding one of the interconnect routes.

[0061] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure encompasses modifications and variations provided that the modifications and variations fall within the scope of the above claims and their equivalents.

Claims

1. A communication interface structure for connecting dies, comprising: a first memory die comprising a first interface edge, wherein the first interface edge is split into a plurality of interface groups; at least one second memory die comprising a second interface edge, wherein the second interface edge has a greater number of communication channels than each of the plurality of interface groups; as well as a plurality of processing dies, each of the plurality of processing dies comprising a third interface edge and at least one fourth interface edge, wherein each of the fourth interface edges has a greater number of communication channels than the third interface edge, The third interface edge of each of the plurality of processing dies is respectively connected to each of the plurality of interface groups of the first memory die via a first interconnect routing, and each of the at least one fourth interface edge of each of the plurality of processing dies is respectively connected to the second interface edge of each of the at least one second memory die via a second interconnect routing. 2 . The communication interface structure according to claim 1 , wherein the first interface edge is split into two interface groups and the number of the processing dies connected to the two interface groups through the first interconnect routing is two. 3 . The communication interface structure of claim 2 , wherein each of the interface groups has half the number of communication channels of the total communication channels of the first interface edge.

4. The communication interface structure of claim 1, wherein the second interface edge of the second memory die is further split into a plurality of interface groups for connecting to the fourth interface edge of the processing die.

5. The communication interface structure of claim 1, wherein the second interface edge of the second memory die is not split into a plurality of groups. The communication interface structure according to claim 1 , wherein the processing dies have the same function and the same quality when manufactured.

7. The communication interface structure of claim 1, wherein the processing die comprises at least one processing die having different functionality from another processing die.

8. The communication interface structure of claim 1, wherein the processing die comprises at least one processing die having a different manufacturing quality than another processing die.

9. The communication interface structure of claim 1, wherein the first interface edge comprises 1024 communication channels or a multiple of 1024 communication channels.

10. The communication interface structure of claim 1, wherein the first interface edge and the second interface edge comprise contact elements arranged in a contact pattern, the contact elements being connected by a corresponding one of the interconnect routes.

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