A method of manufacturing a semiconductor device and a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and semiconductor device. The method comprises the following steps: forming a buffer structure on a part of the spacer material layer above the protruding structure pattern, the buffer structure covering each protruding structure; etching the buffer structure and the spacer material layer, and separating the spacer material layer between two adjacent protruding structures to form a spacer structure covering each protruding structure and the upper surface. The buffer structure can protect the protruding structure from being damaged due to over-etching of the spacer material layer, because the step of setting the buffer structure is added. The spacer structure covers not only the two sidewalls of the protruding structure pattern, but also the upper surface of the protruding structure, so that the protection effect of the spacer structure on the bit line pattern or the gate pattern is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0002] In semiconductor manufacturing, one step requires forming two sidewalls on the two sidewalls of a bit line, followed by fabricating a memory node contact hole pattern on the substrate between the bit lines. Current technology requires plasma etching to fabricate the sidewalls and process the memory node contact hole pattern in the substrate. During plasma etching, over-etching can damage the bit lines, leading to defects such as poor contact. Summary of the Invention

[0003] This invention provides a semiconductor device manufacturing method and a semiconductor device. When etching to form a spacer structure, it prevents etching damage to raised structure patterns such as bit lines and gates. At the same time, the spacer structure not only covers the two sidewalls of the raised structure pattern, but also covers the upper surface of the raised structure, thereby improving the protective effect of the spacer structure on the bit line pattern or gate pattern.

[0004] In a first aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming a raised structure pattern on the substrate, the raised structure pattern including a plurality of spaced-apart raised structures; depositing a spacer material layer on the upper surface of the substrate, the upper surface of the raised structure pattern, and the sidewalls; forming a buffer structure covering each raised structure on the spacer material layer located above the raised structure pattern; etching the buffer structure and the spacer material layer on the substrate between two adjacent raised structures to form a spacer structure covering only the sidewalls and upper surface of each raised structure, and a residual buffer structure covering at least the upper surface of each spacer structure; and removing the residual buffer structure.

[0005] In the above-described scheme, a buffer structure is first formed on the spacer material layer on top of the raised structure pattern, covering each raised structure. Then, the buffer structure and the spacer material layer are etched to separate the spacer material layers between adjacent raised structures, forming a spacer structure that only covers each raised structure and its upper surface. Compared to the prior art method of directly etching the spacer material layer using plasma etching after deposition, the scheme of this application, by adding the step of setting the buffer structure, protects the raised structure during the subsequent etching of the spacer material layer to form the spacer structure. This prevents damage to the raised structure due to over-etching of the spacer material layer and avoids defects such as poor contact in the raised structure. Furthermore, the spacer structure covers not only the two sidewalls of the raised structure pattern but also the upper surface of the raised structure, improving the protection effect of the spacer structure on the bit line pattern or gate pattern.

[0006] In one specific implementation, the buffer structure is made of any one of tungsten, titanium nitride, or aluminum, so that the buffer structure can be etched away after the spacer structure is formed.

[0007] In one specific embodiment, forming a buffer structure covering each protrusion on the spacer material layer above the protrusion pattern involves forming the buffer structure covering the upper surface of each protrusion on the spacer material layer above the protrusion pattern using physical vapor deposition. This facilitates the formation of a buffer structure covering the position above the protrusion pattern.

[0008] In one specific embodiment, the buffer structure includes a top cover covering the upper surface of each protrusion and two side edges connected to the top cover and located opposite each protrusion, so as to improve the protective effect of the buffer structure on the protrusion.

[0009] In one specific implementation, the edge does not completely cover the sidewall of the protrusion, so that the edge does not affect the subsequent etching and separation of the spacer material layer, while improving the protective effect of the buffer structure on the protrusion.

[0010] In one specific embodiment, there is a gap between the edges of the buffer structure on any two adjacent protrusions, so as to facilitate the etching and separation of the spacer material layer between the two adjacent protrusions to form a spacer structure.

[0011] In one specific implementation, the bump structure pattern is a bit line pattern or a gate pattern.

[0012] In one specific embodiment, the manufacturing method further includes: forming a recessed structural pattern in a substrate, wherein the recessed structural pattern is located between raised structural patterns.

[0013] In one specific embodiment, after etching a spacer material layer on the substrate between the buffer structure and two adjacent protrusions, forming a spacer structure that covers only the sidewalls and upper surface of each protrusion and a residual buffer structure that covers at least the upper surface of each spacer structure, the manufacturing method further includes: etching the substrate between the two adjacent protrusions to form the recessed structure pattern on the substrate. This allows the residual buffer structure to continue protecting the protrusion structure pattern during the etching process.

[0014] In one specific implementation, the raised structure pattern is a bit line pattern, and the recessed structure pattern is a storage node contact hole pattern.

[0015] In one specific embodiment, etching a buffer structure and a spacer material layer on a substrate between two adjacent protrusions to form a spacer structure covering only the sidewalls and upper surface of each protrusion, and a residual buffer structure covering at least the upper surface of each spacer structure includes: etching the buffer structure and the adjacent spacer material layer on the substrate using a plasma etching method or a wet etching method to form a spacer structure covering only the sidewalls and upper surface of each protrusion, and a residual buffer structure covering at least the upper surface of each spacer structure. This facilitates the etching of the spacer material layer and buffer structure between two adjacent protrusions, separating the spacer material layer to form the spacer structure.

[0016] In a second aspect, the present invention also provides a semiconductor device comprising a substrate and a cluster of protruding structures formed on the substrate, wherein the cluster of protruding structures comprises a plurality of spaced-apart protrusions. It further includes spacer structures forming sidewalls and a top surface covering each protrusion.

[0017] In the above solution, the spacer structure surrounding the protruding structure covers not only the sidewalls of the protruding structure but also its upper surface, thereby improving the protection and support of the protruding structure. Compared with the prior art, which only covers the sidewalls of the protruding structure, the spacer structure in this application also covers the upper surface of the protruding structure, thus forming a spacer structure with an inverted U-shaped cross-section, improving the protection and support of the protruding structure and preventing defects such as poor contact.

[0018] In one specific implementation, the raised structure pattern is a bit line pattern or a gate pattern to improve the protection effect of the spacer structure on the bit line pattern or gate pattern.

[0019] In one specific embodiment, a recessed structural pattern is also formed on the substrate, and the recessed structural pattern is located between the raised structural patterns.

[0020] In one specific implementation, the raised structure pattern is a bit line pattern, and the recessed structure pattern is a storage node contact hole pattern. Attached Figure Description

[0021] Figure 1a This is a structural schematic diagram of a step in the prior art for manufacturing bit line sidewalls and memory node contact hole patterns;

[0022] Figure 1b This is a structural schematic diagram of another step in the prior art for manufacturing bit line sidewalls and storage node contact hole patterns;

[0023] Figure 1c This is a structural schematic diagram of another step in the prior art for manufacturing bit line sidewalls and storage node contact hole patterns;

[0024] Figure 1d This is a structural schematic diagram of another step in the prior art for manufacturing bit line sidewalls and storage node contact hole patterns;

[0025] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of one step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention.

[0031] Figures 1a to 1d Figure labels in the diagram:

[0032] 1-Substrate 2-Substrate line 3-Spacer material layer 4-Spacer

[0033] Figures 3-7 Figure labels in the diagram:

[0034] 10-Base 20-Raised Structure 21-Metal Pattern

[0035] 22-Mask pattern; 30-Spacer material layer; 31-Spacer structure

[0036] 40-Buffer structure 41-Top cover 42-Edge

[0037] 43-Residual buffer structure 50-Depression structure Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] To facilitate understanding of the semiconductor device manufacturing method provided in this embodiment of the invention, the application scenario of the semiconductor device manufacturing method provided in this embodiment of the invention will be described first. This semiconductor device manufacturing method is applied to a raised structure pattern having bit line patterns, gate patterns, etc., and processes the spacing structure of the raised structure pattern. The semiconductor device manufacturing method will now be described in detail with reference to the accompanying drawings.

[0040] refer to Figures 2-6 The method for manufacturing a semiconductor device provided in this embodiment of the invention includes:

[0041] Step 10: Provide a substrate 10;

[0042] Step 20: Form a raised structure pattern on the substrate 10, the raised structure pattern including a plurality of spaced raised structures 20;

[0043] Step 30: Deposit spacer material layer 30 on the upper surface of the substrate 10, the upper surface of the raised structure pattern, and the sidewalls;

[0044] Step 40: Form a buffer structure 40 covering each protruding structure 20 on the spacer material layer 30 located above the protruding structure pattern;

[0045] Step 50: Etch the buffer structure 40 and the spacer material layer 30 located on the substrate 10 between the two adjacent protrusion structures 20 to form a spacer structure 31 that covers only the sidewalls and upper surface of each protrusion structure 20, and a residual buffer structure 43 that covers at least the upper surface of each spacer structure 31.

[0046] Step 60: Remove residual buffer structure 43.

[0047] In the above-described scheme, a buffer structure 40 is first formed on a portion of the spacer material layer 30 above the raised structure pattern, covering each raised structure 20. Then, the buffer structure 40 and the spacer material layer 30 are etched to separate the spacer material layer 30 between adjacent raised structures 20, forming a spacer structure 31 that covers only each raised structure 20 and its upper surface. Compared to the prior art method of directly etching the spacer material layer 30 using plasma etching after deposition, the scheme of this application, by adding the step of setting the buffer structure 40, protects the raised structure 20 during the subsequent etching of the spacer material layer 30 to form the spacer structure 31. This prevents damage to the raised structure 20 due to over-etching of the spacer material layer 30 and prevents defects such as poor contact in the raised structure 20. Furthermore, the spacer structure 31 covers not only the two sidewalls of the raised structure pattern but also the upper surface of the raised structure 20, improving the protection effect of the spacer structure 31 on the bit line pattern or gate pattern. The following section provides a detailed explanation of each of the above steps in conjunction with the accompanying drawings.

[0048] First, refer to Figure 3 A substrate 10 is provided. The substrate 10 can be a structure comprising a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, etc. The substrate 10 can also be a stacked structure in which a partial semiconductor structure has already been formed.

[0049] Next, continue to refer to Figure 3 A raised structure pattern is formed on the substrate 10, comprising a plurality of spaced-apart raised structures 20. Specifically, the upper surface of each raised structure 20 in the raised structure pattern is higher than the upper surface of the substrate 10, thereby forming a step with a height difference between the substrate 10 and the raised structure 20. This raised structure pattern can specifically be a bit line pattern or a gate pattern. (Reference) Figure 3 Each raised structure 20 in the raised structure pattern may include a lower metal pattern 21 and a mask pattern 22 stacked on top of the metal pattern 21. Of course, the raised structure pattern may also be a raised structure pattern formed by a single material layer, or it may be a raised structure pattern formed by stacking more than two material layers.

[0050] Next, refer to Figure 4 A spacer material layer 30 is deposited on the upper surface of the substrate 10, the upper surface of the raised structure pattern, and the sidewalls. That is, the spacer material layer 30 covers the upper surface between two adjacent raised structures 20 on the substrate 10, and also covers the upper surface of each raised structure 20 and the two sidewalls of each raised structure 20.

[0051] Next, refer to Figure 5A buffer structure 40 is formed on the spacer material layer 30 above the raised structure pattern, covering each raised structure 20. That is, the buffer structure 40 is only disposed on a portion of the spacer material layer 30, and is not deposited on all parts of the spacer material layer 30. Furthermore, the buffer structure 40 only covers the portion of the spacer material layer 30 above the raised structure 20, so that in a vertical projection, the buffer structure 40 can completely cover each raised structure 20 below. This allows the buffer structure 40 to be etched first when the spacer material layer 30 between two raised structures 20 is subsequently etched to separate and form the spacer structure 31, preventing over-etching that could damage the lower raised structure 20, thus protecting the lower raised structure 20.

[0052] When determining the buffer structure 40, the material of the buffer structure 40 can be any one of tungsten, titanium nitride, and aluminum, so that the buffer structure 40 can be etched away after the spacer structure 31 is formed.

[0053] When forming a buffer structure 40 covering each protruding structure 20 on the spacer material layer 30 above the protruding structure pattern, a physical vapor deposition (PVD) method can be used to form the buffer structure 40 covering the upper surface of each protruding structure 20 on the spacer material layer 30 above the protruding structure pattern. Since the physical vapor deposition process has poor step coverage and poor conformability, the process can be controlled to ensure that the buffer structure 40 at least covers the area above the protruding structure pattern is formed.

[0054] When determining the shape of the buffer structure 40, refer to Figure 5 The buffer structure 40 may include a top cover 41 covering the upper surface of each protrusion 20, and edges 42 connected to the top cover 41 and located on opposite sides of each protrusion 20. That is, the buffer structure 40 not only includes the top cover 41 on the upper surface of each protrusion 20, but may also have edges 42 connected to the top cover 41 and hanging downwards in the vertical direction. This allows the top cover 41 and edges 42 to protect the protrusion 20 together, preventing etching damage to the protrusion 20 due to over-etching. The edges 42 may not completely cover the sidewalls of the protrusion 20, so that the edges 42 do not affect the subsequent etching and separation of the spacer material layer 30, while improving the protective effect of the buffer structure 40 on the protrusion 20 during etching. (Continue to refer to...) Figure 5 This allows for a gap between the edges 42 of the buffer structure 40 on any two adjacent protrusions 20, so as to facilitate etching and separating the spacer material layer 30 between the two adjacent protrusions 20 to form a spacer structure 31.

[0055] Next, refer to Figure 6The spacer material layer 30 located on the substrate 10 between the buffer structure 40 and the two adjacent protrusions 20 is etched to form a spacer structure 31 that covers only the sidewalls and upper surface of each protrusion 20, and a residual buffer structure 43 that covers at least the upper surface of the spacer structure 31. That is, by etching the spacer material layer 30 located on the substrate 10 between the two adjacent protrusions 20, the spacer material layer 30 between the two adjacent protrusions 20 is removed, forming a spacer structure 31 that covers only the sidewalls and upper surface of each protrusion 20. Because the buffer structure 40 is etched simultaneously with the spacer material layer 30, the protrusion pattern is not directly etched, thus protecting the protrusion pattern and preventing defects such as poor contact in the protrusions 20. In this step, since the buffer structure 40 is not completely removed, a residual buffer structure 43 is retained after etching, covering at least the upper surface of each spacer structure 31. This prevents the buffer structure 40 from being completely etched during the etching of the spacer material layer 30, thus preventing etching damage to the formed spacer structure 31. Specifically, the residual buffer structure 43 after etching in this step may only cover the upper surface of each spacer structure 31; or it may cover both the upper surface of each spacer structure 31 and part of the upper sidewall of each spacer structure 31.

[0056] When etching the spacer material layer 30 on the substrate 10 between the specific etched buffer structure 40 and the two adjacent protrusions 20, forming a spacer structure 31 covering only the sidewalls and upper surface of each protrusion 20, and a residual buffer structure 43 covering at least the upper surface of each spacer structure 31, a plasma etching method or a wet etching method can be used to etch the buffer structure 40 and the spacer material layer 30 on the substrate 10 between the two adjacent protrusions 20 to remove the spacer material layer 30 on the substrate 10 between the two adjacent protrusions 20, forming a spacer structure 31 covering only the sidewalls and upper surface of each protrusion 20, and a residual buffer structure 43 covering at least the upper surface of each spacer structure 31. This facilitates the etching of the spacer material layer 30 and the buffer structure 40 between the two adjacent protrusions 20, separating the spacer material layer 30 to form the spacer structure 31.

[0057] Next, the residual buffer structure 43 is removed, specifically by etching.

[0058] The existing technology for manufacturing sidewalls on both sides of the positioning line is as follows: Figures 1a to 1c As shown, first refer to Figure 1a A substrate 1 is provided, on which a bit line pattern is formed, the bit line pattern comprising a plurality of spaced bit lines 2. Next, refer to... Figure 1b A layer of insulating material is deposited on substrate 1 and the bit line pattern. Then refer to... Figure 1cThe isolation material layer 3 between two adjacent bit lines 2 is etched from top to bottom using a plasma etching process, thereby separating the isolation material layer 3 to form a layer as shown in the figure. Figure 1c The sidewall 4 shown is deformed due to the continuous influence of plasma etching on the upper part of the bit line pattern during the etching process, resulting in a shape resembling... Figure 1d The sidewall 4 of the bit line 2 shown is detached, resulting in defects such as poor contact of the bit line 2.

[0059] The solution in this application, by adding a step of setting a buffer structure 40, can protect the protrusion structure 20 during the subsequent etching of the spacer material layer 30 to separate it and form the spacer structure 31. This prevents over-etching of the spacer material layer 30 from damaging the protrusion structure 20 and avoids defects such as poor contact in the protrusion structure 20. Furthermore, the spacer structure 31 not only covers the two sidewalls of the protrusion structure pattern but also the upper surface of the protrusion structure 20, improving the protection effect of the spacer structure 31 on the bit line pattern or gate pattern.

[0060] Additionally, refer to Figure 6 and Figure 7 After forming a spacer material layer 30 on the substrate 10 between the etched buffer structure 40 and two adjacent protrusions 20, and after forming a spacer structure 31 covering only the sidewalls and upper surface of each protrusion 20, and a residual buffer structure 43 covering at least the upper surface of each spacer structure 31, the manufacturing method may further include forming a recessed structure pattern in the substrate 10, wherein the recessed structure pattern is located between the protrusion structure patterns. (Reference) Figure 7 The recessed structure pattern includes multiple recessed structures 50 distributed in the active region of the substrate 10. Since this requires not only etching the spacer material layer 30 to separate it and form the spacer structure 31, but also etching to form the recessed structure pattern, the etching process needs at least two steps and is relatively long. The thickness of the buffer structure 40 can be adjusted so that each etching operation only removes a portion of the buffer structure 40. This prevents subsequent etching processes from directly etching the raised structure pattern after the buffer structure 40 has been removed in the initial etching process, thus reducing the protective effect on the raised structure pattern. (Reference) Figure 6 and Figure 7 That is, after first etching the buffer structure 40 and the spacer material layer 30, a residual buffer structure 43 is formed that at least covers the upper surface of the spacer structure 31; then the substrate 10 located between the two protruding structures 20 is etched to form a recessed structure pattern on the substrate 10. Specifically, refer to Figure 6When etching the spacer material layer 30 on the substrate 10 between the buffer structure 40 and the two adjacent protrusions 20, the buffer structure 40 is etched until only the residual buffer structure 43 located on the upper surface of each spacer structure 31 is retained. That is, in this etching step, the buffer structure 40 is not completely etched away, but a portion of the buffer structure is retained as the residual buffer structure 43. For example, a portion of the buffer structure can be retained as the residual buffer structure 43. Figure 6 The top cover 41 of the buffer structure 40 shown is designed to allow the remaining buffer structure 43 to continue protecting the raised structure pattern in subsequent etching processes.

[0061] For details, please refer to Figure 6 When specifically etching the substrate 10 between two adjacent protrusions 20, the residual buffer structure 43 can protect the spacer structure 31 and the protrusion 20 below the spacer structure 31, so that when etching to form a recessed structure pattern, the retained residual buffer structure 43 protects the protrusion structure pattern. After forming the recessed structure pattern, refer to Figure 7 This can remove residual buffer structure 43.

[0062] When determining the specific structure of the raised and recessed structural patterns, if the raised structural pattern can be a bit line pattern, the recessed structural pattern can be a memory node contact hole pattern. The memory node contact hole pattern includes multiple memory node contact holes distributed in the active region of the substrate 10, and the memory node contact holes are located between the bit line patterns, so that the memory node contact plugs filling the memory node contact holes electrically connect the source / drain of the active region and the capacitor of the semiconductor device.

[0063] By first forming a buffer structure 40 covering each protruding structure 20 on a portion of the spacer material layer 30 above the protruding structure pattern, and then etching the buffer structure 40 and the spacer material layer 30, the spacer material layer 30 between two adjacent protruding structures 20 is separated, forming a spacer structure 31 covering only each protruding structure 20 and its upper surface. Compared with the prior art method of directly etching the spacer material layer 30 using plasma etching after depositing the spacer material layer 30, the solution of this application, by adding the step of setting the buffer structure 40, can protect the protruding structure 20 during the subsequent etching of the spacer material layer 30 to separate it and form the spacer structure 31. This prevents the protruding structure 20 from being damaged by over-etching the spacer material layer 30, and prevents defects such as poor contact in the protruding structure 20. Furthermore, the spacer structure 31 not only covers the two sidewalls of the raised structure pattern, but also covers the upper surface of the raised structure 20, thereby improving the protection effect of the spacer structure 31 on the bit line pattern or gate pattern.

[0064] In addition, embodiments of the present invention also provide a semiconductor device, see reference. Figure 7 The semiconductor device includes a substrate 10 and a raised structure pattern formed on the substrate 10, wherein the raised structure pattern includes a plurality of spaced-apart raised structures 20. It also includes spacer structures 31 forming a layer covering the sidewalls and upper surface of each raised structure 20. In the above embodiment, the spacer structures 31 disposed around the raised structures 20 cover not only the sidewalls of the raised structures 20 but also the upper surface of the raised structures 20, thereby improving the protection and support effect of the raised structures 20 and preventing defects such as poor contact. Compared with the prior art where only the sidewalls of the raised structures 20 are covered, the spacer structures 31 of this application also cover the upper surface of the raised structures 20, thereby forming a spacer structure 31 with an inverted U-shaped cross-section, further improving the protection and support effect of the raised structures 20 and preventing defects such as poor contact.

[0065] When specifically determining the protrusion structure pattern, the protrusion structure pattern can be a bit line pattern or a gate pattern to improve the protection effect of the spacer structure 31 on the bit line pattern or gate pattern.

[0066] refer to Figure 7 A recessed structure pattern can also be formed on the substrate 10, and the recessed structure pattern is located between the raised structure patterns. In a specific configuration, the recessed structure pattern includes multiple recessed structures 50 distributed in the active region of the substrate 10. When determining the specific structure of the raised and recessed structure patterns, if the raised structure pattern can be a bit line pattern, the recessed structure pattern can be a memory node contact hole pattern. The memory node contact hole pattern includes multiple memory node contact holes distributed in the active region of the substrate 10, such that the memory node contact plugs filling the memory node contact holes electrically connect the source / drain of the active region and the capacitor of the semiconductor device.

[0067] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; A raised structure pattern is formed on the substrate, the raised structure pattern comprising a plurality of spaced raised structures; A spacer material layer is deposited on the upper surface of the substrate, the upper surface of the raised structural pattern, and the sidewalls; A buffer structure is formed on the spacer material layer above the raised structure pattern, covering each raised structure; The buffer structure includes: a top cover covering the upper surface of each protrusion structure, and edges connected to the top cover and located on opposite sides of each protrusion structure, the edges not completely covering the sidewalls of the protrusion structure, and a gap between the edges of the buffer structure on any two adjacent protrusion structures; The spacer material layer located on the substrate between the buffer structure and two adjacent protrusions is etched to form a spacer structure that covers only the sidewalls and upper surface of each protrusion structure, and a residual buffer structure that covers at least the upper surface of each spacer structure. The substrate between two adjacent protrusions is etched to form a recessed structural pattern on the substrate, while the residual buffer structure can protect the spacer structure and the protrusion structure. Remove the residual buffer structure.

2. The manufacturing method as described in claim 1, characterized in that, The material of the buffer structure is any one of tungsten, titanium nitride, and aluminum.

3. The manufacturing method as described in claim 1, characterized in that, Specifically, forming a buffer structure covering each protruding structure on the spacer material layer located above the protruding structure pattern involves: A buffer structure is formed on the spacer material layer located above the raised structure pattern using physical vapor deposition, covering the upper surface of each raised structure.

4. The manufacturing method as described in claim 1, characterized in that, The raised structure pattern is a bit line pattern or a gate pattern.

5. The manufacturing method as described in claim 4, characterized in that, The recessed structural pattern is located between the raised structural patterns.

6. The manufacturing method as described in claim 5, characterized in that, The raised structure pattern is a bit line pattern, and the recessed structure pattern is a storage node contact hole pattern.

7. The manufacturing method as described in claim 1, characterized in that, The etching of the spacer material layer on the substrate between the buffer structure and two adjacent protrusions forms a spacer structure that covers only the sidewalls and upper surface of each protrusion structure, and a residual buffer structure that covers at least the upper surface of each spacer structure, including: The buffer structure and the spacer material layer located on the substrate between two adjacent protrusions are etched using a plasma etching method or a wet etching method to form a spacer structure that covers only the sidewalls and upper surface of each protrusion structure, and a residual buffer structure that covers only at least the upper surface of each spacer structure.

8. A semiconductor device, characterized in that, include: Base; A raised structure pattern formed on the substrate, the raised structure pattern comprising a plurality of spaced-apart raised structures; A method for forming a spacer structure covering the sidewalls and top surface of each protruding structure includes: depositing a spacer material layer on the top surface of the substrate, the top surface of the protruding structure pattern, and the sidewalls; forming a buffer structure covering each protruding structure on the spacer material layer located above the protruding structure pattern; the buffer structure includes: a top cover covering the top surface of each protruding structure, and edges connected to the top cover and located on opposite sides of each protruding structure, the edges not completely covering the sidewalls of the protruding structure, and a gap between the edges of the buffer structure on any two adjacent protruding structures; etching the buffer structure and the spacer material layer located on the substrate between two adjacent protruding structures to form a spacer structure covering only the sidewalls and top surface of each protruding structure, and a residual buffer structure covering at least the top surface of each spacer structure. A recessed structural pattern is also formed on the substrate, the formation method of which includes: etching the substrate between two adjacent protrusions to form the recessed structural pattern on the substrate, while the residual buffer structure can protect the spacer structure and the protrusion structure.

9. The semiconductor device as claimed in claim 8, characterized in that, The raised structure pattern is a bit line pattern or a gate pattern.

10. The semiconductor device as claimed in claim 9, characterized in that, The recessed structural pattern is located between the raised structural patterns.

11. The semiconductor device as claimed in claim 10, characterized in that, The raised structure pattern is a bit line pattern, and the recessed structure pattern is a storage node contact hole pattern.

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