Driving backplane and display panel

Abstract

The driving backplane and display panel provided by the present application are configured by arranging a gate layer, an interlayer dielectric layer and a first electrode layer between the first active layer and the second active layer, so that the first electrode of the first electrode layer is connected to the first active layer and the second active layer respectively, and the second electrode of the first electrode layer is connected to the gate layer and the second active layer respectively, so that the first electrode serves as a common electrode of the first active layer and the second active layer, and the gate layer serves as a common electrode layer of the first active layer and the second active layer. Compared with the prior art that sets an independent transistor as a control element for control, the driving backplane of the present application can omit at least one non-gate electrode structure and at least one gate electrode structure to achieve a smaller size, optimize the driving backplane structure, meet the needs of the panel market for high pixel density, and save preparation costs.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving backplane and a display panel thereof. Background Art

[0002] In the field of flat panel displays, whether it is a small-size display panel or a large-size display panel, achieving higher pixel density, higher refresh rate and lower energy consumption has always been the direction of development in this field. Thin film transistors are mainly used to control and drive pixel light emission and are important electronic devices in this field. Among them, display panels with higher pixel density require thin film transistors to have smaller sizes, and display panels with lower energy consumption require thin film transistors to have stronger stability. Among thin film transistors, oxide thin film transistors have the advantages of high mobility, good uniformity, and low-temperature process. Therefore, the driving backplane technology based on oxide thin film transistors is widely used to achieve high resolution, high refresh rate, narrow border, low power consumption, large size of organic light emitting diode display panels, mini light emitting diode display panels, micro light emitting diode display panels and liquid crystal display devices.

[0003] However, due to the high mobility characteristics, the oxide thin film transistor has a high carrier, which easily causes the threshold voltage of the thin film transistor to be negatively biased, thereby deteriorating the stability of the thin film transistor. To this end, the prior art sets a control element at the output end of the oxide thin film transistor, and through the control element, when the oxide thin film transistor is in the off state, the output end of the oxide thin film transistor always maintains a low potential, so as to solve the problem of negative bias of the threshold voltage of the thin film transistor.

[0004] However, the addition of control elements increases the space occupied by the driving backplane, which is not conducive to meeting the demand for high pixel density display panels in the art. Therefore, it is necessary to improve the driving backplane. Summary of the invention

[0005] The present application provides a driving backplane and a display panel thereof, which realizes miniaturization by reducing the space occupied by control elements and transistors, thereby simplifying the overall structure of the driving backplane and meeting the needs of a high pixel density display panel.

[0006] In a first aspect, the present application provides a driving backplane, comprising:

[0007] substrate;

[0008] a first active layer, wherein the first active layer is disposed on the substrate;

[0009] A gate layer, wherein the gate layer is disposed on a side of the first active layer away from the substrate, and the first active layer is insulated from the gate;

[0010] an interlayer dielectric layer, the interlayer dielectric layer being disposed on the substrate and covering the first active layer and the gate layer;

[0011] a first electrode layer, the first electrode layer being arranged on a side of the interlayer dielectric layer away from the substrate, the first electrode layer comprising a first electrode and a second electrode, the first electrode being connected to the first active layer, and the second electrode being connected to the gate layer; and,

[0012] A second active layer, wherein the second active layer is arranged on a side of the first electrode layer away from the substrate, and the second active layer is connected to the first electrode and the second electrode.

[0013] In the driving backplane provided in the present application, the first electrode layer further includes a third electrode, and the third electrode is connected to the first active layer.

[0014] In the driving backplane provided in the present application, the driving backplane further comprises a gate insulating layer, and the gate insulating layer is arranged between the first active layer and the gate layer;

[0015] The first active layer includes a first main part, a second main part and a third main part connecting the first main part and the second main part, and a projection of the third main part on the substrate coincides with a projection of the gate insulating layer on the substrate.

[0016] In the driving backplane provided in the present application, the driving backplane includes a first via hole, a second via hole and a third via hole, and the first via hole, the second via hole and the third via hole all penetrate the interlayer dielectric layer;

[0017] Among them, the first via is located directly above the first main part, the second via is located directly above the second main part, the third via is located directly above the gate layer, the first electrode is connected to the first main part through the first via, the second electrode is connected to the gate layer through the third via, and the third electrode is connected to the second main part through the second via.

[0018] In the driving backplane provided in the present application, the second active layer includes a first portion, a second portion, and a third portion connecting the first portion and the second portion;

[0019] The first portion is located on the first electrode, the second portion is located on the third electrode, and the third portion is located between the first electrode and the second electrode.

[0020] In the driving backplane provided in the present application, the first partial covering the first electrode, and / or the second partial covering the second electrode.

[0021] In the driving backplane provided in the present application, the driving backplane further comprises a second electrode layer, and the second electrode layer is arranged on a side of the interlayer dielectric layer away from the substrate;

[0022] The second electrode layer further includes a third electrode, and the third electrode is connected to the first active layer.

[0023] In the driving backplane provided in the present application, the driving backplane includes a first transistor and a second transistor, the gate of the first transistor, one of the source and the drain of the first transistor, and the gate of the second transistor are electrically connected, and the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; wherein,

[0024] The gate of the first transistor and the gate of the second transistor both include the gate layer; one of the source and the drain of the first transistor includes the second electrode, the other of the source and the drain of the first transistor and one of the source and the drain of the second transistor both include the first electrode, and the other of the source and the drain of the second transistor includes the third electrode.

[0025] In the driving backplane provided in the present application, the first active layer is a metal oxide semiconductor layer, and the second active layer is a P-type oxide semiconductor layer.

[0026] In a second aspect, the present application also provides a display panel, comprising any of the aforementioned driving backplanes.

[0027] The driving backplane provided by the present application is configured by arranging a gate layer, an interlayer dielectric layer and a first electrode layer between the first active layer and the second active layer, so that the first electrode of the first electrode layer is connected to the first active layer and the second active layer respectively, and the second electrode of the first electrode layer is connected to the gate layer and the second active layer respectively, so that the first electrode is used as a common electrode of the first active layer and the second active layer, and the gate layer is used as a common electrode layer of the first active layer and the second active layer; therefore, the control element composed of the first electrode, the second electrode, the gate layer and the second active layer can control the output end of the transistor including the first active layer. Compared with the prior art that sets an independent transistor as a control element for control, the driving backplane provided by the present application can omit at least one non-gate electrode structure and at least one gate electrode structure, thereby reducing the space occupied by the transistor to achieve a smaller size, and then optimizing the driving backplane structure to meet the needs of the panel market for high pixel density and narrow frame, while saving the preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A first equivalent circuit diagram of a driving backplane provided in an embodiment of the present application;

[0029] Figure 2 A second equivalent circuit diagram of the driving backplane provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the first structure of the driving backplane provided in an embodiment of the present application;

[0031] Figure 4 A second structural schematic diagram of a drive backplane provided in an embodiment of the present application;

[0032] Figure 5 A third structural schematic diagram of the driving backplane provided in an embodiment of the present application;

[0033] Figure 6 A schematic flow chart of a method for preparing a driving backplane provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0035] In addition, the following descriptions of the embodiments of the application are with reference to the attached drawings to illustrate specific embodiments of the invention that the present invention can be implemented in. The directional terms mentioned in this application, such as "upper", "lower", "front", "back", "one side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0036] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish different objects, rather than to describe a specific order. The terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. Since the source and drain of the transistor used in this application are symmetrical, the source and drain are interchangeable. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end is the source, and the output end is the drain.

[0037] See also Figure 1 , Figure 1This is the first equivalent circuit diagram of the driving backplane provided in the embodiment of the present application. Figure 1 As shown, the driving backplane includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1, one of the source and drain of the first transistor T1, and the gate of the second transistor T2 are electrically connected, and the other of the source and drain of the first transistor T1 is electrically connected to one of the source and drain of the second transistor T2. That is, the gate of the first transistor T1 and the gate of the second transistor T2 can be controlled by the same control voltage.

[0038] When the first transistor T1 is turned on, the source and drain of the first transistor T1 form a path. At this time, the gate of the second transistor T2 is connected to one of the source and drain of the first transistor T1, and one of the source and drain of the second transistor T2 is connected to the other of the source and drain of the first transistor T1, so that the gate of the second transistor T2 is short-circuited with one of the source and drain of the second transistor T2. Therefore, during the time period when the first transistor T1 is in the on state, one of the source and drain of the second transistor T2 is always at a low potential.

[0039] For further information, see Figure 2 , Figure 2 This is a second equivalent circuit diagram of the driving backplane provided in the embodiment of the present application. Figure 2 As shown, the difference between the second equivalent circuit diagram and the above equivalent circuit diagram is that the first transistor T1 and the second transistor T2 are different types of transistors, that is, when the first transistor T1 is a P-type transistor, the second transistor T2 is an N-type transistor; or, when the first transistor T1 is an N-type transistor, the second transistor T2 is a P-type transistor. Therefore, when the gates of the first transistor T1 and the second transistor T2 are controlled by the same control voltage, the first transistor T1 is in the on state, and correspondingly, the second transistor T2 is in the off state; similarly, when the first transistor T1 is in the off state, correspondingly, the second transistor T2 is in the on state.

[0040] In the case where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, based on the fact that the gates of the first transistor T1 and the second transistor T2 are simultaneously connected to a low gate voltage, the first transistor T1 is turned on, the second transistor T2 is turned off, and the source and drain of the first transistor T1 form a path to short-circuit the gate of the second transistor T2 with one of the source and drain of the second transistor T2. Thus, when the second transistor T2 is turned off, the first transistor T1 can ensure that one of the source and drain of the second transistor T2 is maintained at a low potential to solve the negative bias of the threshold voltage of the second transistor T2. In addition, when the first transistor T1 is turned off, the second transistor T2 is normally turned on, so that the first transistor T1 will not affect the second transistor T2 in a normally turned-on state.

[0041] See also Figure 3 , Figure 3 This is a schematic diagram of the first structure of the drive backplane provided in the embodiment of the present application. Figure 3 As shown, the driving backplane 100 includes:

[0042] Substrate 10, substrate 10 can be a rigid substrate or a flexible substrate. When substrate 10 is a rigid substrate, substrate 10 can be made of glass; when substrate 10 is a flexible substrate, substrate 10 can be made of a single layer or a multilayer material made of at least one of polyimide material, polycarbonate material and polyethylene terephthalate material. The thickness of substrate 10 is 1000 angstroms to 5000 angstroms.

[0043] The first active layer 20 is disposed on the substrate 10. Specifically, the first active layer 20 may be made of metal oxide semiconductor materials, such as one or more materials such as indium gallium zinc oxide materials, indium tin zinc oxide materials, indium gallium tin oxides, and indium gallium zinc tin oxides; the first active layer 20 may be made of P-type oxide semiconductor materials, such as copper oxide, silver oxide, nickel oxide, and tin oxide, which exhibit p-type conductivity even without adding p-type impurities, or a P-type oxide semiconductor material containing indium oxide, gallium oxide, or zinc oxide in copper oxide, silver oxide, nickel oxide, or tin oxide. The thickness of the first active layer 20 is 100 angstroms to 1000 angstroms.

[0044] Specifically, the first active layer 20 includes a first main portion 201, a second main portion 202 and a third main portion 203 connecting the first main portion 201 and the second main portion 202. The first main portion 201 and the second main portion 202 serve as conductor regions, and the third main portion serves as a channel region.

[0045] The gate insulating layer 70 is disposed on a side of the first active layer 20 away from the substrate 10 to achieve insulation between the first active layer 20 and the gate layer 30. Specifically, the gate insulating layer 70 may be made of one or more of silicon oxide and silicon nitride materials. The thickness of the gate insulating layer 70 is 1000 angstroms to 3000 angstroms.

[0046] It should be noted that the projection of the gate insulating layer 70 on the substrate 10 may coincide with the projection of the first active layer 20 on the substrate 10 . Of course, the projection of the gate insulating layer 70 on the substrate 10 may not coincide with the projection of the first active layer 20 on the substrate 10 . Figure 3The projection of the gate insulating layer 70 on the substrate 10 shown does not overlap with the projection of the first active layer 20 on the substrate 10, and the projection of the first active layer 20 on the substrate 10 covers the projection of the gate insulating layer 70 on the substrate 10. The purpose of such a setting is to enable the portion of the first active layer 20 not covered by the gate insulating layer 70 to be directly connected to the interlayer dielectric layer 40. In the subsequent process, when the driving backplane 100 is opened, the gate insulating layer 70 can be omitted to open a hole to achieve the connection between the first electrode layer 50 and the first active layer 20.

[0047] The gate layer 30 is disposed on the side of the gate insulating layer 70 away from the substrate 10. The gate layer 30 can be made of at least one material selected from metals such as molybdenum, aluminum, copper, titanium, and alloys. The thickness of the gate layer 30 is 2000 angstroms to 8000 angstroms.

[0048] It should be noted that the projection of the gate layer 30 on the substrate 10 may coincide with the projection of the gate insulating layer 70 on the substrate 10 . Of course, the projection of the gate layer 30 on the substrate 10 may not coincide with the projection of the gate insulating layer 70 on the substrate 10 . Figure 3 It is shown that the projection of the gate layer 30 on the substrate 10 overlaps with the projection of the gate insulating layer 70 on the substrate 10. The advantage of such a setting is that the gate insulating layer 70 can be etched based on the pattern of the gate layer 30 in industrial production to etch away the portion of the gate insulating layer 70 that does not overlap with the gate layer 30, so as to subsequently form a conductor region and a channel region on the first active layer 20 using a self-alignment technique. In some other embodiments of the present application, the gate layer 30 and the gate insulating layer 70 may also be an island structure, that is, the projection of the gate insulating layer 70 on the substrate 10 covers the projection of the gate layer 30 on the substrate 10, so that there is a portion of the gate insulating layer 70 that is not covered by the gate layer 30.

[0049] The interlayer dielectric layer 40 is disposed on the substrate 10, and covers the first active layer 20, the gate insulating layer 70 and the gate layer 30. The interlayer dielectric layer 40 may be made of one or more materials selected from silicon oxide compounds and silicon nitride compounds. The thickness of the interlayer dielectric layer 40 is 1000 angstroms to 3000 angstroms.

[0050] Specifically, in the driving backplane 100 provided in this embodiment, the interlayer dielectric layer 40 includes a first via hole 801, a second via hole 802, and a third via hole 803. The first via hole 801 penetrates the interlayer dielectric layer 40, and the first via hole 801 is located directly above the first main part 201, so that the first main part 201 is exposed through the first via hole 801, so that the first electrode layer 50 is connected to the first main part 201. The second via hole 802 penetrates the interlayer dielectric layer 40, and the second via hole 802 is located directly above the second main part 202, so that the second main part is exposed through the second via hole 802, so that the first electrode layer 50 is connected to the second main part 202. The third via hole 803 penetrates the interlayer dielectric layer 40, and the third via hole 803 is located directly above the gate layer 30, so that the gate layer 30 is exposed through the third via hole 803, so that the first electrode layer 50 is connected to the gate layer 30.

[0051] The first electrode layer 50 is disposed on the side of the interlayer dielectric layer 40 away from the substrate 10. The first electrode layer 50 can be made of at least one material selected from metals such as molybdenum, aluminum, copper, titanium, manganese, and alloys. The thickness of the first electrode layer 50 is 2000 angstroms to 10000 angstroms. The first electrode layer 50 is used to form a first electrode 501, a second electrode 502, and a third electrode 503 in an image-based manner.

[0052] Specifically, the first electrode 501, the second electrode 502 and the third electrode 503 are all formed by patterning the first electrode layer 50, so that the first electrode 501, the second electrode 502 and the third electrode 503 are adjacent to each other and arranged in the same layer. Among them, the first electrode 501 is connected to the first main part 201 through the first via hole 801, the second electrode 502 is connected to the gate layer 30 through the third via hole 803, and the third electrode 503 is connected to the second main part 202 through the second via hole 802.

[0053] It should be noted that when the first electrode 501 serves as a source, the second electrode 502 and the third electrode 503 serve as a drain; similarly, when the first electrode 501 serves as a drain, the second electrode 502 and the third electrode 503 serve as a source.

[0054] The second active layer 60 is disposed on a side of the first electrode layer 50 away from the substrate, and the second active layer 60 is connected to the first electrode 501 and the second electrode 502 of the first electrode layer 50. The second active layer 60 may be made of a metal oxide semiconductor material, for example, one or more materials such as indium gallium zinc oxide material, indium tin zinc oxide material, indium gallium tin oxide, and indium gallium zinc tin oxide; the second active layer 60 may be made of a P-type oxide semiconductor material, for example, a P-type oxide semiconductor that exhibits p-type conductivity even without adding p-type impurities, such as copper oxide, silver oxide, nickel oxide, and tin oxide, or a P-type oxide semiconductor material containing indium oxide, gallium oxide, or zinc oxide in copper oxide, silver oxide, nickel oxide, or tin oxide.

[0055] Specifically, the second active layer 60 includes a first portion 601, a second portion 602, and a third portion 603 connecting the first portion 601 and the second portion 602. The first portion 601 is located on the first electrode 501, and the first portion 601 is connected to the first main portion 201 of the first active layer 20 through the first electrode 501; the second portion 602 is located on the second electrode 502, and the second portion 602 is connected to the gate layer 30 through the second electrode 502; the third portion 603 is between the first portion 601 and the second portion 602, and the third portion 603 is located on the interlayer dielectric layer 40. Therefore, the first portion 601 and the second portion 602 serve as the conductor region of the second active layer 60, and the third portion 603 serves as the channel region of the second active layer 60.

[0056] It is worth mentioning that in this embodiment, the driving backplane may further include a buffer layer. The buffer layer may be disposed between the substrate 10 and the first active layer 20 to provide buffer protection for the film layers away from the substrate 10. The buffer layer may be a thin film composed of one or more materials selected from silicon-oxygen materials and silicon-nitrogen materials.

[0057] It is worth mentioning that in this embodiment, the driving backplane may further include a passivation layer. The passivation layer is disposed on the side of the second active layer 60 away from the substrate 10, and the passivation layer covers the interlayer dielectric layer 40, the first electrode layer 50 and the second active layer 60. The passivation layer is used to form a planarized surface on the side of the second active layer 60 away from the substrate, so as to prepare a pixel electrode on the side of the passivation layer away from the substrate 10.

[0058] In the driving backplane 100 provided in the present embodiment, a gate layer 30, an interlayer dielectric layer 40 and a first electrode layer 50 are arranged between the first active layer 20 and the second active layer 60, so that the first electrode 501 of the first electrode layer 50 is respectively connected to the first active layer 20 and the second active layer 60, and the second electrode 502 of the first electrode layer 50 is respectively connected to the gate layer 30 and the second active layer 60, so that the first electrode 501 is connected to the first active layer 20 and the second active layer 60 through the first electrode 501, so that the first electrode 501 is a non-gate common electrode of the first active layer 20 and the second active layer 60; the second electrode 502 is connected to the second active layer 60 and the gate layer 30, so that the gate layer 30 is a gate common electrode of the first active layer 20 and the second active layer 60.

[0059] Therefore, combined with Figures 1 to 3 It can be known that the first electrode 501, the second electrode 502, the gate layer 30, the interlayer dielectric layer 40 and the second active layer 60 can be equivalent to the first transistor T1; the first electrode 501, the third electrode 503, the first active layer 20, the gate insulating layer 70 and the gate layer 30 can be equivalent to the second transistor T2. Based on the first electrode 501 being the common electrode of the first active layer 20 and the second active layer 60, one of the source and the drain of the first transistor T1 is electrically connected to one of the source and the drain of the second transistor; based on the gate layer 30 being the common electrode of the first active layer 20 and the second active layer 60, the gate of the first transistor T1 is electrically connected to the gate of the second transistor T2; based on the second active layer 60 being connected to the gate layer 30 through the second electrode 502, the gate of the first transistor T1 is electrically connected to the other of the source and the drain of the first transistor T1.

[0060] Therefore, when the first transistor T1 is turned on, the source and drain of the first transistor T1 form a path, so that the gate of the second transistor T2 is short-circuited with one of the source and drain of the second transistor T2, so during the time period when the first transistor T1 is in the on state, one of the source and drain of the second transistor T2 is always at a low potential. In the case where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first transistor T1 is turned on, and the second transistor T2 is turned off. The first transistor T1 can ensure that one of the source and drain of the second transistor T2 is maintained at a low potential, so as to solve the negative bias of the threshold voltage of the second transistor T2 and ensure the stability of the second transistor T2 during use.

[0061] Therefore, in the driving backplane provided in this embodiment, at least one gate electrode structure and at least one non-gate electrode structure can be omitted, thereby reducing the space occupied by the transistor to achieve a smaller size, and then optimizing the driving backplane structure to meet the high pixel density and narrow border requirements of the panel market while saving preparation costs.

[0062] In some embodiments, see Figure 4 , Figure 4 FIG. 2 shows a second structural schematic diagram of a driving backplane provided in an embodiment of the present application. Figure 4 As shown, the difference between the driving backplane provided in the embodiment of the present application and the driving backplane provided in the above-mentioned embodiment is that: the first portion 601 of the second active layer 60 completely covers the first electrode 501 and the second portion 602 of the second active layer 60 completely covers the second electrode 502. Thus, the first portion 601 of the second active layer 60 completely covers the first electrode 501, thereby increasing the contact area between the second active layer 60 and the first electrode 501; the second portion 602 of the second active layer completely covers the second electrode 502, thereby increasing the contact area between the second active layer 60 and the second electrode 502.

[0063] Of course, in other embodiments of the present application, the first portion 601 may not completely cover the first electrode 501, or the second portion 602 may not completely cover the second electrode 502. When the second portion 602 does not completely cover the second electrode 502, misconnection of the second electrode 502 and the third electrode 503 disposed on the same layer can be avoided, thereby ensuring the production yield of the driving backplane.

[0064] In some embodiments, see Figure 5 , Figure 5 FIG. 3 shows a third structural schematic diagram of a driving backplane provided in an embodiment of the present application. Figure 5 As shown, the driving backplane provided in the embodiment of the present application is different from the above-mentioned embodiment in that: the first electrode layer 50 includes a first electrode 501 and a second electrode 502, the first electrode 501 is connected to the first main part 201, and the second electrode 502 is connected to the gate layer 30. The second interlayer dielectric layer 80 is arranged on the side of the interlayer dielectric layer 40 away from the substrate 10, and the second interlayer dielectric layer 80 covers the first electrode layer 50 and the second active layer 60. The second electrode layer is arranged on the side of the second interlayer dielectric layer 80 away from the substrate 10, and the second electrode layer includes a third electrode 901, and the third electrode 901 is connected to the first active layer 20.

[0065] That is, in this embodiment, the first electrode 501 connecting the first active layer 20 and the second active layer 60 is arranged in the same layer as the second electrode 502 connecting the second active layer 60 and the gate layer 30, and the third electrode 901 is arranged in a different layer from the second electrode 502. Thus, the first via hole 801 penetrates the interlayer dielectric layer 40 to expose the first main part 201, and the first electrode 501 is connected to the first main part 201 through the first via hole 801; the third via hole 803 penetrates the interlayer dielectric layer 40 to expose part of the gate layer 30, so that the second electrode 502 is connected to the gate layer 30 through the third via hole 803; the second via hole 802 penetrates the second interlayer dielectric layer 80 and the interlayer dielectric layer 40, so that the third electrode 901 is connected to the first active layer 20 through the second via hole 802. The third electrode 901 and the second electrode 502 are arranged in different layers, which can avoid the second active layer 60 and the third electrode 901 from being mistakenly connected when the second active layer 60 is prepared on the side of the first electrode 501 and the second electrode 502 away from the substrate 10, thereby ensuring the production yield of the driving backplane 100.

[0066] It should be noted that in some other embodiments of the present application, the second electrode layer may be firstly arranged on the side of the interlayer dielectric layer 40 away from the substrate 10, and then the second interlayer dielectric layer 80 may be arranged on the side of the interlayer dielectric layer 40 away from the substrate 10, and the second interlayer dielectric layer 80 covers the second electrode layer and the interlayer dielectric layer 40, and then the first electrode layer 50 is arranged on the side of the interlayer dielectric layer 40 away from the substrate 10, so as to realize that the first electrode 501 and the second electrode 502 are arranged on the same layer, and the second electrode 502 and the third electrode 901 are arranged on different layers. Thus, the first via hole 801 penetrates the interlayer dielectric layer 40 and the second interlayer dielectric layer 80 to expose the first main part 201, the third via hole 803 penetrates the interlayer dielectric layer 40 and the second interlayer dielectric layer 80 to expose the gate layer 30, and the second via hole 802 penetrates the second interlayer dielectric layer 80 to expose the second main part 202, and similarly, the second active layer 60 and the third electrode 901 can be prevented from being connected by mistake.

[0067] It is worth mentioning that the driving backplane provided in the embodiment of the present application reduces the space occupied by the transistor, thereby optimizing the structure. Therefore, it can be used as a driving backplane of an organic light emitting diode display panel, as a driving backplane of a mini light emitting diode display panel, and as a driving backplane of a micro light emitting diode display panel. Of course, it is also suitable for a driving backplane of a liquid crystal display device.

[0068] The present application also provides a display panel, which includes any one of the driving backplanes in the aforementioned embodiments.

[0069] This application also provides a method for preparing a drive backplane, see Figure 6 , Figure 6 The following is a schematic diagram of a process for preparing a driving backplane according to an embodiment of the present application. Figure 6 As shown, the method for preparing the driving backplane includes the following steps:

[0070] Step S1, providing a substrate; the substrate may be a rigid substrate made of glass material, or a flexible substrate made of at least one of polyimide material, polycarbonate material and polyethylene terephthalate material.

[0071] It should be noted that before performing step S2, a buffer layer can be deposited on the entire surface of the substrate, and the thickness of the buffer layer can be controlled to be between 1000 angstroms and 5000 angstroms. The buffer layer can be a multilayer structure film formed by depositing one or more materials of silicon oxide compounds or silicon nitrogen compounds to play a buffer protection role.

[0072] Step S2, depositing a first active layer on the substrate, wherein the thickness of the first active layer is controlled to be between 100 angstroms and 1000 angstroms, and etching to form a patterned first active layer; the first active layer can be made of a metal oxide semiconductor material, such as one or more materials such as indium gallium zinc oxide material, indium tin zinc oxide material, indium gallium tin oxide, and indium gallium zinc tin oxide; the first active layer can also be made of a P-type oxide semiconductor material, such as copper oxide, silver oxide, nickel oxide, and tin oxide, which are p-type oxide semiconductors that exhibit p-type conductivity even without adding p-type impurities, or a P-type oxide semiconductor material containing indium oxide, gallium oxide, or zinc oxide in copper oxide, silver oxide, nickel oxide, or tin oxide.

[0073] Step S3, depositing a gate insulating layer on the side of the first active layer away from the substrate; controlling the thickness of the gate insulating layer to be between 1000 angstroms and 3000 angstroms, and the gate insulating layer can be a multilayer structure film formed by depositing one or more materials selected from silicon oxide compounds and silicon nitrogen compounds.

[0074] Step S4, depositing a gate layer on the side of the gate insulating layer away from the substrate, and forming a patterned gate through a yellow light process; the thickness of the gate layer is controlled to be 2000 angstroms-8000 angstroms, and the gate layer can be made of at least one material selected from metals such as molybdenum, aluminum, copper, titanium, and alloys.

[0075] It should be noted that after the patterned gate is formed through step S4, a self-alignment process can be used based on the patterned gate to etch away the portion of the gate insulating layer not covered by the gate layer, and then the entire surface is subjected to a plasma process, so that the portion of the first active layer not covered by the gate layer serves as a conductor region, and the portion of the first active layer covered by the gate layer serves as a channel region while maintaining semiconductor characteristics.

[0076] Step S5, depositing an interlayer dielectric layer on the side of the first active layer away from the substrate, so that the interlayer dielectric layer covers the first active layer, the gate insulating layer and the gate layer, and etching the interlayer dielectric layer to form a first via hole, a second via hole and a third via hole. The first active layer is exposed through the first via hole and the second via hole respectively, and the gate layer is exposed through the third via hole. The thickness of the interlayer dielectric layer can be controlled to be 1000 angstroms to 3000 angstroms, and the interlayer dielectric layer can be a multilayer structure film formed by depositing one or more materials selected from silicon oxide compounds and silicon nitrogen compounds.

[0077] Step S6, depositing a first electrode layer on a side of the interlayer dielectric layer away from the substrate, and etching the first electrode layer to form a patterned first electrode layer; the thickness of the first electrode layer is 2000 angstroms to 10000 angstroms, and the first electrode layer can be made of at least one material selected from metals such as molybdenum, aluminum, copper, titanium, manganese, and alloys.

[0078] Specifically, in step S6, the patterned first electrode layer includes a first electrode, a second electrode and a third electrode, so that the first electrode is connected to the first active layer through the first via hole, the third electrode is connected to the first active layer through the second via hole, and the second electrode is connected to the gate layer through the third via hole.

[0079] Step S7, depositing and patterning a second active layer on a side of the first electrode layer away from the substrate; the second active layer can be made of a metal oxide semiconductor material or a P-type oxide semiconductor material.

[0080] It should be noted that the deposited second active layer needs to cover at least a portion of the first electrode and at least a portion of the second electrode to achieve connection between the second active layer and the first electrode and the second electrode, so that the second active layer covering the first electrode and the portion covering the second electrode serves as the conductor region of the second active layer, and the portion of the second active layer not covering the first electrode and the second electrode serves as the channel region of the second active layer.

[0081] It should be noted that after step S7, a passivation layer can be prepared on the side of the second active layer away from the substrate, so that the passivation layer covers the interlayer dielectric layer, the first electrode layer and the second active layer; the passivation layer can be made of inorganic material, and the thickness of the passivation layer is controlled to be between 1000 angstroms and 5000 angstroms to play a buffering and protective role, so as to facilitate the subsequent production of pixel electrodes.

[0082] Therefore, in the manufacturing method of the driving backplane provided in this embodiment, at least one gate preparation step and at least one non-gate electrode preparation step can be omitted, which can save preparation costs while reducing the space occupied by the transistor, achieving smaller size, and optimizing the driving backplane structure.

[0083] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A driving backplane, characterized in that: include: substrate; a first active layer, wherein the first active layer is disposed on the substrate; A gate layer, wherein the gate layer is disposed on a side of the first active layer away from the substrate, and the first active layer is insulated from the gate layer; an interlayer dielectric layer, the interlayer dielectric layer being disposed on the substrate and covering the first active layer and the gate layer; a first electrode layer, the first electrode layer being arranged on a side of the interlayer dielectric layer away from the substrate, the first electrode layer comprising a first electrode and a second electrode, the first electrode being connected to the first active layer, and the second electrode being connected to the gate layer; as well as, a second active layer, wherein the second active layer is disposed on a side of the first electrode layer away from the substrate, and the second active layer is connected to the first electrode and the second electrode; Wherein, the first electrode layer also includes a third electrode, and the third electrode is connected to the first active layer; the driving backplane includes a first transistor and a second transistor, the gate of the first transistor, one of the source and the drain of the first transistor and the gate of the second transistor are electrically connected, and the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; wherein, the gate of the first transistor and the gate of the second transistor both include the gate layer; one of the source and the drain of the first transistor includes the second electrode, the other of the source and the drain of the first transistor and one of the source and the drain of the second transistor both include the first electrode, and the other of the source and the drain of the second transistor includes the third electrode.

2. The driving backplane according to claim 1, characterized in that: The driving backplane further comprises a gate insulating layer, wherein the gate insulating layer is arranged between the first active layer and the gate layer; The first active layer includes a first main part, a second main part and a third main part connecting the first main part and the second main part, and a projection of the third main part on the substrate coincides with a projection of the gate insulating layer on the substrate.

3. The driving backplane according to claim 2, characterized in that: The driving backplane comprises a first via hole, a second via hole and a third via hole, and the first via hole, the second via hole and the third via hole all penetrate the interlayer dielectric layer; Among them, the first via is located directly above the first main part, the second via is located directly above the second main part, the third via is located directly above the gate layer, the first electrode is connected to the first main part through the first via, the second electrode is connected to the gate layer through the third via, and the third electrode is connected to the second main part through the second via.

4. The driving backplane according to claim 1, characterized in that: The second active layer includes a first portion, a second portion, and a third portion connecting the first portion and the second portion; The first portion is located on the first electrode, the second portion is located on the second electrode, and the third portion is located between the first electrode and the second electrode.

5. The driving backplane according to claim 4, characterized in that: The first partial covering of the first electrode, and / or the second partial covering of the second electrode.

6. The driving backplane according to claim 1, characterized in that: The driving backplane further comprises a second electrode layer, and the second electrode layer is arranged on a side of the interlayer dielectric layer away from the substrate; The second electrode layer further includes a third electrode, and the third electrode is connected to the first active layer.

7. The driving backplane according to claim 1, characterized in that: The first active layer is a metal oxide semiconductor layer, and the second active layer is a P-type oxide semiconductor layer.

8. A display panel, characterized in that: Comprising the driving backplane described in any one of claims 1-7.

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