Memory and manufacturing method thereof

Abstract

An embodiment of the present invention provides a memory and a method for manufacturing the same, the method comprising: forming a plurality of first address lines, a plurality of first phase-change memory cells, and a plurality of second address rings arranged in a stacked manner; the first address lines extending along a first direction, the second address ring extending along a second direction perpendicular to the first direction, and the first phase-change memory cells being perpendicular to both the first and second directions; forming a plurality of second phase-change memory cell rings extending along the second direction on the second address ring; the second address ring and the second phase-change memory cell ring each having a first end and a second end arranged opposite to each other in the second direction; simultaneously removing the first ends and the second ends of the second address ring and the second phase-change memory cell ring to form a plurality of second address lines and a plurality of second phase-change memory cell lines; and using the second phase-change memory cell lines to form a plurality of second phase-change memory cells perpendicular to both the first and second directions.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a method for manufacturing a memory and a memory. Background Art

[0002] Three-dimensional cross-point memory, such as phase change memory (PCM), is a storage technology that uses chalcogenides as a storage medium, exploiting the difference in resistance between the material's different states to store data. PCM offers advantages such as bit-by-bit addressability, data preservation after power failure, high storage density, and fast read / write speeds, making it considered a promising next-generation memory.

[0003] However, in the related art, three-dimensional cross-point memory still faces various challenges. Summary of the Invention

[0004] To solve the related technical problems, embodiments of the present invention provide a memory and a manufacturing method thereof.

[0005] An embodiment of the present invention provides a method for manufacturing a memory, comprising:

[0006] A plurality of first address lines, a plurality of first phase-change memory cells, and a plurality of second address rings are formed in a stacked manner; the first address lines extend along a first direction, the second address rings extend along a second direction perpendicular to the first direction, and the first phase-change memory cells are perpendicular to both the first and second directions;

[0007] A plurality of second phase-change memory cell rings are formed on the second address ring, each extending along the second direction; the second address ring and the second phase-change memory cell ring each have a first end and a second end oppositely disposed in the second direction;

[0008] Simultaneously removing the second address ring and the first end and the second end of the second phase-change memory cell ring to form a plurality of second address lines and a plurality of second phase-change memory cell lines;

[0009] The second phase-change memory cell lines are used to form a plurality of second phase-change memory cells perpendicular to both the first direction and the second direction.

[0010] In the above scheme,

[0011] The method of simultaneously removing the second address ring and the first end and the second end of the second phase-change memory cell ring to form a plurality of second address lines and a plurality of second phase-change memory cell lines includes:

[0012] forming a first mask layer on the second phase-change memory cell ring;

[0013] The first mask layer is used to perform a first etching to simultaneously remove the second address ring and the first end and the second end of the second phase-change memory cell ring to form a plurality of second address lines and a plurality of second phase-change memory cell lines.

[0014] In the above solution, before forming the second phase-change memory unit, a third address line material layer is formed on the second phase-change memory unit line;

[0015] The method of forming a plurality of second phase-change memory cells perpendicular to both the first direction and the second direction by using the second phase-change memory cell line includes:

[0016] Performing a second etching on the third address line material layer and the second phase-change memory cell line to form a third address ring and a second phase-change memory cell; the third address ring extends along a first direction and has a third end and a fourth end oppositely disposed in the first direction; and the second phase-change memory cell is perpendicular to both the first direction and the second direction;

[0017] The method further comprises:

[0018] A plurality of third address lines extending along a first direction are formed on the second phase-change memory unit by utilizing the third address ring.

[0019] In the above scheme,

[0020] The method further comprises:

[0021] Before forming the third address line, forming a third phase-change memory cell ring on the third address ring; the third phase-change memory cell ring extends along the first direction and has a third end and a fourth end oppositely disposed in the first direction;

[0022] The method of forming a plurality of third address lines extending along the first direction on the second phase-change memory unit by using the third address ring includes:

[0023] Simultaneously removing the third end and the fourth end of the third address ring and the third phase-change memory cell ring to form a third address line and a third phase-change memory cell line;

[0024] The method further comprises:

[0025] The third phase-change memory cell line is used to form a plurality of third phase-change memory cells perpendicular to both the first direction and the second direction.

[0026] In the above scheme,

[0027] The method further comprises:

[0028] Before forming the third phase-change memory cell, forming a fourth address line material layer on the third phase-change memory cell line;

[0029] The method of forming a plurality of third phase-change memory cells perpendicular to both the first direction and the second direction by using the third phase-change memory cell line includes:

[0030] The fourth address line material layer and the third phase-change memory cell line are subjected to a third etching process to form a third phase-change memory cell and a fourth address ring, wherein the third phase-change memory cell is perpendicular to both the first direction and the second direction.

[0031] In the above solution, the method further includes:

[0032] After forming the fourth address ring, forming a fourth phase-change memory cell ring on the fourth address ring; the fourth address ring and the fourth phase-change memory cell ring both extend along the second direction and have a first end and a second end oppositely disposed in the second direction;

[0033] Simultaneously removing the first end and the second end of the fourth address ring and the fourth phase-change memory cell ring to form a fourth address line and a fourth phase-change memory cell line;

[0034] The fourth phase-change memory cell line is used to form a plurality of fourth phase-change memory cells perpendicular to the first direction and the second direction, and a plurality of fifth address lines extending along the first direction are formed on the fourth phase-change memory cells.

[0035] In the above solution, the method further includes:

[0036] Before forming a plurality of second phase-change memory cell rings extending along the second direction on the second address ring, a sixth address ring is formed on the second address ring; the sixth address ring extends along the second direction and has a first end and a second end disposed opposite to each other in the second direction;

[0037] The forming of a plurality of second phase-change memory cell rings on the second address ring, all extending along the second direction, comprises:

[0038] forming a plurality of second phase-change memory cell rings on the sixth address ring, all extending along the second direction;

[0039] The method of simultaneously removing the second address ring and the first end and the second end of the second phase-change memory cell ring to form a plurality of second address lines and a plurality of second phase-change memory cell lines includes:

[0040] The second address ring, the sixth address ring, and the first end and the second end of the second phase-change memory cell ring are removed at the same time to form a second address line, a sixth address line, and a second phase-change memory cell line.

[0041] In the above solution, the forming of a plurality of first address lines, a plurality of first phase-change memory cells, and a plurality of second address rings includes:

[0042] forming a first address line material layer and a first phase-change memory cell material layer that are stacked;

[0043] performing a fourth etching on the first address line material layer and the first phase-change memory cell material layer to divide the first address line material layer and the first phase-change memory cell material layer into a first address ring and a first phase-change memory cell ring extending along a first direction; the first address ring and the first phase-change memory cell ring having a third end and a fourth end disposed opposite to each other in the first direction;

[0044] Simultaneously removing the first address ring and the third end and the fourth end of the first phase-change memory cell ring to form a first address line and a first phase-change memory cell line;

[0045] forming a second address line material layer on the first phase-change memory cell line;

[0046] The second address line material layer and the first phase-change memory cell line are subjected to a fifth etching process to form a second address ring and a first phase-change memory cell.

[0047] In the above solution, two adjacent second address rings in the plurality of second address rings are separated by a first distance along the first direction; and two adjacent second address lines in the plurality of second address lines are separated by a second distance along the first direction.

[0048] The first distance is twice the second distance.

[0049] In the above solution, the first phase-change memory unit includes a first electrode, a gating element, a second electrode, a phase-change memory element, and a third electrode that are stacked.

[0050] An embodiment of the present invention further provides a memory formed by using the method described in any of the above solutions.

[0051] A method for manufacturing a memory provided by an embodiment of the present invention includes: forming a plurality of first address lines, a plurality of first phase-change memory cells, and a plurality of second address rings arranged in a stacked manner; the first address lines extend along a first direction, the second address rings extend along a second direction perpendicular to the first direction, and the first phase-change memory cells are perpendicular to both the first and second directions; forming a plurality of second phase-change memory cell rings on the second address rings, all extending along the second direction; the second address rings and the second phase-change memory cell rings each having a first end and a second end arranged opposite to each other in the second direction; simultaneously removing the first ends and the second ends of the second address rings and the second phase-change memory cell rings to form a plurality of second address lines and a plurality of second phase-change memory cell lines; and using the second phase-change memory cell lines to form a plurality of second phase-change memory cells perpendicular to both the first and second directions. In an embodiment of the present invention, after forming the second address ring and the second phase-change memory cell ring, the first and second ends of the second address ring and the second phase-change memory cell ring are simultaneously removed to form a plurality of second address lines and a plurality of second phase-change memory cell lines. This simplifies the process steps compared to separately removing the first and second ends of the second address ring and the first and second ends of the second phase-change memory cell ring. Furthermore, simultaneously removing the first and second ends of the second address ring and the second phase-change memory cell ring can reduce the number of times the first and second ends are removed, thereby reducing damage to the address line connection portion caused by removing the first and second ends, thereby saving process costs and improving memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic diagram of a partial three-dimensional structure of a phase change memory according to an embodiment of the present invention;

[0053] Figure 2a A top view of a bit line layer structure of a phase change memory according to an embodiment of the present invention;

[0054] Figure 2b A top view of a word line layer structure of a phase change memory according to an embodiment of the present invention;

[0055] Figure 3a is a schematic top view of a phase change memory according to an embodiment of the present invention;

[0056] Figure 3b is an enlarged top view schematic diagram of a phase change memory according to an embodiment of the present invention;

[0057] Figure 3c FIG1 is a partial Z-direction schematic diagram of a phase change memory cell array having four stacked layers according to an embodiment of the present invention;

[0058] Figure 4a-4h3D schematic diagram of a method for manufacturing a phase change memory according to an embodiment of the present invention;

[0059] Figure 5a-5f A cross-sectional schematic diagram illustrating an implementation process of a method for manufacturing a phase change memory according to an embodiment of the present invention;

[0060] Figure 6 1 is a schematic diagram of an implementation flow of a method for manufacturing a phase change memory according to an embodiment of the present invention;

[0061] Figure 7a-7m A schematic three-dimensional structural diagram of an implementation process of another method for manufacturing a phase change memory according to an embodiment of the present invention;

[0062] Figure 8a-8l It is a cross-sectional schematic diagram of the implementation process of another method for manufacturing a phase change memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0063] The following describes exemplary embodiments of the present invention in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0064] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present invention; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0065] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0066] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present invention, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present invention.

[0067] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0068] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0069] The memory involved in the embodiments of the present invention may include a memory composed of bit lines, word lines, and memory cells that are staggered horizontally and vertically, including but not limited to phase change memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc. The following description only uses phase change memory as an example.

[0070] Figure 1 FIG. 1 is a schematic diagram of a partial three-dimensional architecture of a phase change memory provided by an embodiment of the present invention. Figure 1 As shown, the phase-change memory includes a first address line 101, a first phase-change memory unit 102, a second address line 103, a second phase-change memory unit 104, and a third address line 105, which are stacked sequentially from bottom to top. The first phase-change memory unit 102 and the second phase-change memory unit 104 each include a first electrode 1021, a gating element 1022, a second electrode 1023, a phase-change memory element 1024, and a third electrode 1025, which are stacked sequentially from bottom to top. The phase-change memory can transform the phase-change memory element 1024 between an amorphous state and a crystalline state by heating and quenching the phase-change memory element 1024, thereby utilizing the difference in resistivity between the amorphous state and the crystalline state of the phase-change memory element 1024 to store data.

[0071] from Figure 1 As can be seen, first address line 101 is parallel to third address line 105, and both first address line 101 and third address line 105 are perpendicular to second address line 103. Furthermore, first phase-change memory cell 102 is perpendicular to both first address line 101 and second address line 103, and second phase-change memory cell 104 is perpendicular to both second address line 103 and third address line 105. First address line 101 and third address line 105 can function as bit lines, while second address line 103 can function as a word line. In practical applications, phase-change memory cells connected to both a selected word line and a selected bit line are selected by activating the selected word line and bit line.

[0072] In practical applications, the first address line 101, the second address line 103, and the third address line 105 are usually formed by equal-width lines (L / S, Line / Space) with a line width of 20 nm / 20 nm formed after a patterning process. Considering that the distribution density of address lines (word lines and bit lines) in a memory is generally designed to be relatively high, that is, the gap between word lines or bit lines is very small, the resolution of a general lithography machine is not sufficient to directly form a strip pattern with a very small gap (the strip pattern with a very small gap is used as a mask for word lines or bit lines). In some embodiments, when forming the address lines of a phase change memory, a two-time self-aligned double patterning (SADP, Self-aligned Double Patterning) process can be used to form the address lines.

[0073] The specific process of the two-time self-aligned double patterning may include, after a series of processes, obtaining multiple bit line loops in a similar figure-eight shape before cutting as shown in Figure 2a and multiple word line loops in a similar figure-eight shape before cutting as shown in Figure 2b ; next, both sides of each bit line loop in a similar figure-eight shape are cut, for example, cut at the dotted line position in Figure 2a to form two adjacent bit lines. At the same time, both sides of each word line loop in a similar figure-eight shape are cut, for example, cut at the dotted line position in Figure 2b to form two adjacent word lines.

[0074] That is to say, in the related art, due to the insufficient lithography resolution, a mask that can be used to form the final word lines and bit lines is not directly formed. Instead, a structure similar to a figure-eight shape is first obtained as a word line loop or bit line loop in an intermediate state, and then both sides of the figure-eight shape structure are cut to obtain the final word lines or bit lines, thereby reducing the requirement for resolution. However, many problems may occur when cutting the word line loop or bit line loop in the intermediate state. For example, the additional cutting process not only increases the manufacturing cost of the memory, but also may cause damage to the word line connection part (here, the connection part can be expressed as Contact in English, and the connection part can also be called a contact) and the bit line connection part during the cutting process.

[0075] Figure 3a is a top view schematic diagram of a phase change memory in an embodiment of the present invention; Figure 3b is an enlarged top view schematic diagram of a phase change memory in an embodiment of the present invention; Figure 3c is a partial schematic diagram in the Z direction of a phase change memory cell array with four-layer stacking in an embodiment of the present invention. As can be seen from Figure 3a-3c , in a phase change memory in an embodiment of the present invention, there are multiple connection parts connecting word lines and bit lines distributed.

[0076] Figure 4a-4h A schematic diagram of a three-dimensional structure of an implementation process of a method for manufacturing a memory provided by an embodiment of the present invention. Figure 5a-5f A cross-sectional diagram of the implementation process of a method for manufacturing a memory provided by an embodiment of the present invention is provided. A method for manufacturing a memory provided by an embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0077] An embodiment of the present invention provides a method for manufacturing a memory, comprising:

[0078] forming a first address line material layer and a first phase-change memory cell material layer that are stacked;

[0079] like Figure 4a As shown, the first address line material layer and the first phase-change memory cell material layer are subjected to a fourth etching process to divide the first address line material layer and the first phase-change memory cell material layer into a first address ring 101' and a first phase-change memory cell ring 102' extending along the first direction; the first address ring 101' and the first phase-change memory cell ring 102' have third and fourth ends that are oppositely arranged in the first direction;

[0080] like Figure 4b As shown, the third end and the fourth end of the first address ring 101' and the first phase-change memory cell ring 102' are removed at the same time to form a first address line 101 and a first phase-change memory cell line 102';

[0081] forming a second address line material layer on the first phase-change memory cell line 102″;

[0082] like Figure 4c as well as Figure 5a As shown, the second address line material layer and the first phase-change memory cell line 102" are subjected to a fifth etching process to form a second address ring 103' and a first phase-change memory cell 102. The first address line 101 extends along a first direction, the second address ring 103' extends along a second direction perpendicular to the first direction, and the first phase-change memory cell 102 is perpendicular to both the first and second directions. The second address ring 103' has a first end and a second end that are oppositely disposed in the second direction.

[0083] like Figure 4d as well as Figure 5b As shown, the first end and the second end of the second address ring 103 ′ are removed to form a plurality of second address lines 103 ;

[0084] like Figure 4e as well as Figure 5cAs shown, a plurality of second phase-change memory cell rings 104' are formed on the second address line 103, all extending along the second direction; each of the second phase-change memory cell rings 104' has a first end and a second end that are oppositely arranged in the second direction;

[0085] like Figure 4f as well as Figure 5d As shown, the first end and the second end of the second phase-change memory cell ring 104' are removed to form a plurality of second phase-change memory cell lines 104".

[0086] The second phase-change memory cell lines 104 ″ are used to form a plurality of second phase-change memory cells 104 perpendicular to both the first direction and the second direction, and a plurality of third address lines 105 extending along the first direction are formed on the second phase-change memory cells 104 .

[0087] In some embodiments, the second phase-change memory cell line 104" is used to form a plurality of second phase-change memory cells 104 perpendicular to both the first direction and the second direction, and a plurality of third address lines 105 extending along the first direction are formed on the second phase-change memory cells 104, including:

[0088] forming a third address line material layer on the second phase-change memory cell line 104″;

[0089] like Figure 4g as well as Figure 5e As shown, the third address line material layer and the second phase-change memory cell line 104" are subjected to a second etching process to form a third address ring 105' and a second phase-change memory cell 104; the third address ring 105' extends along a first direction and has a third end and a fourth end oppositely disposed in the first direction, and the second phase-change memory cell 104 is perpendicular to both the first direction and the second direction;

[0090] A plurality of third address lines 105 extending along the first direction are formed on the second phase-change memory unit 104 by using the third address ring 105 ′.

[0091] In some embodiments, forming a plurality of third address lines 105 extending along the first direction on the second phase-change memory unit 104 using the third address ring 105 ′ includes:

[0092] like Figure 4h as well as Figure 5f As shown, the third end and the fourth end of the third address ring 105 ′ are removed, and a plurality of third address lines 105 extending along the first direction are formed on the second phase-change memory unit 104 ;

[0093] The method further comprises:

[0094] A third phase-change memory cell ring 106 ′ is formed on the third address line 105 ; the third phase-change memory cell ring 106 ′ extends along the first direction and has a third end and a fourth end oppositely disposed in the first direction;

[0095] The third end and the fourth end of the third phase-change memory cell ring 106 ′ are removed to form a third phase-change memory cell line 106 ″;

[0096] The third phase change memory cell line 106 ″ is used to form a plurality of third phase change memory cells 106 perpendicular to both the first direction and the second direction, and a plurality of fourth address lines 107 extending along the second direction are formed on the third phase change memory cells 106 .

[0097] The phase-change memory also includes a plurality of connectors connected to the first address line 101, the second address line 103, the third address line 105, and the fourth address line 107. In the phase-change memory, each of the plurality of phase-change memory cells needs to be coupled to an address line adjacent to the corresponding phase-change memory cell. To access the phase-change memory cells, each address line needs to be connected to a peripheral circuit via a corresponding connector.

[0098] It is understandable that in the method for manufacturing a phase change memory provided in the above embodiment, the first address ring 101', the first phase change memory cell ring 102', the second address ring 103', the second phase change memory cell ring 104', the third address ring 105', the fourth memory cell ring, and the fourth address ring 107' are first formed in an intermediate state similar to the U-shaped structure, and then the two sides of the U-shaped structure are cut to obtain the final address line and phase change memory cell. Since multiple cutting processes are required to remove the first end, the second end, the third end, and the fourth end, and as the number of stacked layers of the three-dimensional phase change memory increases, the required cutting processes will also increase accordingly. The increase in cutting processes is not only an increase in a process step, but these processes will also bring additional defect problems, such as damage to the address line connection portion.

[0099] Based on the above problems, an embodiment of the present invention proposes another method for manufacturing a memory. Figure 6 FIG. 1 is a flow chart showing the implementation of a method for manufacturing a memory, as shown in FIG. Figure 6 As shown, the method for manufacturing the memory includes:

[0100] Step 601: forming a plurality of first address lines 101, a plurality of first phase-change memory cells 102, and a plurality of second address rings 103' in a stacked arrangement; the first address lines 101 extend along a first direction, the second address rings 103' extend along a second direction perpendicular to the first direction, and the first phase-change memory cells 102 are perpendicular to both the first and second directions;

[0101] Step 602: forming a plurality of second phase-change memory cell rings 104' on the second address ring 103', each extending along the second direction; the second address ring 103' and the second phase-change memory cell ring 104' each having a first end and a second end oppositely disposed in the second direction;

[0102] Step 603: Simultaneously remove the second address ring 103' and the first end and the second end of the second phase-change memory cell ring 104' to form a plurality of second address lines 103 and a plurality of second phase-change memory cell lines 104".

[0103] Step 604 : Utilize the second phase-change memory cell line 104 ″ to form a plurality of second phase-change memory cells 104 perpendicular to both the first direction and the second direction.

[0104] Figure 7a-7m It is a three-dimensional structural diagram of the implementation process of a method for manufacturing a memory according to an embodiment of the present invention. Figure 8a-8l Schematic diagram of the cross section of the implementation process of the method for manufacturing a memory according to an embodiment of the present invention. Figure 7a-7m as well as Figure 8a-8l The manufacturing process of the memory according to the embodiment of the present invention is described in detail.

[0105] Among them, in step 601, reference Figure 7a-7c , mainly forming a plurality of first address lines 101, a plurality of first phase-change memory units 102 and a plurality of second address rings 103'.

[0106] In some embodiments, the forming of the plurality of first address lines 101, the plurality of first phase-change memory cells 102, and the plurality of second address rings 103' includes:

[0107] forming a first address line material layer and a first phase-change memory cell material layer that are stacked;

[0108] like Figure 7aAs shown, the first address line material layer and the first phase-change memory cell material layer are subjected to a fourth etching process to divide the first address line material layer and the first phase-change memory cell material layer into a first address ring 101' and a first phase-change memory cell ring 102' extending along the first direction; the first address ring 101' and the first phase-change memory cell ring 102' have third and fourth ends arranged opposite to each other in the first direction;

[0109] like Figure 7b As shown, the third end and the fourth end of the first address ring 101' and the first phase-change memory cell ring 102' are removed at the same time to form a first address line 101 and a first phase-change memory cell line 102';

[0110] forming a second address line material layer on the first phase-change memory cell line 102″;

[0111] like Figure 7c as well as Figure 8a-Figure 8b As shown, the second address line material layer and the first phase-change memory cell line 102 ″ are subjected to a fifth etching process to form a second address ring 103 ′ and a first phase-change memory cell 102 .

[0112] Here, the constituent material of the first address line material layer includes a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al) or polysilicon.

[0113] In some embodiments, the first phase-change memory unit 102 includes a first electrode, a gating element, a second electrode, a phase-change memory element, and a third electrode that are stacked.

[0114] The second phase-change memory unit 104 , the third phase-change memory unit 106 , and the fourth phase-change memory unit 108 may each include a first electrode, a gating element, a second electrode, a phase-change memory element, and a third electrode that are stacked.

[0115] Here, the stacking arrangement may be a stacking arrangement from top to bottom on the substrate, or a stacking arrangement from bottom to top on the substrate.

[0116] Here, forming the first phase-change memory cell material layer includes forming a first electrode material layer, a gate material layer, a second electrode material layer, a phase-change memory material layer, and a third electrode material layer that are stacked.

[0117] In practical applications, a first address line material layer, a first electrode material layer, a selection material layer, a second electrode material layer, a phase change storage material layer, and a third electrode material layer can be formed on the surface of the substrate through a deposition process, and the deposition process includes but is not limited to a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a combination thereof.

[0118] Here, the constituent material of the substrate may include semiconductor materials, such as silicon, germanium, or gallium arsenide.

[0119] Here, the constituent materials of the gating layer may include: threshold selection switch (OTS, Ovonic Threshold Switching) materials, such as zinc telluride (ZnaTeb), germanium telluride (GeaTeb), niobium oxide (NbaOb) or silicon arsenic telluride (SiaAsbTec), etc. The constituent materials of the phase change memory layer may include: chalcogenide-based alloys, such as GST (Ge-Sb-Te) alloys, but are not limited thereto. The constituent materials of the phase change memory layer may also include any other suitable phase change materials. It should be noted that when the phase change memory layer undergoes a phase change, the resistance of the phase change memory layer changes. The phase change memory can store data according to the change in the resistance state of the phase change memory layer.

[0120] Here, the material of the electrode may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide, or any combination thereof. In some specific embodiments, the material of the electrode includes carbon, such as amorphous carbon.

[0121] The first and second directions herein may be directions parallel to the substrate. In practical applications, the first direction may be understood as the X-axis direction shown in the accompanying drawings of the present invention, and it should be understood that the first direction is not limited to the X-axis direction. The second direction may be understood as the Y-axis direction shown in the accompanying drawings of the present invention, and it should be understood that the second direction is not limited to the Y-axis direction.

[0122] In practical applications, the fourth etching and the fifth etching include but are not limited to dry plasma etching.

[0123] In step 602 , the second phase-change memory cell ring 104 ′ is mainly formed.

[0124] like Figure 7d as well as Figure 8cAs shown, a second phase-change memory cell ring 104' is formed on the second address ring 103'.

[0125] In practical applications, forming the second phase-change memory cell ring 104' on the second address ring 103' includes forming a second phase-change memory cell material layer on the second address ring 103' and etching the second phase-change memory cell material layer to form the second phase-change memory cell ring 104'.

[0126] In some embodiments, the method further comprises:

[0127] Before forming a plurality of second phase-change memory cell rings 104' extending along the second direction on the second address ring 103', a sixth address ring 1010' is formed on the second address ring 103'; the sixth address ring 1010' extends along the second direction and has a first end and a second end oppositely disposed in the second direction;

[0128] The plurality of second phase-change memory cell rings 104' formed on the second address ring 103' and extending along the second direction include:

[0129] forming a plurality of second phase-change memory cell rings 104' on the sixth address ring 1010', all extending along the second direction;

[0130] The method of simultaneously removing the second address ring 103' and the first end and the second end of the second phase-change memory cell ring 104' to form a plurality of second address lines 103 and a plurality of second phase-change memory cell lines 104' includes:

[0131] At the same time, the second address ring 103', the sixth address ring 1010', and the first and second ends of the second phase-change memory cell ring 104' are removed to form the second address line 103, the sixth address line 1010, and the second phase-change memory cell line 104".

[0132] Among them, in step 603, if Figure 7e as well as Figure 8d As shown, a plurality of second address lines 103 and a plurality of second phase-change memory cell lines 104 are mainly formed.

[0133] Here, the second phase-change memory cell ring 104' can be understood as the second phase-change memory cell ring 104' having a hollow ring structure, and the second phase-change memory cell line 104" can be understood as the second phase-change memory cell line 104" having a solid linear structure. Specifically, the second phase-change memory cell ring 104' can refer to Figure 7dFor understanding, the second phase-change memory cell ring 104' is a hollow ring structure. For example, the second phase-change memory cell ring 104' can be a rectangular ring with two long sides and two short sides. When the second phase-change memory cell ring 104' is cut to form the second phase-change memory cell line 104", the two short sides are removed, and the parts of the two long sides close to the two short sides are removed at the same time. The two long sides of the remaining part are two parallel linear structures, that is, the following is formed. Figure 7e The second phase-change memory cell line 104″ shown in the figure and one second phase-change memory cell ring 104′ can form two second phase-change memory cell lines 104″. It should be noted that the second phase-change memory cell ring 104′ being a rectangular ring is only an exemplary description and is not used to limit the shape of the second phase-change memory cell ring 104′ in the present invention. The “ring” and “line” elsewhere in the embodiments of the present invention can also be understood with reference to the above explanation of the second phase-change memory cell ring 104′ and the second phase-change memory cell line 104″.

[0134] In some embodiments, the simultaneous removal of the second address ring 103' and the first end and the second end of the second phase-change memory cell ring 104' to form a plurality of second address lines 103 and a plurality of second phase-change memory cell lines 104" includes:

[0135] forming a first mask layer on the second phase-change memory cell ring 104';

[0136] The first mask layer is used to perform a first etching to simultaneously remove the second address ring 103' and the first and second ends of the second phase-change memory cell ring 104' to form a plurality of second address lines 103 and a plurality of second phase-change memory cell lines 104".

[0137] Here, the first mask layer may include a photoresist mask or a hard mask patterned based on a photolithography mask, for example, silicon nitride or the like.

[0138] It is understandable that the second address ring 103' and the first end and the second end of the second phase-change memory cell ring 104' are removed simultaneously, and the second address ring 103' and the second phase-change memory cell ring 104' are not removed separately. This can save process steps, reduce the amount of mask layer used, improve the process window, and reduce damage to the address line connection part.

[0139] In some embodiments, two adjacent second address rings 103 ′ in the plurality of second address rings 103 ′ are separated by a first distance along the first direction; and two adjacent second address lines 103 in the plurality of second address lines 103 are separated by a second distance along the first direction.

[0140] The first distance is twice the second distance.

[0141] It can be understood that after removing the first end and the second end of the second address ring 103', one second address ring 103' forms two second address lines 103, and the number of second address lines 103 is twice the number of second address rings 103'. Therefore, the distance between adjacent second address rings 103' is twice the distance between adjacent second address lines 103, and the spacing between each word line and each bit line is exactly the same.

[0142] In step 604 , the second phase-change memory unit 104 and the third address line 105 are mainly formed.

[0143] In some embodiments, before forming the second phase-change memory cell 104 , a third address line material layer is formed on the second phase-change memory cell line 104 ″;

[0144] The second phase-change memory cell line 104 ″ is used to form a plurality of second phase-change memory cells 104 perpendicular to both the first direction and the second direction, including:

[0145] like Figure 7f as well as Figure 8e As shown, the third address line material layer and the second phase-change memory cell line 104" are subjected to a second etching process to form a third address ring 105' and a second phase-change memory cell 104; the third address ring 105' extends along a first direction and has a third end and a fourth end oppositely disposed in the first direction, and the second phase-change memory cell 104 is perpendicular to both the first direction and the second direction;

[0146] The method further comprises:

[0147] A plurality of third address lines 105 extending along the first direction are formed on the second phase-change memory unit 104 by using the third address ring 105 ′.

[0148] In some embodiments, the method further comprises:

[0149] like Figure 7g as well as Figure 8f As shown, before forming the third address line 105, a third phase-change memory cell ring 106' is formed on the third address ring 105'; the third phase-change memory cell ring 106' extends along the first direction and has a third end and a fourth end oppositely arranged in the first direction;

[0150] The method of forming a plurality of third address lines 105 extending along the first direction on the second phase-change memory unit 104 by using the third address ring 105 ′ includes:

[0151] like Figure 7h as well as Figure 8gAs shown, the third end and the fourth end of the third address ring 105' and the third phase-change memory cell ring 106' are removed at the same time to form a third address line 105 and a third phase-change memory cell line 106".

[0152] The method further comprises:

[0153] The third phase-change memory cell line 106 ″ is used to form a plurality of third phase-change memory cells 106 perpendicular to both the first direction and the second direction.

[0154] In some embodiments, the method further comprises:

[0155] Before forming the third phase-change memory cell 106 , forming a fourth address line material layer on the third phase-change memory cell line 106 ″;

[0156] The third phase-change memory cell line 106 ″ is used to form a plurality of third phase-change memory cells 106 perpendicular to both the first direction and the second direction, including:

[0157] like Figure 7i as well as Figure 8h As shown, the fourth address line material layer and the third phase change memory cell line 106' are subjected to a third etching to form a third phase change memory cell 106 and a fourth address ring 107'. The third phase change memory cell 106 is perpendicular to both the first direction and the second direction.

[0158] In some embodiments, the method further comprises:

[0159] like Figure 7j as well as Figure 8i As shown, after the fourth address ring 107' is formed, a fourth phase-change memory cell ring 108' is formed on the fourth address ring 107'; the fourth address ring 107' and the fourth phase-change memory cell ring 108' both extend along the second direction and have a first end and a second end that are oppositely arranged in the second direction;

[0160] like Figure 7k as well as Figure 8j As shown, the first end and the second end of the fourth address ring 107' and the fourth phase-change memory cell ring 108' are removed at the same time to form a fourth address line 107 and a fourth phase-change memory cell line 108".

[0161] like Figure 7l-7m as well as Figure 8k-8l As shown, the fourth phase-change memory cell line 108" is used to form a plurality of fourth phase-change memory cells 108 perpendicular to both the first direction and the second direction, and a plurality of fifth address lines 109 extending along the first direction are formed on the fourth phase-change memory cells 108.

[0162] In some embodiments, the fourth phase-change memory cell line 108" is used to form a plurality of fourth phase-change memory cells 108 perpendicular to both the first direction and the second direction, and a plurality of fifth address lines 109 extending along the first direction are formed on the fourth phase-change memory cells 108, including:

[0163] forming a fifth address line material layer on the fourth phase-change memory cell line 108″;

[0164] The fifth address line material layer and the fourth phase-change memory cell line 108" are etched to form a fifth address ring 109' and a fourth phase-change memory cell 108; the fifth address ring 109' extends along the first direction and has a third end and a fourth end oppositely disposed in the first direction;

[0165] The third end and the fourth end of the fifth address ring 109 ′ are removed to form the fifth address line 109 .

[0166] It is understandable that in the embodiment of the present invention, through the joint adjustment of layout design and process, the first end and the second end of the second address ring 103' and the second phase-change memory cell ring 104' are removed at the same time, the third end and the fourth end of the third address ring 105' and the third phase-change memory cell ring 106' are removed at the same time, and the first end and the second end of the fourth address ring 107' and the fourth phase-change memory cell ring 108' are removed at the same time. In this way, three masks can be saved and three processes for removing the ring ends can be saved. As the number of stacked layers of the three-dimensional phase-change memory increases, the amount of photoresist saved will also increase accordingly. While saving photoresist, the process window will be improved and damage to the address line connection portion will be reduced.

[0167] A method for manufacturing a memory provided by an embodiment of the present invention includes: forming a plurality of first address lines, a plurality of first phase-change memory cells, and a plurality of second address rings arranged in a stacked manner; the first address lines extend along a first direction, the second address rings extend along a second direction perpendicular to the first direction, and the first phase-change memory cells are perpendicular to both the first and second directions; forming a plurality of second phase-change memory cell rings on the second address rings, all extending along the second direction; the second address rings and the second phase-change memory cell rings each having a first end and a second end arranged opposite to each other in the second direction; simultaneously removing the first ends and the second ends of the second address rings and the second phase-change memory cell rings to form a plurality of second address lines and a plurality of second phase-change memory cell lines; and using the second phase-change memory cell lines to form a plurality of second phase-change memory cells perpendicular to both the first and second directions. In an embodiment of the present invention, after forming the second address ring and the second phase-change memory cell ring, the first and second ends of the second address ring and the second phase-change memory cell ring are simultaneously removed to form a plurality of second address lines and a plurality of second phase-change memory cell lines. This simplifies the process steps compared to separately removing the first and second ends of the second address ring and the first and second ends of the second phase-change memory cell ring. Furthermore, simultaneously removing the first and second ends of the second address ring and the second phase-change memory cell ring can reduce the number of times the first and second ends are removed, thereby reducing damage to the address line connection portion caused by removing the first and second ends, thereby saving process costs and improving memory performance.

[0168] Based on the above-mentioned method for manufacturing a memory, an embodiment of the present invention further provides a memory, wherein the memory is formed by the method described in any one of the above-mentioned embodiments.

[0169] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention. The serial numbers of the above-mentioned embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0170] The methods disclosed in the several method embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method embodiments.

[0171] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be covered by the scope of protection of the present invention.

Claims

1. A method for manufacturing a memory, characterized in that: include: A plurality of first address lines, a plurality of first phase-change memory cells, and a plurality of second address rings are formed in a stacked manner; the first address lines extend along a first direction, the second address rings extend along a second direction perpendicular to the first direction, and the first phase-change memory cells are perpendicular to both the first and second directions; forming a sixth address ring on the second address ring; the sixth address ring extending along the second direction; A plurality of second phase-change memory cell rings are formed on the sixth address ring, all extending along the second direction; the second address ring, the sixth address ring, and the second phase-change memory cell ring all have first and second ends that are oppositely arranged in the second direction; forming a first mask layer on the second phase-change memory cell ring; Performing a first etching process using the first mask layer to simultaneously remove the second address ring, the sixth address ring, and the first end and the second end of the second phase-change memory cell ring to form a plurality of second address lines, a plurality of sixth address lines, and a plurality of second phase-change memory cell lines; The second phase-change memory cell lines are used to form a plurality of second phase-change memory cells perpendicular to both the first direction and the second direction.

2. The method according to claim 1, characterized in that Before forming the second phase-change memory cell, forming a third address line material layer on the second phase-change memory cell line; The method of forming a plurality of second phase-change memory cells perpendicular to both the first direction and the second direction by using the second phase-change memory cell line includes: Performing a second etching on the third address line material layer and the second phase-change memory cell line to form a third address ring and a second phase-change memory cell; the third address ring extends along a first direction and has a third end and a fourth end oppositely disposed in the first direction; and the second phase-change memory cell is perpendicular to both the first direction and the second direction; The method further comprises: A plurality of third address lines extending along a first direction are formed on the second phase-change memory unit by utilizing the third address ring.

3. The method according to claim 2, characterized in that The method further comprises: Before forming the third address line, forming a third phase-change memory cell ring on the third address ring; the third phase-change memory cell ring extends along the first direction and has a third end and a fourth end oppositely disposed in the first direction; The method of forming a plurality of third address lines extending along the first direction on the second phase-change memory unit by using the third address ring includes: Simultaneously removing the third end and the fourth end of the third address ring and the third phase-change memory cell ring to form a third address line and a third phase-change memory cell line; The method further comprises: The third phase-change memory cell line is used to form a plurality of third phase-change memory cells perpendicular to both the first direction and the second direction.

4. The method according to claim 3, characterized in that The method further comprises: Before forming the third phase-change memory cell, forming a fourth address line material layer on the third phase-change memory cell line; The method of forming a plurality of third phase-change memory cells perpendicular to both the first direction and the second direction by using the third phase-change memory cell line includes: The fourth address line material layer and the third phase-change memory cell line are subjected to a third etching process to form a third phase-change memory cell and a fourth address ring, wherein the third phase-change memory cell is perpendicular to both the first direction and the second direction.

5. The method according to claim 4, characterized in that The method further comprises: After forming the fourth address ring, forming a fourth phase-change memory cell ring on the fourth address ring; the fourth address ring and the fourth phase-change memory cell ring both extend along the second direction and have a first end and a second end oppositely disposed in the second direction; Simultaneously removing the first end and the second end of the fourth address ring and the fourth phase-change memory cell ring to form a fourth address line and a fourth phase-change memory cell line; The fourth phase-change memory cell line is used to form a plurality of fourth phase-change memory cells perpendicular to the first direction and the second direction, and a plurality of fifth address lines extending along the first direction are formed on the fourth phase-change memory cells.

6. The method according to claim 1, characterized in that The forming of a plurality of first address lines, a plurality of first phase-change memory units, and a plurality of second address rings includes: forming a first address line material layer and a first phase-change memory cell material layer that are stacked; performing a fourth etching on the first address line material layer and the first phase-change memory cell material layer to divide the first address line material layer and the first phase-change memory cell material layer into a first address ring and a first phase-change memory cell ring extending along a first direction; the first address ring and the first phase-change memory cell ring having a third end and a fourth end disposed opposite to each other in the first direction; Simultaneously removing the first address ring and the third end and the fourth end of the first phase-change memory cell ring to form a first address line and a first phase-change memory cell line; forming a second address line material layer on the first phase-change memory cell line; The second address line material layer and the first phase-change memory cell line are subjected to a fifth etching process to form a second address ring and a first phase-change memory cell.

7. The method according to claim 1, characterized in that Two adjacent second address rings in the plurality of second address rings are separated by a first distance along the first direction; two adjacent second address lines in the plurality of second address lines are separated by a second distance along the first direction; The first distance is twice the second distance.

8. The method according to claim 1, characterized in that The first phase-change memory unit includes a first electrode, a gating element, a second electrode, a phase-change memory element, and a third electrode that are stacked.

9. A memory, characterized in that: The method according to any one of claims 1 to 8 is used for forming the present invention.

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