Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: forming a first sidewall on a sidewall of a gate structure; forming source / drain doped regions in a substrate on both sides of the gate structure; forming a bottom dielectric layer on the gate structure and the sidewall of the first sidewall; forming a source / drain interconnection layer in the bottom dielectric layer and contacting the source / drain doped regions; forming a source / drain plug penetrating the bottom dielectric layer and the top dielectric layer at an end of the source / drain interconnection layer; forming a spacing opening penetrating the top dielectric layer at a top of the source / drain interconnection layer and exposing the first sidewall; removing the first sidewall exposed by the spacing opening to form a gap; filling an etching stop layer in the spacing opening to seal the gap and the gap to form an air gap; and forming a gate plug penetrating the top dielectric layer at a top of the gate structure. The embodiment of the present application reduces the risk of the material of the gate plug or the source / drain plug filling in the air gap, optimizes the performance of the semiconductor structure, and improves the process compatibility of forming the air gap and forming the gate plug and the source / drain plug.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and a substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped regions for connecting the source / drain doped regions to external circuitry.

[0003] Furthermore, as device dimensions shrink, the distance between the gate structure and the source / drain contact plugs is also decreasing. To reduce the coupling capacitance between the gate structure and the source / drain contact plugs, a method has been proposed to form an air gap sidewall between them. The air gap has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k or ultra-low-k dielectric materials), which helps to significantly reduce the coupling capacitance between the gate structure and the source / drain contact plugs.

[0004] However, the current semiconductor structure formation process still presents significant challenges. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the risk of material from the gate plug or source / drain plug filling the air gap and improves the process compatibility between forming the air gap and forming the gate plug and source / drain plug.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a plurality of gate structures disposed on the substrate; source / drain doped regions located within the substrate on both sides of the gate structures; a bottom dielectric layer located on the side of the gate structures and covering the source / drain doped regions; a top dielectric layer located on the bottom dielectric layer and covering the top of the gate structures; a source / drain interconnect layer penetrating the bottom dielectric layer at the top of the source / drain doped regions and in contact with the source / drain doped regions, wherein a gap exists between the source / drain interconnect layer and the sidewall of the gate structures; a source / drain plug penetrating the bottom dielectric layer and the top dielectric layer at the ends of the source / drain interconnect layer and in contact with the source / drain doped regions; an etch stop layer penetrating the top dielectric layer at the top of the source / drain interconnect layer, wherein the etch stop layer seals the gap and forms an air gap with the gap; and a gate plug penetrating the top dielectric layer at the top of the gate structures and in contact with the gate structures.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein discrete gate structures are formed on the substrate, a first sidewall is formed on the sidewall of the gate structure, source / drain doped regions are formed in the substrate on both sides of the gate structure, a bottom dielectric layer covering the source / drain doped regions is formed on the side of the gate structure and the first sidewall, a source / drain interconnect layer in contact with the source / drain doped regions is formed in the bottom dielectric layer, a top dielectric layer is formed on the bottom dielectric layer, a source / drain plug penetrating the bottom dielectric layer and the top dielectric layer is formed at the end of the source / drain interconnect layer and in contact with the source / drain doped regions, and a spacer opening penetrating the top dielectric layer is formed at the top of the source / drain interconnect layer to expose the first sidewall; removing the first sidewall exposed by the spacer opening to form a gap between the source / drain interconnect layer and the gate structure; filling the spacer opening with an etch stop layer, and the etch stop layer seals the gap and forms an air gap with the gap; after forming the etch stop layer, forming a gate plug penetrating the top of the gate structure and in contact with the gate structure.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by this invention, there is a gap between the source / drain interconnect layer and the sidewall of the gate structure. The semiconductor structure also includes an etch barrier layer that penetrates the top dielectric layer above the source / drain interconnect layer. The etch barrier layer seals the gap and forms an air gap with the gap. The etch barrier layer has an etch selectivity ratio with the top dielectric layer or the bottom dielectric layer. The etch barrier layer is not easily etched during the semiconductor structure formation process (e.g., the formation process of the gate plug), thereby protecting and sealing the air gap. This prevents the etch barrier layer from being etched open, which would allow other materials (e.g., the material of the gate plug) to fill the air gap. This ensures the effectiveness of the air gap in reducing the coupling capacitance between the gate structure and the source / drain interconnect layer, thereby optimizing the performance of the semiconductor structure.

[0010] In the semiconductor structure formation method provided in the embodiments of the present invention, after providing the source-drain interconnect layer and the source-drain plug, and the spacer opening exposing the first sidewall, the first sidewall exposed by the spacer opening is removed to form a gap, and then an etch barrier layer is formed in the spacer opening to seal the gap and form an air gap. In this embodiment of the invention, since the air gap is formed after the source-drain interconnect layer and the source-drain plug, material from the source-drain interconnect layer and the source-drain plug is prevented from filling the air gap. Furthermore, after the gap is formed, an etch barrier layer is formed to seal the gap. The etch barrier layer has an etch selectivity with the top dielectric layer. The process of forming the gate plug typically includes the step of forming a gate contact hole. The process of forming the gate contact hole has a low probability of damaging the etch barrier layer, thereby reducing the risk of the air gap being opened during the formation of the gate contact hole. This helps prevent the problem of gate plug material filling the air gap. In summary, this embodiment of the invention can reduce the risk of gate plug or source-drain plug material filling the air gap, ensuring the effectiveness of the air gap in reducing the coupling capacitance between the gate structure and the source-drain interconnect layer, thereby optimizing the performance of the semiconductor structure. It also improves the process compatibility between forming the air gap and forming the gate plug and source-drain plug. Attached Figure Description

[0011] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 10 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] As the background technology shows, the current semiconductor structure formation process still presents significant challenges. Specifically, the formation of air gap sidewalls remains particularly challenging. This paper analyzes the reasons for these challenges in forming air gap sidewalls, using a semiconductor structure formation method as an example.

[0014] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 The system provides a substrate 10, a gate structure 20 on the substrate 10, a first sidewall 32 on the sidewall of the gate structure 20, source / drain doped regions 11 on both sides of the gate structure 20 within the substrate 10, and a bottom dielectric layer 12 on the side of the gate structure 20 and covering the source / drain doped regions 11.

[0016] refer to Figure 2 A source-drain interconnect layer 40 is formed that penetrates the bottom dielectric layer 12 and is in contact with the source-drain doped region 11.

[0017] refer to Figure 3 Remove the first sidewall 30 to form a gap 35 between the sidewall of the gate structure 20 and the source-drain interconnect layer 30.

[0018] refer to Figure 4 A sealing layer 13 is formed on the sidewall and bottom of the gap 35, and the sealing layer 13 located at the top corner of the gap 35 is in contact with each other, thus sealing the gap 35 to form an air gap 50.

[0019] refer to Figure 5 A top dielectric layer 14 is formed on the bottom dielectric layer 12, covering the source-drain interconnect layer 40, the sealing layer 13, and the gate structure 20.

[0020] refer to Figures 6 to 7 A source / drain contact plug 60 is formed, penetrating the top dielectric layer 14 of the source / drain interconnect layer 40 and contacting the source / drain interconnect layer 40. The step of forming the source / drain contact plug 60 typically includes: forming a source / drain contact hole 61 penetrating the top dielectric layer 14 of the source / drain interconnect layer 40 to expose the source / drain interconnect layer 40; and filling the source / drain contact hole 61 with a conductive material to form the source / drain contact plug 60.

[0021] refer to Figures 8 to 9 A gate contact plug 70 is formed, penetrating the top dielectric layer 14 of the gate structure 20 and contacting the gate structure 20. The step of forming the gate contact plug 70 typically includes: forming a gate contact hole 71 penetrating the top dielectric layer 14 of the gate structure 20 to expose the gate structure 20; and filling the gate contact hole 71 with a conductive material to form the gate contact plug 70.

[0022] In the above forming method, when forming the source / drain contact hole 61 (e.g. Figure 6 (as shown) or gate contact hole 71 (as shown) Figure 8 During the process (as shown), the top of the sealing layer 13 is easily etched, causing the top of the air gap 50 to be opened. Accordingly, conductive material (such as...) is filled into the source / drain contact hole 61. Figure 7 (as shown), and filling the gate contact hole 71 with conductive material (such as...) Figure 8 During the process shown, conductive material can easily fill the air gap 50, which reduces the effectiveness of the air gap 50 in reducing parasitic capacitance, thereby leading to reduced device performance or device failure.

[0023] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. After providing a source / drain interconnect layer, a source / drain plug, and a spacer opening exposing a first sidewall, the first sidewall exposed by the spacer opening is removed to form a gap. Subsequently, an etch barrier layer is formed in the spacer opening to seal the gap and form an air gap. Since the air gap is formed after the source / drain interconnect layer and the source / drain plug, material from the source / drain interconnect layer and the source / drain plug is prevented from filling the air gap. Furthermore, after forming the gap, an etch barrier layer is formed to seal the gap, and the etch barrier layer and the top dielectric layer have an etch selectivity. In contrast, the process of forming a gate plug typically includes the step of forming a gate contact hole. The process of forming a gate contact hole has a low probability of damaging the etch barrier layer, thereby reducing the risk of the air gap being opened during the formation of the gate contact hole. Correspondingly, this helps to prevent the problem of gate plug material filling the air gap. In summary, the embodiments of the present invention can reduce the risk of gate plug or source / drain plug material filling the air gap, ensure the effectiveness of the air gap in reducing the coupling capacitance between the gate structure and the source / drain interconnect layer, and also improve the process compatibility of forming the air gap with forming the gate plug and source / drain plug.

[0024] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] For ease of understanding, the method for forming the semiconductor structure according to the embodiments of the present invention will be described in detail below. Figures 10 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0026] refer to Figures 10 to 15A substrate 100 is provided, on which discrete gate structures 110 are formed. A first sidewall 130 is formed on the sidewall of the gate structure 110. Source and drain doped regions 140 are formed in the substrate 100 on both sides of the gate structure 110. A bottom dielectric layer 115 covering the source and drain doped regions 140 is formed on the side of the gate structure 110 and the first sidewall 130. A source and drain interconnect layer 150 in contact with the source and drain doped regions 140 is formed in the bottom dielectric layer 115. A top dielectric layer 125 is formed on the bottom dielectric layer 115. A source and drain plug 160 penetrating the bottom dielectric layer 115 and the top dielectric layer 125 is formed at the end of the source and drain interconnect layer 150 and in contact with the source and drain doped regions 140. A spaced opening 170 penetrating the top dielectric layer 125 is formed at the top of the source and drain interconnect layer 150, exposing the first sidewall 130.

[0027] Substrate 100 is used to provide a process platform for subsequent process manufacturing.

[0028] In this embodiment, the substrate 100 is a three-dimensional substrate, which includes a substrate and a channel structure located on the substrate. The channel structure is used to provide a conductive channel for the transistor to operate.

[0029] In this embodiment, the channel structure is along the transverse direction (e.g. Figure 12 (As shown in the X direction). Specifically, there are multiple channel structures, which are arranged at intervals along the longitudinal direction, perpendicular to the transverse direction.

[0030] As an example, substrate 100 is used to form a fin field-effect transistor (FinFET), with a fin-like channel structure. In other embodiments, depending on the type of transistor actually formed, the channel structure can be other types of channel structures, for example, when forming a fully enclosed gate transistor, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced channel layers. In other embodiments, the substrate can also be a planar substrate. In this embodiment, the fin and the substrate are made of the same material, which is silicon. In other embodiments, the fin and the substrate can be made of other suitable materials.

[0031] The gate structure 110 is used to control the turn-on and turn-off of the conductive channel of the field-effect transistor.

[0032] In this embodiment, the gate structure 110 is along the longitudinal direction (e.g., Figure 12 Extending in the Y direction (as shown), the direction parallel to the surface of the substrate 100 and perpendicular to the longitudinal direction is the transverse direction. In this embodiment, the gate structure 110 is located on the substrate, and the gate structure 110 spans the fin and covers part of the top and part of the sidewalls of the fin.

[0033] In this embodiment, the gate structure 110 is a metal gate structure, including a high-k gate dielectric layer, a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer. In other embodiments, depending on actual process requirements, the gate structure can also be a polysilicon gate structure.

[0034] The high-k gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the substrate 100. The material of the high-k gate dielectric layer is a high-k dielectric material. The work function layer is used to adjust the work function of the gate structure 110. The gate electrode layer is used as an external electrode for connecting the gate structure 110 to external circuits or interconnect structures.

[0035] In this embodiment, a gate cap layer 120 is also formed on the top of the gate structure 110. The gate cap layer 120 is used to protect the top of the gate structure 110. For example, in the step of forming the source-drain plug 160 and the source-drain interconnect layer 150, the gate cap layer 120 is used to protect the top of the gate structure 110 to prevent short circuits between the source-drain plug 160 or the source-drain interconnect layer 150 and the gate structure 110.

[0036] The gate cap layer 120 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the gate cap layer 120 is made of silicon nitride.

[0037] The first sidewall 130 is used to protect the sidewall of the gate structure 110. The first sidewall 130 is also used to isolate the gate structure 110 from the source-drain interconnect layer 150 or the source-drain plug 160. The first sidewall 130 located between the source-drain interconnect layer 150 and the gate structure 110 is also used as a pseudo sidewall, which is subsequently removed to form a gap.

[0038] In this embodiment, the first sidewall 130 is located on the sidewall of the gate structure 110 and the gate cap layer 120.

[0039] The first sidewall 130 is located between the gate structure 110 and the source / drain plug 160, and it also affects the parasitic capacitance between the gate structure 110 and the source / drain plug 160. Therefore, the dielectric constant of the material of the first sidewall 130 cannot be too high. In addition, the first sidewall 130 has an etch selectivity with the bottom dielectric layer 115 or the top dielectric layer 125 and the gate cap layer 120 to facilitate the subsequent removal of the first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110.

[0040] In this embodiment, the material of the first sidewall 130 includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, low-k dielectric material, and ultra-low-k dielectric material. As an example, the first sidewall 130 is a single-layer structure, thereby reducing the process complexity of subsequently removing the first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110. Specifically, the material of the first sidewall 130 is a low-k dielectric material.

[0041] In this embodiment, a second sidewall 132 is formed at the bottom of the first sidewall 130 and between the sidewall of the first sidewall 130 and the sidewall of the gate structure 110, and a third sidewall 133 is formed on the sidewall of the first sidewall 130 opposite to the sidewall of the gate structure 110.

[0042] The first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110 is subsequently removed, leaving a gap formed by the second sidewall 132 and the third sidewall 133. The second sidewall 132 and the third sidewall 133 surround the sidewall and bottom of the first sidewall 130, which helps reduce the likelihood of damage to the gate structure 110, the substrate 100, and the source / drain doped region 140 during the subsequent removal of the first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110.

[0043] Accordingly, the second sidewall 132 or the third sidewall 133 has an etching selectivity ratio with the first sidewall 130, so that the second sidewall 132 and the third sidewall 133 are not easily damaged in the subsequent step of removing the first sidewall 130 between the source-drain interconnect layer 150 and the gate structure 110.

[0044] As an example, the material of the second sidewall 132 and the third sidewall 133 is silicon nitride.

[0045] The source / drain doped regions 140 are used to provide a carrier source. In this embodiment, the source / drain doped regions 140 are also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped regions 140 are located in the fins on both sides of the gate structure 110.

[0046] When forming an NMOS transistor, the source / drain doped region 140 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doped region 140 includes a stress layer doped with P-type ions.

[0047] The bottom dielectric layer 115 is used to provide isolation between adjacent gate structures 110. The top dielectric layer 125 is used to provide electrical isolation between source / drain plugs 160 and between source / drain plugs 160 and gate plugs.

[0048] The bottom dielectric layer 115 and the top dielectric layer 125 are made of dielectric materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0049] The source-drain interconnect layer 150 is used to realize the connection between the source-drain doped regions 140 located in the multiple channel structure layers. The source-drain interconnect layer 150 is also connected to the source-drain plug 160 for electrical connection with external circuits through the source-drain plug 160.

[0050] The source / drain plug 160 is used to realize the electrical connection between the source / drain doped region 140 and the external circuit. Specifically, the source / drain plug 160 is located at one end of the source / drain interconnect layer 150 and is in contact with the source / drain interconnect layer 150.

[0051] In this embodiment, the source-drain interconnect layer 150 and the source-drain plug 160 are an integral structure, which is beneficial to improve the contact performance between the source-drain interconnect layer 150 and the source-drain plug 160, thereby reducing the contact resistance between the source-drain interconnect layer 150 and the source-drain plug 160 and improving the electrical connection performance of the semiconductor structure.

[0052] The source-drain interconnect layer 150 and the source-drain plug 160 are made of conductive materials, such as one or more of W, Co, Ru, Cu, and Al. In this embodiment, the source-drain interconnect layer 150 and the source-drain plug 160 are made of the same material.

[0053] The spacer opening 170 extends through the top dielectric layer 125 above the source / drain interconnect layer 150 and exposes the first sidewall 130 to facilitate subsequent removal of the first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110 through the spacer opening 170. The spacer opening 170 also provides space for forming an etch barrier layer.

[0054] The following, in conjunction with the accompanying drawings, details the steps of providing a substrate 100, a gate structure 110, a first sidewall 130, a source / drain doped region 140, a bottom dielectric layer 115, a top dielectric layer 125, a source / drain interconnect layer 150, a source / drain plug 160, and a spacer opening 170 in this embodiment.

[0055] like Figure 10 As shown, a substrate 100, a gate structure 110, a first sidewall 130, a source / drain doped region 140, and a bottom dielectric layer 115 are provided.

[0056] As an example, the gate structure 110 is formed by a process of forming a high k last metal gate last after forming a high k last gate dielectric layer. Therefore, the steps of providing a substrate 100, a gate structure 110, a first sidewall 130, a source / drain doped region 140, and a bottom dielectric layer 115 may include: providing a substrate 100; forming a dummy gate structure (not shown) on the substrate 100; forming a first sidewall 130 on the sidewall of the dummy gate structure; forming source / drain doped regions 140 in the substrate 100 on both sides of the dummy gate structure; forming a bottom dielectric layer 115 covering the source / drain doped regions 140 on the sides of the dummy gate structure and the first sidewall 130; removing the dummy gate structure and forming a gate opening (not shown) in the bottom dielectric layer 115; and forming the gate structure 110 in the gate opening.

[0057] The method for forming a semiconductor structure after forming a gate structure 110 in the gate opening further includes: removing a portion of the thickness of the gate structure 110; and filling the top of the remaining gate structure 110 with a gate cap layer 120.

[0058] like Figure 10 As shown, a top dielectric layer 125 is formed on the bottom dielectric layer 115.

[0059] like Figures 11 to 13 As shown, the source / drain contact material 180, which forms the bottom dielectric layer 115 and the top dielectric layer 125 through the top of the source / drain doped region 140, includes an interconnect region 180a and a plug region 180b located at the end of the interconnect region 180a.

[0060] The source / drain contact material 180 of interconnect region 180a is used to form a source / drain interconnect layer after subsequent etching process, and the source / drain contact material 180 of plug region 180b is used to form a source / drain plug.

[0061] In this embodiment, a source / drain contact material 180 with an integral structure is first formed, and then the source / drain contact material 180 of the interconnect region 180a is removed to form a source / drain interconnect layer and a source / drain plug. Accordingly, the source / drain interconnect layer and the source / drain plug formed subsequently are an integral structure, which is beneficial to improving the contact performance between the source / drain interconnect layer and the source / drain plug.

[0062] In this embodiment, the step of forming the source / drain contact material 180 includes: as follows Figure 11 As shown, a source / drain contact opening 185 is formed, penetrating the bottom dielectric layer 115 and the top dielectric layer 125, exposing the source / drain doped region 140; as Figure 12 and Figure 13 As shown, Figure 12 This is a top view. Figure 13 for Figure 12 A cross-sectional view along the bb direction shows that source / drain contact material 180 is formed in the source / drain contact opening 185.

[0063] The source / drain contact opening 185 is used to provide space for the formation of the source / drain contact material 180.

[0064] In this embodiment, the step of forming source / drain contact material 180 in source / drain contact opening 185 includes: filling source / drain contact opening 185 with initial source / drain contact material (not shown), the initial source / drain contact material also being formed on top dielectric layer 125; removing the initial source / drain contact material located on top dielectric layer 125, and using the remaining initial source / drain contact material filling source / drain contact opening 185 as source / drain contact material 180.

[0065] In this embodiment, based on the actual process, one or more of chemical vapor deposition, physical vapor deposition, and electrochemical plating processes are used to form the initial source / drain contact material; a planarization process (e.g., chemical mechanical planarization) is used to remove the initial source / drain contact material located on the top dielectric layer 125.

[0066] like Figure 14 and Figure 15 As shown, Figure 14 This is a top view. Figure 15 for Figure 14 In the cross-sectional view along the aa direction, the source / drain contact material 180 located in the interconnect region 180a and above the first sidewall 130 is removed to form a spacer opening 170, exposing the first sidewall 130. The remaining source / drain contact material 180 in the interconnect region 180a is used as the source / drain interconnect layer 150, and the source / drain contact material 180 in the plug region 180b is used as the source / drain plug 160.

[0067] By forming the source / drain interconnect layer 150 and the source / drain plug 160 in the same step, the process is simplified. Furthermore, compared to the approach of forming the source / drain interconnect layer in the bottom dielectric layer that contacts the source / drain doped region, and then forming the source / drain plug that penetrates the top dielectric layer and contacts the source / drain interconnect layer, this embodiment eliminates the need for alignment between the source / drain plug 160 and the source / drain interconnect layer 150 during the formation of the source / drain interconnect layer 150 and the source / drain plug 160. This helps prevent alignment overlay problems between the source / drain plug 160 and the source / drain interconnect layer 150. This reduces the process difficulty of forming the source / drain plug 160 and increases the process window for forming the source / drain plug 160. Furthermore, the source / drain plug 160 and the source / drain interconnect layer 150 are an integral structure, which helps to reduce the resistance of the source / drain plug 160 and the source / drain interconnect layer 150, as well as the contact resistance of the source / drain plug 160 and the source / drain interconnect layer 150. This improves the electrical connection performance between the source / drain plug 160 and the source / drain interconnect layer 150, thereby improving the downstream RC (resistor-capacitor) delay, reducing power consumption, and increasing the circuit response speed. The performance of the semiconductor structure is thus improved.

[0068] Furthermore, in the step of removing the source / drain contact material 180 located in the interconnect region 180a and above the first sidewall 130 to form the source / drain interconnect layer 150 and the source / drain plug 160, a spacer opening 170 exposing the first sidewall 130 is simultaneously formed. Accordingly, there is no need to perform an additional step of forming the spacer opening 170, which also helps to simplify the process and improve production efficiency. Moreover, the position of the spacer opening 170 corresponds to that of the source / drain interconnect layer 150, which also helps to improve the positional accuracy of the spacer opening 170. In addition, in this embodiment, the source / drain interconnect layer 150, the source / drain plug 160 and the spacer opening 170 are formed in the same step, which also helps to save the photomask and thus save process costs.

[0069] Accordingly, in this embodiment, the spacer opening 170 is formed by the source / drain plug 160, the source / drain interconnect layer 150, and the top dielectric layer 125.

[0070] In this embodiment, the step of removing the source / drain contact material 180 located in the interconnect region 180a and higher than the first sidewall 130 includes: forming a hard mask layer 135 on the source / drain contact material 180 in the plug region 180b, the hard mask layer 135 exposing the source / drain contact material 180 in the interconnect region 180a; and removing the source / drain contact material 180 higher than the first sidewall 130 using the hard mask layer 135 as a mask.

[0071] The hard mask layer 135 is used as a mask for etching the source / drain contact material 180. In this embodiment, the hard mask layer 135 corresponds to the position of the source / drain plug.

[0072] In actual processes, depending on the requirements, one or both of dry etching and wet etching processes are selected to remove the source / drain contact material 180 located in the interconnect region 180a and above the first sidewall 130.

[0073] It should be noted that, in this embodiment, for ease of illustration and explanation, only the bottom dielectric layer 115 and the top dielectric layer 125 are shown in the cross-sectional view.

[0074] It should also be noted that the steps of providing the substrate 100, gate structure 110, first sidewall 130, source / drain doped region 140, bottom dielectric layer 115, top dielectric layer 125, source / drain interconnect layer 150, source / drain plug 160, and spacer opening 170 described above are only examples. The steps of providing the substrate 100, gate structure 110, first sidewall 130, source / drain doped region 140, bottom dielectric layer 115, top dielectric layer 125, source / drain interconnect layer 150, source / drain plug 160, and spacer opening 170 in this embodiment are not limited to this.

[0075] For example, in other embodiments, the steps of providing a substrate, a gate structure, a first sidewall, a source / drain doped region, a bottom dielectric layer, a top dielectric layer, a source / drain interconnect layer, a source / drain plug, and a spacer opening may further include: providing a substrate, a gate structure, a first sidewall, a source / drain doped region, and a bottom dielectric layer; forming a source / drain interconnect layer and a bottom plug located at the end of the source / drain interconnect layer in the bottom dielectric layer, both of the source / drain interconnect layer and the bottom plug being in contact with the source / drain doped region; forming a top dielectric layer on the bottom dielectric layer; forming a top plug in the top dielectric layer that penetrates the top of the bottom plug, the top plug and the bottom plug constituting a source / drain plug; and after forming the top plug, forming a spacer opening in the top dielectric layer that penetrates the top of the source / drain interconnect layer, exposing the first sidewall.

[0076] refer to Figure 16 and Figure 17 , Figure 16 This is a top view. Figure 17 for Figure 16 A cross-sectional view along the aa direction shows the first sidewall 130 exposed by the spacer opening 170 removed, forming a gap 190 between the source / drain interconnect layer 150 and the gate structure 110.

[0077] A gap 190 is formed between the source / drain interconnect layer 150 and the gate structure 110 so that after the subsequent formation of the etch barrier layer sealing the gap 190, the etch barrier layer and the gap 190 form an air gap.

[0078] Accordingly, an air gap is subsequently formed between the source / drain interconnect layer 150 and the gate structure 110. In semiconductor processes, the length of the source / drain interconnect layer 150 is typically much greater than the length of the source / drain plug 160 along the vertical direction. Compared to the relative area between the source / drain plug 160 and the gate structure 110, the relative area between the source / drain interconnect layer 150 and the gate structure 110 is larger. By forming an air gap between the source / drain interconnect layer 150 and the gate structure 110, the coupling capacitance between the source / drain interconnect layer 150 and the gate structure 110 can be reduced, thereby significantly reducing the parasitic capacitance of the semiconductor structure and improving the performance of the semiconductor structure.

[0079] Furthermore, compared to removing the first sidewall between the source / drain plug and the gate structure or removing all of the first sidewalls, in this embodiment, removing only the first sidewall 130 exposed by the spacer opening 170 helps to reduce the difficulty of forming the gap 190 and improves compatibility with existing processes.

[0080] In this embodiment, since the gap 190 and the subsequent air gap are formed after the source-drain interconnect layer 150 and the source-drain plug 160, the material of the source-drain interconnect layer 150 and the source-drain plug 160 is prevented from filling the air gap. This ensures the effectiveness of the air gap in reducing the coupling capacitance between the gate structure 110 and the source-drain interconnect layer 150, thereby optimizing the performance of the semiconductor structure and improving the process compatibility between forming the air gap and forming the source-drain plug 160.

[0081] Specifically, in this embodiment, the first sidewall 130 exposed by the gap opening 170 is removed, so that the second sidewall 132 and the third sidewall 133 form a gap 190.

[0082] In this embodiment, the process of removing the first sidewall 130 exposed by the spacer opening 170 includes one or both of dry etching and wet etching.

[0083] After the first sidewall 130 exposed by the spacer opening 170 is removed to form a gap 190, the gap 190 is connected to the spacer opening 170. The lateral dimension of the gap 190 is small, so that during the subsequent process of forming an etching barrier layer in the spacer opening 170, the etching barrier layer will not fill the gap 190 completely, thereby sealing the top of the gap 190.

[0084] In this embodiment, after forming the gap 190, the forming method further includes: removing the hard mask layer 135.

[0085] refer to Figures 18 to 20 , Figure 18 This is a top view. Figure 19 for Figure 18 Cross-sectional view along the aa direction. Figure 20 for Figure 18 In the cross-sectional view along the bb direction, the etch barrier layer 210 is filled in the spaced opening 170, and the etch barrier layer 210 seals the gap 190, forming an air gap 200 with the gap 190.

[0086] The air gap 200 has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), which helps to further reduce the effective capacitance between the gate structure 110 and the source-drain interconnect layer 150, reduce RC delay, and thus improve the performance of the semiconductor structure.

[0087] In this embodiment, an etch barrier layer 210 is formed to form a sealing gap 190. The etch barrier layer 210 and the top dielectric layer 125 have an etch selectivity ratio. The subsequent process of forming the gate plug usually includes the step of forming a gate contact hole through the top dielectric layer 125 of the gate structure 110. The process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, thereby reducing the risk that the air gap 200 will be opened during the process of forming the gate contact hole. Correspondingly, it is beneficial to prevent the material of the gate plug from filling into the air gap 200.

[0088] Moreover, the subsequent process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, reducing the risk of short circuit between the gate plug and the source-drain interconnect layer 150 and improving the reliability of the semiconductor structure.

[0089] Furthermore, in this embodiment, a gate plug that contacts the gate structure 110 is subsequently formed in the top dielectric layer 125 between adjacent etch stop layers 210 along the lateral direction. The etch stop layer 210 can also define the formation position of the gate plug along the lateral direction, thereby realizing the self-alignment of the gate plug position, which helps to reduce the formation difficulty of the gate plug and accurately locate the formation position of the gate plug.

[0090] Therefore, the etch barrier layer 210 is made of a material with high etch selectivity between it and the top dielectric layer 125. Moreover, in this embodiment, the subsequent gate plug penetrates the gate cap layer 120 and the top dielectric layer 125 at the top of the gate structure 110, and the etch barrier layer 210 and the gate cap layer 120 also have a high etch selectivity ratio, so as to prevent the process of forming the gate plug from causing mis-etching of the etch barrier layer 210.

[0091] As an example, the etching barrier layer 210 can be made of materials commonly used in source and drain capping layers in semiconductor processes, so as to ensure that the etching barrier layer 210, the top dielectric layer 125 and the gate capping layer 120 all have high etching selectivity, thereby enabling the etching barrier layer 210 to protect the air gap 200 and the source and drain interconnect layer 150, while also improving compatibility with existing processes.

[0092] In this embodiment, the material of the etch barrier layer 210 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the etch barrier layer 210 is silicon carbide.

[0093] In this embodiment, the step of forming the etching barrier layer 210 includes: filling the spacer opening 170 with a barrier material layer (not shown), the barrier material layer sealing the gap 190 and also forming on the top dielectric layer 125; removing the barrier material layer located on the top dielectric layer 125, and the remaining barrier material layer filling the spacer opening 170 as the etching barrier layer 210.

[0094] In this embodiment, based on the actual dimensions of the gap 190 in the transverse direction, the process of forming the barrier material layer is reasonably adjusted to ensure that the barrier material layer does not completely fill the gap 190, thereby achieving a seal on the gap 190, while also filling the gap opening 170.

[0095] In this embodiment, the process for forming the barrier material layer includes chemical vapor deposition (CVD). CVD is a low-cost, mature process with high compatibility.

[0096] In this embodiment, a planarization process (e.g., chemical mechanical planarization) is used to remove the barrier material layer on the top dielectric layer 125, which helps to improve the flatness and height consistency of the top surface of the etch barrier layer 210, the top dielectric layer 125, and the source / drain plug 160, so as to provide a flat surface for subsequent processes.

[0097] refer to Figures 21 to 23 , Figure 21 This is a top view. Figure 22 for Figure 21 Cross-sectional view along the aa direction. Figure 23 for Figure 21 In the cross-sectional view along the bb direction, after the etch barrier layer 210 is formed, a gate plug 220 is formed that penetrates the top dielectric layer 125 of the gate structure 110 and is in contact with the gate structure 110.

[0098] The gate plug 220 is used to realize the electrical connection between the gate structure 110 and the external circuit.

[0099] The process of forming the gate plug 220 typically includes forming a gate contact hole through the top dielectric layer 125 of the gate structure 110. The etch selectivity between the etch barrier layer 210 and the top dielectric layer 125 reduces the likelihood of damage to the etch barrier layer 210 during the formation of the gate contact hole, thereby reducing the risk of the air gap 200 being opened during the formation of the gate contact hole. This also prevents material from the gate plug 220 from filling the air gap 200, ensuring the effectiveness of the air gap 200 in reducing the coupling capacitance between the gate structure 110 and the source-drain interconnect layer 150, optimizing the performance of the semiconductor structure, and improving the process compatibility between forming the air gap 200 and forming the gate plug 220 and the source-drain plug 160.

[0100] In this embodiment, the gate plug 220 is made of a conductive material, such as one or more of W, Co, Ru, Cu and Al.

[0101] In this embodiment, the step of forming the gate plug 220 includes: using the etch stop layer 210 as the etch stop layer in the lateral direction, forming the gate plug 220 in the top dielectric layer 125 between adjacent etch stop layers 210 in the lateral direction, thereby self-aligning the formation position of the gate plug 220, improving the positional accuracy of the gate plug 220, and also reducing the formation difficulty of the gate plug 220.

[0102] Accordingly, the gate plug 220 is located laterally between the source and drain interconnect layers 160 and longitudinally between adjacent gate plugs 220. The gate plug 220 is an active gate contact hole plug (COAG). The gate plug 220 contacts the gate structure 110 of the active region, which helps to further save chip area. Therefore, this embodiment improves the compatibility of forming the air gap 200 with the COAG process.

[0103] In this embodiment, the gate plug 220 penetrates the gate cap layer 120 and the top dielectric layer 125.

[0104] More specifically, the step of forming the gate plug 220 includes: using the etch stop layer 210 as an etch stop layer in the lateral direction, forming a gate contact hole (not shown) between adjacent etch stop layers 210 in the lateral direction, penetrating the top dielectric layer 125 and the gate cap layer 120; and forming the gate plug 220 in the gate contact hole.

[0105] It should be noted that this embodiment uses the COAG process as an example. In other embodiments, when the gate plug is formed on top of the gate structure in the isolation region, the semiconductor structure formation method provided in this embodiment can still reduce the effective capacitance between the source / drain interconnect layer and the gate structure, and improve the process compatibility of forming the air gap with forming the source / drain plug and the gate plug.

[0106] Accordingly, the present invention also provides a semiconductor structure. (See reference) Figures 21 to 23 , Figure 21 This is a top view. Figure 22 for Figure 21 Cross-sectional view along the aa direction. Figure 23 for Figure 21 A cross-sectional view along the bb direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0107] In this embodiment, the semiconductor structure includes: a substrate 100; a plurality of gate structures 110, disposed on the substrate 100; source / drain doped regions 140, located within the substrate 100 on both sides of the gate structures 110; a bottom dielectric layer 115, located on the side of the gate structures 110 and covering the source / drain doped regions 140; a top dielectric layer 125, located on the bottom dielectric layer 115 and covering the top of the gate structures 110; and a source / drain interconnect layer 150, penetrating the bottom dielectric layer 115 above the source / drain doped regions 140 and in contact with the source / drain doped regions 140. A gap 190 is provided between the interconnect layer 150 and the sidewall of the gate structure 110; a source / drain plug 160 penetrates the bottom dielectric layer 115 and the top dielectric layer 125 at the end of the source / drain interconnect layer 150 and is in contact with the source / drain doped region 140; an etch barrier layer 210 penetrates the top dielectric layer 125 at the top of the source / drain interconnect layer 150 and seals the gap 190, forming an air gap 200 with the gap 190; a gate plug 220 penetrates the top dielectric layer 125 at the top of the gate structure 110 and is in contact with the gate structure 110.

[0108] A gap 190 exists between the source / drain interconnect layer 150 and the sidewall of the gate structure 110. The semiconductor structure also includes an etch barrier layer 210 that penetrates the top dielectric layer 125 of the source / drain interconnect layer 150. The etch barrier layer 210 seals the gap 190 and forms an air gap 200 with the gap 190. The etch barrier layer 210 has an etch selectivity with the top dielectric layer 125 or the bottom dielectric layer 115. During the formation process of the semiconductor structure (e.g., the formation process of the gate plug 220), the etch barrier layer 210 is not easily etched by mistake, thereby protecting and sealing the air gap 200. This prevents the etch barrier layer 210 from being etched open, which would allow other materials (e.g., the material of the gate plug 220) to fill into the air gap 200. This ensures that the air gap 200 reduces the coupling capacitance between the gate structure 110 and the source / drain interconnect layer 150, thus optimizing the performance of the semiconductor structure.

[0109] The substrate 100 provides a process platform for the formation of semiconductor structures. In this embodiment, the substrate 100 is a three-dimensional substrate, comprising a substrate and a channel structure located on the substrate. The channel structure provides conductive channels for transistor operation.

[0110] In this embodiment, the channel structure is along the transverse direction (e.g. Figure 21 (As shown in the X direction). Specifically, there are multiple channel structures, which are arranged at intervals along the longitudinal direction.

[0111] As an example, substrate 100 is used to form a fin field-effect transistor (FinFET), with a fin-like channel structure. In other embodiments, depending on the type of transistor actually formed, the channel structure can be other types of channel structures, for example, when forming a fully enclosed gate transistor, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced-apart channel layers. In other embodiments, the substrate can also be a planar substrate. In this embodiment, the fin and the substrate are made of the same material, which is silicon. In other embodiments, the fin and the substrate can be made of other suitable materials.

[0112] The gate structure 110 is used to control the turn-on and turn-off of the conductive channel of the field-effect transistor.

[0113] In this embodiment, the gate structure 110 is along the longitudinal direction (e.g., Figure 21 Extending in the Y direction (as shown), the direction parallel to the surface of the substrate 100 and perpendicular to the longitudinal direction is the transverse direction. In this embodiment, the gate structure 110 is located on the substrate, and the gate structure 110 spans the fin and covers part of the top and part of the sidewalls of the fin.

[0114] In this embodiment, the gate structure 110 includes a first gate sidewall 111 that is opposite to the source-drain interconnect layer 150 and is longitudinally arranged, and a second gate sidewall 112 that is not opposite to the source-drain interconnect layer 150 and is longitudinally arranged.

[0115] In this embodiment, the gate structure 110 is a metal gate structure, including a high-k gate dielectric layer, a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer. The high-k gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the substrate 100, and the material of the high-k gate dielectric layer is a high-k dielectric material. The work function layer is used to adjust the work function of the gate structure 110. The gate electrode layer is used as an external electrode for connection to external circuits or interconnect structures. In other embodiments, depending on actual process requirements, the gate structure can also be a polysilicon gate structure.

[0116] The semiconductor structure also includes a gate cap layer 120, located between the top of the gate structure 110 and the top dielectric layer 125. The gate cap layer 120 is used to protect the top of the gate structure 110. The material of the gate cap layer 120 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 120 is silicon nitride.

[0117] The source / drain doped regions 140 are used to provide a carrier source. In this embodiment, the source / drain doped regions 140 are also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped regions 140 are located in the fins on both sides of the gate structure 110.

[0118] When forming an NMOS transistor, the source / drain doped region 140 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doped region 140 includes a stress layer doped with P-type ions.

[0119] The bottom dielectric layer 115 is used to provide isolation between adjacent gate structures 110. The top dielectric layer 125 is used to provide electrical isolation between source / drain plugs 160 and between source / drain plugs 160 and gate plugs 220.

[0120] The bottom dielectric layer 115 and the top dielectric layer 125 are made of dielectric materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0121] It should be noted that, in this embodiment, for ease of illustration and explanation, only the bottom dielectric layer 115 and the top dielectric layer 125 are shown in the cross-sectional view.

[0122] The source-drain interconnect layer 150 is used to realize the connection between the source-drain doped regions 140 located in the multiple channel structure layers. The source-drain interconnect layer 150 is also connected to the source-drain plug 160 for electrical connection with external circuits through the source-drain plug 160.

[0123] The source / drain plug 160 is used to realize the electrical connection between the source / drain doped region 140 and the external circuit. Specifically, the source / drain plug 160 is located at one end of the source / drain interconnect layer 150 and is in contact with the source / drain interconnect layer 150.

[0124] In this embodiment, the source-drain interconnect layer 150 and the source-drain plug 160 are an integral structure, which is beneficial to improve the contact performance between the source-drain interconnect layer 150 and the source-drain plug 160, thereby reducing the contact resistance between the source-drain interconnect layer 150 and the source-drain plug 160 and improving the electrical connection performance of the semiconductor structure.

[0125] The source-drain interconnect layer 150 and the source-drain plug 160 are made of conductive materials, such as one or more of W, Co, Ru, Cu, and Al. In this embodiment, the source-drain interconnect layer 150 and the source-drain plug 160 are made of the same material.

[0126] The gap 190 is located between the source-drain interconnect layer 150 and the gate structure 110, and is used to form an air gap 200 with the etch barrier layer 210.

[0127] In this embodiment, the gate structure 110 includes a first gate sidewall 111 that is opposite to the source-drain interconnect layer 150 and is longitudinally arranged, and a second gate sidewall 112 that is not opposite to the source-drain interconnect layer 150 and is longitudinally arranged; the semiconductor structure further includes: a first sidewall 130 located on the second gate sidewall 112; and a gap 190 located between the source-drain interconnect layer 150 and the first gate sidewall 111, and longitudinally dividing the first sidewall 130.

[0128] In this embodiment, the gap 190 is formed by removing the first sidewall 130 located between the source-drain interconnect layer 150 and the first gate sidewall 111.

[0129] Compared to the solution of removing the first sidewall 130 located on the second gate sidewall 112, in this embodiment, the gap 190 is formed by removing the first sidewall 130 located on the first gate sidewall 111, which helps to reduce the difficulty of forming the gap 190 and improve compatibility with existing processes.

[0130] The first sidewall 130 is located between the gate structure 110 and the source / drain plug 160, and it also affects the parasitic capacitance between the gate structure 110 and the source / drain plug 160. Therefore, the dielectric constant of the material of the first sidewall 130 cannot be too high. In addition, the first sidewall 130 has an etch selectivity with the bottom dielectric layer 115 or the top dielectric layer 125 and the gate cap layer 120 to facilitate the formation of the gap 190 by removing the first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110.

[0131] In this embodiment, the first sidewall 130 is made of one or more of the following materials: silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, low-k dielectric material, and ultra-low-k dielectric material. As an example, the first sidewall 130 is a single-layer structure, thereby reducing the process complexity of removing the first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110 to form the gap 190. Specifically, the material of the first sidewall 130 is a low-k dielectric material.

[0132] In this embodiment, the semiconductor structure further includes: a second sidewall 132 located on the first gate sidewall 111, between the sidewall of the first sidewall 130 and the second gate sidewall 112, and at the bottom of the gap 190 and the bottom of the first sidewall 130; and a third sidewall 133 located on the sidewall of the source-drain interconnect layer 150 exposed by the gap 190, and on the sidewall of the first sidewall 130 opposite to the gate structure 110.

[0133] During the formation of the semiconductor structure, the first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110 is removed, and the second sidewall 132 and the third sidewall 133 form the gap 190. The second sidewall 132 and the third sidewall 133 surround the sidewalls and bottom of the first sidewall 130, which helps to reduce the probability of damage to the gate structure 110, the substrate 100, and the source / drain doped region 140 during the step of removing the first sidewall 130 between the source / drain interconnect layer 150 and the gate structure 110.

[0134] Accordingly, the second sidewall 132 or the third sidewall 133 has an etching selectivity ratio with the first sidewall 130, so that the second sidewall 132 and the third sidewall 133 are not easily damaged during the formation step of the gap 190.

[0135] As an example, the material of the second sidewall 132 and the third sidewall 133 is silicon nitride.

[0136] In this embodiment, the source-drain interconnect layer 150, the source-drain plug 160, and the top dielectric layer 125 form a spacer opening 170. During the formation of the semiconductor structure, the spacer opening 170 exposes the first sidewall 130 so that the gap 190 between the first sidewall 130 and the gate structure 110 can be removed through the spacer opening 170.

[0137] Specifically, the spacer opening 170 is formed by first forming a source / drain contact material that penetrates the bottom dielectric layer 115 and the top dielectric layer 125 and contacts the source / drain doped region 140, and then removing the source / drain contact material of the interconnect region to form the source / drain interconnect layer 150 and the source / drain plug 160. After the source / drain interconnect layer 150 and the source / drain plug 160 are formed, the first sidewall 130 exposed by the spacer opening 170 is removed to form the gap 190, thereby preventing the material of the source / drain interconnect layer 150 and the source / drain plug 160 from filling the air gap 200. This ensures the effectiveness of the air gap 200 in reducing the coupling capacitance between the gate structure 110 and the source / drain interconnect layer 150, thereby optimizing the performance of the semiconductor structure and improving the process compatibility between forming the air gap 200 and forming the source / drain plug 160.

[0138] The air gap 200 has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), which helps to further reduce the effective capacitance between the gate structure 110 and the source-drain interconnect 150, reduce RC delay, and thus improve the performance of the semiconductor structure.

[0139] In this embodiment, the air gap 200 is located between the source / drain interconnect layer 150 and the gate structure 110. In the semiconductor field, the length of the source / drain interconnect layer 150 is usually much larger than the length of the source / drain plug 160 along the longitudinal direction. Compared with the relative area between the source / drain plug 160 and the gate structure 110, the relative area between the source / drain interconnect layer 150 and the gate structure 110 is larger. By providing an air gap 200 between the source / drain interconnect layer 150 and the gate structure 110, the coupling capacitance between the source / drain interconnect layer 150 and the gate structure 110 can be reduced, thereby significantly reducing the parasitic capacitance of the semiconductor structure and improving the performance of the semiconductor structure.

[0140] In this embodiment, the etching barrier layer 210 fills the spacer opening 170.

[0141] In this embodiment, there is an etch selectivity between the etch barrier layer 210 and the top dielectric layer 125. The formation process of the gate plug 220 typically includes the step of forming a gate contact hole through the top dielectric layer 125 of the gate structure 110. The process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, thereby reducing the risk that the air gap 200 will be opened during the formation of the gate contact hole. Correspondingly, it helps to prevent the problem of material of the gate plug 220 filling the air gap 200.

[0142] Moreover, the process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, which reduces the risk of short circuit between the gate plug 220 and the source-drain interconnect layer 150, thereby improving the reliability of the semiconductor structure.

[0143] Furthermore, in this embodiment, the gate plug 220 is located in the top dielectric layer 125 between adjacent etch stop layers 210 along the lateral direction. The etch stop layer 210 can also define the formation position of the gate plug 220 along the lateral direction, thereby realizing the self-alignment of the gate plug 20 position. It also helps to reduce the formation difficulty of the gate plug 220 and accurately locate the formation position of the gate plug 220.

[0144] Therefore, the etch barrier layer 210 is made of a material with high etch selectivity between it and the top dielectric layer 125. Moreover, in this embodiment, the gate plug 220 penetrates the gate cap layer 120 and the top dielectric layer 125 at the top of the gate structure 110, and the etch barrier layer 210 and the gate cap layer 120 also have a high etch selectivity ratio to avoid erroneous etching of the etch barrier layer 210.

[0145] As an example, the etch barrier layer 210 can be made of materials commonly used in source / drain capping layers in semiconductor processes, so as to ensure that the etch barrier layer 210, the top dielectric layer 125, and the gate capping layer 120 all have high etch selectivity, thereby protecting the air gap 200 and the source / drain interconnect layer 150, and also improving compatibility with existing processes.

[0146] In this embodiment, the material of the etch barrier layer 210 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the etch barrier layer 210 is silicon carbide.

[0147] The gate plug 220 is used to realize the electrical connection between the gate structure 110 and the external circuit. The gate plug 220 is made of a conductive material, such as one or more of W, Co, Ru, Cu and Al.

[0148] The process of forming the gate plug 220 typically includes forming a gate contact hole through the top dielectric layer 125 of the gate structure 110. The etch stop layer 210 and the top dielectric layer 125 have an etch selectivity ratio, which reduces the probability of the etch stop layer 210 being damaged during the formation of the gate contact hole. This reduces the risk of the air gap 200 being opened during the formation of the gate contact hole, and consequently helps to prevent the material of the gate plug 220 from filling into the air gap 200. This ensures the effectiveness of the air gap 200 in reducing the coupling capacitance between the gate structure 110 and the source-drain interconnect layer 150, thereby optimizing the performance of the semiconductor structure. It also improves the process compatibility between forming the air gap 200 and forming the gate plug 220 and the source-drain plug 160.

[0149] In this embodiment, along the lateral direction, the gate plug 200 is located in the top dielectric layer 125 between adjacent etch stop layers 210. Thus, during the formation of the gate plug 220, the etch stop layer 210 can be used as an etch stop layer along the lateral direction, thereby self-aligning the position of the gate plug 220, improving the positional accuracy of the gate plug 220, and also reducing the formation difficulty of the gate plug 220.

[0150] Accordingly, in this embodiment, the gate plug 220 is located in the region between the source and drain interconnect layers 160 in the lateral direction and between adjacent gate plugs 220 in the longitudinal direction. The gate plug 220 is an active gate contact hole plug. The gate plug 220 is in contact with the gate structure 110 of the active region, which is beneficial to further save the chip area.

[0151] Accordingly, in this embodiment, the compatibility of the air gap 200 with the COAG process is improved.

[0152] In this embodiment, the gate plug 220 penetrates the gate cap layer 120 and the top dielectric layer 125.

[0153] It should be noted that in this embodiment, the gate plug 220 is described as a COAG. In other embodiments, when the gate plug is located on top of the gate structure in the isolation region, the semiconductor structure provided in this embodiment can still reduce the effective capacitance between the source / drain interconnect layer and the gate structure, and improve the compatibility of the air gap with the processes for forming the source / drain plug and the gate plug.

[0154] The semiconductor structure can be formed using the formation method of the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0155] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a plurality of gate structures on the substrate; source / drain doped regions in the substrate on both sides of the gate structures; a bottom dielectric layer on the sides of the gate structures and covering the source / drain doped regions; a top dielectric layer on the bottom dielectric layer and covering the top of the gate structures; a source / drain interconnect layer through the bottom dielectric layer on top of the source / drain doped regions and in contact with the source / drain doped regions, the source / drain interconnect layer having a gap between the source / drain interconnect layer and the sidewalls of the gate structures; a source / drain plug through the bottom dielectric layer and the top dielectric layer on the ends of the source / drain interconnect layer and in contact with the source / drain doped regions; an etch stop layer through the top dielectric layer on top of the source / drain interconnect layer, the etch stop layer sealing the gap and forming an air gap with the gap, the etch stop layer having an etch selectivity ratio with the top dielectric layer; a gate plug through the top dielectric layer on top of the gate structures and in contact with the gate structures.

2. The semiconductor structure of claim 1, wherein, The source / drain interconnect layer and the source / drain plug are an integral structure.

3. The semiconductor structure of claim 1 or 2, wherein, The source / drain interconnect layer and the source / drain plug, and the top dielectric layer form a spacing opening; the etch stop layer fills the spacing opening.

4. The semiconductor structure of claim 1, wherein, The gate structures extend in a longitudinal direction; the gate structures include a first gate sidewall opposite the source / drain interconnect layer and in the longitudinal direction, and a second gate sidewall not opposite the source / drain interconnect layer and in the longitudinal direction. The semiconductor structure further comprises: a first sidewall on the second gate sidewall; the gap is between the source / drain interconnect layer and the first gate sidewall and divides the first sidewall in the longitudinal direction.

5. The semiconductor structure of claim 4, wherein, The semiconductor structure further comprises: a second sidewall between the first sidewall and the second gate sidewall, on the sidewall of the first sidewall, and on the bottom of the gap and the first sidewall; a third sidewall on the sidewall of the source / drain interconnect layer exposed by the gap, and on the sidewall of the first sidewall opposite the gate structures.

6. The semiconductor structure of claim 4, wherein, The material of the first sidewall includes one or more of silicon nitride, silicon carbon nitride, silicon carbon oxide, silicon carbide, low-k dielectric material, and ultra-low-k dielectric material.

7. The semiconductor structure of claim 1, wherein, The gate structures extend in a longitudinal direction; a direction parallel to the substrate and perpendicular to the longitudinal direction is a lateral direction; in the lateral direction, the gate plugs are in the top dielectric layer between adjacent etch stop layers.

8. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a gate cap layer between the top of the gate structures and the top dielectric layer; the gate plugs pass through the gate cap layer and the top dielectric layer.

9. The semiconductor structure of claim 1, wherein, The material of the etch stop layer includes one or more of silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride, and boron carbon nitride.

10. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: A substrate is provided, on which discrete gate structures are formed. A first sidewall is formed on the sidewall of the gate structure. Source and drain doped regions are formed in the substrate on both sides of the gate structure. A bottom dielectric layer covering the source and drain doped regions is formed on the side of the gate structure and the first sidewall. A source and drain interconnect layer in contact with the source and drain doped regions is formed in the bottom dielectric layer. A top dielectric layer is formed on the bottom dielectric layer. A source and drain plug penetrating the bottom dielectric layer and the top dielectric layer is formed at the end of the source and drain interconnect layer and in contact with the source and drain doped regions. A spaced opening penetrating the top dielectric layer is formed at the top of the source and drain interconnect layer, exposing the first sidewall. Remove the first sidewall exposed by the spacer opening to form a gap between the source / drain interconnect layer and the gate structure; An etch barrier layer is filled into the gap opening, and the etch barrier layer seals the gap, forming an air gap with the gap. The etch barrier layer and the top dielectric layer have an etch selectivity ratio. After the etching barrier layer is formed, a gate plug is formed that penetrates the top dielectric layer of the gate structure and contacts the gate structure.

11. The method of forming a semiconductor structure of claim 10, wherein, The steps of providing a substrate, a gate structure, a first sidewall, source / drain doped regions, a bottom dielectric layer, a top dielectric layer, a source / drain interconnect layer, source / drain plugs, and spacer openings include: A substrate, a gate structure, a first sidewall, source / drain doped regions, and the bottom dielectric layer are provided; The top dielectric layer is formed on the bottom dielectric layer; Source / drain contact material is formed through the bottom dielectric layer and the top dielectric layer, which extend through the top of the source / drain doped region, including an interconnect region and a plug region located at the end of the interconnect region; Remove the source / drain contact material located in the interconnect region and above the first sidewall to form the spacer opening, exposing the first sidewall. The remaining source / drain contact material in the interconnect region is used as the source / drain interconnect layer, and the source / drain contact material in the plug region is used as the source / drain plug.

12. The method of forming a semiconductor structure of claim 11, wherein, The step of forming the source / drain contact material includes: forming a source / drain contact opening penetrating the bottom dielectric layer and the top dielectric layer to expose the source / drain doped region; and forming the source / drain contact material in the source / drain contact opening. The step of removing source / drain contact material located in the interconnect region and above the first sidewall includes: forming a hard mask layer on the source / drain contact material in the plug region, the hard mask layer exposing the source / drain contact material in the interconnect region; and removing the source / drain contact material above the first sidewall using the hard mask layer as a mask.

13. The method of forming a semiconductor structure of claim 10, wherein, The steps of providing a substrate, a gate structure, a first sidewall, source / drain doped regions, a bottom dielectric layer, a top dielectric layer, a source / drain interconnect layer, source / drain plugs, and spacer openings include: A substrate, a gate structure, a first sidewall, source / drain doped regions, and the bottom dielectric layer are provided; The source / drain interconnect layer and the bottom plug located at the end of the source / drain interconnect layer are formed in the bottom dielectric layer, and both the source / drain interconnect layer and the bottom plug are in contact with the source / drain doped region; The top dielectric layer is formed on the bottom dielectric layer; forming a top plug of the top dielectric layer penetrating the top of the bottom plug, the top plug and the bottom plug being used to form the source / drain plug; forming the spaced-apart opening of the top dielectric layer penetrating the top of the source / drain interconnect layer after forming the top plug, the first sidewall being exposed.

14. The method of forming a semiconductor structure of claim 10, wherein, The gate structure extends in a longitudinal direction, and a direction parallel to the substrate and perpendicular to the longitudinal direction is a lateral direction. The step of forming the gate plug includes forming the gate plug in the top dielectric layer between adjacent etch stop layers in the lateral direction, the etch stop layers being in contact with the gate structure.

15. The method of forming a semiconductor structure of claim 14, wherein, In the step of providing the substrate, a gate cap layer is further formed on top of the gate structure; the gate plug penetrates the gate cap layer and the top dielectric layer.

16. The method of forming a semiconductor structure of claim 10, wherein, In the step of providing the substrate, a second sidewall is further formed between a bottom of the first sidewall and a sidewall of the gate structure, and a third sidewall is further formed on a sidewall of the gate structure opposite to the first sidewall; the first sidewall exposed by the removal of the spaced-apart opening is surrounded by the second sidewall and the third sidewall.

17. The method of forming a semiconductor structure of claim 10, wherein, The first sidewall comprises one or more of silicon nitride, silicon carbon nitride, silicon carbon oxide, silicon carbide, low-k dielectric material, and ultra-low-k dielectric material.

18. The method of forming a semiconductor structure of claim 10, wherein, The process of removing the first sidewall exposed by the spaced-apart opening comprises one or both of dry etching and wet etching.

19. The method of forming a semiconductor structure of claim 10, wherein, The process of forming the etch stop layer comprises a chemical vapor deposition process.

20. The method of forming a semiconductor structure of claim 10, wherein, The etch stop layer comprises one or more of silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitride oxide, silicon oxynitride, boron nitride, and boron carbon nitride.

Images