Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, a gate structure, a source-drain doped region, a bottom dielectric layer and a top dielectric layer; forming a source-drain contact structure in contact with the source-drain doped region, and a sacrificial sidewall layer on sidewalls of the source-drain contact structure, the source-drain contact structure comprising a source-drain interconnection layer penetrating the bottom dielectric layer at a top of the source-drain doped region, and a source-drain plug at an end of the source-drain interconnection layer and penetrating the bottom dielectric layer and the top dielectric layer, a top of the source-drain interconnection layer being formed with a blocking opening; removing the sacrificial sidewall layer to form a gap in the sidewalls of the source-drain contact structure; filling an etching blocking layer in the blocking opening, the top of the gap being sealed with the gap to form an air gap; and forming a gate plug penetrating the top dielectric layer at a top of the gate structure. The embodiment reduces the risk of the material of the source-drain contact structure or the gate plug filling into the air gap, and improves the process compatibility of forming the air gap and forming the gate plug and the source-drain contact structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and a substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped regions for connecting the source / drain doped regions to external circuitry.

[0003] Furthermore, as device dimensions shrink, the distance between the gate structure and the source / drain contact plugs is also decreasing. To reduce the coupling capacitance between the gate structure and the source / drain contact plugs, a method has been proposed to form an air gap sidewall between them. The air gap has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k or ultra-low-k dielectric materials), which helps to significantly reduce the coupling capacitance between the gate structure and the source / drain contact plugs.

[0004] However, the current semiconductor structure formation process still presents significant challenges. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the risk of material from the source / drain contact structure or gate plug being filled into the air gap, and improves the process compatibility between forming the air gap and forming the gate plug and source / drain contact structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a plurality of gate structures disposed on the substrate; source / drain doped regions located within the substrate on both sides of the gate structures; a bottom dielectric layer located on the side of the gate structures and covering the source / drain doped regions; a top dielectric layer located on the bottom dielectric layer and covering the top of the gate structures; a source / drain contact structure in contact with the source / drain doped regions, the source / drain contact structure including a source / drain interconnect layer penetrating the top of the bottom dielectric layer through the source / drain doped regions, and a source / drain plug located at the end of the source / drain interconnect layer and penetrating the bottom dielectric layer and the top dielectric layer; wherein, a gap is further formed in the sidewall of the source / drain contact structure; an etch barrier layer penetrating the top of the top dielectric layer through the source / drain interconnect layer, and the etch barrier layer sealing the top of the gap, forming an air gap with the gap; and a gate plug penetrating the top of the top dielectric layer through the gate structures and in contact with the gate structures.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein discrete gate structures are formed on the substrate, source and drain doped regions are formed in the substrate on both sides of the gate structures, a bottom dielectric layer covering the source and drain doped regions is formed on the side of the gate structure, and a top dielectric layer is formed on the bottom dielectric layer, covering the top of the gate structure; forming a source and drain contact structure in contact with the source and drain doped regions, and a sacrificial sidewall layer located on the sidewall of the source and drain contact structure, the source and drain contact structure including a source and drain interconnect layer extending through the bottom dielectric layer to the top of the source and drain doped regions, and a source and drain plug located at the end of the source and drain interconnect layer and extending through the bottom dielectric layer and the top dielectric layer, a blocking opening extending through the top dielectric layer being formed on the top of the source and drain interconnect layer; removing the sacrificial sidewall layer to form a gap on the sidewall of the source and drain contact structure; filling the blocking opening with an etch stop layer, the etch stop layer also sealing the top of the gap and forming an air gap with the gap; and after forming the etch stop layer, forming a gate plug extending through the top dielectric layer to the top of the gate structure and in contact with the gate structure.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention has a gap formed on the sidewall of the source / drain contact structure, and an etch barrier layer seals the top of the gap, forming an air gap with the gap. Correspondingly, the air gap is located on the sidewall of the source / drain contact structure. Compared to an air gap located only between the source / drain interconnect layer and the gate structure, or only on the sidewall of the source / drain plug, the air gap in this embodiment of the invention can improve the effect on parasitic capacitance. Furthermore, the etch barrier layer penetrates the top dielectric layer above the source / drain interconnect layer, and the etch barrier layer has an etch selectivity ratio with the top or bottom dielectric layer. During the semiconductor structure formation process (e.g., the gate plug formation process), the etch barrier layer is less likely to be accidentally etched, thereby protecting and sealing the air gap. This prevents the etch barrier layer from being etched open, allowing other materials (e.g., the gate plug material) to fill the air gap, ensuring the air gap's effect in reducing parasitic capacitance between the gate structure and the source / drain contact structure, and thus optimizing the performance of the semiconductor structure.

[0010] In the semiconductor structure formation method provided by this invention, the source / drain contact structure and sacrificial sidewall layer are formed first, then the sacrificial sidewall layer is removed to form a gap, and an etch barrier layer is formed to seal the gap. The etch barrier layer and the gap form an air gap, thereby preventing the material of the source / drain contact structure from filling the air gap. Moreover, after forming the etch barrier layer and the air gap, the gate plug is formed. The process of forming the gate plug is less likely to cause accidental etching of the etch barrier layer, thereby avoiding opening the top of the air gap and preventing the material of the gate plug from filling the air gap. In summary, the embodiments of the present invention are beneficial in preventing material from the source / drain contact structure or gate plug from filling the air gap, thereby ensuring that the air gap serves to reduce parasitic capacitance. Furthermore, they improve the process compatibility between forming the air gap and forming the source / drain contact structure and gate plug. In addition, the sacrificial sidewall layer is formed on the sidewall of the source / drain contact structure, and correspondingly, the air gap is also located on the sidewall of the source / drain contact structure. Compared to air gaps located only between the source / drain interconnect layer and the gate structure or only on the sidewall of the source / drain plug, the air gaps formed in the embodiments of the present invention can improve the effect on reducing parasitic capacitance. Attached Figure Description

[0011] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 10 to 27 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] As the background technology shows, the current semiconductor structure formation process still presents significant challenges. Specifically, the formation of air gap sidewalls remains particularly challenging. This paper analyzes the reasons why forming air gap sidewalls remains a significant challenge, using a semiconductor structure formation method as an example.

[0014] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 Provides a substrate 10, a gate structure 20 located on the substrate 10, and a gate structure 20 located on the gate structure 20.

[0016] The first sidewall 32 of the sidewall, the source and drain doped regions 11 located in the substrate 10 on both sides of the gate structure 20, and the bottom dielectric layer 12 on the side of the gate structure 20 and covering the source and drain doped regions 11.

[0017] refer to Figure 2 A source-drain interconnect layer 40 is formed that penetrates the bottom dielectric layer 12 and is in contact with the source-drain doped region 11.

[0018] refer to Figure 3 Remove the first sidewall 30 to form a gap 35 between the sidewall of the gate structure 20 and the source-drain interconnect layer 40.

[0019] refer to Figure 4 A sealing layer 13 is formed on the sidewall and bottom of the gap 35, and the sealing layer 13 located at the top corner of the gap 35 is in contact with each other, thus sealing the gap 35 to form an air gap 50.

[0020] refer to Figure 5 A top dielectric layer 14 is formed on the bottom dielectric layer 12, covering the source-drain interconnect layer 40, the sealing layer 13, and the gate structure 20.

[0021] refer to Figures 6 to 7 A source / drain contact plug 60 is formed, penetrating the top dielectric layer 14 of the source / drain interconnect layer 40 and contacting the source / drain interconnect layer 40. The step of forming the source / drain contact plug 60 typically includes: forming a source / drain contact hole 61 penetrating the top dielectric layer 14 of the source / drain interconnect layer 40 to expose the source / drain interconnect layer 40; and filling the source / drain contact hole 61 with a conductive material to form the source / drain contact plug 60.

[0022] refer to Figures 8 to 9 A gate contact plug 70 is formed, penetrating the top dielectric layer 14 of the gate structure 20 and contacting the gate structure 20. The step of forming the gate contact plug 70 typically includes: forming a gate contact hole 71 penetrating the top dielectric layer 14 of the gate structure 20 to expose the gate structure 20; and filling the gate contact hole 71 with a conductive material to form the gate contact plug 70.

[0023] In the above forming method, when forming the source / drain contact hole 61 (e.g. Figure 6 (as shown) or gate contact hole 71 (as shown) Figure 8 During the process (as shown), the top of the sealing layer 13 is easily etched, causing the top of the air gap 50 to be opened. Accordingly, conductive material (such as...) is filled into the source / drain contact hole 61. Figure 7 (as shown), and filling the gate contact hole 71 with conductive material (such as...) Figure 8 During the process shown, conductive material can easily fill the air gap 50, which reduces the effectiveness of the air gap 50 in reducing parasitic capacitance, thereby leading to reduced device performance or device failure.

[0024] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure. First, a source / drain contact structure and a sacrificial sidewall layer are formed. Then, the sacrificial sidewall layer is removed to form a gap, and an etch barrier layer is formed to seal the gap. The etch barrier layer and the gap form an air gap, thereby preventing material from the source / drain contact structure from filling the air gap. Furthermore, after forming the etch barrier layer and the air gap, the gate plug is formed. The process of forming the gate plug is less likely to cause accidental etching of the etch barrier layer, thus avoiding opening the top of the air gap and preventing material from filling the gate plug. In summary, the embodiments of the present invention help prevent material from the source / drain contact structure or gate plug from filling the air gap, thereby ensuring that the air gap serves to reduce parasitic capacitance. Furthermore, it improves the process compatibility between forming the air gap and forming the source / drain contact structure and gate plug. In addition, the sacrificial sidewall layer is formed on the sidewall of the source / drain contact structure, and correspondingly, the air gap is also located on the sidewall of the source / drain contact structure. Compared to air gaps located only between the source / drain interconnect layer and the gate structure or only on the sidewall of the source / drain plug, the air gap formed in the embodiments of the present invention can improve the effect on reducing parasitic capacitance.

[0025] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] For ease of understanding, the method for forming the semiconductor structure according to the embodiments of the present invention will be described in detail below. Figures 10 to 27 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0027] refer to Figure 10A substrate 100 is provided, on which a discrete gate structure 110 is formed. Active and drain doped regions 140 are formed in the substrate 100 on both sides of the gate structure 110. A bottom dielectric layer 115 covering the active and drain doped regions 140 is formed on the side of the gate structure 110. A top dielectric layer 125 is formed on the bottom dielectric layer 115, covering the top of the gate structure 110.

[0028] The substrate 100 provides a process platform for subsequent process fabrication. In this embodiment, the substrate 100 is a three-dimensional substrate, including a substrate and a channel structure located on the substrate. The channel structure provides a conductive channel for transistor operation.

[0029] In this embodiment, the channel structure extends laterally. Specifically, there are multiple channel structures, which are arranged at intervals along the longitudinal direction, with the longitudinal direction perpendicular to the transverse direction.

[0030] As an example, substrate 100 is used to form a fin field-effect transistor (FinFET), with a fin-like channel structure. In other embodiments, depending on the type of transistor actually formed, the channel structure can be other types of channel structures, for example, when forming a fully enclosed gate transistor, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced-apart channel layers. In other embodiments, the substrate can also be a planar substrate. In this embodiment, the fin and the substrate are made of the same material, which is silicon. In other embodiments, the fin and the substrate can be made of other suitable materials.

[0031] The gate structure 110 is used to control the turn-on and turn-off of the conductive channel of the field-effect transistor.

[0032] In this embodiment, the gate structure 110 extends longitudinally, and its direction parallel to the surface of the substrate 100 and perpendicular to the longitudinal direction is transverse. In this embodiment, the gate structure 110 is located on the substrate, and the gate structure 110 spans the fin and covers part of the top and part of the sidewalls of the fin.

[0033] In this embodiment, the gate structure 110 is a metal gate structure, including a high-k gate dielectric layer, a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer. The high-k gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the channel, and the material of the high-k gate dielectric layer is a high-k dielectric material. The work function layer is used to adjust the work function of the gate structure 110. The gate electrode layer is used as an external electrode for connecting the gate structure 110 to external circuits or interconnect structures.

[0034] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on the actual process requirements.

[0035] In this embodiment, a gate cap layer 120 is also formed on the top of the gate structure 110. The gate cap layer 120 is used to protect the top of the gate structure 110. For example, in the subsequent step of forming the source-drain contact structure, the gate cap layer 120 is used to protect the top of the gate structure 110 to prevent short circuit between the source-drain contact structure and the gate structure 110.

[0036] The gate cap layer 120 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the gate cap layer 120 is made of silicon nitride.

[0037] In this embodiment, a sidewall 130 is also formed on the sidewall of the gate structure 110 to protect the sidewall of the gate structure 110 and to isolate the gate structure 110 from the subsequent source-drain contact structure. Specifically, the sidewall 130 is located on the sidewall of the gate structure 110 and the gate cap layer 120.

[0038] After the source-drain contact structure is formed, the sidewall 130 is located between the gate structure 110 and the source-drain contact structure. The sidewall 130 also affects the parasitic capacitance between the gate structure 110 and the source-drain contact structure. Therefore, the dielectric constant of the material of the sidewall 130 cannot be too high.

[0039] The sidewall 130 can be a single-layer or multi-layer structure. In this embodiment, the material of the sidewall 130 includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, low-k dielectric materials, and ultra-low-k dielectric materials. As an example, the sidewall 130 is a single-layer structure, and the material of the sidewall 130 is silicon nitride.

[0040] The source / drain doped region 140 is used to provide a carrier source. In this embodiment, the source / drain doped region 140 is also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped region 140 is located in the fins on both sides of the gate structure 110. When forming an NMOS transistor, the source / drain doped region 140 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doped region 140 includes a stress layer doped with P-type ions.

[0041] The bottom dielectric layer 115 is used to achieve isolation between adjacent gate structures 110.

[0042] Subsequently, a source-drain contact structure is formed that contacts the source-drain doped region 140. The source-drain contact structure includes a source-drain plug that penetrates the bottom dielectric layer 115 and the top dielectric layer 125, and a gate plug that penetrates the top dielectric layer 125 and contacts the gate structure 110. The top dielectric layer 125 is used to achieve electrical isolation between the source-drain plugs and between the source-drain plugs and the gate plug.

[0043] The bottom dielectric layer 115 and the top dielectric layer 125 are made of dielectric materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0044] As an example, the steps of providing a substrate 100, a gate structure 110, source / drain doped regions 140, a bottom dielectric layer 115, and a top dielectric layer 125 include: providing a substrate 100; forming a dummy gate structure (not shown) on the substrate 100; forming sidewalls 130 on the sidewalls of the dummy gate structure; forming source / drain doped regions 140 in the substrate 100 on both sides of the dummy gate structure; forming a bottom dielectric layer 115 on the substrate 100 on the sidewalls of the dummy gate structure and the sidewalls of the sidewalls 130; removing the dummy gate structure to form a gate opening (not shown); forming a gate structure 110 and a gate capping layer 120 on top of the gate structure 110 in the gate opening; and forming a top dielectric layer 125 on the bottom dielectric layer 115 to cover the gate capping layer 120.

[0045] It should be noted that, in this embodiment, for ease of illustration and explanation, only the bottom dielectric layer 115 and the top dielectric layer 125 are shown in the cross-sectional view.

[0046] refer to Figures 11 to 19 A source / drain contact structure 300 is formed in contact with the source / drain doped region 140, and a sacrificial sidewall layer 310 is located on the sidewall of the source / drain contact structure 300. The source / drain contact structure 300 includes a source / drain interconnect layer 150 that penetrates the bottom dielectric layer 115 at the top of the source / drain doped region 140, and a source / drain plug 160 located at the end of the source / drain interconnect layer 150 and penetrating the bottom dielectric layer 115 and the top dielectric layer 125. A blocking opening 170 that penetrates the top dielectric layer 125 is formed at the top of the source / drain interconnect layer 150.

[0047] The source / drain contact structure 300 is used to realize the electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures. The source / drain interconnect layer 150 is used to connect the source / drain doped region 140 located in multiple channel structures, and is also used to electrically connect with the source / drain plug 160; the source / drain plug 160 is electrically connected to the source / drain doped region 140 and the source / drain interconnect layer 150, thereby realizing the electrical connection between the source / drain doped region 140 and the subsequent interconnect structure.

[0048] Furthermore, the source-drain interconnect layer 150 only penetrates the bottom dielectric layer 115. The top surface of the source-drain interconnect layer 150 is lower than the top surface of the source-drain plug 160, which not only facilitates the formation of an etch barrier layer in the barrier opening 170, but also helps to increase the distance between the top surface of the source-drain interconnect layer 150 and the subsequent gate plug in the direction perpendicular to the surface of the substrate 100. Correspondingly, it helps to further reduce the probability of short circuit problems between the gate plug and the source-drain interconnect layer 150.

[0049] Specifically, the source / drain plug 160 is located at one end of the source / drain interconnect layer 150 and is in contact with the source / drain interconnect layer 150.

[0050] In this embodiment, the source / drain contact structure 300 is along the longitudinal direction (e.g., ...). Figure 16 (As shown in the Y direction) the source-drain contact structure 300 extends in the same direction as the gate structure 110.

[0051] In this embodiment, the source-drain contact structure 300 is an integral structure, which is beneficial to improve the contact performance between the source-drain interconnect layer 150 and the source-drain plug 160, reduce the contact resistance between the source-drain interconnect layer 150 and the source-drain plug 160, and reduce the resistance of the source-drain contact structure 300, thereby improving the electrical connection performance of the semiconductor structure.

[0052] The source-drain contact structure 300 is made of a conductive material, such as one or more of W, Co, Ru, Cu and Al.

[0053] The barrier opening 170 is used to provide space for the formation of the etch barrier layer. In this embodiment, the barrier opening 170 is surrounded by the source / drain interconnect layer 150, the source / drain plug 160, and the top dielectric layer 125.

[0054] The sacrificial sidewall layer 310 is used to pre-occupy a space for forming a gap, that is, the gap is formed by subsequently removing the sacrificial sidewall layer 310.

[0055] Therefore, in order to reduce the difficulty of subsequent removal of the sacrificial sidewall layer 310, the sacrificial sidewall layer 310 is made of a material that is easy to remove. In addition, in order to reduce the impact of the subsequent removal of the sacrificial sidewall layer 310 on other film structures (e.g., bottom dielectric layer 115, top dielectric layer 125, and sidewall 130), the material of the sacrificial sidewall layer 310 also has an etching selectivity ratio with the materials of the bottom dielectric layer 115, the top dielectric layer 125, and the sidewall 130.

[0056] In this embodiment, the material of the sacrificial sidewall layer 310 includes one or more of amorphous silicon, silicon oxycarbide, silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, boron nitride, aluminum oxide, aluminum nitride, and silicon oxynitride. As an example, the material of the sacrificial sidewall layer 310 is amorphous silicon.

[0057] It should be noted that the thickness of the sacrificial sidewall layer 310 should not be too small or too large. If the thickness of the sacrificial sidewall layer 310 is too small, it will easily increase the difficulty of subsequent removal of the sacrificial sidewall layer 310, making it difficult to remove the sacrificial sidewall layer 310 completely. Moreover, after the gap is formed by removing the sacrificial sidewall layer 310, the size of the gap along the direction perpendicular to the sidewall of the source-drain contact structure 300 will also be too small. When forming the etching barrier layer on top of the sealing gap, the size of the enclosed air gap will also be too small, resulting in the air gap's effect on reducing parasitic capacitance being insignificant. If the thickness of the sacrificial sidewall layer 310 is too large, it will easily occupy too much space, resulting in a reduction in the volume of the source-drain contact structure 300, which will then easily have an adverse effect on the resistance of the source-drain contact structure 300. Therefore, in this embodiment, the thickness of the sacrificial sidewall layer 310 is... to

[0058] The steps for forming the source / drain contact structure 300, the sacrificial sidewall layer 310, and the blocking opening 170 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0059] like Figure 11 As shown, a source / drain contact opening 185 is formed through the bottom dielectric layer 115 and the top dielectric layer 125, penetrating the top of the source / drain doped region 140, exposing the source / drain doped region 140. The source / drain contact opening 185 provides space for the formation of the sacrificial sidewall layer 310 and the source / drain contact material.

[0060] In this embodiment, the step of forming the source / drain contact opening 185 includes: forming a first hard mask layer 145 on the top dielectric layer 125; using the first hard mask layer 145 as a mask, etching the top dielectric layer 125 and the bottom dielectric layer 115 to form the source / drain contact opening 185.

[0061] In this embodiment, after forming the source / drain contact opening 185, the method further includes removing the first hard mask layer 145.

[0062] like Figures 12 to 13 As shown, a sacrificial sidewall layer 310 is formed on the sidewall of the source-drain contact opening 185.

[0063] In this embodiment, the step of forming the sacrificial layer sidewall layer 310 includes: as follows Figure 12 As shown, a sidewall material layer 320 is formed on the bottom and sidewalls of the source / drain contact opening 185 and on the top dielectric layer 125; as Figure 13 As shown, the sidewall material layer 320 located at the bottom of the source / drain contact opening 185 and the top of the top dielectric layer 125 is removed, and the sidewall material layer 320 located on the sidewall of the source / drain contact opening 185 is retained as a sacrificial sidewall layer 310.

[0064] In this embodiment, the process of forming the sidewall material layer 320 includes atomic layer deposition, which improves the conformal coverage capability of the sidewall material layer 320 in the source / drain contact opening 185, also helps to improve the thickness uniformity of the sidewall material layer 320, and makes it easy to precisely control the deposition thickness of the sidewall material layer 320 to obtain a sidewall material layer 320 with a thickness that meets the preset requirements.

[0065] In this embodiment, an anisotropic etching process (e.g., anisotropic dry etching process) is used to remove the sidewall material layer 320 located at the bottom of the source / drain contact opening 185 and the top of the top dielectric layer 125.

[0066] like Figure 14 and Figure 15 As shown, Figure 14 This is a top view. Figure 15 for Figure 14 A cross-sectional view along the bb direction shows a source / drain contact material 180 forming a source / drain contact opening 185 on the sacrificial sidewall layer 310, including an interconnect region 180a and a plug region 180b located at the end of the interconnect region 180a.

[0067] The source / drain contact material 180 of interconnect region 180a is used to form a source / drain interconnect layer after a subsequent etch-back step, and the source / drain contact material 180 of plug region 180b is used to form a source / drain plug. The source / drain interconnect layer and the source / drain plug are used to constitute the source / drain contact structure.

[0068] In this embodiment, a source / drain contact material 180 with an integral structure is first formed, and then the source / drain contact material 180 of the interconnect region 180a is removed to form a source / drain contact structure. Accordingly, the source / drain contact structure formed subsequently is an integral structure, which is beneficial to improving the contact performance between the source / drain interconnect layer and the source / drain plug.

[0069] In this embodiment, the step of forming the source / drain contact material 180 that fills the source / drain contact opening 185 includes: filling the source / drain contact opening 185 with an initial source / drain contact material (not shown), the initial source / drain contact material also being formed on the top dielectric layer 125; removing the initial source / drain contact material located on the top dielectric layer 125, and using the remaining initial source / drain contact material filling the source / drain contact opening 185 as the source / drain contact material 180.

[0070] In this embodiment, based on the actual process, one or more of chemical vapor deposition, physical vapor deposition, and electrochemical plating processes are used to form the initial source / drain contact material; a planarization process (e.g., chemical mechanical planarization) is used to remove the initial source / drain contact material located on the top dielectric layer 125.

[0071] like Figure 16 and Figure 17 , Figure 16 This is a top view. Figure 17 for Figure 16 In the cross-sectional view along the aa direction, the source / drain contact material 180 located in the interconnect region 180a and above the bottom dielectric layer 115 is removed. The remaining source / drain contact material 180 is used as the source / drain contact structure 300, which includes the source / drain interconnect layer 150 located in the interconnect region 180a and the source / drain plug 160 located in the plug region 180b. The source / drain interconnect layer 150, the source / drain plug 160, and the top dielectric layer 125 form a blocking opening 170.

[0072] By forming the source / drain interconnect layer 150 and the source / drain plug 160 in the same step, the process is simplified. Furthermore, compared to the approach of forming the source / drain interconnect layer in the bottom dielectric layer that contacts the source / drain doped region, and then forming the source / drain plug that penetrates the top dielectric layer and contacts the source / drain interconnect layer, this embodiment eliminates the need for alignment between the source / drain plug 160 and the source / drain interconnect layer 150 during the formation of the source / drain interconnect layer 150 and the source / drain plug 160. This helps prevent alignment misalignment (overlay) between the source / drain plug 160 and the source / drain interconnect layer 150. This reduces the process difficulty of forming the source / drain plug 160, increases the process window for forming the source / drain plug 160, and the source / drain plug 160 and the source / drain interconnect layer 150 are integrated into a single structure, which helps to reduce the resistance between the source / drain plug 160 and the source / drain interconnect layer 150, as well as the contact resistance between the source / drain plug 160 and the source / drain interconnect layer 150, thereby improving the electrical connection performance between the source / drain plug 160 and the source / drain interconnect layer 150. This, in turn, helps to improve the subsequent RC (resistance-capacitance) delay, reduce power consumption, and improve the circuit response speed, thus improving the performance of the semiconductor structure.

[0073] Furthermore, in the step of removing the source / drain contact material 180 located in the interconnect region 180a and above the bottom dielectric layer 115 to form the source / drain contact structure 300, the blocking opening 170 is formed simultaneously. Accordingly, there is no need to perform an additional step of forming the blocking opening 170, which is beneficial to simplify the process and improve production efficiency. Moreover, the blocking opening 170 can correspond to the position of the source / drain interconnect layer 150, which is beneficial to improve the positional accuracy of the blocking opening 170. In addition, in this embodiment, the source / drain interconnect layer 150, the source / drain plug 160 and the blocking opening 170 are formed in the same step, which is also beneficial to save the photomask and thus save process costs.

[0074] The formation method further includes: during the process of removing the source / drain contact material 180 located in the interconnect region 180a and above the bottom dielectric layer 115, the sacrificial sidewall layer 310 located in the interconnect region 180a and above the bottom dielectric layer 115 is also removed, thereby reducing the height of the sacrificial sidewall layer 310 located in the interconnect region 180a, which can shorten the subsequent process time for removing the sacrificial sidewall layer 310 and reduce the difficulty of subsequently removing the sacrificial sidewall layer 310.

[0075] In this embodiment, the step of removing the source / drain contact material 180 and the sacrificial sidewall layer 310 located in the interconnect region 180a and above the bottom dielectric layer 115 includes: forming a second hard mask layer 135 on the source / drain contact material 180 in the plug region 180b, the second hard mask layer 135 exposing the source / drain contact material 180 in the interconnect region 180a; and removing the source / drain contact material 180 and the sacrificial sidewall layer 310 above the bottom dielectric layer 115 using the second hard mask layer 135 as a mask.

[0076] The second hard mask layer 135 is used as a mask for etching the source / drain contact material 180. In this embodiment, the second hard mask layer 135 corresponds to the position of the source / drain plug.

[0077] In actual processes, depending on the requirements, one or both of dry etching and wet etching processes are selected to remove the source / drain contact material 180 and sacrificial sidewall layer 310 located in the interconnect region 180a and above the bottom dielectric layer 115.

[0078] like Figure 18 and Figure 19 , Figure 18 This is a top view. Figure 19 for Figure 18 The cross-sectional view along the aa direction shows that the method of formation also includes: removing the second hard mask layer 135 to expose the sacrificial sidewall layer 310 located on the sidewall of the source / drain plug 160, so as to facilitate the subsequent removal of the sacrificial sidewall layer 310.

[0079] refer to Figure 20 and Figure 21 , Figure 20 This is a top view. Figure 21 for Figure 20 A cross-sectional view along the aa direction shows the removal of the sacrificial sidewall layer 310, forming a gap 190 in the sidewall of the source-drain contact structure 300.

[0080] A gap 190 is formed on the sidewall of the source-drain contact structure 300 so that after the subsequent formation of the etch barrier layer sealing the gap 190, the etch barrier layer and the gap 190 form an air gap.

[0081] Furthermore, the gap 190 is formed on the sidewall of the source-drain contact structure 300. Correspondingly, the air gap formed subsequently is also located on the sidewall of the source-drain contact structure 300. Compared with the air gap being located only between the source-drain interconnect layer and the gate structure or only on the sidewall of the source-drain plug, the air gap formed in this embodiment can improve the effect of parasitic capacitance.

[0082] In this embodiment, the process for removing the sacrificial sidewall layer 310 includes one or both of dry etching and wet etching.

[0083] In this embodiment, the gap 190 is connected to the blocking opening 170, and the lateral dimension of the gap 190 is small. Therefore, during the subsequent process of forming an etching barrier layer in the blocking opening 170, the etching barrier layer will not fill the gap 190 completely, thereby sealing the top of the gap 190.

[0084] refer to Figures 22 to 24 , Figure 22 This is a top view. Figure 23 for Figure 22 Cross-sectional view along the aa direction. Figure 24 for Figure 22 In the cross-sectional view along the bb direction, the etched barrier layer 210 is filled in the barrier opening 170, and the etched barrier layer 210 also seals the top of the gap 190, forming an air gap 200 with the gap 190.

[0085] The air gap 200 has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), which helps to further reduce the effective capacitance between the gate structure 110 and the source-drain contact structure 300, reduce RC delay, and thus improve the performance of the semiconductor structure.

[0086] In this embodiment, since the source / drain contact structure 300 and the sacrificial sidewall layer 310 are formed first, and then the sacrificial sidewall layer 310 is removed to form the gap 190, and the etching barrier layer 210 forms the sealing gap 190, the etching barrier layer 210 and the gap 190 form an air gap 200, thereby preventing the material of the source / drain contact structure 300 from filling the air gap 200.

[0087] In this embodiment, there is an etch selectivity between the etch barrier layer 210 and the top dielectric layer 125. The subsequent process of forming the gate plug typically includes the step of forming a gate contact hole through the top dielectric layer 125 of the gate structure 110. The process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, thereby reducing the risk that the air gap 200 will be opened during the process of forming the gate contact hole. Correspondingly, it helps to prevent the problem of gate plug material filling the air gap 200.

[0088] Moreover, the subsequent process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, which reduces the risk of short circuit between the gate plug and the source / drain contact structure 300 and improves the reliability of the semiconductor structure.

[0089] Furthermore, in this embodiment, a gate plug that contacts the gate structure 110 is subsequently formed in the top dielectric layer 125 between adjacent etch stop layers 210 along the lateral direction. The etch stop layer 210 can also define the formation position of the gate plug along the lateral direction, thereby realizing the self-alignment of the gate plug position, which helps to reduce the formation difficulty of the gate plug and accurately locate the formation position of the gate plug.

[0090] Therefore, the etch barrier layer 210 is made of a material with high etch selectivity between it and the top dielectric layer 125. Moreover, in this embodiment, the subsequent gate plug penetrates the gate cap layer 120 and the top dielectric layer 125 at the top of the gate structure 110, and the etch barrier layer 210 and the gate cap layer 120 also have a high etch selectivity ratio to avoid erroneous etching of the etch barrier layer 210.

[0091] As an example, the etch barrier layer 210 can be made of materials commonly used in source and drain capping layers in semiconductor processes, so as to ensure that the etch barrier layer 210, the top dielectric layer 125 and the gate capping layer 120 all have high etch selectivity, thereby protecting the air gap 200 and the source and drain contact structure 300, and also improving compatibility with existing processes.

[0092] In this embodiment, the material of the etch barrier layer 210 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the etch barrier layer 210 is silicon carbide.

[0093] In this embodiment, the step of forming the etching barrier layer 210 includes: filling the barrier opening 170 with a barrier material layer (not shown), the barrier material layer sealing the gap 190 and also forming on the top dielectric layer 125; removing the barrier material layer located on the top dielectric layer 125, and the remaining barrier material layer filling the barrier opening 170 and sealing the gap 190 serves as the etching barrier layer 210.

[0094] In this embodiment, based on the actual size of the gap 190 along the direction perpendicular to the sidewall of the source-drain contact structure 300, the process of forming the barrier material layer is reasonably adjusted to ensure that the barrier material layer does not fill the gap 190 completely, thereby achieving the sealing of the gap 190, while also filling the barrier opening 170.

[0095] In this embodiment, the process for forming the barrier material layer includes chemical vapor deposition (CVD). CVD is a low-cost, mature process with high compatibility.

[0096] In this embodiment, a planarization process (e.g., chemical mechanical planarization) is used to remove the barrier material layer on the top dielectric layer 125, which helps to improve the flatness and height consistency of the top surface of the etch barrier layer 210, the top dielectric layer 125, and the source / drain plug 160, so as to provide a flat surface for subsequent processes.

[0097] refer to Figures 25 to 27 , Figure 25 This is a top view. Figure 26 for Figure 25 Cross-sectional view along the aa direction. Figure 27 for Figure 25 In the cross-sectional view along the bb direction, after the etch barrier layer 210 is formed, a gate plug 220 is formed that penetrates the top dielectric layer 125 of the gate structure 110 and contacts the gate structure 110. The gate plug 220 is used to realize the electrical connection between the gate structure 110 and the external circuit.

[0098] The process of forming the gate plug 220 typically includes forming a gate contact hole through the top dielectric layer 125 of the gate structure 110. There is an etch selectivity between the etch barrier layer 210 and the top dielectric layer 125, so the process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, thereby reducing the risk of the air gap 200 being opened during the formation of the gate contact hole. This helps to prevent the problem of material from the gate plug 220 filling the air gap 200, ensuring the effectiveness of the air gap 200 in reducing parasitic capacitance, thereby optimizing the performance of the semiconductor structure. It also improves the process compatibility between forming the air gap 200 and forming the gate plug 220 and the source / drain contact structure 300.

[0099] In this embodiment, the gate plug 220 is made of a conductive material, such as one or more of W, Co, Ru, Cu and Al.

[0100] In this embodiment, the step of forming the gate plug 220 includes: using the etch stop layer 210 as the etch stop layer in the lateral direction, forming the gate plug 220 in the top dielectric layer 125 between adjacent etch stop layers 210 in the lateral direction, thereby self-aligning the formation position of the gate plug 220, improving the positional accuracy of the gate plug 220, and also reducing the formation difficulty of the gate plug 220.

[0101] Accordingly, the gate plug 220 is located laterally between the source and drain interconnect layers 160. In the region between adjacent gate plugs 220 in the longitudinal direction, the gate plug 220 is an active gate contact hole plug (COAG). The gate plug 220 contacts the gate structure 110 of the active region, which helps to further save chip area. Therefore, this embodiment improves the compatibility of forming the air gap 200 with the COAG process.

[0102] In this embodiment, the gate plug 220 penetrates the gate cap layer 120 and the top dielectric layer 125.

[0103] More specifically, the step of forming the gate plug 220 includes: using the etch stop layer 210 as an etch stop layer in the lateral direction, forming a gate contact hole (not shown) between adjacent etch stop layers 210 in the lateral direction, penetrating the top dielectric layer 125 and the gate cap layer 120; and forming the gate plug 220 in the gate contact hole.

[0104] It should be noted that this embodiment uses the COAG process as an example. In other embodiments, when the gate plug is formed on top of the gate structure in the isolation region, the semiconductor structure formation method provided in this embodiment can still reduce the effective capacitance between the source / drain contact structure and the gate structure, and improve the compatibility of forming the air gap with the processes of forming the source / drain plug and the gate plug.

[0105] Accordingly, the present invention also provides a semiconductor structure. (See reference) Figures 25 to 27 , Figure 25 This is a top view. Figure 26 for Figure 25 Cross-sectional view along the aa direction. Figure 27 for Figure 25 A cross-sectional view along the bb direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0106] In this embodiment, the semiconductor structure includes: a substrate 100; a plurality of gate structures 110 disposed on the substrate 100; source / drain doped regions 140 located within the substrate 100 on both sides of the gate structures 110; a bottom dielectric layer 115 located on the side of the gate structures 110 and covering the source / drain doped regions 140; a top dielectric layer 125 located on the bottom dielectric layer 115 and covering the top of the gate structures 110; and a source / drain contact structure 300 in contact with the source / drain doped regions 140, the source / drain contact structure 300 including a bottom dielectric layer penetrating the top of the source / drain doped regions 140. The source-drain interconnect layer 150 of the source-drain interconnect layer 115, and the source-drain plug 160 located at the end of the source-drain interconnect layer 150 and penetrating the bottom dielectric layer 115 and the top dielectric layer 125; wherein, the sidewall of the source-drain contact structure 300 is also formed with a gap 190; an etch barrier layer 210 penetrates the top dielectric layer 125 at the top of the source-drain interconnect layer 150, and the etch barrier layer 210 seals the top of the gap 190, forming an air gap 200 with the gap 190; a gate plug 220 penetrates the top dielectric layer 125 at the top of the gate structure 110 and is in contact with the gate structure 110.

[0107] The source-drain contact structure 300 also has a gap 190 formed on its sidewall, and the etch barrier layer 210 seals the top of the gap 190, forming an air gap 200 with the gap 190. Accordingly, the air gap 200 is located on the sidewall of the source-drain contact structure 300. Compared with an air gap that is only located between the source-drain interconnect layer and the gate structure or only located on the sidewall of the source-drain plug, the air gap 200 in this embodiment can improve the effect on parasitic capacitance.

[0108] Furthermore, the etch barrier layer 210 penetrates the top dielectric layer 125 above the source-drain interconnect layer 150. The etch barrier layer 210 has an etch selectivity ratio with the top dielectric layer 125 or the bottom dielectric layer 115. During the semiconductor structure formation process (e.g., the formation process of the gate plug 220), the etch barrier layer 210 is not easily etched by mistake, thereby protecting and sealing the air gap 200. This prevents the etch barrier layer 210 from being etched open, which would cause other materials (e.g., the material of the gate plug) to fill the air gap 200. This ensures that the air gap 200 is effective in reducing the parasitic capacitance between the gate structure 110 and the source-drain contact structure 300, thereby optimizing the performance of the semiconductor structure.

[0109] In this embodiment, the substrate 100 is a three-dimensional substrate, comprising a substrate and a channel structure located on the substrate. The channel structure provides a conductive channel for transistor operation. In this embodiment, the channel structure is located laterally (e.g., ...). Figure 25Extending in the X direction (as shown in the middle). Specifically, there are multiple channel structures, and these multiple channel structures extend longitudinally (as shown in the middle X direction). Figure 25 (As shown in the Y direction) Alternating arrangement.

[0110] As an example, substrate 100 is used to form a fin field-effect transistor (FinFET), wherein the channel structure is a fin. In other embodiments, depending on the type of transistor actually formed, the channel structure may also be other types of channel structures, for example, when forming a fully enclosed gate transistor, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced channel layers. In still other embodiments, the substrate may also be a planar substrate.

[0111] In this embodiment, the fins and the substrate are made of the same material, namely silicon. In other embodiments, the fins and the substrate may be made of other suitable materials.

[0112] The gate structure 110 is used to control the opening and closing of the conductive channel of the field-effect transistor.

[0113] In this embodiment, the gate structure 110 extends longitudinally, and the direction parallel to the surface of the substrate 100 and perpendicular to the longitudinal direction is transverse. In this embodiment, the gate structure 110 is located on the substrate, and the gate structure 110 spans the fin and covers part of the top and part of the sidewalls of the fin.

[0114] In this embodiment, the gate structure 110 is a metal gate structure, including a high-k gate dielectric layer, a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer. In other embodiments, depending on actual process requirements, the gate structure may also be a polysilicon gate structure.

[0115] The semiconductor structure further includes a gate cap layer 120, located between the top of the gate structure 110 and the top dielectric layer 125, for protecting the top of the gate structure 110. The gate cap layer 120 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the gate cap layer 120 is made of silicon nitride.

[0116] In this embodiment, the semiconductor structure further includes a sidewall 130 located on the sidewall of the gate structure 110, used to protect the sidewall of the gate structure 110 and to isolate the gate structure 110 from the source / drain contact structure 300. Specifically, the sidewall 130 is located on the sidewall of the gate structure 110 and the gate cap layer 120.

[0117] The sidewall 130 is located between the gate structure 110 and the source-drain contact structure 300, and the sidewall 130 also affects the parasitic capacitance between the gate structure 110 and the source-drain contact structure 300. Therefore, the dielectric constant of the material of the sidewall 130 cannot be too high.

[0118] The sidewall 130 can be a single-layer or multi-layer structure. In this embodiment, the material of the sidewall 130 includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, low-k dielectric materials, and ultra-low-k dielectric materials. As an example, the sidewall 130 is a single-layer structure, and the material of the sidewall 130 is silicon nitride.

[0119] The source / drain doped region 140 is used to provide a carrier source. In this embodiment, the source / drain doped region 140 is also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped region 140 is located in the fins on both sides of the gate structure 110. When forming an NMOS transistor, the source / drain doped region 140 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doped region 140 includes a stress layer doped with P-type ions.

[0120] The bottom dielectric layer 115 is used to provide isolation between adjacent gate structures 110. The top dielectric layer 125 is used to provide electrical isolation between source / drain plugs 160 and between source / drain plugs 160 and gate plugs 220.

[0121] The bottom dielectric layer 115 and the top dielectric layer 125 are made of dielectric materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0122] It should be noted that, in this embodiment, for ease of illustration and explanation, only the bottom dielectric layer 115 and the top dielectric layer 125 are shown in the cross-sectional view.

[0123] The source / drain contact structure 300 is used to realize the electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures. The source / drain interconnect layer 150 is used to electrically connect the source / drain doped region 140 located in the multiple channel structures, and also to electrically connect with the source / drain plug 160; the source / drain plug 160 is electrically connected to the source / drain doped region 140 and the source / drain interconnect layer 150, thereby realizing the electrical connection between the source / drain doped region 140 and the subsequent interconnect structure.

[0124] Furthermore, the source-drain interconnect layer 150 only penetrates the bottom dielectric layer 115, and the top surface of the source-drain interconnect layer 150 is lower than the top surface of the source-drain plug 160, which helps to increase the distance between the top surface of the source-drain interconnect layer 150 and the gate plug 220 in the direction perpendicular to the surface of the substrate 100, and correspondingly helps to further reduce the probability of short circuit problems between the gate plug 220 and the source-drain interconnect layer 150.

[0125] Specifically, the source / drain plug 160 is located at one end of the source / drain interconnect layer 150 and is in contact with the source / drain interconnect layer 150.

[0126] In this embodiment, the source / drain contact structure 300 is along the longitudinal direction (e.g., Figure 25 Extending in the Y direction, the extension direction of the source-drain contact structure 300 is the same as the extension direction of the gate structure 110.

[0127] In this embodiment, the source-drain contact structure 300 is an integral structure, which is beneficial to improving the contact performance between the source-drain interconnect layer 150 and the source-drain plug 160, thereby reducing the contact resistance between the source-drain interconnect layer 150 and the source-drain plug 160, and reducing the resistance of the source-drain contact structure 300, thus improving the electrical connection performance of the semiconductor structure.

[0128] The source-drain contact structure 300 is made of a conductive material, such as one or more of W, Co, Ru, Cu and Al.

[0129] In this embodiment, the source / drain plug 160, the source / drain interconnect layer 150, and the top dielectric layer 125 form a blocking opening 170. The blocking opening 170 provides space for the etch barrier layer 210.

[0130] The gap 190 is located on the sidewall of the source-drain contact structure 300, and is used to form an air gap 200 with the etch barrier layer 210. In this embodiment, the gap 190 is located on the sidewall of the source-drain contact structure 300, and correspondingly, the air gap 200 is also located on the sidewall of the source-drain contact structure 300. Compared with the air gap being located only between the source-drain interconnect layer and the gate structure or only on the sidewall of the source-drain plug, the air gap 200 in this embodiment can improve the effect on parasitic capacitance.

[0131] In this embodiment, the gap 190 includes: a bottom gap (not shown) located between the source / drain contact structure 300 and the sidewall 130, and between the source / drain contact structure 300 and the bottom dielectric layer 115, and a top gap (not shown) located between the source / drain contact structure 300 and the top dielectric layer 125, wherein the top gap is connected to the bottom gap.

[0132] It should be noted that the width of the gap 190 along the direction perpendicular to the sidewall of the source-drain contact structure 300 should not be too small or too large. The gap 190 is formed by removing the sacrificial sidewall layer. If the width of the gap 190 is too small, it increases the difficulty of removing the sacrificial sidewall layer to form the gap 190. Furthermore, the size of the air gap 200 formed by the etching barrier layer 210 and the gap 190 is also too small, which can lead to the air gap 200 being ineffective in reducing parasitic capacitance. If the width of the gap 190 is too large, it can occupy too much space, reducing the volume of the source-drain contact structure 300, which can adversely affect the resistance of the source-drain contact structure 300. Therefore, in this embodiment, the width of the gap 190 along the direction perpendicular to the sidewall of the source-drain contact structure 300 is... to

[0133] An etch barrier layer 210 is used to seal the gap 190 to form an air gap 200 with the gap 190. In this embodiment, the etch barrier layer 210 is located on top of the source-drain interconnect layer 150 and fills the barrier opening 170.

[0134] The air gap 200 has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), which helps to further reduce the effective capacitance between the gate structure 110 and the source-drain contact structure 300, reduce RC delay, and thus improve the performance of the semiconductor structure.

[0135] In this embodiment, there is an etch selectivity between the etch barrier layer 210 and the top dielectric layer 125. The formation process of the gate plug 220 typically includes the step of forming a gate contact hole through the top dielectric layer 125 of the gate structure 110. The process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, thereby reducing the risk that the air gap 200 will be opened during the formation of the gate contact hole. Correspondingly, it helps to prevent the problem of material of the gate plug 220 filling the air gap 200.

[0136] Moreover, the process of forming the gate contact hole has a low probability of damaging the etch barrier layer 210, which reduces the risk of short circuit between the gate plug 220 and the source / drain contact structure 300 and improves the reliability of the semiconductor structure.

[0137] Furthermore, in this embodiment, the gate plug 220 is located in the top dielectric layer 125 between adjacent etch stop layers 210 along the lateral direction. The etch stop layer 210 can also define the formation position of the gate plug 220 along the lateral direction, thereby realizing the self-alignment of the position of the gate plug 220. This helps to reduce the formation difficulty of the gate plug 220 and accurately locate the formation position of the gate plug 220.

[0138] Therefore, the etch barrier layer 210 is made of a material with high etch selectivity between it and the top dielectric layer 125. Moreover, in this embodiment, the gate plug 220 penetrates the gate cap layer 120 and the top dielectric layer 125 at the top of the gate structure 110, and the etch barrier layer 210 and the gate cap layer 120 also have a high etch selectivity ratio to avoid erroneous etching of the etch barrier layer 210.

[0139] As an example, the etch barrier layer 210 can be made of materials commonly used in source and drain capping layers in semiconductor processes, so as to ensure that the etch barrier layer 210, the top dielectric layer 125 and the gate capping layer 120 all have high etch selectivity, thereby protecting the air gap 200 and the source and drain contact structure 300, and also improving compatibility with existing processes.

[0140] In this embodiment, the material of the etch barrier layer 210 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the etch barrier layer 210 is silicon carbide.

[0141] The gate plug 220 is used to realize the electrical connection between the gate structure 110 and the external circuit. In this embodiment, the gate plug 220 is made of a conductive material, such as one or more of W, Co, Ru, Cu and Al.

[0142] The process of forming the gate plug 220 typically includes forming a gate contact hole through the top dielectric layer 125 of the gate structure 110. The etch stop layer 210 and the top dielectric layer 125 have an etch selectivity ratio, which reduces the probability of the etch stop layer 210 being damaged during the formation of the gate contact hole. This reduces the risk of the air gap 200 being opened during the formation of the gate contact hole, and correspondingly helps to prevent the problem of material from the gate plug 220 filling into the air gap 200. This ensures the effectiveness of the air gap 200 in reducing the coupling capacitance between the gate structure 110 and the source-drain interconnect layer 150, thereby optimizing the performance of the semiconductor structure and improving the process compatibility between forming the air gap 200 and forming the gate plug 220 and the source-drain contact structure 300.

[0143] In this embodiment, the gate plug 220 is located between the etch stop layers 210 on both sides of the gate structure 110 in the lateral direction. Thus, during the formation of the gate plug 220, the etch stop layer 210 can be used as the etch stop layer in the lateral direction to self-align the position of the gate plug 220, thereby improving the positional accuracy of the gate plug 220 and reducing the formation difficulty of the gate plug 220.

[0144] Accordingly, in this embodiment, the gate plug 220 is located laterally between the source and drain interconnect layers 160 and longitudinally between adjacent gate plugs 220. The gate plug 220 is an active gate contact hole plug (COAG). The gate plug 220 is in contact with the gate structure 110 of the active region, which helps to further save the chip area.

[0145] Accordingly, in this embodiment, the compatibility of the air gap 200 with the COAG process is improved.

[0146] In this embodiment, the gate plug 220 penetrates the gate cap layer 120 and the top dielectric layer 125.

[0147] It should be noted that in this embodiment, the gate plug 220 is described as a COAG. In other embodiments, when the gate plug is located on top of the gate structure in the isolation region, the semiconductor structure provided in this embodiment can still reduce the effective capacitance between the source / drain interconnect layer and the gate structure, and improve the compatibility of the air gap with the processes for forming the source / drain plug and the gate plug.

[0148] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0149] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a plurality of gate structures formed on the substrate; source-drain doped regions formed in the substrate on both sides of the gate structures; a bottom dielectric layer formed on the sides of the gate structures and covering the source-drain doped regions; a top dielectric layer formed on the bottom dielectric layer and covering the top of the gate structures; a source-drain contact structure in contact with the source-drain doped regions, the source-drain contact structure comprising a source-drain interconnect layer penetrating the bottom dielectric layer on the top of the source-drain doped regions, and a source-drain plug penetrating the bottom dielectric layer and the top dielectric layer on the ends of the source-drain interconnect layer, wherein the sidewall of the source-drain interconnect layer and the sidewall of the source-drain plug of the same source-drain contact structure further form a gap connected therewith; an etching stop layer penetrating the top dielectric layer on the top of the source-drain interconnect layer, the etching stop layer sealing the top of the gap and forming an air gap with the gap, the etching stop layer having an etching selectivity ratio with the top dielectric layer; and a gate plug penetrating the top dielectric layer on the top of the gate structure and in contact with the gate structure.

2. The semiconductor structure of claim 1, wherein, The source-drain contact structure is an integrated structure.

3. The semiconductor structure of claim 1 or 2, wherein, The source-drain plug, the source-drain interconnect layer, and the top dielectric layer form a blocking opening, and the etching stop layer is located on the top of the source-drain interconnect layer and fills the blocking opening.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a sidewall formed on the sidewall of the gate structure. The gap comprises a bottom gap between the source-drain contact structure and the sidewall, and between the source-drain contact structure and the bottom dielectric layer, and a top gap between the source-drain contact structure and the top dielectric layer.

5. The semiconductor structure of claim 1, wherein, The width of the gap is 10-80 angstroms in a direction perpendicular to the sidewall of the source-drain contact structure.

6. The semiconductor structure of claim 1, wherein, The material of the etching stop layer comprises one or more of silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride, and boron carbon nitride.

7. The semiconductor structure of claim 1, wherein, The extension direction of the gate structure is longitudinal, and the direction parallel to the substrate and perpendicular to the longitudinal direction is lateral; along the lateral direction, the gate plug is located between the etching stop layers on both sides of the gate structure.

8. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a gate cap layer located between the top of the gate structure and the top dielectric layer; the gate plug penetrates the gate cap layer and the top dielectric layer.

9. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: a substrate; a plurality of gate structures formed on the substrate; source-drain doped regions formed in the substrate on both sides of the gate structures; a bottom dielectric layer formed on the sides of the gate structures and covering the source-drain doped regions; a top dielectric layer formed on the bottom dielectric layer and covering the top of the gate structures; a source-drain contact structure in contact with the source-drain doped regions, the source-drain contact structure comprising a source-drain interconnect layer penetrating the bottom dielectric layer on the top of the source-drain doped regions, and a source-drain plug penetrating the bottom dielectric layer and the top dielectric layer on the ends of the source-drain interconnect layer, the top of the source-drain interconnect layer forming a blocking opening penetrating the top dielectric layer; removing the sacrificial sidewall layer to form a gap in a sidewall of the source-drain contact structure, the gap in the sidewall of the source-drain contact structure being in communication with the gap between the sidewall of the source-drain interconnect layer and the sidewall of the source-drain plug in the same source-drain contact structure; filling the blocking opening with an etch blocking layer, the etch blocking layer also sealing a top of the gap, the etch blocking layer and the top dielectric layer surrounding an air gap with the gap; forming a gate plug through the top dielectric layer on top of the gate structure after forming the etch blocking layer, the gate plug being in contact with the gate structure.

10. The method of forming a semiconductor structure of claim 9, wherein, The steps of forming the source-drain contact structure and the sacrificial sidewall layer, and the blocking opening include: forming a source-drain contact opening through a bottom dielectric layer and a top dielectric layer on top of the source-drain doped region, the source-drain doped region being exposed; forming a sacrificial sidewall layer on sidewalls of the source-drain contact opening; forming a source-drain contact material on the sacrificial sidewall layer, the source-drain contact material filling the source-drain contact opening, the source-drain contact material including an interconnect region and a plug region on an end of the interconnect region; removing the source-drain contact material on the interconnect region and above the bottom dielectric layer, the remaining source-drain contact material being used as a source-drain contact structure, the source-drain contact structure including the source-drain interconnect layer on the interconnect region and the source-drain plug on the plug region, the source-drain interconnect layer and the source-drain plug and the top dielectric layer surrounding the blocking opening.

11. The method of forming a semiconductor structure of claim 10, wherein, The step of forming the sacrificial sidewall layer includes: forming a sidewall material layer on a bottom and sidewalls of the source-drain contact opening and the top dielectric layer; removing the sidewall material layer on the bottom of the source-drain contact opening and on a top of the top dielectric layer, the sidewall material layer on the sidewalls of the source-drain contact opening being reserved as the sacrificial sidewall layer.

12. The method of forming a semiconductor structure of claim 10, wherein, The method of forming the semiconductor structure further includes: during the removing of the source-drain contact material on the interconnect region and above the bottom dielectric layer, the sacrificial sidewall layer on the interconnect region and above the bottom dielectric layer is also removed.

13. The method of forming a semiconductor structure of claim 9, wherein, The gate structure has a longitudinal direction, and a lateral direction is parallel to the substrate and perpendicular to the longitudinal direction; The step of forming the gate plug includes: using the etch blocking layer as a lateral etch stop layer, and forming the gate plug in the top dielectric layer between adjacent etch blocking layers in the lateral direction.

14. The method of forming a semiconductor structure of claim 9, wherein, In the step of providing the substrate, a gate cap layer is also formed on top of the gate structure; the gate plug penetrates the gate cap layer and the top dielectric layer.

15. The method of forming a semiconductor structure of claim 9, wherein, The material of the sacrificial sidewall layer includes one or more of amorphous silicon, silicon oxycarbide, silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, boron nitride, aluminum oxide, aluminum nitride, and silicon oxynitride.

16. The method of forming a semiconductor structure of claim 9, wherein, The process of forming the sacrificial sidewall layer includes an atomic layer deposition process.

17. The method of forming a semiconductor structure of claim 9, wherein, The thickness of the sacrificial sidewall layer is 10 Å to 80 Å.

18. The method of forming a semiconductor structure of claim 9, wherein, The process of removing the sacrificial sidewall layer includes one or both of a dry etching process and a wet etching process.

19. The method of forming a semiconductor structure of claim 9, wherein, The process of filling the blocking opening with the etch blocking layer includes a chemical vapor deposition process.

20. The method of forming a semiconductor structure of claim 9, wherein, The material of the etch stop layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. The material of the etch stop layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

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