Display Panel

Abstract

The present invention provides a display panel, including a substrate, a first transistor and a second transistor located on the substrate, the first transistor including a first active layer, the second transistor including a second active layer, the second active layer and the first active layer are arranged in different layers, and a buffer layer is arranged between the first active layer and the second active layer. In the present invention, the buffer layer is arranged to include a first buffer layer arranged in contact with the first active layer and a second buffer layer arranged in contact with the second active layer, so as to continuously form the first buffer layer and the second buffer layer through the same process, thereby reducing the difficulty of integrating the first transistor and the second transistor, and effectively reducing the cost of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to the field of display panel manufacturing technology, and specifically to display panels. Background Art

[0002] In the current display industry, the addition of human-computer interaction functions has become an important direction for the development of new display technologies, and the integration of optical sensors in panels also provides a basis for this.

[0003] Among them, in the new self-luminous display technology, it is necessary to use transistor devices with higher mobility such as indium gallium zinc oxide to achieve driving. However, the main photosensitivity range of transistor devices made of indium gallium zinc oxide is higher energy blue light and ultraviolet light, while the sensing effect of green light and red light is poor. Therefore, it is necessary to use transistor devices made of other materials on the basis of transistor devices made of indium gallium zinc oxide to achieve light detection. Due to the differences in the process technology and materials of the two transistor devices, it is difficult to integrate the two transistor devices, causing the cost of the display panel to rise sharply.

[0004] Therefore, the integration of transistor devices in the existing new self-luminous display technology is difficult, causing the cost of display panels to rise sharply, and improvement is urgently needed. Summary of the invention

[0005] The embodiment of the present invention provides a display panel to solve the technical problem that the integration of transistor devices in the existing novel self-luminous display technology is relatively difficult, resulting in a sharp increase in the cost of the display panel.

[0006] An embodiment of the present invention provides a display panel, including:

[0007] substrate;

[0008] A first transistor, located on the substrate, comprising a first active layer;

[0009] a second transistor, located on the substrate, comprising a second active layer, wherein the second active layer and the first active layer are arranged in different layers;

[0010] The buffer layer is located between the first active layer and the second active layer, and includes a first buffer layer disposed in contact with the first active layer and a second buffer layer disposed in contact with the second active layer.

[0011] In one embodiment, a constituent material of the first active layer includes metal oxide, and a constituent material of the second active layer includes amorphous silicon.

[0012] In one embodiment, the first active layer is located on a side of the buffer layer away from the substrate.

[0013] In one embodiment, a constituent material of the first buffer layer includes silicon oxide, and a constituent material of the second buffer layer includes silicon nitride.

[0014] In one embodiment, the first transistor further includes a first source-drain electrode layer disposed corresponding to the first active layer, and the second transistor further includes a second source-drain electrode layer disposed corresponding to the second active layer;

[0015] Wherein, the second active layer, the second source-drain layer and the first source-drain layer are arranged in the same layer.

[0016] In one embodiment, the buffer layer is provided with a via hole, the via hole is arranged opposite to the first active layer, the first source and drain layer is electrically connected to the first active layer through the via hole; the second source and drain layer is arranged in contact with the second active layer.

[0017] In one embodiment, the first transistor further includes a first gate layer located on a side of the first active layer close to or away from the substrate, and the second transistor further includes a second gate layer located on a side of the second active layer away from the substrate.

[0018] In one embodiment, it further includes:

[0019] The dielectric layer is located between the first active layer and the second gate layer, and the component material of the second gate layer includes a transparent conductive material.

[0020] In one embodiment, the first transistor further includes a first gate layer and a first source-drain layer, the first gate layer is located on a side of the first active layer close to or away from the substrate, and the first source-drain layer is located on a side of the first active layer close to or away from the substrate;

[0021] The second transistor further includes a second gate layer and a second source-drain layer, the second gate layer is located on a side of the second active layer close to or away from the substrate, and the second source-drain layer is located on a side of the second active layer close to or away from the substrate.

[0022] In one embodiment, it further includes:

[0023] The pixel driving circuit comprises a plurality of third transistors, wherein the plurality of third transistors are arranged in the same layer as the first transistor or the second transistor.

[0024] The present invention provides a display panel, comprising: a substrate; a first transistor, located on the substrate, comprising a first active layer; a second transistor, located on the substrate, comprising a second active layer, wherein the second active layer and the first active layer are arranged in different layers; a buffer layer, located between the first active layer and the second active layer, comprising a first buffer layer arranged in contact with the first active layer and a second buffer layer arranged in contact with the second active layer. In the present invention, by arranging the first buffer layer arranged in contact with the first active layer and the second buffer layer arranged in contact with the second active layer between the second active layer and the first active layer, the first buffer layer and the second buffer layer are continuously formed through the same process on the basis of acting on the first active layer and the second active layer respectively at the same time, the increase in the number of process changes caused by forming the first buffer layer and the second buffer layer twice at intervals can be avoided, the manufacturing efficiency of the buffer layer is improved, and the integration difficulty of the first transistor and the second transistor is reduced, and the cost of the display panel is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention is further described below by means of the accompanying drawings. It should be noted that the accompanying drawings described below are only used to explain some embodiments of the present invention, and those skilled in the art can also obtain other accompanying drawings based on these accompanying drawings without paying creative labor.

[0026] Figure 1 A first cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention.

[0027] Figure 2 A second cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention.

[0028] Figure 3 A third cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0030] The terms "first", "second", "third", etc. in the present invention are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules that are not listed, or may optionally include other steps or modules that are inherent to these processes, methods, products or devices.

[0031] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0032] Embodiments of the present invention provide a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0033] In one embodiment, in combination Figures 1 to 3 As shown, the display panel 100 includes: a substrate 10; a first transistor 20, located on the substrate 10, including a first active layer 201; a second transistor 30, located on the substrate 10, including a second active layer 301, and the second active layer 301 and the first active layer 201 are arranged in different layers; a buffer layer 40, located between the first active layer 201 and the second active layer 301, including a first buffer layer 401 contacting the first active layer 201 and a second buffer layer 402 contacting the second active layer 301.

[0034] Specifically, the substrate 10 may be a flexible substrate or a rigid substrate to carry film layers including but not limited to the first active layer 201, the second active layer 301, the buffer layer 40, etc., disposed thereon. The second active layer 301 and the first active layer 201 disposed in different layers may be composed of different materials, so that the first transistor 20 and the second transistor 30 have different characteristics respectively; based on this, in this embodiment, the buffer layer 40 is configured as a first buffer layer 401 disposed in contact with the first active layer 201, and a second buffer layer 402 disposed in contact with the second active layer 301, that is, the first buffer layer 401 can at least prevent the first active layer 201 from contacting the substrate 10 and causing an effect, and the second buffer layer 402 can at least prevent the second active layer 301 from contacting the first buffer layer 401 and causing an effect.

[0035] It can be understood that in the present embodiment, the second active layer 301 and the first active layer 201 are arranged in different layers, and the buffer layer 40 including the first buffer layer 401 and the second buffer layer 402 arranged in a stacked manner can act on the first active layer 201 and the second active layer 301 respectively at the same time, so that the first buffer layer 401 and the second buffer layer 402 are formed twice at intervals, which increases the number of process changes. Instead, the first buffer layer 401 and the second buffer layer 402 can be continuously formed through the same process. Under the premise of ensuring the working reliability of both the first transistor 20 and the second transistor 30, the manufacturing efficiency of the buffer layer 40 is improved, thereby reducing the difficulty of integrating the first transistor 20 and the second transistor 30, and effectively reducing the cost of the display panel 100.

[0036] Further, a light shielding layer may be formed on the side of at least one of the first active layer 201 and the second active layer 301 close to the substrate 10 to block light from entering the first active layer 201 and / or the second active layer 301 to reduce the reliability of the operation of the first transistor 20 and / or the second transistor 30, wherein the constituent materials of the light shielding layer may include but are not limited to molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, calcium, titanium, tantalum, tungsten or copper. Further, a barrier layer may also be provided on the side of the light shielding layer close to the substrate 10 to prevent the diffusion of impurity ions and the penetration of moisture or external air, and also to flatten the substrate 10, and the constituent materials of the barrier layer may include but are not limited to silicon nitride, silicon oxide or silicon oxynitride. Of course, depending on the type of substrate 10 or process conditions, the barrier layer may also be omitted. Among them, the buffer layer 40 in this embodiment may be located on the side of the light shielding layer away from the substrate 10.

[0037] In this embodiment, there is no restriction on the specific structure and relative position of the first transistor 20 and the second transistor 30, and there is no restriction on the relative position of the second active layer 301 and the first active layer 201. It is only necessary that the second active layer 301 and the first active layer 201 are arranged in different layers, and the buffer layer 40 as described above is arranged between the second active layer 301 and the first active layer 201. Specifically, as Figure 1 As shown, the first transistor may further include a first gate layer and a first source-drain layer, the first gate layer may be located on a side of the first active layer 201 close to or away from the substrate 10, and the first source-drain layer may be located on a side of the first active layer close to or away from the substrate 10; the second transistor may further include a second gate layer and a second source-drain layer, the second gate layer is located on a side of the second active layer 301 close to or away from the substrate 10, and the second source-drain layer is located on a side of the second active layer 301 close to or away from the substrate 10.

[0038] In one embodiment, in combination Figures 1 to 3As shown, the constituent material of the first active layer 201 includes metal oxide, and the constituent material of the second active layer 301 includes amorphous silicon. It can be understood that the first transistor 20 formed by the first active layer 201 made of metal oxide has the advantage of high mobility and can be used to drive the device to work, and the second transistor 30 formed by the second active layer 301 made of amorphous silicon has the advantage of a large photosensitivity range and can be used to make a photosensitive device. Therefore, it can be considered that the display panel 100 including the first transistor 20 and the second transistor 30 in this embodiment can take into account both high driving performance and high photosensitivity performance, and on this basis, the first transistor 20 and the second transistor 30 can have a lower integration difficulty, effectively reducing the cost of the display panel 100.

[0039] Specifically, the metal oxides mentioned above may include but are not limited to any one of oxides based on titanium, hafnium, zirconium, aluminum, tantalum, germanium, zinc, gallium, tin or indium or their composite oxides. Further, for the first active layer 201 made of metal oxide, it can include an active layer body and doped parts located on two opposite sides of the active layer body, and the doped parts can be understood as parts formed by doping ions and being conductive, and compared with the active layer body, the doped parts can have higher conductivity and lower resistance.

[0040] In one embodiment, in combination Figures 1 to 3 As shown, the first active layer 201 is located on the side of the buffer layer 40 away from the substrate 10. Specifically, in combination with the above discussion, the buffer layer 40 is located between the first active layer 201 and the second active layer 301 arranged in different layers, that is, it can be considered that in the direction away from the substrate 10, the second active layer 301, the buffer layer 40 and the first active layer 201 are arranged in sequence. It can be understood that based on the constituent material of the first active layer 201 including metal oxide, further, in this embodiment, the first active layer 201 is arranged on the side of the buffer layer 40 away from the substrate 10, so that the buffer layer 40 can block the first active layer 201 made of metal oxide from directly contacting the substrate 10, and the probability of impurities on the substrate 10 penetrating into the first active layer 201 can be reduced, thereby reducing the risk of failure of the first active layer 201.

[0041] In one embodiment, in combination Figures 1 to 3As shown, the constituent material of the first buffer layer 401 includes silicon oxide, and the constituent material of the second buffer layer 402 includes silicon nitride. It can be understood that, based on the constituent material of the first active layer 201 including metal oxide, and the constituent material of the second active layer 301 including amorphous silicon, further, in this embodiment, the constituent material of the first buffer layer 401 disposed in contact with the first active layer 201 includes silicon oxide, that is, the first buffer layer 401 may not react with the first active layer 201 and affect the reliability of the first active layer 201, and further, since the first buffer layer 401 directly contacts the second active layer 301 and may react with the second active layer 301, in this embodiment, the constituent material of the second buffer layer 402 disposed in contact with the second active layer 301 includes silicon nitride, that is, the second buffer layer 402 can avoid the first buffer layer 401 directly contacting the second active layer 301 and affecting the reliability of the second active layer 301.

[0042] In one embodiment, if Figure 2 As shown, the first transistor 20 further includes a first source-drain layer 202 disposed corresponding to the first active layer 201, and the second transistor 30 further includes a second source-drain layer 302 disposed corresponding to the second active layer 301; wherein the second active layer 301, the second source-drain layer 302 and the first source-drain layer 202 are disposed in the same layer. Specifically, the first source-drain layer 202 may include a first source portion 2021 and a first drain portion 2022 disposed at intervals, and the second source-drain layer 302 may include a second source portion 3021 and a second drain portion 3022 disposed at intervals. Further, in combination with the above discussion, the first active layer 201 made of metal oxide may include an active layer body and doped portions with higher conductivity located on two opposite sides of the active layer body. In this embodiment, the first source portion 2021 and the first drain portion 2022 may be electrically connected to the corresponding two doped portions, respectively, and the second source portion 3021 and the second drain portion 3022 may be electrically connected to the opposite sides of the corresponding second active layer 301, respectively.

[0043] It can be understood that in this embodiment, since the second active layer 301 made of amorphous silicon does not need to be conductively processed, the second active layer 301 and the second source and drain layer 302 are arranged in the same layer to reduce the thickness of the second transistor 30. Based on the first active layer 201 made of metal oxide, since it needs to be conductively processed, the first source and drain layer 202 can be arranged in a different layer from the first active layer 201 to avoid affecting the conductive processing. Furthermore, in this embodiment, the first source and drain layer 202 arranged in a different layer from the first active layer 201 is arranged to be arranged in the same layer as the second source and drain layer 302, which can further reduce the sum of the thicknesses of the first transistor 20 and the second transistor 30. Furthermore, the first source and drain layer 202 and the second source and drain layer 302 can be made simultaneously with the same material to simplify the manufacturing process of the display panel 100. Among them, the constituent materials of the first source and drain layer 202 and the constituent materials of the second source and drain layer 302 may include one or more metals selected from molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, calcium, titanium, tantalum, tungsten, and copper. The first source and drain layer 202 and the second source and drain layer 302 may be single-layer films or multi-layer films. For example, the multi-layer film may be formed into a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0044] In one embodiment, if Figure 2 As shown, the buffer layer 40 is provided with a via hole 50, the via hole 50 is arranged opposite to the first active layer 201, the first source-drain layer 202 is electrically connected to the first active layer 201 through the via hole 50; the second source-drain layer 302 is arranged in contact with the second active layer 301. Specifically, in combination with the above discussion, the via hole 50 in this embodiment may include a first via hole 501 arranged opposite to the first source electrode portion 2021, and a second via hole 502 arranged opposite to the first drain electrode portion 2022. The via hole 50 may be filled with a conductive material to electrically connect the first active layer 201 and the first source-drain electrode layer 202. Furthermore, the constituent material of the conductive material and the constituent material of the first active layer 201 may be the same, so that the first active layer 201 filled in the via hole 50 and extending to the buffer layer 40 is formed by the same process. Specifically, in combination with the above discussion, the second source-drain layer 302 is arranged in the same layer as the second active layer 301. Further, the second source portion 3021 and the second drain portion 3022 arranged at intervals in the second source-drain layer 302 can be respectively contacted with the two opposite sides of the second active layer 301 to be electrically connected to the two opposite sides of the second active layer 301.

[0045] It can be understood that the first buffer layer 401 and the second buffer layer 402 in the buffer layer 40 of the present invention are stacked, and a via hole 50 penetrating the first buffer layer 401 and the second buffer layer 402 can be formed at one time, thereby avoiding the formation of the first buffer layer 401 and the second buffer layer 402 at intervals, thereby avoiding the formation of a first sub-via hole penetrating the first buffer layer 401 and a second sub-via hole penetrating the second buffer layer 402 by two via hole processes at intervals, thereby simplifying the process of the display panel 100 and reducing the cost of the display panel 100.

[0046] In one embodiment, if Figure 2 As shown, the first transistor 20 further includes a first gate layer 203 located on a side of the first active layer 201 close to or away from the substrate 10 , and the second transistor 30 further includes a second gate layer 303 located on a side of the second active layer 301 away from the substrate 10 . Specifically, for the first transistor 20, since the first active layer 201 and the first source-drain layer 202 are arranged in different layers, and the first source-drain layer 202 is arranged opposite to the two opposite sides of the first active layer 201, further, if the first gate layer 203 is arranged on the side of the first active layer 201 close to the substrate 10, the first gate layer 203 and the first source-drain layer 202 can be arranged in the same layer to reduce the thickness of the first transistor 20. Furthermore, the constituent material of the first gate layer 203 and the constituent material of the first source-drain layer 202 can be the same so that the two can be manufactured at the same time. If the first gate layer 203 is arranged on the side of the first active layer 201 away from the substrate 10, a gate insulating layer 204 can be arranged between the first gate layer 203 and the first active layer 201 to insulate the two, wherein the active layer body mentioned above can be arranged at least opposite to the first gate layer 203. Of course, no matter what the specific position of the first gate layer 203 is, the first gate layer 203 can be made of one or more metals selected from molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, calcium, titanium, tantalum, tungsten, and copper to have low resistance.

[0047] Specifically, for the second transistor 30, since the second active layer 301 is made of amorphous silicon, the second transistor 30 can be used to make a photosensitive device. Furthermore, the second gate layer 303 in this embodiment is located on the side of the second active layer 301 away from the substrate 10, that is, the second gate layer 303 is arranged closer to the light-emitting surface of the display panel 100 compared with other film layers in the second transistor 30, which can reduce the perception distance of the second gate layer 303 to external light, thereby improving the perception ability of the second transistor 30 to external light.

[0048] In one embodiment, if Figure 2As shown, the display panel 100 further includes: a dielectric layer 60, which is located between the first active layer 201 and the second gate layer 303, and the constituent material of the second gate layer 303 includes a transparent conductive material. It should be noted that in this embodiment, the constituent materials of the second gate layer 303 and the first active layer 201 located on the side of the buffer layer 40 away from the substrate 10 are different, so the dielectric layer 60 is provided to insulate the two, and the constituent materials of the dielectric layer 60 may include but are not limited to silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide and other inorganic insulating substances. Further, since the second gate layer 303 and the first active layer 201 are arranged at intervals in the horizontal direction, the dielectric layer 60 may at least cover the space between the second gate layer 303 and the first active layer 201 to insulate the two. Among them, the constituent materials of the second gate layer 303 may include but are not limited to tin-doped indium oxide.

[0049] Among them, on the side of the dielectric layer 60 away from the substrate, a circuit layer made of the same material as the second gate layer 303 can be set to transmit the corresponding signal to save the process. Further, a flat layer can be set on the side of the dielectric layer 60 away from the substrate 10 and the side of the second gate layer 303 away from the substrate 10 to form a flat surface, and then a light-emitting device is formed on the side of the flat layer away from the substrate 10. The light-emitting device may include but is not limited to a micro light-emitting diode and a sub-millimeter light-emitting diode.

[0050] In one embodiment, if Figure 3 As shown, the display panel 100 further includes: a pixel driving circuit, including a plurality of third transistors 40, and the plurality of third transistors 30 are arranged in the same layer as the first transistor 20 or the second transistor 30. Specifically, it is explained here by taking the constituent material of the third transistor 30 as the same as the constituent material of the first transistor 20 as an example, that is, the plurality of third transistors 40 and the first transistor 20 can both realize the driving of the device, based on this, further, the number and type of film layers in the plurality of third transistors 30 can be the same as the number and type of film layers in the first transistor 20, and further, each film layer in the plurality of third transistors 30 and the corresponding film layer in the first transistor 20 are made of the same material, in the same layer and at the same time.

[0051] The present invention provides a display panel, comprising: a substrate; a first transistor, located on the substrate, comprising a first active layer; a second transistor, located on the substrate, comprising a second active layer, wherein the second active layer and the first active layer are arranged in different layers; a buffer layer, located between the first active layer and the second active layer, comprising a first buffer layer arranged in contact with the first active layer and a second buffer layer arranged in contact with the second active layer. In the present invention, by arranging the first buffer layer arranged in contact with the first active layer and the second buffer layer arranged in contact with the second active layer between the second active layer and the first active layer, the first buffer layer and the second buffer layer are continuously formed through the same process on the basis of acting on the first active layer and the second active layer respectively at the same time, the increase in the number of process changes caused by forming the first buffer layer and the second buffer layer twice at intervals can be avoided, the manufacturing efficiency of the buffer layer is improved, and the integration difficulty of the first transistor and the second transistor is reduced, and the cost of the display panel is effectively reduced.

[0052] The display panel provided in the embodiments of the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A first transistor, located on the substrate, comprising a first active layer, wherein the first active layer is located on a side of the buffer layer away from the substrate; a second transistor, located on the substrate, comprising a second active layer, wherein the second active layer and the first active layer are arranged in different layers; a buffer layer, located between the first active layer and the second active layer, including a first buffer layer disposed in contact with the first active layer and a second buffer layer disposed in contact with the second active layer, wherein a constituent material of the first buffer layer is different from a constituent material of the second buffer layer; Wherein, the constituent material of the first active layer includes metal oxide, and the constituent material of the second active layer includes amorphous silicon; The first transistor further includes a first source-drain electrode layer arranged corresponding to the first active layer, the second transistor further includes a second source-drain electrode layer arranged corresponding to the second active layer, the second active layer, the second source-drain electrode layer and the first source-drain electrode layer are arranged in the same layer, and the second active layer is located on a side of the first active layer close to the substrate; The first transistor further includes a first gate layer located on a side of the first active layer away from the substrate, and the second transistor further includes a second gate layer located on a side of the second active layer away from the substrate.

2. The display panel according to claim 1, characterized in that: The constituent material of the first buffer layer includes silicon oxide, and the constituent material of the second buffer layer includes silicon nitride.

3. The display panel according to claim 1, characterized in that: The buffer layer is provided with a via hole, the via hole is arranged opposite to the first active layer, the first source and drain layer is electrically connected to the first active layer through the via hole; the second source and drain layer is arranged in contact with the second active layer.

4. The display panel according to claim 1, characterized in that: Also includes: The dielectric layer is located between the first active layer and the second gate layer, and the component material of the second gate layer includes a transparent conductive material.

5. The display panel according to claim 1, characterized in that: Also includes: The pixel driving circuit comprises a plurality of third transistors, wherein the plurality of third transistors are arranged in the same layer as the first transistor or the second transistor.

Images