Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate comprising a substrate and a fin on the substrate, the substrate comprising a first region for forming a first device and a second region for forming a second device, a channel width of the first device being smaller than a channel width of the second device; an isolation layer on the substrate exposed by the fin and covering part of the sidewall of the fin; a device gate structure on the isolation layer and across the fin, the device gate structure covering part of the top and part of the sidewall of the fin; a fin sidewall under the device gate structure in the first region, the fin sidewall covering part of the sidewall of the fin exposed by the isolation layer. The application makes the height of the fin controlled by the device gate structure in the first region smaller under the action of the fin sidewall, and the effective channel width of the fin in the first region correspondingly smaller, thereby realizing the effect of the first device and the second device having different channel widths and improving the flexibility of adjusting the effective channel width of the device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the gradual development of semiconductor process technology, the semiconductor process node is constantly reduced following the development trend of Moore's law. In order to adapt to the reduction of the process node, the channel length of the MOSFET field effect transistor is also shortened accordingly. However, as the device channel length is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel is poor, and the difficulty of the gate voltage to pinch off the channel is also increasing, making the subthreshold leakage phenomenon, namely the so-called short channel effect (SCE) more likely to occur.

[0003] Therefore, in order to better adapt to the requirement of device size scaling down, the semiconductor process gradually starts to transition from the planar MOSFET to the three-dimensional transistor with higher efficiency, such as the Fin Field-Effect Transistor (FinFET). In the FinFET, the gate can at least control the ultra-thin body (fin) from two sides, compared with the planar MOSFET, the control ability of the gate to the channel is stronger, and the short channel effect can be well suppressed; and the FinFET has better compatibility with the existing integrated circuit manufacturing compared with other devices. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, to improve the flexibility of adjusting the effective channel width of the device.

[0005] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate comprising a substrate and a fin on the substrate, the substrate comprising a first region for forming a first device and a second region for forming a second device, the channel width of the first device being smaller than the channel width of the second device; an isolation layer on the exposed substrate of the fin and covering part of the sidewall of the fin; a device gate structure on the isolation layer and across the fin, the device gate structure covering part of the top and part of the sidewall of the fin; a fin sidewall under the device gate structure in the first region, the fin sidewall covering part of the sidewall of the fin exposed by the isolation layer.

[0006] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, including a substrate and a fin on the substrate, the substrate including a first region for forming a first device and a second region for forming a second device, a channel width of the first device being smaller than a channel width of the second device, an isolation layer covering part of a side wall of the fin being formed on the substrate exposed by the fin, a pseudo gate structure being formed on the isolation layer and crossing the fin, the pseudo gate structure covering part of a top and part of a side wall of the fin; performing a patterning process on the pseudo gate structure, for removing the pseudo gate structure in the second region and part of the pseudo gate structure in the first region, forming a residual pseudo gate structure in the first region, the residual pseudo gate structure covering part of a side wall of the fin exposed by the isolation layer; after the patterning process on the pseudo gate structure, forming a device gate structure on the isolation layer and the residual pseudo gate structure and crossing the fin at a position of the pseudo gate structure, the device gate structure covering part of a top and part of a side wall of the fin.

[0007] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0008] In the semiconductor structure provided by the embodiment of the present application, a fin side wall is formed below the device gate structure of the first region, the fin side wall covering part of a side wall of the fin exposed by the isolation layer; in the first region, part of a side wall of the fin is covered by the fin side wall, and the remaining fin exposed by the fin side wall is controlled by the device gate structure, so that, under the action of the fin side wall, the fin controlled by the device gate structure in the first region has a smaller height compared with the fin in the second region, and accordingly, the effective channel width of the fin in the first region is smaller, thereby achieving the effect that the first device and the second device have different channel widths, and improving the flexibility of adjusting the effective channel width of the device.

[0009] The forming method of the semiconductor structure provided by the embodiment of the present application includes: performing a patterning process on the dummy gate structure, so as to remove the dummy gate structure in the second region and part of the dummy gate structure in the first region, and form a residual dummy gate structure in the first region, the residual dummy gate structure covering part of the sidewall of the fin exposed by the isolation layer, and after the patterning process on the dummy gate structure, a device gate structure is formed on the isolation layer and the residual dummy gate structure and across the fin; in the first region, part of the sidewall of the fin is covered by the residual dummy gate structure, and the remaining fin exposed by the residual dummy gate structure is controlled by the device gate structure, so that the height of the fin controlled by the device gate structure in the first region is reduced by forming the residual dummy gate structure in the first region, and correspondingly, the effective channel width of the fin in the first region is reduced, so that the first device and the second device have different channel widths, and the flexibility of adjusting the effective channel width of the device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a structure schematic diagram of an embodiment of the semiconductor structure of the present application;

[0011] Figure 2 is a structure schematic diagram of another embodiment of the semiconductor structure of the present application;

[0012] Figure 3 is a structure schematic diagram of still another embodiment of the semiconductor structure of the present application;

[0013] Figures 4 to 8 is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application;

[0014] Figure 9 is a structure schematic diagram of another embodiment of the forming method of the semiconductor structure of the present application;

[0015] Figures 10 to 11 is a structure schematic diagram corresponding to each step in still another embodiment of the forming method of the semiconductor structure of the present application;

[0016] Figures 12 to 14 is a structure schematic diagram corresponding to each step in still another embodiment of the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0017] In actual process, according to the design requirement, devices with different channel widths need to be formed on the same substrate. The current fin field effect transistor (FinFET) generally includes a substrate, a fin standing on the substrate, and a gate structure across the fin and covering part of the top and part of the sidewall of the fin, wherein the fin covered by the gate structure provides the channel width.

[0018] In the current FinFET structure, the channel width of a single fin is fixed and cannot be changed, and the effective channel width of a device can only be changed by changing the number of fins corresponding to the device. This results in the effective channel width being increased only in multiples of positive integers, thereby resulting in the effective channel width of each device on the substrate being unable to be adjusted freely according to design.

[0019] To solve the technical problem, an embodiment of the present application provides a semiconductor structure, comprising: a substrate comprising a substrate and a fin on the substrate, the substrate comprising a first region for forming a first device and a second region for forming a second device, a channel width of the first device being smaller than a channel width of the second device; an isolation layer on the substrate exposed by the fin and covering part of a sidewall of the fin; a device gate structure on the isolation layer and across the fin, the device gate structure covering part of a top and part of a sidewall of the fin; a fin sidewall under the device gate structure in the first region, the fin sidewall covering part of a sidewall of the fin exposed by the isolation layer.

[0020] In the semiconductor structure provided by the embodiment of the present application, the fin sidewall is formed under the device gate structure in the first region, the fin sidewall covering part of a sidewall of the fin exposed by the isolation layer; in the first region, part of a sidewall of the fin is covered by the fin sidewall, and the remaining fin exposed by the fin sidewall is controlled by the device gate structure, so that, under the action of the fin sidewall, the fin controlled by the device gate structure in the first region is smaller in height than the fin in the second region, and accordingly, the effective channel width of the fin in the first region is smaller, thereby achieving the effect that the first device and the second device have different channel widths and improving the flexibility of adjusting the effective channel width of the device.

[0021] To make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, specific embodiments of the present application are described in detail below with reference to the drawings.

[0022] Figure 1 is a structure schematic diagram of an embodiment of the semiconductor structure of the present application.

[0023] The semiconductor structure comprises: a substrate (not shown) comprising a substrate 400 and a fin 410 on the substrate 400, the substrate 400 comprising a first region 400a for forming a first device and a second region 400b for forming a second device, a channel width of the first device being smaller than a channel width of the second device; an isolation layer 420 on the substrate 400 exposed by the fin 410 and covering part of the sidewall of the fin 410; a device gate structure 490 on the isolation layer 420 and across the fin 410, the device gate structure 490 covering part of the top and part of the sidewall of the fin 410; and a fin sidewall 460 under the device gate structure 490 in the first region 400a, the fin sidewall 460 covering part of the sidewall of the fin 410 exposed by the isolation layer 420.

[0024] The fin sidewall 460 is formed under the device gate structure 490 in the first region 400a, the fin sidewall 460 covering part of the sidewall of the fin 410 exposed by the isolation layer 420; in the first region 400a, part of the sidewall of the fin 410 is covered by the fin sidewall 460, and the remaining fin 410 exposed by the fin sidewall 460 is controlled by the device gate structure 490, so that, under the action of the fin sidewall 460, the height of the fin 410 controlled by the device gate structure 490 in the first region 400a is smaller than that of the fin 410 in the second region 400b, and accordingly, the effective channel width of the fin 410 in the first region 400a is smaller, thereby achieving the effect of the first device and the second device having different channel widths and improving the flexibility of adjusting the effective channel width of the device.

[0025] The substrate provides a process operation basis for the forming process of the semiconductor structure.

[0026] In the embodiment, the semiconductor structure is a fin field effect transistor, and the substrate accordingly comprises a substrate 400 and a fin 410 on the substrate 400.

[0027] In the embodiment, the material of the substrate 400 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials such as indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates.

[0028] The fin 410 is separated on the substrate 400, and part of the height of the fin 410 is used to provide a channel of the fin field effect transistor.

[0029] In this embodiment, the fin 410 and the substrate 400 are an integral structure, and the material of the fin 410 and the substrate 400 is the same, both being silicon. In other embodiments, the material of the fin can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. In other embodiments, depending on the actual situation, the fin can also be a semiconductor layer epitaxially grown on the substrate, and the materials of the fin and the substrate can also be different.

[0030] In this embodiment, in the arrangement direction of the plurality of fins 410, the substrate 400 includes a first region 400a for forming a first device and a second region 400b for forming a second device, wherein the channel width of the first device is smaller than the channel width of the second device.

[0031] The top and sidewalls of the fin 410, which are covered by the device gate structure 490, together provide the channel width. Therefore, FinFET provides a channel width per unit area compared to planar transistors.

[0032] The isolation layer 420 serves as a shallow trench isolation (STI) structure to isolate adjacent devices. The isolation layer 420 is made of an insulating material. As an example, the isolation layer 120 is made of silicon oxide. In other embodiments, the isolation layer may also be made of silicon nitride, silicon oxynitride, or silicon carbonitride.

[0033] The device gate structure 490 spans the fin 410 and covers part of the top and part of the sidewall of the fin 410. The device gate structure 490 is used to control the opening or closing of the device channel.

[0034] In this embodiment, the device gate structure 490 includes a metal gate structure, thereby improving the short-channel effect as device feature sizes continue to shrink. Specifically, the device gate structure 490 includes a gate dielectric layer 470 and a gate layer 480 covering the gate dielectric layer 470.

[0035] The gate dielectric layer 470 is used to isolate the gate layer 480 and the channel. In this embodiment, the gate dielectric layer 470 is made of a high-k dielectric material, where a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the gate dielectric layer 470 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the gate dielectric layer 470 is HfO2.

[0036] The gate layer is a metal gate layer, which is used to lead out the electrical property of the metal gate structure. The material of the gate layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. As an example, the material of the gate layer is W.

[0037] In this embodiment, the gate dielectric layer 470 covers the fin sidewall 460 correspondingly, so as to isolate the fin sidewall 460 from other film layers in the device gate structure 490, thereby reducing or avoiding the influence of the fin sidewall 460 on the device performance.

[0038] In this embodiment, the metal gate structure includes a work function layer (not shown in the figure) between the gate dielectric layer 470 and the gate layer 480. The work function layer is used to adjust the threshold voltage of the fin field effect transistor. When the device is a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when the device is an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, ALN and TiAlC.

[0039] It should be noted that the metal gate structure can also include an interface layer (IL) between the gate dielectric layer 470 and the surface of the fin 410. In this embodiment, the material of the interface layer is silicon oxide.

[0040] The fin sidewall 460 is located below the device gate structure 490 in the first region 400a and covers the part of the sidewall of the fin 410 exposed by the isolation layer 420, and the top of the fin sidewall is lower than the top of the fin 410.

[0041] The fin 410 covered by the fin sidewall 460 is not controlled by the device gate structure 490, and therefore, under the action of the fin sidewall 460, the height of the fin 410 covered by the device gate structure 490 is reduced, which correspondingly plays a role in adjusting the effective channel width of the first device, so that the first device and the second device can have different channel widths, and the flexibility of adjusting the effective channel width of the device is improved.

[0042] In this embodiment, the material of the fin sidewall 460 includes one or more of polysilicon, amorphous silicon and silicon oxide. Polysilicon, amorphous silicon or silicon oxide has high compatibility with semiconductor processes and has little influence on the device performance.

[0043] In this embodiment, the fin sidewall 460 is a residual dummy gate structure.

[0044] In the forming process of the semiconductor structure, a dummy gate structure is usually formed to occupy the position of the device gate structure 490, and after forming an interlayer dielectric layer (not shown), the dummy gate structure is removed to form a gate opening in the interlayer dielectric layer, and then the device gate structure 490 is formed in the gate opening. The fin side wall 460 is a residual dummy gate structure, that is, the fin side wall 460 is formed by retaining part of the dummy gate structure in the process of removing the dummy gate structure of the first region 400a, which makes the fin side wall 460 be formed in a way that is highly compatible with the current process, the process of forming the fin side wall 460 is simple, and no additional material is needed, thus reducing the process cost.

[0045] Moreover, the fin side wall 460 is made of the same material as the dummy gate structure, and the existence of the fin side wall 460 has little effect on the device performance.

[0046] In addition, the residual dummy gate structure is easily oxidized in the process of forming the interface layer, and is also easily oxidized in the annealing process after forming the gate dielectric layer 470, therefore, the material on the surface of the fin side wall 460 can also be an oxide material, so as to further reduce the effect of the fin side wall 460 on the device performance.

[0047] Therefore, taking the material of the dummy gate structure, which is polysilicon, as an example, the fin side wall 460 can be a polysilicon layer, or include a polysilicon layer and a silicon oxide layer covering the surface of the polysilicon layer.

[0048] In the embodiment, the semiconductor structure further includes a gate oxide layer 430 located between the residual dummy gate structure (i.e., the fin side wall 460) and the sidewall of the fin 410.

[0049] In the forming process of the semiconductor structure, the gate oxide layer 430 usually covers the surface of the fin 410 exposed to the isolation layer 420, the dummy gate structure correspondingly covers the gate oxide layer 430, and the gate oxide layer 430 is used as an etching stop layer when the dummy gate structure is removed, so as to reduce the damage to the fin 410 caused by the process of removing the dummy gate structure. Therefore, the embodiment uses the residual dummy gate structure as the fin side wall 460, which can adjust the effective channel width of the device while reducing the damage to the fin 410.

[0050] In the embodiment, the material of the gate oxide layer 430 is silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.

[0051] It should be noted that the fin 410 height covered by the fin side wall 460 should not be too small or too large. If the fin 410 height covered by the fin side wall 460 is too small, the effect of adjusting the effective channel width of the device is not obvious; if the fin 410 height covered by the fin side wall 460 is too large, the fin 410 height controlled by the device gate structure 490 is too small, thereby the control ability of the device gate structure 490 on the channel is weakened, and further the device leakage current is large. Therefore, in the embodiment, the fin 410 height covered by the fin side wall 460 is 10-50 nm. to

[0052] In the embodiment, the fin side wall 460 covers the top of the isolation layer 420 exposed by the fin 410 and covers part of the sidewall of the fin 410.

[0053] Figure 2 is a structure schematic diagram of another embodiment of the semiconductor structure of the present application.

[0054] The same parts of the embodiment and the foregoing embodiments are not repeated here, and the difference between the embodiment and the foregoing embodiments is that the fin side wall 560 is located at the corner of the top of the fin 510 and the isolation layer 520 and covers part of the sidewall of the fin 510.

[0055] In the embodiment, taking the fin side wall 560 as an example of the residual pseudo-gate structure, in the forming process of the semiconductor structure, by controlling the removal amount of the pseudo-gate structure and the etching rate, the fin side wall 560 covering part of the sidewall of the fin 510 is easily formed at the corner of the top of the fin 510 and the isolation layer 520.

[0056] Specifically, in the process of etching and removing the pseudo-gate structure, once the top of the fin 510 is exposed, the etching rate of the pseudo-gate structure on the sidewall of the fin 510 is slow, and the etching rate of the pseudo-gate structure on the top of the isolation layer 520 is fast, so that after the pseudo-gate structure on the isolation layer 520 is removed, the corner of the top of the fin 510 and the isolation layer 520 is easy to have the residual of the pseudo-gate structure.

[0057] Correspondingly, in other embodiments, when the etching rate of the dummy gate structure in different regions on the substrate (not shown) has a difference, the partial fin side wall can also be located at the corner of the fin and the isolation layer top and cover part of the fin sidewall, and the remaining fin side wall covers the exposed isolation layer top of the fin and covers part of the fin sidewall. For example, the fin pitch on the substrate in different regions is different, the smaller the space between adjacent fins, the smaller the etching rate when etching the dummy gate structure between the fins, and therefore, after the dummy gate structure on the isolation layer in the remaining region is removed, part of the thickness of the dummy gate structure on the isolation layer top remains in the region with a smaller space between adjacent fins.

[0058] The specific description of the semiconductor structure can be combined with the corresponding description in the foregoing embodiments, which will not be repeated here.

[0059] Figure 3 is a structural schematic diagram of another embodiment of the semiconductor structure of the present application.

[0060] The same parts of the embodiments of the present application as the foregoing embodiments will not be repeated here, and the difference between the embodiments of the present application and the foregoing embodiments is that the semiconductor structure further comprises: a partition structure 680 located on the isolation layer 620 at the junction of the first region 600a and the second region 600b, and the partition structure 680 is used to isolate the device gate structure 695 in the first region 600a and the second region 600b in the arrangement direction of the fin 610.

[0061] Specifically, the partition structure 680 penetrates the device gate structure 695 at the junction of the first region 600a and the second region 600b. The partition structure 680 is used to insulate the device gate structure 695 in the first region 600a and the second region 600b from each other.

[0062] In the embodiment, the hardness and density of the material of the partition structure 680 are high, thereby reducing the probability of damage to the partition structure 680 in the process of forming the semiconductor structure, and further ensuring the isolation performance of the partition structure 680. As an example, the material of the partition structure 680 is silicon nitride. In other embodiments, the partition structure can also be other nitrogen-containing dielectric materials (such as silicon oxynitride, etc.). In other embodiments, the material of the partition structure can also be silicon oxide.

[0063] In the embodiment, the device gate structure 695 comprises a gate dielectric layer 670 and a gate electrode layer 690 covering the gate dielectric layer 670.

[0064] In this embodiment, the device gate structure 695 is formed by removing the dummy gate structure, thus the gate dielectric layer 670 in each region also extends to cover the sidewall of the isolation structure 680.

[0065] In this embodiment, the fin sidewall 660 is the residual dummy gate structure, and in the first region 600a, the fin sidewall 660 between the isolation structure 680 and the adjacent fin 610 covers the top of the isolation layer 620 exposed by the fin 610 and covers part of the sidewall of the fin 610, and the remaining fin sidewall 660 is located at the corner of the fin 610 and the top of the isolation layer 620 and covers part of the sidewall of the fin 610.

[0066] In the first region 600a, the interval between the isolation structure 680 and the adjacent fin 610 is smaller than the interval between the adjacent fins 610, thus in the process of etching to remove the dummy gate structure, the etching rate of the dummy gate structure between the isolation structure 680 and the adjacent fin 610 is smaller, and when the dummy gate structure on the top of the isolation layer 620 in the remaining positions is removed, the dummy gate structure on the top of the isolation layer 620 in the region between the isolation structure 680 and the adjacent fin 610 still has a part of the thickness reserved, so that the fin sidewall 660 between the isolation structure 680 and the adjacent fin 610 covers the top of the isolation layer 620 exposed by the fin 610 and covers part of the sidewall of the fin 610, and the remaining fin sidewall 660 is located at the corner of the fin 610 and the top of the isolation layer 620 and covers part of the sidewall of the fin 610.

[0067] It should be noted that the interval between the isolation structure 680 and the adjacent fin 610 is smaller, and by making the fin sidewall 660 between the isolation structure 680 and the adjacent fin 610 cover the top of the isolation layer 620 exposed by the fin 610, the aspect ratio of the trench surrounded by the isolation structure 680, the adjacent fin 610 and the fin sidewall 660 is reduced, so as to facilitate the formation of each film layer of the device gate structure 695 in the trench, and to improve the quality and performance of the device gate structure 695.

[0068] Figures 4 to 8 is the structure diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure.

[0069] Reference Figure 4, a substrate is provided, including a substrate 100 and fins 110 on the substrate 100, the substrate 100 including a first region 100a for forming a first device and a second region 100b for forming a second device, a channel width of the first device being smaller than a channel width of the second device, an isolation layer 120 being formed on the substrate 100 exposed by the fins 110, the isolation layer 120 covering part of sidewalls of the fins 110, and a dummy gate structure 140 being formed on the isolation layer 120, the dummy gate structure 140 covering part of top and sidewalls of the fins 110.

[0070] The substrate provides a process operation basis for a forming process of the semiconductor structure.

[0071] In this embodiment, the semiconductor structure is a fin field effect transistor, and the substrate accordingly includes a substrate 100 and fins 110 on the substrate 100.

[0072] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0073] The fins 110 are separated on the substrate 100, and part of the height of the fins 110 is used to provide a channel of a fin field effect transistor. In this embodiment, the fins 110 and the substrate 100 are an integral structure, and the material of the fins 110 is the same as that of the substrate 100, both being silicon. In other embodiments, the material of the fins can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. In other embodiments, the fins can also be a semiconductor layer epitaxially grown on the substrate according to actual conditions, and the materials of the fins and the substrate can also be different.

[0074] In this embodiment, in the arrangement direction of the plurality of fins 110, the substrate 100 includes a first region 100a for forming a first device and a second region 100b for forming a second device, a channel width of the first device being smaller than a channel width of the second device.

[0075] The isolation layer 120 serves as a shallow trench isolation structure (STI) and is used to isolate adjacent devices. In addition, the isolation layer 120 is used to define an effective height of the fins 110, that is, the entire fin 110 or part of the fin 110 exposed by the isolation layer 120 is used as a channel of a device.

[0076] The material of the isolation layer 120 is insulating material. As an example, the material of the isolation layer 120 is silicon oxide. In other embodiments, the material of the isolation layer can also be silicon nitride, silicon oxynitride or silicon oxycarbonitride.

[0077] The dummy gate structure 140 is used to occupy space position for forming device gate structure later. The material of the dummy gate structure 140 includes one or more of polysilicon and amorphous silicon. Polysilicon or amorphous silicon has higher process compatibility, and it is easy to achieve higher etching selectivity between the material and silicon oxide, thereby reducing damage to the isolation layer 120 or interlayer dielectric layer (not shown in the figure) in the process of etching the dummy gate structure 140 later.

[0078] It should be noted that the dummy gate structure 140 is also formed with an interlayer dielectric layer (not shown in the figure) on the side isolation layer 120. The interlayer dielectric layer is used to provide a process basis for the formation of the device gate structure, and also used to isolate adjacent devices. The material of the interlayer dielectric layer is insulating material. As an example, the material of the interlayer dielectric layer is silicon oxide.

[0079] In this embodiment, the exposed surface of the fin 110 and the dummy gate structure 140 are also formed with a gate oxide layer 130 in the step of providing the substrate.

[0080] When the dummy gate structure 140 is etched later, the gate oxide layer 130 can be used as an etching stop layer, thereby reducing damage to the fin 110 in the process of etching the dummy gate structure 140. In addition, for devices with higher operating voltage (for example, for input / output devices), the gate oxide layer 130 can also be reserved to isolate the device gate structure and the channel. As an example, the material of the gate oxide layer 130 is silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.

[0081] In combination with reference to Figure 5 and Figure 6 The dummy gate structure 140 is patterned to remove the dummy gate structure 140 in the second region 100b, and part of the dummy gate structure 140 in the first region 100a, and form a residual dummy gate structure 160 (as shown in Figure 6 The residual dummy gate structure 160 covers part of the sidewall of the exposed fin 110 of the isolation layer 120.

[0082] In this embodiment, after the dummy gate structure 140 is patterned, a gate opening 101 is formed in the interlayer dielectric layer (not shown in the figure), the gate opening 101 spans the fin 110, and the gate opening 101 is used to provide a space position for the formation of the device gate structure.

[0083] Further, a device gate structure is formed on the isolation layer 120 and the residual dummy gate structure 160 and across the fin 110. In the first region 100a, the residual dummy gate structure 160 serves as a fin sidewall, the part of the sidewall of the fin 110 covered by the residual dummy gate structure 160, and the remaining fin 110 exposed by the residual dummy gate structure 160 is controlled by the device gate structure. Therefore, by forming the residual dummy gate structure 160 in the first region 100a, the height of the fin 110 controlled by the device gate structure in the first region 100a is reduced, and accordingly, the effective channel width of the fin 110 in the first region 100a is reduced, thereby achieving the effect that the first device and the second device have different channel widths and improving the flexibility of adjusting the effective channel width of the device.

[0084] In the embodiment, in the first region 100a, the residual dummy gate structure 160 covers part of the sidewall of the fin 110 exposed by the gate opening 101.

[0085] In the embodiment, in the step of performing the patterning process on the dummy gate structure 140, the material of the residual dummy gate structure 160 is the same as that of the dummy gate structure 140. The residual dummy gate structure 160 is formed of the same material as the dummy gate structure 140, and the residual dummy gate structure 160 has little effect on the performance of the device.

[0086] Further, the residual dummy gate structure 160 is formed by retaining part of the dummy gate structure 140 in the process of removing the dummy gate structure 140 in the first region 100a, which makes the formation of the residual dummy gate structure 160 highly compatible with the current process, the process of forming the residual dummy gate structure 160 is simple, no additional material is needed, and the process cost is low.

[0087] As shown in FIG. 2, the step of performing the patterning process on the dummy gate structure 140 includes performing a first etching process on the dummy gate structure 140 in the second region 100b to remove part of the thickness of the dummy gate structure 140. Figure 5

[0088] Subsequently, a second etching process is performed on the dummy gate structure 140 in the first region 100a and the second region 100b. Since the first etching process is performed first, the thickness of the dummy gate structure 140 in the second region 100b is smaller than that of the dummy gate structure 140 in the first region 100a. Therefore, when the second etching process is performed, the dummy gate structure 140 in the second region 100b is removed early, so that part of the dummy gate structure 140 in the first region 100a can be retained while the dummy gate structure 140 in the second region 100b is removed.

[0089] ​It is to be noted that, in the first-time etching process, the etching amount of the dummy gate structure 140 in the second region 100b is determined according to the height of the fin 110 covered by the residual dummy gate structure and the etching rate of the dummy gate structure 140.

[0090] Specifically, the step of performing the first-time etching process on the dummy gate structure 140 in the second region 100b includes: forming a mask layer 150 covering the first region 100a; and performing the first-time etching process with the mask layer 150 as a mask.

[0091] In the embodiment, the mask layer 150 is formed on the top of the dummy gate structure 140 in the first region 100a.

[0092] The material of the mask layer 150 is selected to be capable of playing a role of etching mask in the process of etching the dummy gate structure 140, and the process of removing the mask layer 150 has less damage to the dummy gate structure 140, so as to reduce the influence on the subsequent process of etching the dummy gate structure 140.

[0093] As an example, the material of the mask layer 150 is photoresist.

[0094] In the embodiment, in the step of performing the first-time etching process on the dummy gate structure 140 in the second region 100b, a dry etching process (for example, an anisotropic dry etching process) is used to etch the dummy gate structure 140 in the second region 100b. The dry etching process has the characteristic of anisotropic etching, which is beneficial to improve the controllability of etching and improve the flatness of the top surface of the residual dummy gate structure 140 after etching.

[0095] As an example, after the first-time etching process, the top of the residual dummy gate structure 140 in the second region 100b is higher than the top of the fin 110, so that the etching effect of the first-time etching process is less affected by the fin 110, and it is easy to make the residual dummy gate structure 140 after etching have a relatively flat top surface.

[0096] In the embodiment, after the first-time etching process, the mask layer 150 is removed to expose the top of the dummy gate structure 140 in the first region 100a, so as to perform a second-time etching process on the dummy gate structure 140 in the first region 100a and the second region 100b.

[0097] As Figure 6As shown, the step of patterning the dummy gate structure 140 further includes: after the first etching back process, performing a second etching back process on the dummy gate structure 140 in the first region 100a and the second region 100b until the dummy gate structure 140 in the second region 100b is removed and the remaining dummy gate structure 140 in the first region 100a is reserved as a residual dummy gate structure 160.

[0098] The dummy gate structure 140 in the second region 100b has a smaller thickness, and thus, after the dummy gate structure 140 in the second region 100b is removed, part of the dummy gate structure 140 in the first region 100a can be reserved as a residual dummy gate structure 160, which covers part of the sidewall of the fin 110.

[0099] Moreover, in the embodiment, when performing the second etching back process, a mask layer is not needed to selectively etch, and thus, compared with the conventional process of removing the dummy gate structure 140, no new mask is needed to meet the requirement of process cost control.

[0100] In the embodiment, in the step of the second etching back process, a dry etching process (for example, an anisotropic dry etching process) is used to etch the dummy gate structure 140 in the first region 100a and the second region 100b. The dry etching process has the characteristic of anisotropic etching and has high controllability of etching, and thus, while continuously reducing the thickness of the dummy gate structure 140, it is easy to reserve the remaining dummy gate structure 140 covering part of the sidewall of the fin 110.

[0101] It should be noted that the dummy gate structure 140 covers the gate oxide layer 130, and in the process of etching the dummy gate structure 140, the gate oxide layer 130 is used as an etching stop layer to reduce the damage of the process of etching the dummy gate structure to the fin 110. Thus, the process of forming the residual dummy gate structure 160 in the embodiment has less damage to the fin 410.

[0102] It should be noted that the height H of the fin 110 covered by the residual dummy gate structure 160 should not be too small or too large. If the height H of the fin 110 covered by the residual dummy gate structure 160 is too small, it is easy to cause the effect of adjusting the effective channel width of the device to be not obvious, and if the height H of the fin 110 covered by the residual dummy gate structure 160 is too large, it is easy to cause the height of the fin 110 controlled by the gate structure of the device to be too small, thus causing the control ability of the gate structure of the device to the channel to be weak, and further causing the leakage current of the device to be large. Therefore, in the embodiment, the height H of the fin 110 covered by the residual dummy gate structure 160 is to

[0103] In this embodiment, the residual dummy gate structure 160 covers the top of the isolation layer 120 exposed by the fin 110 and covers part of the sidewall of the fin 110.

[0104] Referring to Figure 7 After the patterning process on the dummy gate structure 140, the gate oxide layer 130 in the second region 100b and the gate oxide layer 130 exposed by the residual dummy gate structure 160 are removed.

[0105] By removing the exposed gate oxide layer 130, the fin 110 used as a channel is exposed, thereby providing a process basis for subsequent formation of a device gate structure.

[0106] Specifically, the gate oxide layer 130 can be removed by one or both of a wet etching process and a dry etching process. It should be noted that the gate oxide layer 130 and the residual dummy gate structure 160 have an etching selectivity ratio, so the process of removing the gate oxide layer 130 has little effect on the residual dummy gate structure 160.

[0107] In this embodiment, the residual dummy gate structure 160 and the sidewall of the fin 110 are separated by the gate oxide layer 130, further reducing the influence of the residual dummy gate structure 160 on device performance.

[0108] Referring to Figure 8 After the patterning process on the dummy gate structure 140 (as shown in Figure 4 At the position of the dummy gate structure 140, a device gate structure 190 is formed on the isolation layer 120 and the residual dummy gate structure 160 and across the fin 110, the device gate structure 190 covering part of the top and part of the sidewall of the fin 110.

[0109] Specifically, the device gate structure 190 is formed in the gate opening 101.

[0110] The device gate structure 190 is used to control the opening or closing of the device channel.

[0111] In this embodiment, the device gate structure 190 includes a metal gate structure, thereby improving the short channel effect in the case of continuous reduction in device feature size.

[0112] Specifically, the device gate structure 190 includes a gate dielectric layer 170 and a gate layer 180 covering the gate dielectric layer 170.

[0113] The gate dielectric layer 470 is used to isolate the gate layer 480 and the channel.

[0114] In this embodiment, the gate dielectric layer 170 covers the fin sidewall 160 correspondingly, so as to isolate the fin sidewall 160 from other film layers in the device gate structure 190, thereby reducing or avoiding the influence of the fin sidewall 160 on the device performance.

[0115] Further, the gate dielectric layer 170 is formed after the formation of the residual dummy gate structure 160, so as to avoid damage to the gate dielectric layer 170 caused by the process of forming the residual dummy gate structure 160.

[0116] In this embodiment, the material of the gate dielectric layer 170 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the gate dielectric layer 170 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the gate dielectric layer 170 is HfO2.

[0117] The gate layer 180 is a metal gate layer, which is used to lead out the electrical property of the metal gate structure. The material of the gate layer 180 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. As an example, the material of the gate layer 180 is W.

[0118] In this embodiment, the metal gate structure further includes a work function layer (not shown in the figure) between the gate dielectric layer 170 and the gate layer 180.

[0119] The work function layer is used to adjust the threshold voltage of the fin field effect transistor. When the device is a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when the device is an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0120] In this embodiment, in the process of forming the device gate structure 190, before forming the gate dielectric layer 170, it further includes forming an interface layer (not shown in the figure) on the exposed surface of the fin 110.

[0121] The interface layer provides a good interface state for the formation of the gate dielectric layer 170.

[0122] As an example, the material of the interface layer is silicon oxide.

[0123] It should be noted that the process of forming the interface layer is usually carried out in an oxygen-containing environment. Therefore, during the formation of the interface layer, the residual pseudo-gate structure 160 is easily oxidized to a certain extent. Correspondingly, the material on the surface of the residual pseudo-gate structure 160 is easily converted into an oxide material, or the entire residual pseudo-gate structure 160 is oxidized into an oxide material. During the annealing process after forming the gate dielectric layer 170, the residual pseudo-gate structure 160 is also easily oxidized to a certain extent, converting the material on the surface of the residual pseudo-gate structure 160 into an oxide material, or the entire residual pseudo-gate structure 160 is oxidized into an oxide material, thereby further reducing the impact of the residual pseudo-gate structure 160 on device performance.

[0124] For example, if the material of the pseudo-gate structure 140 is polycrystalline silicon, the oxide material is silicon oxide.

[0125] Depending on the degree of oxidation of the residual pseudo-gate structure 160, a silicon oxide layer can be formed on the surface of the residual pseudo-gate structure 160, or the residual pseudo-gate structure 160 can be completely oxidized into a silicon oxide layer.

[0126] Figure 9 This is a schematic diagram of another embodiment of the semiconductor structure formation method of the present invention.

[0127] The similarities between the embodiments of the present invention and the foregoing embodiments will not be repeated here. The difference between the embodiments of the present invention and the foregoing embodiments is that the residual pseudo-gate structure 160 is located at the corner of the top of the fin 210 and the isolation layer 220 and covers part of the sidewall of the fin 210.

[0128] In this embodiment, during the patterning process of the pseudo-gate structure, by controlling the amount of pseudo-gate structure removed and the etching rate, it is easy to form a residual pseudo-gate structure 160 covering part of the sidewall of the fin 210 at the corner of the top of the fin 210 and the isolation layer 220.

[0129] Specifically, during the etching process to remove the pseudo-gate structure, once the top of the fin 210 is exposed, the etching rate of the pseudo-gate structure located on the sidewall of the fin 210 is slower, while the etching rate of the pseudo-gate structure on the top of the isolation layer 220 is faster. Therefore, after removing the pseudo-gate structure on the top of the isolation layer 220, there is a tendency for pseudo-gate structure residues to remain at the corners of the fin 210 and the top of the isolation layer 220.

[0130] In other words, the morphology of the residual pseudo-gate structure 160 is adjusted according to the etching rate of the pseudo-gate structure, the spacing between adjacent fins 210, and the etching amount of the pseudo-gate structure.

[0131] Correspondingly, in other embodiments, when the etching rate of the dummy gate structure in different regions of the substrate has a difference, the residual dummy gate structure 160 can also be partially located at the corner of the fin and the top of the isolation layer and cover part of the sidewall of the fin, and the remaining residual dummy gate structure 160 covers the exposed top of the isolation layer of the fin and covers part of the sidewall of the fin.

[0132] For example, the pitch of the fin in different regions of the substrate is different, the smaller the space between adjacent fins, the smaller the etching rate of the dummy gate structure between the fins during etching, and therefore, after the dummy gate structure on the isolation layer in the remaining region is removed, the dummy gate structure with part of the thickness of the top of the isolation layer remains in the region with smaller space between adjacent fins.

[0133] The specific description of the method for forming the semiconductor structure can be combined with the corresponding description in the foregoing embodiments, which will not be repeated here.

[0134] Figures 10 to 11 is a structure schematic diagram corresponding to each step in another embodiment of the method for forming the semiconductor structure of the application.

[0135] The same as the foregoing embodiments, the differences between the embodiments of the application and the foregoing embodiments are that: in the step of providing the substrate, the isolation layer 320 at the junction of the first region 300a and the second region 300b is formed with a partition structure 390, and the partition structure 390 is used to isolate the dummy gate structure 340 in the first region 300a and the second region 300b in the arrangement direction of the fin 310.

[0136] Reference Figure 10 Specifically, the partition structure 390 penetrates the dummy gate structure 340 at the junction of the first region 300a and the second region 300b.

[0137] The partition structure 390 is used to insulate the dummy gate structure 340 in the first region 300a and the second region 300b from each other, so that the device gate structure formed subsequently is insulated from each other.

[0138] As an example, the step of forming the partition structure 390 includes: etching the dummy gate structure 340 at the junction of the first region 300a and the second region 300b to form a partition opening (not shown in the figure) in the dummy gate structure 340, the partition opening divides the dummy gate structure 340 in the arrangement direction of the fin 310; and forming the partition structure 390 in the partition opening.

[0139] In this embodiment, the material of the partition structure 390 has high hardness and density, thereby reducing the probability of damage to the partition structure 390 in subsequent processes, and thus ensuring the isolation performance of the partition structure 390. As an example, the material of the partition structure 390 is silicon nitride. In other embodiments, the partition structure can also be other nitrogen-containing dielectric materials. In other embodiments, the material of the partition structure can also be silicon oxide.

[0140] Reference Figure 11 In the step of performing the patterning process on the dummy gate structure 340, in the first region 300a, the residual dummy gate structure 360 between the partition structure 390 and the adjacent fin 310 covers the top of the isolation layer 320 exposed by the fin 310 and covers part of the sidewall of the fin 310, and the remaining residual dummy gate structure 360 is located at the corner of the top of the isolation layer 320 and the fin 310 and covers part of the sidewall of the fin 310.

[0141] In the first region 300a, the spacing between the partition structure 390 and the adjacent fin 310 is smaller than the spacing between the adjacent fins 310, so that the etching rate of the dummy gate structure 340 between the partition structure 390 and the adjacent fin 310 is smaller during the etching of the dummy gate structure 340. After the dummy gate structure 340 on the top of the isolation layer 320 at other positions is removed, the dummy gate structure 340 on the top of the isolation layer 320 between the partition structure 390 and the adjacent fin 310 still has a certain thickness, so that the residual dummy gate structure 360 between the partition structure 390 and the adjacent fin 310 covers the top of the isolation layer 320 exposed by the fin 310 and covers part of the sidewall of the fin 310, and the remaining residual dummy gate structure 360 is located at the corner of the top of the isolation layer 320 and the fin 310 and covers part of the sidewall of the fin 310.

[0142] It should be noted that the partition structure 390, the adjacent fin 310, and the residual dummy gate structure 360 form a trench 302, and the spacing between the partition structure 390 and the adjacent fin 310 is small. By making the residual dummy gate structure 360 between the partition structure 390 and the adjacent fin 310 cover the top of the isolation layer 320 exposed by the fin 310, the aspect ratio of the trench 302 is reduced, so as to facilitate the formation of various film layers of the device gate structure in the trench 302 in subsequent processes, and improve the quality and performance of the device gate structure.

[0143] Specifically, the subsequent device gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer, and when the device gate structure is formed, the gate dielectric layer in the first region 300a and the second region 300b also extends to cover the sidewall of the partition structure 390.

[0144] The specific description of the method for forming the semiconductor structure can be combined with the corresponding description in the foregoing embodiments, which will not be repeated here.

[0145] Figures 12 to 14 FIG. 7 is a structural schematic diagram of each step in another embodiment of the method for forming the semiconductor structure of the present application.

[0146] The same parts of the embodiments of the present application as the foregoing embodiments will not be repeated here, and the different parts of the embodiments of the present application from the foregoing embodiments are that the step of performing the patterning process on the dummy gate structure is different.

[0147] Reference Figure 12 The step of performing the patterning process on the dummy gate structure includes: performing a second etching process on the dummy gate structure in the first region 700a and the second region 700b, and retaining the remaining dummy gate structure covering part of the sidewall of the fin 710 as the residual dummy gate structure 760.

[0148] In this embodiment, the dummy gate structure in the first region 700a and the second region 700b is etched by a maskless etching method. Specifically, the etching process is a dry etching process.

[0149] The specific description of the etching process and the residual dummy gate structure 760 can be referred to the related description in the foregoing embodiments, which will not be repeated here.

[0150] Reference Figure 13 After the second etching process, a first etching process is performed on the dummy gate structure (i.e., the residual dummy gate structure 760) in the second region 700b, for removing the residual dummy gate structure 760 in the second region 700b.

[0151] In this embodiment, the step of performing the first etching process on the dummy gate structure in the second region 700b includes: forming a mask layer 750 shielding the first region 700a; and performing the first etching process with the mask layer 750 as a mask.

[0152] Specifically, the mask layer 750 covers the residual dummy gate structure 760 and the fin 710 in the first region 700a. As an example, the material of the mask layer 750 is photoresist.

[0153] The specific description of the etching process and the mask layer 750 can be referred to the related description in the foregoing embodiments, which will not be repeated here.

[0154] In this embodiment, after removing the residual dummy gate structure 760 in the second region 700b, the mask layer 750 is removed, thereby preparing for removing the exposed gate oxide layer 730.

[0155] In this embodiment, the dummy gate structure is patterned by sequentially performing the second etching process and the first etching process. In the first etching process, no mask layer is needed, so compared with the conventional process for removing the dummy gate structure, no additional mask is needed, thereby meeting the requirement of process cost control.

[0156] It should be noted that in other embodiments, according to process requirements, the dummy gate structure in the second region can be removed and the part of the dummy gate structure in the first region can be removed in different steps, respectively. For example, two masks are used to etch the dummy gate structure in the first region and the second region, respectively.

[0157] The specific description of the method for forming the semiconductor structure can be combined with the corresponding description in the foregoing embodiments, which will not be repeated here.

[0158] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure further comprises: a gate oxide layer between the residual dummy gate structure and the sidewall of the fin. The material of the fin sidewall comprises one or more of polysilicon, amorphous silicon, and silicon oxide. The height of the fin covered by the fin sidewall is 5A to 200A. The device gate structure comprises a gate dielectric layer and a gate layer covering the gate dielectric layer. The device gate structure comprises a metal gate structure.

2. The semiconductor structure of claim 1, wherein, The material of the substrate comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, or germanium on insulator. The material of the fin comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The material of the isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

3. The semiconductor structure of claim 1, wherein, The material of the gate oxide layer comprises silicon oxide or silicon oxynitride. The material of the gate dielectric layer comprises HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

4. The semiconductor structure of claim 1, wherein, The material of the gate layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

5. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a gate oxide layer between the residual dummy gate structure and the sidewall of the fin.

6. The semiconductor structure of claim 1, wherein, The material of the fin sidewall comprises one or more of polysilicon, amorphous silicon, and silicon oxide.

7. The semiconductor structure of claim 1, wherein, The height of the fin covered by the fin sidewall is 5A to 200A.

8. The semiconductor structure of claim 1, wherein, The device gate structure comprises a gate dielectric layer and a gate layer covering the gate dielectric layer.

9. The semiconductor structure of claim 1, wherein, The device gate structure comprises a metal gate structure.

10. The semiconductor structure of claim 1, wherein, The material of the substrate comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, or germanium on insulator.

11. The semiconductor structure of claim 1, wherein, The material of the fin comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

12. The semiconductor structure of claim 3, wherein, The material of the isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

13. The semiconductor structure of claim 4, wherein, The material of the gate oxide layer comprises silicon oxide or silicon oxynitride.

14. The semiconductor structure of claim 7, wherein, The material of the gate dielectric layer comprises HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

15. The semiconductor structure of claim 7, wherein, The material of the gate layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

16. A method of forming a semiconductor structure, comprising: The semiconductor structure further comprises: a gate oxide layer between the residual dummy gate structure and the sidewall of the fin. The material of the fin sidewall comprises one or more of polysilicon, amorphous silicon, and silicon oxide. The height of the fin covered by the fin sidewall is 5A to 200A. The device gate structure comprises a gate dielectric layer and a gate layer covering the gate dielectric layer. The device gate structure comprises a metal gate structure. The material of the substrate comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, or germanium on insulator. The material of the fin comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The material of the isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. The material of the gate oxide layer comprises silicon oxide or silicon oxynitride. The material of the gate dielectric layer comprises HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. The material of the gate layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. The semiconductor structure further comprises: a gate oxide layer between the residual dummy gate structure and the sidewall of the fin. The material of the fin sidewall comprises one or more of polysilicon, amorphous silicon, and silicon oxide. The height of the fin covered by the fin sidewall is 5A to 200A. The device gate structure comprises a gate dielectric layer and a gate layer covering the gate dielectric layer. The device gate structure comprises a metal gate structure. The material of the substrate comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, or germanium on insulator. The material of the fin comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The material of the isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. The material of the gate oxide layer comprises silicon oxide or silicon oxynitride. The material of the gate dielectric layer comprises HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. The material of the gate layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. A substrate is provided, including a substrate and a fin on the substrate, the substrate including a first region for forming a first device and a second region for forming a second device, a channel width of the first device being smaller than a channel width of the second device, an isolation layer covering part of a sidewall of the fin being formed on the substrate exposed by the fin, a dummy gate structure being formed on the isolation layer and across the fin, the dummy gate structure covering part of a top and part of a sidewall of the fin; The dummy gate structure is patterned for removing the dummy gate structure in the second region and part of the dummy gate structure in the first region, forming a residual dummy gate structure in the first region, the residual dummy gate structure covering part of a sidewall of the fin exposed by the isolation layer; After the dummy gate structure is patterned, a device gate structure is formed on the isolation layer and the residual dummy gate structure and across the fin at a position of the dummy gate structure, the device gate structure covering part of a top and part of a sidewall of the fin.

17. The method of forming a semiconductor structure of claim 16, wherein, The step of patterning the dummy gate structure includes performing a first etch-back process on the dummy gate structure in the second region to remove part of a thickness of the dummy gate structure; After the first etch-back process, a second etch-back process is performed on the dummy gate structure in the first region and the second region until the dummy gate structure in the second region is removed and a residual dummy gate structure in the first region is retained.

18. The method of forming a semiconductor structure of claim 16, wherein, The step of patterning the dummy gate structure includes performing a second etch-back process on the dummy gate structure in the first region and the second region to retain a residual dummy gate structure covering part of a sidewall of the fin as a residual dummy gate structure; After the second etch-back process, a first etch-back process is performed on the dummy gate structure in the second region for removing the residual dummy gate structure in the second region.

19. The method of forming a semiconductor structure of claim 17 or 18, wherein, The step of performing the first etch-back process on the dummy gate structure in the second region includes forming a mask layer shielding the first region; and performing the first etch-back process with the mask layer as a mask.

20. The method of forming a semiconductor structure of claim 16, wherein, In the step of patterning the dummy gate structure, the residual dummy gate structure is located at a corner of the fin and the isolation layer top and covers part of a sidewall of the fin; Alternatively, the residual dummy gate structure covers part of a top of the isolation layer exposed by the fin and covers part of a sidewall of the fin; Alternatively, part of the residual dummy gate structure is located at a corner of the fin and the isolation layer top and covers part of a sidewall of the fin, and the remaining residual dummy gate structure covers part of a top of the isolation layer exposed by the fin and covers part of a sidewall of the fin.

21. The method of forming a semiconductor structure of claim 16, wherein, In the step of providing the substrate, a partition structure is formed on the isolation layer at a boundary between the first region and the second region, the partition structure being used for isolating the dummy gate structure in the first region and the second region in an arrangement direction of the fin; In the step of patterning the dummy gate structure, in the first region, the residual dummy gate structure between the partition structure and the adjacent fin exposes the top of the isolation layer of the fin and covers part of the sidewall of the fin, and the residual dummy gate structure remaining at the corner of the fin and the top of the isolation layer covers part of the sidewall of the fin.

22. The method of forming a semiconductor structure of claim 16, wherein, In the step of providing the substrate, a gate oxide layer is further formed between the exposed fin surface of the isolation layer and the dummy gate structure.

23. The method of forming a semiconductor structure of claim 22, wherein, After the step of patterning the dummy gate structure, before the step of forming the device gate structure, the method further comprises: removing the gate oxide layer in the second region and the gate oxide layer exposed by the residual dummy gate structure.

24. The method of forming a semiconductor structure of claim 16, wherein, In the step of patterning the dummy gate structure, a dry etching process is used to etch the dummy gate structure in the first region to form the residual dummy gate structure.

25. The method of forming a semiconductor structure of claim 16, wherein, In the step of forming the device gate structure, the device gate structure comprises a gate dielectric layer and a gate electrode layer covering the gate dielectric layer.

26. The method of forming a semiconductor structure of claim 16, wherein, The device gate structure comprises a metal gate structure.

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