A driving circuit and a control method

Abstract

The present application discloses a drive circuit and control method. In the drive circuit, a first drive signal generation module is connected in parallel between the gate and source of a first MOS transistor, and a second drive signal generation module is connected in parallel between the gate and source of a second MOS transistor. The source of the first MOS transistor is connected to the drain of the second MOS transistor, the gate of a first power switch is connected to the source of the second MOS transistor, and the drain of the first power switch is connected to the gate of the second MOS transistor. When the second MOS transistor is in a first off-state, if the first MOS transistor switches from the second off-state to the on-state, the positive peak value of the gate-source voltage of the second MOS transistor is reduced by using the equivalent capacitance of the first power switch in the on-state. In this way, the positive peak value of the gate-source voltage of the second MOS transistor is reduced by using the equivalent capacitance of the first power switch in the on-state, so that the positive peak value of the gate-source voltage of the second MOS transistor does not exceed the voltage threshold when the second MOS transistor is on, thereby preventing the second MOS transistor from being mis-turned on when the first MOS transistor is on, thereby achieving the purpose of alternating conduction of the first and second MOS transistors.

Description

Technical Field

[0001] The present application relates to power electronics technology, and in particular to a silicon carbide MOSFET bridge drive circuit and a control method. Background Art

[0002] Silicon carbide MOSFET has the characteristics of fast switching speed and low loss, and is increasingly used in power electronic circuits. For silicon carbide MOSFET connected in a bridge structure, Figure 1 The figure is a schematic diagram of the bridge structure connection of the existing silicon carbide MOSFET. Figure 1 As shown, it includes an upper tube Q1, a lower tube Q2, resistors Rg1 and Rg2, and drive signal generating modules M1 and M2. One end of M1 is connected to the gate of Q1 through Rg1, and the other end of M1 is connected to the source of Q1. The source of Q1 is connected to the drain of Q2. One end of M2 is connected to the gate of Q2 through Rg2, and the other end of M2 is connected to the source of Q2. Cgd1 is the parasitic capacitance between the gate and drain of Q1, Cgs1 is the parasitic capacitance between the gate and source of Q1, Cds1 is the parasitic capacitance between the drain and source of Q1, Cgd2 is the parasitic capacitance between the gate and drain of Q2, Cgs2 is the parasitic capacitance between the gate and source of Q2, and Cds2 is the parasitic capacitance between the drain and source of Q2.

[0003] The following circuit is described using the lower transistor Q2 as an example. Figure 2(a) shows the first timing diagram of the conventional upper transistor Q1 and lower transistor Q2. As shown in Figure 2(a), when Q2's gate-source voltage Vgs2 is 0 (i.e., M2 provides a low-level signal to Q2, and no current flows between the source and drain), and current flows through Q2's body diode, Q2 is in the first off-state. At this time, Q2's drain-source voltage Vds2 is approximately 0. If Q1's gate-source voltage Vgs1 switches from 0 (i.e., M1 provides a low-level signal to Q1, and no current flows between the source and drain) to 1 (i.e., M1 provides a high-level signal to Q1), Q1 transitions from the second off-state to the on-state. Current commutates from Q2's body diode to the drain and source of Q1. Due to the fast switching speed of the upper and lower transistors, Q1's Vds1 drops rapidly from Vdc to 0, while Q2's Vds2 rises rapidly from 0 to Vdc. The rapid rise in Q2's Vds2 generates a large crosstalk current between Q2's drain and gate. This crosstalk current flows through the parasitic capacitance Cgs2 between the gate and source to charge Cgs2, causing Q2's Vgs2 voltage to rise. Therefore, even if Q2 is in the off state, its Vgs2 voltage will rise (i.e., crosstalk). If the positive peak of Vgs2 exceeds the voltage threshold Vth, it will cause Q2 to be mis-turned on, and then cause the upper tube Q1 and the lower tube Q2 to be turned on at the same time. This is contrary to the characteristic of the alternating conduction of the upper and lower tubes in the silicon carbide MOSFET bridge circuit. Summary of the Invention

[0004] In order to solve the above technical problems, the present application hopes to provide a driving circuit and a control method.

[0005] The technical solution of this application is achieved as follows:

[0006] In a first aspect, a driving circuit is provided, the circuit comprising: a first driving signal generating module, a first MOS transistor, a second driving signal generating module, a second MOS transistor and a first switching transistor;

[0007] The first drive signal generating module is connected in parallel between the gate and source of the first MOS transistor, the second drive signal generating module is connected in parallel between the gate and source of the second MOS transistor, the source of the first MOS transistor is connected to the drain of the second MOS transistor, and the first switch transistor is connected in parallel between the gate and source of the second MOS transistor; the first drive signal generating module is used to generate a first drive signal, and the second drive signal generating module is used to generate a second drive signal;

[0008] When the second MOS transistor is in the first off-state, if the first MOS transistor is switched from the second off-state to the on-state, the positive peak value of the gate-source voltage of the second MOS transistor is reduced by using the equivalent capacitance of the first power switch in the on-state;

[0009] Among them, when the second drive signal is a low-level signal and current flows through the body diode of the second MOS transistor, the second MOS transistor is in a first off-state; when the first drive signal is a low-level signal, the first MOS transistor is in a second off-state; when the first drive signal is a high-level signal, the first MOS transistor is in a conducting state.

[0010] In the above solution, when the second MOS transistor is in the second off-state, if the first MOS transistor switches from the on-state to the second off-state, the negative peak value of the gate-source voltage of the second MOS transistor is increased by utilizing the equivalent capacitance of the first switch transistor in the on-state; wherein, when the second drive signal is a low-level signal, the second MOS transistor is in the second off-state.

[0011] In the above solution, the driving circuit further includes a second power switch tube; wherein the gate of the second power switch tube is connected to the source of the first MOS tube, and the drain of the second power switch tube is connected to the source of the first MOS tube.

[0012] In the above scheme, the driving circuit also includes a first capacitor and a second capacitor; the source of the first power switch tube is suspended, or the first capacitor is connected in parallel between the source and the gate of the first power switch tube; the source of the second power switch tube is suspended, or the second capacitor is connected in parallel between the source and the gate of the second power switch tube.

[0013] In the above solution, the driving circuit further includes a first resistor and a second resistor; wherein the first resistor is connected in parallel across the first capacitor, and the second resistor is connected in parallel across the second capacitor.

[0014] In the above solution, the driving circuit further includes a third resistor and a fourth resistor; wherein the third resistor is connected in series between the gate of the second MOS transistor and the second driving signal generating module, and the fourth resistor is connected in series between the gate of the first MOS transistor and the first driving signal generating module.

[0015] In a second aspect, a control method for a drive circuit is provided, wherein the drive circuit is the drive circuit described in any one of the above embodiments; the method comprises:

[0016] Controlling the second driving signal generating module to generate a second driving signal;

[0017] When the second driving signal is a low level signal, the first power switch tube is controlled to be in an on state;

[0018] When the second driving signal is a low-level signal and current flows through the body diode of the second MOS transistor, the second MOS transistor is controlled to be in a first off-state;

[0019] Controlling the first driving signal generating module to generate a first driving signal;

[0020] When the first driving signal is switched from a low level signal to a high level signal, the positive peak value of the gate-source voltage of the second MOS tube is reduced by utilizing the equivalent capacitance of the first power switch tube in the on state.

[0021] In the above solution, the method further includes: when the second drive signal is a low-level signal, controlling the second MOS transistor to be in a second off-state; when the first drive signal switches from a high-level signal to a low-level signal, using the equivalent capacitance of the first power switch tube in the on-state to increase the negative peak value of the gate-source voltage of the second MOS tube.

[0022] In a second aspect, a control device for a drive circuit is provided, wherein the drive circuit is the drive circuit described in any one of the above embodiments; a control unit is configured to control the second drive signal generating module to generate a second drive signal;

[0023] The control unit is further configured to control the first power switch tube to be in an on state when the second drive signal is a low-level signal;

[0024] The control unit is further configured to control the second MOS transistor to be in a first off-state when the second drive signal is a low-level signal and current flows through the body diode of the second MOS transistor;

[0025] The control unit is further configured to control the first drive signal generating module to generate a first drive signal;

[0026] The processing unit is configured to reduce the positive peak value of the gate-source voltage of the second MOS tube by utilizing the equivalent capacitance of the first power switch tube in the on state when the first drive signal is switched from a low-level signal to a high-level signal.

[0027] According to a third aspect, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program implements the steps of the aforementioned method when executed by a processor.

[0028] The present application discloses a drive circuit and control method. The equivalent capacitance of a first power switch tube in the on state is used to reduce the positive peak value of the gate-source voltage of a second MOS tube, so that the positive peak value of the gate-source voltage of the second MOS tube does not exceed the voltage threshold when the second MOS tube is turned on. This prevents the second MOS tube from being mis-turned on when the first MOS tube is turned on, thereby achieving the purpose of alternating conduction of the first and second MOS tubes. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the bridge structure connection of existing silicon carbide MOSFETs;

[0030] FIG2( a ) is a first timing diagram of the conventional upper tube Q1 and lower tube Q2 ;

[0031] FIG2( b ) is a second timing diagram of the conventional upper tube Q1 and lower tube Q2;

[0032] Figure 3 This is a first structural diagram of the driving circuit in an embodiment of the present application;

[0033] Figure 4 This is a flow chart of a control method for a driving circuit in an embodiment of the present application;

[0034] Figure 5 This is a schematic diagram of the structure of the control device of the drive circuit in an embodiment of the present application;

[0035] Figure 6 This is a second structural diagram of the driving circuit in an embodiment of the present application;

[0036] Figure 7 1 is a timing diagram of the drive signal Vg1 between the gate and source of Q1, the drive signal Vg2 between the gate and source of Q2, the gate-source voltage Vgs_Q2 of Q2, the drain-source voltage Vds_Q2 of Q2, the gate-source voltage Vgs_P1 of P1, and the equivalent capacitance of P1 in the embodiment of the present application;

[0037] Figure 8 Schematic diagram of the relationship between the parasitic capacitance and drain-source voltage of a silicon carbide MOSFET in an embodiment of the present application;

[0038] Figure 9 This is a schematic diagram of a first equivalent circuit connected in parallel between Q2 in an embodiment of the present application;

[0039] Figure 10 This is a schematic diagram of a second equivalent circuit connected in parallel between Q2 in the embodiment of the present application;

[0040] Figure 11 Schematic diagram of the third structure of the driving circuit in the embodiment of the present application;

[0041] Figure 12 This is a fourth structural diagram of the driving circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0043] The embodiment of the present application provides a driving circuit, Figure 3 This is a first structural diagram of the driving circuit in the embodiment of the present application. Figure 3 As shown, the driving circuit includes: a first driving signal generating module M1, a first MOS transistor Q1, a second driving signal generating module M2, a second MOS transistor Q2 and a first power switch tube P1.

[0044] The two output terminals of M1 are connected to the gate and source of Q1, respectively. The two output terminals of M2 are connected to the gate and source of Q2, respectively. The source of Q1 is connected to the drain of Q2, the gate of P1 is connected to the source of Q2, and the drain of P1 is connected to the gate of Q2. M1 is used to generate a first drive signal, and M2 is used to generate a second drive signal. Cgd1 is the parasitic capacitance between the gate and drain of Q1, Cgs1 is the parasitic capacitance between the gate and source of Q1, Cds1 is the parasitic capacitance between the drain and source of Q1, Cgd2 is the parasitic capacitance between the gate and drain of Q2, Cgs2 is the parasitic capacitance between the gate and source of Q2, and Cds2 is the parasitic capacitance between the drain and source of Q2.

[0045] When the second MOS transistor Q2 is in the first off-state, if the first MOS transistor Q1 changes from the second off-state to the on-state, the equivalent capacitance of the first power switch P1 in the on-state is used to reduce the positive peak value of the gate-source voltage of the second MOS transistor Q2. When the second drive signal is a low-level signal and current flows through the body diode of the second MOS transistor Q2, the second MOS transistor Q2 is in the first off-state; when the first drive signal is a low-level signal, the first MOS transistor Q1 is in the second off-state; and when the first drive signal is a high-level signal, the first MOS transistor Q1 is in the on-state.

[0046] Here, when M2 provides a low-level signal between the gate and source of Q2 (i.e., no current flows between the drain and source), and current flows through the body diode of Q2, it indicates that Q2 is in the first off-state, at which time the drain-source voltage of Q2 is 0. When M1 provides a low-level signal between the gate and source of Q1, and no current flows through the body diode of Q2, it indicates that Q1 is in the second off-state. If Q1 switches from the second off-state to the on-state, the current commutates from the body diode of Q2 to the drain and source of Q1. The fast switching speed of the upper and lower tubes causes the drain-source voltage of Q1 to drop rapidly from the power supply voltage Vdc to 0, and the drain-source voltage of Q2 to rise rapidly from 0 to Vdc. The rapid rise of the drain-source voltage of Q2 causes a large crosstalk current to be generated between the drain and gate of Q2. This crosstalk current will flow through the parasitic capacitance Cgs2 between the gate and source of Q2 to charge the parasitic capacitance, thereby raising the gate-source voltage Vgs2 of Q2. Since P1 is connected in parallel between the gate and source of Q2, when Q2 is in the first off state, P1 is in the on state. At this time, the equivalent capacitance of P1 is connected in parallel between the gate and source of Q2. Combined with I = Cdv / dt, it can be seen that when the crosstalk current I remains unchanged, the increase in the capacitance between the gate and source of Q2 reduces the voltage change rate dv / dt of Q2's Vgs2. In this way, the positive peak value of Q2's Vgs2 (Figure 2(a)) will not exceed the voltage threshold Vth corresponding to when Q2 is turned on, avoiding mis-turning on Q2 and achieving the purpose of alternating conduction of Q1 and Q2. Among them, the equivalent capacitance refers to the capacitance presented by P1 in the on state.

[0047] FIG2( b ) is a second timing diagram of the conventional upper tube Q1 and lower tube Q2. As shown in FIG2( b ), when the gate-source voltage Vgs2 of Q2 is 0 (i.e., M2 provides a low-level signal to Q2, and no current flows between the source and drain), and no current flows through the body diode of Q2, Q2 is in the second off-state. At this time, the drain-source voltage Vds2 of Q2 is Vdc. If the gate-source voltage Vgs1 of Q1 switches from 1 (i.e., M1 provides a high-level signal to Q1) to 0 (i.e., M1 provides a low-level signal to Q1, and no current flows between the source and drain), Q1 switches from the on-state to the second off-state, and the current commutates from the body diode of Q2 to the drain and source of Q1. Due to the fast switching speed of the upper and lower tubes, the Vds1 of Q1 quickly rises from 0 to Vdc, and the Vds2 of Q2 quickly drops from Vdc to 0. The rapid drop in Q2's Vds2 generates a large crosstalk current between Q2's drain and gate. This crosstalk current flows through the parasitic capacitance Cgs2 between the gate and source to discharge Cgs2, causing Q2's Vgs2 voltage to drop rapidly. This results in a large rate of change (dv / dt) of change in Vgs2 voltage. If the drop in Vgs2 voltage is too large, Vgs2 may fall below Q2's minimum allowable voltage, causing damage to Q2.

[0048] To ensure that Q2 is not damaged, in some embodiments of the present application, when the second MOS transistor Q2 is in the second off-state, if the first MOS transistor Q1 switches from the on-state to the second off-state, the equivalent capacitance of the first power switch P1 in the on-state is used to increase the negative peak value of the gate-source voltage of the second MOS transistor Q2. When the second drive signal is a low-level signal, the second MOS transistor Q2 is in the second off-state.

[0049] The present application increases the capacitance between the gate and source of Q2 by connecting P1 in parallel between the gate and source of Q2. Combined with I=Cdv / dt, it can be seen that when the crosstalk current I remains unchanged, the increase in the capacitance between the gate and source of Q2 reduces the voltage change rate dv / dt of the gate-source voltage Vgs2 of Q2. In this way, the negative peak value of the gate-source voltage Vgs2 of Q2 (Figure 2(b)) will not be lower than the minimum voltage allowed by Q2, thereby achieving the purpose of protecting Q2.

[0050] Based on the above embodiments, the present invention provides a control method for a driving circuit. Figure 4 FIG. 1 is a flow chart of a control method for a driving circuit according to an embodiment of the present application. Figure 4 As shown, the method may specifically include:

[0051] Step 401: Control the second driving signal generating module to generate a second driving signal.

[0052] Step 402: When the second driving signal is a low level signal, the first power switch is controlled to be in an on state.

[0053] The first power switch tube is driven by the second driving signal of the second MOS tube, so that the first power switch tube does not need to be driven by an additional driving signal, and the implementation method is simple.

[0054] Step 403: When the second driving signal is a low-level signal and current flows through the body diode of the second MOS transistor, the second MOS transistor is controlled to be in a first off-state.

[0055] Step 404: Control the first driving signal generating module to generate a first driving signal.

[0056] Step 405: When the first driving signal switches from a low level signal to a high level signal, the positive peak value of the gate-source voltage of the second MOS tube is reduced by utilizing the equivalent capacitance of the first power switch tube in the on state.

[0057] In some embodiments, the method further includes: when the second drive signal is a low-level signal, controlling the second MOS tube to be in a second off-state; when the first drive signal switches from a high-level signal to a low-level signal, using the equivalent capacitance of the first power switch tube in the on-state to increase the negative peak value of the gate-source voltage of the second MOS tube.

[0058] Using the above technical solution, when a low-level signal is input between the gate and source of the second MOS transistor and current flows through the body diode of the second MOS transistor, the second MOS transistor is in a first off-state. If the drive signal input between the gate and source of the first MOS transistor switches from a low-level signal to a high-level signal at this time, the present application uses the equivalent capacitance of the first switching transistor to reduce the positive peak value of the gate-source voltage of the second MOS transistor, so that the positive peak value of the gate-source voltage of the second MOS transistor does not exceed the voltage threshold when the second MOS transistor is turned on, thereby preventing the second MOS transistor from being mis-turned on when the first MOS transistor is turned on, thereby achieving the purpose of alternating conduction of the first MOS transistor and the second MOS transistor. In addition, when a low-level signal is input between the gate and source of the second MOS transistor and no current flows through the body diode of the second MOS transistor, the second MOS transistor is in a second off-state. If the drive signal input between the gate and source of the first MOS transistor switches from a high-level signal to a low-level signal at this time, the present application uses the equivalent capacitance of the first switching transistor to increase the negative peak value of the gate-source voltage of the second MOS transistor, so that the negative peak value of the gate-source voltage of the second MOS transistor does not fall below the minimum voltage allowed by the second MOS transistor, thereby achieving the purpose of protecting the second MOS transistor.

[0059] In order to implement the method of the embodiment of the present application, based on the same inventive concept, the embodiment of the present application further provides a control device for a drive circuit. Figure 5 FIG. 1 is a schematic diagram showing the structure of the control device of the driving circuit in the embodiment of the present application. Figure 5 As shown, the device 50 includes:

[0060] A control unit 501 is configured to control the second driving signal generating module to generate a second driving signal;

[0061] The control unit 501 is further configured to control the first power switch to be in an on state when the second driving signal is a low level signal;

[0062] The control unit 501 is further configured to control the second MOS transistor to be in a first off state when the second driving signal is a low-level signal and current flows through the body diode of the second MOS transistor;

[0063] The control unit 501 is further configured to control the first drive signal generating module to generate a first drive signal;

[0064] The processing unit 502 is configured to reduce the positive peak value of the gate-source voltage of the second MOS tube by using the equivalent capacitance of the first power switch tube in the on state when the first driving signal switches from a low-level signal to a high-level signal.

[0065] By adopting the above technical solution, the positive peak value of the gate-source voltage of the second MOS tube is reduced by means of the equivalent capacitance of the first power switch tube in the on state, so that the positive peak value of the gate-source voltage of the second MOS tube does not exceed the voltage threshold when the second MOS tube is turned on, thereby avoiding the second MOS tube from being mis-turned on when the first MOS tube is turned on, and achieving the purpose of alternating conduction of the first MOS tube and the second MOS tube.

[0066] In some embodiments, the control unit 501 is further used to control the second MOS tube to be in a second off-state when the second drive signal is a low-level signal; the processing unit 502 is further used to increase the negative peak value of the gate-source voltage of the second MOS tube by using the equivalent capacitance of the first power switch tube in the on-state when the first drive signal is switched from a high-level signal to a low-level signal.

[0067] In some embodiments, the driving circuit further includes a second power switch tube; wherein the gate of the second power switch tube is connected to the source of the first MOS tube, and the drain of the second power switch tube is connected to the source of the first MOS tube.

[0068] In some embodiments, the circuit further includes a first capacitor and a second capacitor; the source of the first power switch tube is suspended, or the first capacitor is connected in parallel between the source and gate of the first power switch tube; the source of the second power switch tube is suspended, or the second capacitor is connected in parallel between the source and gate of the second power switch tube.

[0069] In some embodiments, the driving circuit further includes a first resistor and a second resistor; wherein the first resistor is connected in parallel across the first capacitor, and the second resistor is connected in parallel across the second capacitor.

[0070] In some embodiments, the driving circuit further includes a third resistor and a fourth resistor; wherein the third resistor is connected in series between the gate of the second MOS tube and the second driving signal generating module, and the fourth resistor is connected in series between the gate of the first MOS tube and the first driving signal generating module.

[0071] exist Figure 3 It should be noted that the above embodiment describes Q2 as an example. By connecting P1 in parallel between the gate and source of Q2, the voltage change rate dv / dt of Vgs2 is reduced, thereby solving the problem of Q2 being mis-turned on when Q1 switches from the second off-state to the on-state when Q2 is in the first off-state, and solving the problem of Q2 being damaged when Q1 switches from the on-state to the second off-state when Q2 is in the second off-state. Correspondingly, if Q1 is used as an example, when Q1 is in the first off-state, Q2 switching from the second off-state to the on-state may cause Q1 to be mis-turned on, and when Q1 is in the second off-state, Q2 switching from the on-state to the second off-state may cause Q1 to be damaged. To avoid this situation, the circuit of the embodiment of the present application further includes a second switch transistor P2; wherein the second switch transistor P2 is connected in parallel between the gate and source of the first MOS transistor Q1. Regarding how the increase of P2 avoids the misconduction and damage of Q1, please refer to the working principle of avoiding the misconduction and damage of Q2 when P1 is increased, which will not be elaborated here.

[0072] In some embodiments, the circuit further includes a third resistor R3 and a fourth resistor R4; wherein the third resistor R3 is connected in series between the gate of the second MOS transistor Q2 and the second drive signal generating module M2, and the fourth resistor R4 is connected in series between the gate of the first MOS transistor Q1 and the first drive signal generating module M1.

[0073] Here, R3 can be called the gate resistor of Q2, and its function is to limit current and suppress parasitic oscillation. R4 can be called the gate resistor of Q1, and its function is to limit current and suppress parasitic oscillation.

[0074] Based on the above, when P1 and P2 are MOS tubes, the present application provides a specific silicon carbide MOSFET bridge drive circuit. Figure 6 This is the third structural diagram of the driving circuit in the embodiment of the present application. Figure 6 P1 and P2 are specifically NMOS tubes, and can also be P1MOS tubes or IGBT tubes.

[0075] like Figure 6 As shown, the drain of P1 is connected to the gate of Q2, the gate of P1 is connected to the source of Q2, and the source of P1 is floating; Cgd3 is the parasitic capacitance between the gate and drain of P1, Cgs3 is the parasitic capacitance between the gate and source of P1, and Cds3 is the parasitic capacitance between the drain and source of P1.

[0076] The drain of P2 is connected to the gate of Q1, the gate of P2 is connected to the source of Q1, and the source of P2 is floating; Cgd4 is the parasitic capacitance between the gate and drain of P2, Cgs4 is the parasitic capacitance between the gate and source of P2, and Cds4 is the parasitic capacitance between the drain and source of P2.

[0077] Figure 7 The timing diagram of the drive signal Vg1 between the gate and source of Q1, the drive signal Vg2 between the gate and source of Q2, the gate-source voltage Vgs_Q2 of Q2, the drain-source voltage Vds_Q2 of Q2, the gate-source voltage Vgs_P1 of P1 and the equivalent capacitance of P1 in the embodiment of the present application is shown in FIG. Figure 7 The timing diagram shown is for Figure 6 The working principles of Q1, Q2 and P1 in the driving circuit are explained in detail.

[0078] Before explaining the working principle, the relationship between the parasitic capacitance value and the drain-source voltage of the silicon carbide MOSFET is explained. Figure 8 Figure 2 shows the relationship between the parasitic capacitance and drain-source voltage of a silicon carbide MOSFET in an embodiment of the present application. Crss = Cgd, Ciss = Cgs + Cgd, and Coss = Cds + Cgd. Therefore, Cgs = Ciss - Crss, and Cds = Coss - Crss. The characteristics of silicon carbide MOSFETs show that parasitic capacitance decreases as drain-source voltage Vds increases: Ciss >> Coss > Crss, meaning Cgs >> Cds and Cgs >> Cgd.

[0079] right Figure 6 The working principles of Q1, Q2 and P1 in the silicon carbide MOSFET bridge drive circuit are analyzed as follows:

[0080] Before time t0, Vg2 is a high-level signal, Vgs_Q2 is positive, Q2 is in the on state, and current flows between the drain and source of Q2, then Vds_Q2 is equal to 0.

[0081] Since the gate of P1 is connected to the source of Q2, when Q2 is turned on, the voltage between the gate and source of P1 is negative, then the drain and source of P1 are disconnected, and P1 is in the second off state. At this time, the equivalent circuit connected in parallel with Q2 is as follows: Figure 9As shown in Figure 1, the drain-source parasitic capacitance Cds3 of P1 is connected in series with the gate-source parasitic capacitance Cgs3, and then connected in parallel with the gate-drain parasitic capacitance Cgd3. According to the above-mentioned Cgs>>Cds, the equivalent capacitance of P1 is approximately Coss. Since the drain-source voltage of P1 is approximately equal to the gate-source voltage of Q2, and the gate-source voltage of Q2 is usually 10V to 15V when it is turned on, Figure 8 It can be seen that the equivalent capacitance Coss of P1 is at a relatively low level, so the impact of Coss on the turn-off speed of Q2 is relatively small.

[0082] At time t0, Vg2 switches from a high-level signal to a low-level signal, Vgs_Q2 gradually decreases, and the current between the drain and source of Q2 switches to the body diode of Q2. At this time, Vds_Q2 is still equal to 0.

[0083] At t0~t2, Vgs_Q2 drops to a negative voltage, that is, M2 provides a negative voltage between the gate and source of Q2. M2, R1, P1 body diode and Cgs3 form a loop. This negative voltage charges Cgs3 through P1's body diode and R2, raising P1's gate-source voltage Vgs_P1. When Vgs_P1 exceeds P1's threshold voltage, P1 turns on. After P1 turns on, the equivalent circuit connected in parallel with P1 is as follows Figure 10 As shown, the gate-source parasitic capacitance Cgs3 of P1 is connected in parallel with the gate-drain parasitic capacitance Cgd3, and the equivalent capacitance of P1 is approximately Ciss. At this time, Vds_Q2 is equal to 0, and Figure 8 It can be seen that Ciss is its maximum value. Since Q2 is turned off, Ciss will not affect the turn-off speed of Q2.

[0084] At time t2, while Q2 is in its first off-state, if Vg1 switches from a low-level signal to a high-level signal, Q1 switches from its second off-state to its on-state. The current in Q2's body diode commutates between Q1's drain and source, causing the Vds_Q2 voltage to rise rapidly. This voltage change rate, dv / dt, is large, causing crosstalk current to flow to Q2's gate, raising the Vgs_Q2 voltage and potentially causing Q2 to be mis-turned on. Since Ciss is connected in parallel to Q2's gate at this point, the gate capacitance is significant. As I = Cdv / dt, while the crosstalk current I remains constant, the increase in gate capacitance reduces the gate voltage change rate. Consequently, the positive peak value of Vgs_Q2 does not exceed the voltage threshold Vth corresponding to Q2's on-state. At this point, Q2 is in its second off-state, achieving the goal of alternating conduction between Q1 and Q2.

[0085] At time t3, while Q2 is in its second off-state, if Vg1 switches from a high-level signal to a low-level signal, Q1 switches from the on-state to the second off-state. The drain-source current of Q1 commutates to the body diode of Q2, causing the Vds_Q2 voltage to drop rapidly. This voltage change rate, dv / dt, is large, causing crosstalk current to flow to the Q2 gate, causing the Vgs_Q2 voltage to drop, potentially damaging Q2. Since Ciss is connected in parallel to the Q2 gate at this time, the gate capacitance is large. As I = Cdv / dt, we can see that while the crosstalk current I remains unchanged, the increase in gate capacitance reduces the gate voltage change rate. This ensures that the negative peak value of Vgs_Q2 will not fall below the minimum voltage allowed for Q2, thus protecting Q2.

[0086] At t4, Vg2 switches from a low-level signal to a high-level signal, Q2 switches from the second off-state to the on-state, the Q2 body diode current commutates to between the source and drain of Q2, Vds_Q2 equals 0, the Vgs_Q2 voltage rises, the Vgs_P1 voltage drops to a negative value, P1 is turned off, and the Figure 7 It can be seen that before Q2 is actually turned on, the equivalent capacitance of P1 drops from Ciss to Coss, which means that it has little effect on the turn-on speed of Q2.

[0087] Based on the above embodiments, the present application also provides a driving circuit. Figure 11 This is a third structural diagram of the driving circuit in the embodiment of the present application, as shown in FIG. Figure 11 As shown, the circuit further includes a first capacitor C1 and a second capacitor C2; the first capacitor C1 is connected in parallel between the source and gate of the third MOS transistor P1; and the second capacitor C2 is connected in parallel between the source and gate of the fourth MOS transistor P2.

[0088] Here, C1 is connected in parallel between the source and gate of P1, making the equivalent capacitance of P1 lower than Coss in the off state, further reducing the impact on the turn-off speed of Q2. C1 and C2 have the same function.

[0089] Based on the above embodiments, the present application also provides a driving circuit. Figure 12 This is a fourth structural diagram of the driving circuit in the embodiment of the present application, as shown in FIG. Figure 12 As shown, the circuit further includes a first resistor R1 and a second resistor R2; the first resistor R1 is connected in parallel between the source and gate of the first power switch tube P1, and the second resistor R2 is connected in parallel between the source and gate of the second power switch tube P2.

[0090] Here, the presence of R1 provides an additional discharge path for C1, thus helping C1 discharge more quickly. This ensures that when Q2 turns on, P1 can turn off more quickly, effectively reducing the impact of P1's parasitic capacitance on Q2's turn-on speed. R1 and R2 have the same function.

[0091] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A driving circuit, characterized in that: The driving circuit includes: a first driving signal generating module, a first MOS transistor, a second driving signal generating module, a second MOS transistor and a first power switch tube; The two output ends of the first drive signal generating module are respectively connected to the gate and source of the first MOS transistor, and the two output ends of the second drive signal generating module are respectively connected to the gate and source of the second MOS transistor. The source of the first MOS transistor is connected to the drain of the second MOS transistor, the gate of the first power switch tube is connected to the source of the second MOS transistor, and the drain of the first power switch tube is connected to the gate of the second MOS transistor. The first drive signal generating module is used to generate a first drive signal, and the second drive signal generating module is used to generate a second drive signal. When the second MOS transistor is in the first off-state, if the first MOS transistor is switched from the second off-state to the on-state, the positive peak value of the gate-source voltage of the second MOS transistor is reduced by using the equivalent capacitance of the first power switch in the on-state; Among them, when the second drive signal is a low-level signal and current flows through the body diode of the second MOS transistor, the second MOS transistor is in a first off-state; when the first drive signal is a low-level signal, the first MOS transistor is in a second off-state; when the first drive signal is a high-level signal, the first MOS transistor is in a conducting state.

2. The circuit according to claim 1, characterized in that When the second MOS transistor is in the second off-state, if the first MOS transistor is switched from the on-state to the second off-state, the negative peak value of the gate-source voltage of the second MOS transistor is increased by using the equivalent capacitance of the first power switch transistor in the on-state; When the second driving signal is a low-level signal, the second MOS transistor is in a second off-state.

3. The circuit according to claim 1, wherein: The driving circuit further includes a second power switch tube; wherein the gate of the second power switch tube is connected to the source of the first MOS tube, and the drain of the second power switch tube is connected to the gate of the first MOS tube.

4. The circuit according to claim 3, characterized in that The driving circuit further includes a first capacitor and a second capacitor; The source of the first power switch tube is suspended, or the first capacitor is connected in parallel between the source and the gate of the first power switch tube; The source of the second power switch tube is suspended, or the second capacitor is connected in parallel between the source and the gate of the second power switch tube.

5. The circuit according to claim 4, characterized in that The driving circuit further includes a first resistor and a second resistor; wherein the first resistor is connected in parallel between the source and the gate of the first power switch tube, and the second resistor is connected in parallel between the source and the gate of the second power switch tube.

6. The circuit according to claim 1, wherein: The driving circuit also includes a third resistor and a fourth resistor; wherein the third resistor is connected in series between the gate of the second MOS transistor and the second driving signal generating module, and the fourth resistor is connected in series between the gate of the first MOS transistor and the first driving signal generating module.

7. A control method for a driving circuit, characterized in that: The driving circuit is the driving circuit according to any one of claims 1 to 6; and the method comprises: Controlling the second driving signal generating module to generate a second driving signal; When the second driving signal is a low level signal, the first power switch tube is controlled to be in an on state; When the second driving signal is a low-level signal and current flows through the body diode of the second MOS transistor, the second MOS transistor is controlled to be in a first off-state; Controlling the first driving signal generating module to generate a first driving signal; When the first driving signal is switched from a low level signal to a high level signal, the positive peak value of the gate-source voltage of the second MOS tube is reduced by utilizing the equivalent capacitance of the first power switch tube in the on state.

8. The method according to claim 7, characterized in that The method further comprises: When the second driving signal is a low level signal, the second MOS transistor is controlled to be in a second off state; When the first driving signal is switched from a high level signal to a low level signal, the negative peak value of the gate-source voltage of the second MOS tube is increased by utilizing the equivalent capacitance of the first power switch tube in the on state.

9. A control device for a drive circuit, characterized in that: The driving circuit is the driving circuit according to any one of claims 1 to 6; the device comprises: a control unit, configured to control the second drive signal generating module to generate a second drive signal; The control unit is further configured to control the first power switch tube to be in an on state when the second drive signal is a low-level signal; The control unit is further configured to control the second MOS transistor to be in a first off-state when the second drive signal is a low-level signal and current flows through the body diode of the second MOS transistor; The control unit is further configured to control the first drive signal generating module to generate a first drive signal; The processing unit is configured to reduce the positive peak value of the gate-source voltage of the second MOS tube by utilizing the equivalent capacitance of the first power switch tube in the on state when the first drive signal is switched from a low-level signal to a high-level signal.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 7 to 8 are implemented.

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