Amplification circuit, detection chip and wearable device

Abstract

The application is suitable for the technical field of electronic circuits, and provides an amplification circuit, a detection chip and a wearable device. A first logic module in the amplification circuit is configured to receive a reference voltage and a first signal in a target differential signal, and transmit the first signal to a current generation module. A second logic module is configured to receive the reference voltage and a second signal in the target differential signal, and transmit the second signal to the current generation module. When the first signal and the second signal have a direct current deviation, the current generation module is configured to generate a deviation current according to the direct current deviation, and the deviation current causes the first logic module to generate a first direct current voltage and causes the second logic module to generate a second direct current voltage. A voltage regulation module is configured to collect the first direct current voltage and the second direct current voltage, and regulate the first direct current voltage and the second direct current voltage, so that the first direct current voltage and the second direct current voltage are equal to the reference voltage. The amplification circuit provided by the application can suppress the direct current deviation in the target differential signal.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to an amplifier circuit, a detection chip, and a wearable device. Background Technology

[0002] With increasing public awareness of their health, wearable devices such as smart bracelets have become widely used. Electrocardiogram (ECG) signals are an important reference for human health, and ECG signal detection is a crucial function of wearable devices. Currently, the basic working principle of ECG signal detection involves acquiring differential signals through differential electrodes and transmitting these signals to an ECG signal detection chip. The chip then amplifies, filters, and quantizes the electrical signals. However, the following problem exists in this process: after the differential electrodes come into contact with the human body, the differential signal is transmitted to the amplifier input in the ECG signal detection chip. Due to the DC bias in the differential signal, the amplifier output saturates, failing to amplify the useful small AC signals. Summary of the Invention

[0003] This application provides an amplifier circuit, a detection chip, and a wearable device, which can solve the problem that the output of the amplifier in the wearable device is saturated due to the DC deviation in the acquired differential signal, thus failing to amplify useful small AC signals.

[0004] In a first aspect, embodiments of this application provide an amplifier circuit, including a first logic module, a second logic module, a current generation module, and a voltage regulation module; the current generation module is electrically connected to the first logic module and the second logic module, respectively, and the voltage regulation module is electrically connected to the first logic module and the second logic module, respectively.

[0005] The first logic module is used to receive a first signal from the reference voltage and the target differential signal, and transmit the first signal to the current generation module; the second logic module is used to receive a second signal from the reference voltage and the target differential signal, and transmit the second signal to the current generation module.

[0006] When there is a DC deviation between the first signal and the second signal, the current generation module is used to generate a deviation current according to the DC deviation. The deviation current causes the first logic module to generate a first DC voltage and the second logic module to generate a second DC voltage.

[0007] The voltage regulation module is used to collect the first DC voltage and the second DC voltage, and to regulate the first DC voltage and the second DC voltage so that the first DC voltage and the second DC voltage are equal to the reference voltage.

[0008] In one possible implementation of the first aspect, the first logic module includes a first operational amplifier, a first field-effect transistor, a first current source, a second current source, and a first resistor;

[0009] The positive terminal of the first current source is electrically connected to the positive terminal of the first power supply. The non-inverting input terminal of the first operational amplifier is used to receive the first signal. The inverting input terminal of the first operational amplifier is electrically connected to the source of the first field-effect transistor, the negative terminal of the first current source, and the current generation module. The output terminal of the first operational amplifier is electrically connected to the gate of the first field-effect transistor. The drain of the first field-effect transistor is electrically connected to the first terminal of the first resistor, the positive terminal of the second current source, and the voltage adjustment module. The second terminal of the first resistor is used to receive the reference voltage. The negative terminal of the second current source is electrically connected to the negative terminal of the first power supply. The current provided by the first current source and the current provided by the second current source are equal in magnitude and in the same direction.

[0010] In one possible implementation of the first aspect, the second logic module includes a second operational amplifier, a second field-effect transistor, a third current source, a fourth current source, and a second resistor;

[0011] The positive terminal of the third current source is electrically connected to the positive terminal of the second power supply. The non-inverting input terminal of the second operational amplifier is used to receive the second signal. The inverting input terminal of the second operational amplifier is electrically connected to the source of the second field-effect transistor, the negative terminal of the third current source, and the current generation module, respectively. The output terminal of the second operational amplifier is electrically connected to the gate of the second field-effect transistor. The drain of the second field-effect transistor is electrically connected to the first terminal of the second resistor, the positive terminal of the fourth current source, and the voltage adjustment module, respectively. The second terminal of the second resistor is used to receive the reference voltage. The negative terminal of the fourth current source is electrically connected to the negative terminal of the second power supply. The current provided by the third current source, the current provided by the fourth current source, and the current provided by the first current source are equal in magnitude and in the same direction.

[0012] In one possible implementation of the first aspect, the first field-effect transistor and the second field-effect transistor are P-type field-effect transistors, the first current source and the third current source are P-type current sources, and the second current source and the fourth current source are N-type current sources.

[0013] In one possible implementation of the first aspect, the first logic module includes a third operational amplifier, a third field-effect transistor, a fifth current source, a sixth current source, a first current mirror, and a third resistor;

[0014] The positive terminal of the fifth current source is electrically connected to the positive terminal of the first power supply. The non-inverting input terminal of the third operational amplifier is used to receive the first signal. The inverting input terminal of the third operational amplifier is electrically connected to the source of the third field-effect transistor, the negative terminal of the fifth current source, and the current generation module. The output terminal of the third operational amplifier is electrically connected to the gate of the third field-effect transistor. The drain of the third field-effect transistor is electrically connected to the input terminal of the first current mirror. The output terminal of the first current mirror is electrically connected to the first terminal of the third resistor, the negative terminal of the sixth current source, and the voltage adjustment module. The common terminal of the first current mirror is electrically connected to the negative terminal of the first power supply. The second terminal of the third resistor is used to receive the reference voltage. The positive terminal of the sixth current source is electrically connected to the positive terminal of the first power supply. The current provided by the fifth current source and the current provided by the sixth current source are equal in magnitude and in the same direction.

[0015] In one possible implementation of the first aspect, the second logic module includes a fourth operational amplifier, a fourth field-effect transistor, a seventh current source, an eighth current source, a second current mirror, and a fourth resistor;

[0016] The positive terminal of the seventh current source is electrically connected to the positive terminal of the second power supply. The non-inverting input terminal of the fourth operational amplifier is used to receive the second signal. The inverting input terminal of the fourth operational amplifier is electrically connected to the source of the fourth field-effect transistor, the negative terminal of the seventh current source, and the current generation module, respectively. The output terminal of the fourth operational amplifier is electrically connected to the gate of the fourth field-effect transistor. The drain of the fourth field-effect transistor is electrically connected to the input terminal of the second current mirror. The output terminal of the second current mirror is electrically connected to the first terminal of the fourth resistor, the negative terminal of the eighth current source, and the voltage adjustment module, respectively. The common output terminal of the second current mirror is electrically connected to the negative terminal of the second power supply. The second terminal of the fourth resistor is used to receive the reference voltage. The positive terminal of the eighth current source is electrically connected to the positive terminal of the second power supply. The currents provided by the seventh current source, the eighth current source, and the fifth current source are equal in magnitude and in the same direction.

[0017] In one possible implementation of the first aspect, the current generation module includes a fifth resistor; a first end of the fifth resistor is electrically connected to the first logic module, and a second end of the fifth resistor is electrically connected to the second logic module.

[0018] In one possible implementation of the first aspect, the voltage regulation module includes a first transconductance unit, a second transconductance unit, and a first capacitor;

[0019] The positive input terminal of the first transconductance unit is electrically connected to the positive output terminal of the second logic module and the second transconductance unit, respectively. The negative input terminal of the first transconductance unit is electrically connected to the negative output terminal of the first logic module and the second transconductance unit, respectively. The positive output terminal of the first transconductance unit is electrically connected to the positive terminal of the first capacitor and the negative input terminal of the second transconductance unit, respectively. The negative output terminal of the first transconductance unit is electrically connected to the negative terminal of the first capacitor and the positive input terminal of the second transconductance unit, respectively.

[0020] Secondly, embodiments of this application provide a detection chip, including the amplification circuit described in any one of the first aspects.

[0021] Thirdly, embodiments of this application provide a wearable device including the detection chip described in the second aspect.

[0022] The beneficial effects of the embodiments in this application compared with the prior art are:

[0023] This application provides an amplifier circuit including a first logic module, a second logic module, a current generation module, and a voltage regulation module. The current generation module is electrically connected to both the first and second logic modules, and the voltage regulation module is also electrically connected to both the first and second logic modules. The first logic module receives a first signal from a reference voltage and a target differential signal, and transmits the first signal to the current generation module. The second logic module receives a second signal from the reference voltage and the target differential signal, and transmits the second signal to the current generation module. When a DC deviation exists between the first and second signals in the acquired target differential signal, the current generation module generates a deviation current based on the DC deviation. This deviation current causes the first logic module to generate a first DC voltage, and the second logic module to generate a second DC voltage. Due to the existence of the DC deviation, a discrepancy exists between the first and second DC voltages. As long as this discrepancy exists, the voltage regulation module continuously adjusts the first and second DC voltages until they are equal to the reference voltage, thus eliminating the discrepancy between them. This suppresses the DC deviation between the first and second signals in the target differential signal, preventing the amplifier circuit output from saturating and allowing amplification of useful small AC signals. When the first and second DC voltages are equal to the reference voltage, the current generation module generates a differential current based on the first and second signals. This differential current causes the first logic module to generate the first voltage in the differential voltage, and the second logic module to generate the second voltage in the differential voltage, thus amplifying the small AC signals in the target differential signal.

[0024] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic block diagram of an amplifier circuit provided in one embodiment of this application;

[0027] Figure 2 This is a circuit connection diagram of an amplifier circuit provided in an embodiment of this application;

[0028] Figure 3 This is a circuit connection diagram of an amplifier circuit provided in another embodiment of this application;

[0029] Figure 4 This is a system equivalent diagram of an amplifier circuit provided in an embodiment of this application;

[0030] Figure 5 This is a schematic diagram of the differential mode response of an amplifier circuit provided in an embodiment of this application;

[0031] Figure 6 This is a schematic diagram of the common-mode rejection characteristics of an amplifier circuit provided in an embodiment of this application.

[0032] In the diagram: 100, First logic module; 200, Current generation module; 300, Second logic module; 400, Voltage regulation module. Detailed Implementation

[0033] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0034] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0035] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0036] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0037] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0038] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0039] Wearable devices such as smart bracelets are widely used. The electrocardiogram (ECG) signal detection chips used in these devices must amplify the small AC signals in the acquired differential signals without amplifier saturation. Existing amplifiers use a fully differential structure composed of dual operational amplifiers. However, this structure does not suppress DC deviations present in the differential signals. When the DC deviation is small, the amplifier will not saturate. When the DC deviation is large, it will cause the amplifier output to saturate, failing to amplify the small AC signals in the differential signals.

[0040] To solve the above problems, such as Figure 1As shown, this application embodiment provides an amplifier circuit, including a first logic module 100, a second logic module 300, a current generation module 200, and a voltage regulation module 400. The current generation module 200 is electrically connected to both the first logic module 100 and the second logic module 300. The voltage regulation module 400 is electrically connected to both the first logic module 100 and the second logic module 300.

[0041] Specifically, the first logic module 100 receives a first signal from the reference voltage and the target differential signal, and transmits the first signal to the current generation module 200. The second logic module 300 receives a second signal from the reference voltage and the target differential signal, and transmits the second signal to the current generation module 200.

[0042] When a DC deviation exists between the first signal and the second signal, the current generation module 200 generates a deviation current based on this deviation. This deviation current causes the first logic module 100 to generate a first DC voltage and the second logic module 300 to generate a second DC voltage. Due to the DC deviation, a deviation also exists between the first and second DC voltages. To eliminate this deviation, the voltage regulation module 400 acquires and adjusts the first and second DC voltages to ensure they are equal to the reference voltage. This eliminates the deviation between the first and second DC voltages, thus suppressing the DC deviation between the first and second signals in the target differential signal. This prevents the amplifier circuit output from saturating and allows for the amplification of useful small AC signals.

[0043] When the first DC voltage and the second DC voltage are equal to the reference voltage, the current generation module 200 generates a differential current based on the first signal and the second signal. This differential current causes the first logic module 100 to generate the first voltage in the differential voltage and the second logic module 300 to generate the second voltage in the differential voltage, thus amplifying the small AC signal in the target differential signal.

[0044] It should be noted that the DC deviation is the DC voltage difference between the first signal and the second signal.

[0045] like Figure 2 As shown, the first logic module 100 includes a first operational amplifier AMP1, a first field-effect transistor M1, a first current source I1, a second current source I2, and a first resistor R1. The positive terminal of the first current source I1 is electrically connected to the positive terminal of the first power supply, i.e., electrically connected to the voltage VDD1. The non-inverting input terminal of the first operational amplifier AMP1 is used to receive the first signal V. IPThe inverting input of the first operational amplifier AMP1 is electrically connected to the source of the first field-effect transistor M1, the negative terminal of the first current source I1, and the current generation module 200, respectively. The output of the first operational amplifier AMP1 is electrically connected to the gate of the first field-effect transistor M1. The drain of the first field-effect transistor M1 is electrically connected to the first terminal of the first resistor R1, the positive terminal of the second current source I2, and the voltage adjustment module 400, respectively. The second terminal of the first resistor R1 is used to receive the reference voltage V. REF The negative terminal of the second current source I2 is used to connect electrically to the negative terminal of the first power supply, that is, to voltage VSS1. The current provided by the first current source I1 is equal in magnitude and in the same direction as the current provided by the second current source I2.

[0046] Specifically, the non-inverting input of the first operational amplifier AMP1 receives the first signal V. IP Due to the action of the operational amplifier, the source of the first field-effect transistor M1 is locked, causing the source of the first field-effect transistor M1 to track the first signal V. IP This causes one end of the current generation module 200 to receive the first signal V. IP .

[0047] When the first logic module 100 is analyzed independently, the second terminal of the first resistor R1 receives the reference voltage V. REF The non-inverting input of the first operational amplifier AMP1 receives the first signal V. IP For the first field-effect transistor M1 to function properly, its source voltage must be greater than its drain voltage. Therefore, it only functions correctly when the first signal V... IP Greater than the reference voltage V REF Only when the first field-effect transistor M1 is working properly will the first field-effect transistor M1 operate normally. When the first field-effect transistor M1 is working normally, the current provided by the first current source I1 flows out through the first field-effect transistor M1. Since the current provided by the first current source I1 is equal in magnitude and in the same direction as the current provided by the second current source I2, no current is generated in the first resistor R1, and the voltage output at the first terminal of the first resistor R1 is the reference voltage V. REF .

[0048] like Figure 2 As shown, the second logic module 300 includes a second operational amplifier AMP2, a second field-effect transistor M2, a third current source I3, a fourth current source I4, and a second resistor R2. The positive terminal of the third current source I3 is electrically connected to the positive terminal of the second power supply, i.e., electrically connected to the voltage VDD2. The non-inverting input terminal of the second operational amplifier AMP2 is used to receive the second signal V. INThe inverting input of the second operational amplifier AMP2 is electrically connected to the source of the second field-effect transistor M2, the negative terminal of the third current source I3, and the current generation module 200, respectively. The output of the second operational amplifier AMP2 is electrically connected to the gate of the second field-effect transistor M2. The drain of the second field-effect transistor M2 is electrically connected to the first terminal of the second resistor R2, the positive terminal of the fourth current source I4, and the voltage adjustment module 400, respectively. The second terminal of the second resistor R2 is used to receive the reference voltage V. REF The negative terminal of the fourth current source I4 is used to connect electrically to the negative terminal of the second power supply, that is, to voltage VSS2. The current provided by the third current source I3 and the fourth current source I4 is equal in magnitude and in the same direction as the current provided by the first current source I1.

[0049] Specifically, the non-inverting input of the second operational amplifier AMP2 receives the second signal V. IN Due to the action of the operational amplifier, the source of the second field-effect transistor M2 is locked, causing the source of the second field-effect transistor M2 to track the second signal V. IN This causes the other end of the current generation module 200 to receive the second signal V. IN .

[0050] When the second logic module 300 is analyzed independently, the second terminal of the second resistor R2 receives the reference voltage V. REF The non-inverting input of the second operational amplifier AMP2 receives the second signal V. IN For the second field-effect transistor M2 to function properly, its source voltage must be greater than its drain voltage. Therefore, it only functions when the second signal V... IN Greater than the reference voltage V REF Only when the second field-effect transistor M2 is working properly will the second field-effect transistor M2 operate normally. When the second field-effect transistor M2 is working normally, the current provided by the third current source I3 flows out through the second field-effect transistor M2. Since the current provided by the third current source I3, the current provided by the fourth current source I4, and the current provided by the first current source I1 are equal in magnitude and in the same direction, no current is generated in the second resistor R2, and the voltage output at the first terminal of the second resistor R2 is the reference voltage V. REF .

[0051] For example, the first field-effect transistor M1 and the second field-effect transistor M2 are P-type field-effect transistors. The first current source I1 and the third current source I3 are P-type current sources, and the second current source I2 and the fourth current source I4 are N-type current sources.

[0052] It should be noted that in the embodiments of this application, the first resistor R1 and the second resistor R2 are equal. The first power supply and the second power supply in the embodiments of this application can be the same power supply or two different power supplies.

[0053] like Figure 3As shown, the first logic module 100 includes a third operational amplifier AMP3, a third field-effect transistor M3, a fifth current source I5, a sixth current source I6, a first current mirror CM1, and a third resistor R3. The positive terminal of the fifth current source I5 is electrically connected to the positive terminal of the first power supply, i.e., electrically connected to VDD1. The non-inverting input terminal of the third operational amplifier AMP3 is used to receive the first signal V. IP The inverting input of the third operational amplifier AMP3 is electrically connected to the source of the third field-effect transistor M3, the negative terminal of the fifth current source I5, and the current generation module 200, respectively. The output of the third operational amplifier AMP3 is electrically connected to the gate of the third field-effect transistor M3. The drain of the third field-effect transistor M3 is electrically connected to the input of the first current mirror CM1. The output of the first current mirror CM1 is electrically connected to the first terminal of the third resistor R3, the negative terminal of the sixth current source I6, and the voltage adjustment module 400, respectively. The common terminal of the first current mirror CM1 is used to connect to the negative terminal of the first power supply, i.e., to the voltage VSS1. The second terminal of the third resistor R3 is used to receive the reference voltage V. REF The positive terminal of the sixth current source I6 is used to connect electrically to the positive terminal of the first power supply, that is, to voltage VDD1. The current provided by the fifth current source I5 is equal in magnitude and in the same direction as the current provided by the sixth current source I6.

[0054] Specifically, the non-inverting input of the third operational amplifier AMP3 receives the first signal V. IP Due to the action of the operational amplifier, the source of the third field-effect transistor M3 is locked, causing the source of the third field-effect transistor M3 to track the first signal V. IP This causes one end of the current generation module 200 to receive the first signal V. IP .

[0055] When the first logic module 100 is analyzed independently, the non-inverting input of the third operational amplifier AMP3 receives the first signal V. IP Due to the first signal V IP The voltage must be greater than VSS1 for the third field-effect transistor M3 to function properly. This circuit structure is unaffected by the first signal V. IP It must be greater than the reference voltage V REF The limitations are as follows: When the third field-effect transistor M3 is working normally, the current provided by the fifth current source I5 flows out through the third field-effect transistor M3, and then is replicated through the first current mirror CM1. When the ratio of the first current mirror CM1 is 1:1, the current on the right side of the first current mirror CM1 is the same as the current on the left side. Since the current provided by the fifth current source I5 is equal in magnitude and direction to the current provided by the sixth current source I6, no current flows through the third resistor R3, and the voltage output at the first terminal of the third resistor R3 is the reference voltage V. REF .

[0056] For example, the third field-effect transistor M3 is a P-type field-effect transistor.

[0057] like Figure 3 As shown, the second logic module 300 includes a fourth operational amplifier AMP4, a fourth field-effect transistor M4, a seventh current source I7, an eighth current source I8, a second current mirror CM2, and a fourth resistor R4. The positive terminal of the seventh current source I7 is electrically connected to the positive terminal of the second power supply, i.e., electrically connected to the voltage VDD2. The non-inverting input of the fourth operational amplifier AMP4 is used to receive the second signal V. IN The inverting input of the fourth operational amplifier AMP4 is electrically connected to the source of the fourth field-effect transistor M4, the negative terminal of the seventh current source I7, and the current generation module 200, respectively. The output of the fourth operational amplifier AMP4 is electrically connected to the gate of the fourth field-effect transistor M4. The drain of the fourth field-effect transistor M4 is electrically connected to the input of the second current mirror CM2. The output of the second current mirror CM2 is electrically connected to the first terminal of the fourth resistor R4, the negative terminal of the eighth current source I8, and the voltage adjustment module 400, respectively. The common output of the second current mirror CM2 is used to connect to the negative terminal of the second power supply, i.e., to the voltage VSS2. The second terminal of the fourth resistor R4 is used to receive the reference voltage V. REF The positive terminal of the eighth current source I8 is used to connect electrically to the positive terminal of the second power supply, that is, to voltage VDD2. The current provided by the seventh current source I7, the eighth current source I8, and the fifth current source I5 are equal in magnitude and in the same direction.

[0058] Specifically, the non-inverting input of the fourth operational amplifier AMP4 receives the second signal V. IN Due to the action of the operational amplifier, the source of the fourth field-effect transistor M4 is locked, causing the source of the fourth field-effect transistor M4 to track the second signal V. IN This causes the other end of the current generation module 200 to receive the second signal V. IN .

[0059] When the second logic module 300 is analyzed independently, the non-inverting input of the fourth operational amplifier AMP4 receives the second signal V. IN Due to the second signal V IN The voltage must be greater than VSS2 for the fourth field-effect transistor M4 to function properly. This circuit structure is unaffected by the second signal V. IN It must be greater than the reference voltage V REFThe limitations are as follows: When the fourth field-effect transistor M4 is working normally, the current supplied by the seventh current source I7 flows out through the fourth field-effect transistor M4, and then is replicated through the second current mirror CM2. When the ratio of the second current mirror CM2 is 1:1, the current on the left side of the second current mirror CM2 is the same as the current on the right side. Since the current supplied by the seventh current source I7, the current supplied by the eighth current source I8, and the current supplied by the fifth current source I5 are equal in magnitude and in the same direction, no current flows through the fourth resistor R4, and the voltage output at the first terminal of the fourth resistor R4 is the reference voltage V. REF .

[0060] For example, the fourth field-effect transistor M4 is a P-type field-effect transistor.

[0061] It should be noted that the third resistor R3 and the fourth resistor R4 in the embodiments of this application are equal.

[0062] like Figure 2 , 3 As shown, the current generation module 200 includes a fifth resistor R5. The first terminal of the fifth resistor R5 is electrically connected to the first logic module 100. The second terminal of the fifth resistor R5 is electrically connected to the second logic module 300.

[0063] Specifically, such as Figure 2 As shown, the first terminal of the fifth resistor R5 is electrically connected to the source of the first field-effect transistor M1 in the first logic module 100. The second terminal of the fifth resistor R5 is electrically connected to the source of the second field-effect transistor M2 in the second logic module 300.

[0064] When the first signal V IP With the second signal V IN When a DC deviation exists and is greater than 0 (i.e., the DC voltage across the first terminal of the fifth resistor R5 is greater than the DC voltage across the second terminal of the fifth resistor R5), a DC voltage drop will occur across the fifth resistor R5, resulting in a deviation current flowing from left to right. Based on the above analysis and limitations, since the current provided by the first current source I1 is equal in magnitude and direction to the current provided by the second current source I2, and the currents provided by the third current source I3 and the fourth current source I4 are equal in magnitude and direction to the current provided by the first current source I1, when a deviation current occurs across the fifth resistor R5, it will cause currents to flow from left to right across both the first resistor R1 and the second resistor R2. Therefore, a voltage drop will occur across the first resistor R1, causing the first DC voltage output by the first logic module 100 to be less than the reference voltage V. REF A voltage drop will also occur across the second resistor R2, causing the second DC voltage output by the second logic module 300 to be greater than the reference voltage V. REFThis leads to a deviation between the first DC voltage and the second DC voltage, which affects the normal operation of the amplifier circuit. As long as there is a deviation between the first DC voltage and the second DC voltage, the voltage regulation module 400 will continuously adjust the first DC voltage and the second DC voltage until they are equal to the reference voltage, thus eliminating the deviation between the first DC voltage and the second DC voltage. Therefore, it suppresses the DC deviation between the first signal and the second signal in the target differential signal, preventing the amplifier circuit output from saturating and enabling the amplification of useful small AC signals.

[0065] When the first signal V IP With the second signal V IN When there is no DC deviation, no DC voltage drop or deviation current will be generated across the fifth resistor R5. The first DC voltage and the second DC voltage will be equal to the reference voltage V. REF Keep them equal. When the first DC voltage and the second DC voltage are equal to the reference voltage V... REF When they remain equal, the first signal V IP With the second signal V IN A differential current will be generated in the fifth resistor R5. Let the differential current be (V). IP -V IN ) / R5, the direction of the differential current is from left to right. At this time Figure 2 The current source in the circuit is equivalent to an open circuit. Therefore, the currents flowing through the first resistor R1 and the second resistor R2 are both differential currents, and the current direction is from left to right. The voltage drop across the first resistor R1 is (V). IP -V IN R1 / R5 makes the first voltage V in the differential voltage equal to R1 / R5. O1 Less than the reference voltage V REF V O1 =V REF -(V IP -V IN The voltage drop across the second resistor R2 is (V) * R1 / R5. IP -V IN R2 / R5 makes the second voltage V in the differential voltage equal to R2 / R5. O2 Greater than the reference voltage V REF V O2 =V REF +(V IP -V IN Since the first resistor R1 and the second resistor R2 are equal, the output AC voltage V is calculated as R2 / R5. O =V O2 -V O1 =2(V IP -V IN)*R1 / R5, we can get the gain of the amplifier circuit as 2*R1 / R5, therefore the output of the amplifier circuit is DC biased V. REF Superimposed AC voltage V O .

[0066] like Figure 2 , 3 As shown, the voltage regulation module 400 includes a first transconductance unit G. m1 Second transconducting unit G m2 And the first capacitor C1. The first transconductance unit G m1 The positive input terminals are respectively connected to the second logic module 300 and the second transconductance unit G. m2 The positive output terminal is electrically connected. First transconductance unit G m1 The negative input terminals are respectively connected to the first logic module 100 and the second transconductance unit G. m2 The negative output terminal is electrically connected. First transconductance unit G m1 The positive output terminal is connected to the positive terminal of the first capacitor C1 and the second transconductance unit G, respectively. m2 The negative input terminal is electrically connected. The first transconductance unit G... m1 The negative output terminal is connected to the negative terminal of the first capacitor C1 and the second transconductance unit G, respectively. m2 The positive input terminal is electrically connected.

[0067] Specifically, such as Figure 2 As shown, the first transconductance unit G m1 The positive input terminal is connected to the first terminal of the second resistor R2 and the second transconductance unit G, respectively. m2 The positive output terminal is electrically connected. First transconductance unit G m1 The negative input terminal is connected to the first terminal of the first resistor R1 and the second transconductance unit G, respectively. m2 The negative output terminal is electrically connected. First transconductance unit G m1 The positive output terminal is connected to the positive terminal of the first capacitor C1 and the second transconductance unit G, respectively. m2 The negative input terminal is electrically connected. First transconductance unit G m1 The negative output terminal is connected to the negative terminal of the first capacitor C1 and the second transconductance unit G, respectively. m2 The positive input terminal is electrically connected.

[0068] As can be seen from the analysis above, when the first signal V IP With the second signal V IN When a DC deviation exists and is greater than 0, a deviation also exists between the first DC voltage and the second DC voltage, with the second DC voltage being greater than the first DC voltage. First transconductance unit G m1 The first DC voltage and the second DC voltage are collected, wherein the second DC voltage is greater than the first DC voltage, and the first transconductance unit G m1The positive output terminal outputs current, and the negative output terminal inputs current, thus creating a voltage difference across the first capacitor C1, with the left side positive and the right side negative. Then the second transconductance unit G... m2 The voltage at the positive input terminal is less than the voltage at the negative input terminal, making the second transconductance unit G... m2 The negative output terminal outputs current, and the positive output terminal inputs current. This provides a right-to-left current to the first resistor R1 and a right-to-left current to the second resistor R2, thereby adjusting the voltage drop across the first and second resistors R1 and R2. Ultimately, this brings the deviation between the first and second DC voltages close to zero, and makes them approximately equal to the reference voltage V. REF Keep them equal.

[0069] like Figure 4 As shown, except Figure 2 The circuit consists of the first resistor R1, the second resistor R2, and the voltage regulation module 400. The remaining circuit is represented by a fully differential transconductance unit with a transconductance value of G. m0 =1 / R5, then the voltage regulation module 400 is equivalent to an inductor L, L = C1 / (G m1* G m2 Therefore, the amplifier circuit can be represented as Figure 4 The simplified system diagram is shown on the right. The system transfer function can be expressed as...

[0070] As we can see, s = 0, meaning that under DC conditions, the system transfer function is equal to 0, and the amplifier circuit does not amplify the DC signal, exhibiting high-pass characteristics. At higher frequencies, the independent variable in the denominator is greater than the DC value, and the system transfer function remains constant and equal to the amplifier circuit's gain. The poles of the -3dB bandwidth of the high-pass filter characteristic correspond to s = -2R1 / L. In wearable device applications for detecting ECG signals, this bandwidth needs to be set to less than 1Hz, considering the first transconductance unit G... m1 Second transconducting unit G m2 To achieve a larger inductance, a larger capacitor is needed; for example, if R1 = 10MΩ, then L > 3.2MH is required, and the first transconductance unit G... m1 Second transconducting unit G m2 If the transconductance is 0.1 μS, then the capacitance of the first capacitor C1 is greater than 32 nF. This means that the amplifier circuit uses an external capacitor to achieve DC suppression characteristics for fully differential signals.

[0071] Due to the prevalent 50Hz power frequency interference from the power supply network in the environment, coupled with the equivalent capacitance of the power line, a strong 50Hz signal is constantly perceived by the human body. This signal is collected by the differential electrodes and transmitted to the amplifier input of the wearable device, manifesting as common-mode interference. Therefore, when a wearable device collects differential signals, in addition to suppressing the DC deviation present in the target differential signal, it should also suppress the common-mode signal. Figure 2 As shown, regardless of the first signal V IP With the second signal V IN Is there a DC deviation between them? When a common-mode signal is input, the first signal V IP With the second signal V IN The voltage across the fifth resistor R5 changes simultaneously with the common-mode signal, without generating an AC current across R5. Therefore, the output of the amplifier circuit provided in this embodiment does not have a common-mode interference signal, and common-mode interference is well suppressed.

[0072] This application simulates and verifies the amplifier circuit, setting its high-pass bandwidth to 1Hz, gain to 20x, and DC bias to 100mV, and using a field-effect transistor instead of a current source. Figure 5 The figure shows the simulation results of the differential-mode response of the amplifier circuit. Figure 5 As can be seen, low-frequency signals are suppressed, meaning the amplifier circuit suppresses the DC bias in the target differential signal. The high-pass filter has a -3dB bandwidth of 1Hz and a passband gain of 26dB. For example... Figure 6 The figure shows the simulation results of the common-mode rejection characteristics of the amplifier circuit. From... Figure 6 As can be seen, the common-mode rejection ratio (CMRR) at 50Hz is 92dB. The gain of the target differential signal at 50Hz is 26dB, so the CMRR is 118dB@50Hz.

[0073] This application also provides a detection chip, including the aforementioned amplification circuit.

[0074] Specifically, when a DC deviation exists in the acquired target differential signal, the current generation module in the amplifier circuit generates a deviation current. This deviation current causes the first logic module to generate a first DC voltage, and the second logic module to generate a second DC voltage. Due to the existence of the DC deviation, a discrepancy exists between the first and second DC voltages. As long as this discrepancy exists, the voltage adjustment module continuously adjusts the first and second DC voltages until they are equal to the reference voltage, thus eliminating the discrepancy between them. This suppresses the DC deviation between the first and second signals in the target differential signal, preventing the amplifier circuit output from saturating and allowing amplification of useful small AC signals. When the first and second DC voltages are equal to the reference voltage, the current generation module generates a differential current based on the first and second signals. This differential current causes the first logic module to generate the first voltage in the differential voltage set, and the second logic module to generate the second voltage in the differential voltage set, thus amplifying the small AC signals in the target differential signal. The amplified signal is then transmitted to the detection chip for further processing.

[0075] This application also provides a wearable device, including the detection chip described above.

[0076] The wearable device provided in this application embodiment suppresses the DC deviation between the first and second signals in the target differential signal, so that the output of the amplifier circuit will not saturate, and can amplify useful small AC signals. For the specific working principle, please refer to the description of the working principle of the detection chip and the amplifier circuit described above, which will not be repeated here.

[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0078] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An amplifier circuit, characterized in that, It includes a first logic module, a second logic module, a current generation module, and a voltage regulation module; the current generation module is electrically connected to the first logic module and the second logic module, and the voltage regulation module is electrically connected to the first logic module and the second logic module, respectively. The first logic module is used to receive a first signal from the reference voltage and the target differential signal, and transmit the first signal to the current generation module; The second logic module is used to receive a second signal from the reference voltage and the target differential signal, and transmit the second signal to the current generation module; When there is a DC deviation between the first signal and the second signal, the current generation module is used to generate a deviation current according to the DC deviation. The deviation current causes the first logic module to generate a first DC voltage and the second logic module to generate a second DC voltage. The voltage regulation module is used to acquire the first DC voltage and the second DC voltage, and to regulate the first DC voltage and the second DC voltage so that the first DC voltage and the second DC voltage are equal to the reference voltage; The first logic module includes a first operational amplifier, a first field-effect transistor, a first current source, a second current source, and a first resistor; The positive terminal of the first current source is electrically connected to the positive terminal of the first power supply. The non-inverting input terminal of the first operational amplifier is used to receive the first signal. The inverting input terminal of the first operational amplifier is electrically connected to the source of the first field-effect transistor, the negative terminal of the first current source, and the current generation module. The output terminal of the first operational amplifier is electrically connected to the gate of the first field-effect transistor. The drain of the first field-effect transistor is electrically connected to the first terminal of the first resistor, the positive terminal of the second current source, and the voltage adjustment module. The second terminal of the first resistor is used to receive the reference voltage. The negative terminal of the second current source is electrically connected to the negative terminal of the first power supply. The current provided by the first current source and the current provided by the second current source are equal in magnitude and in the same direction.

2. The amplifier circuit according to claim 1, characterized in that, The second logic module includes a second operational amplifier, a second field-effect transistor, a third current source, a fourth current source, and a second resistor; The positive terminal of the third current source is electrically connected to the positive terminal of the second power supply. The non-inverting input terminal of the second operational amplifier is used to receive the second signal. The inverting input terminal of the second operational amplifier is electrically connected to the source of the second field-effect transistor, the negative terminal of the third current source, and the current generation module, respectively. The output terminal of the second operational amplifier is electrically connected to the gate of the second field-effect transistor. The drain of the second field-effect transistor is electrically connected to the first terminal of the second resistor, the positive terminal of the fourth current source, and the voltage adjustment module, respectively. The second terminal of the second resistor is used to receive the reference voltage. The negative terminal of the fourth current source is electrically connected to the negative terminal of the second power supply. The current provided by the third current source, the current provided by the fourth current source, and the current provided by the first current source are equal in magnitude and in the same direction.

3. The amplifier circuit according to claim 2, characterized in that, The first and second field-effect transistors are P-type field-effect transistors, the first and third current sources are P-type current sources, and the second and fourth current sources are N-type current sources.

4. An amplifier circuit, characterized in that, It includes a first logic module, a second logic module, a current generation module, and a voltage regulation module; the current generation module is electrically connected to the first logic module and the second logic module, and the voltage regulation module is electrically connected to the first logic module and the second logic module, respectively. The first logic module is used to receive a first signal from the reference voltage and the target differential signal, and transmit the first signal to the current generation module; The second logic module is used to receive a second signal from the reference voltage and the target differential signal, and transmit the second signal to the current generation module; When there is a DC deviation between the first signal and the second signal, the current generation module is used to generate a deviation current according to the DC deviation. The deviation current causes the first logic module to generate a first DC voltage and the second logic module to generate a second DC voltage. The voltage regulation module is used to acquire the first DC voltage and the second DC voltage, and to regulate the first DC voltage and the second DC voltage so that the first DC voltage and the second DC voltage are equal to the reference voltage; The first logic module includes a third operational amplifier, a third field-effect transistor, a fifth current source, a sixth current source, a first current mirror, and a third resistor; The positive terminal of the fifth current source is electrically connected to the positive terminal of the first power supply. The non-inverting input terminal of the third operational amplifier is used to receive the first signal. The inverting input terminal of the third operational amplifier is electrically connected to the source of the third field-effect transistor, the negative terminal of the fifth current source, and the current generation module. The output terminal of the third operational amplifier is electrically connected to the gate of the third field-effect transistor. The drain of the third field-effect transistor is electrically connected to the input terminal of the first current mirror. The output terminal of the first current mirror is electrically connected to the first terminal of the third resistor, the negative terminal of the sixth current source, and the voltage adjustment module. The common terminal of the first current mirror is electrically connected to the negative terminal of the first power supply. The second terminal of the third resistor is used to receive the reference voltage. The positive terminal of the sixth current source is electrically connected to the positive terminal of the first power supply. The current provided by the fifth current source and the current provided by the sixth current source are equal in magnitude and in the same direction.

5. The amplifier circuit according to claim 4, characterized in that, The second logic module includes a fourth operational amplifier, a fourth field-effect transistor, a seventh current source, an eighth current source, a second current mirror, and a fourth resistor; The positive terminal of the seventh current source is electrically connected to the positive terminal of the second power supply. The non-inverting input terminal of the fourth operational amplifier is used to receive the second signal. The inverting input terminal of the fourth operational amplifier is electrically connected to the source of the fourth field-effect transistor, the negative terminal of the seventh current source, and the current generation module, respectively. The output terminal of the fourth operational amplifier is electrically connected to the gate of the fourth field-effect transistor. The drain of the fourth field-effect transistor is electrically connected to the input terminal of the second current mirror. The output terminal of the second current mirror is electrically connected to the first terminal of the fourth resistor, the negative terminal of the eighth current source, and the voltage adjustment module, respectively. The common output terminal of the second current mirror is electrically connected to the negative terminal of the second power supply. The second terminal of the fourth resistor is used to receive the reference voltage. The positive terminal of the eighth current source is electrically connected to the positive terminal of the second power supply. The currents provided by the seventh current source, the eighth current source, and the fifth current source are equal in magnitude and in the same direction.

6. The amplifier circuit according to any one of claims 1-5, characterized in that, The current generation module includes a fifth resistor; the first end of the fifth resistor is electrically connected to the first logic module, and the second end of the fifth resistor is electrically connected to the second logic module.

7. The amplifier circuit according to any one of claims 1-5, characterized in that, The voltage regulation module includes a first transconductance unit, a second transconductance unit, and a first capacitor; The positive input terminal of the first transconductance unit is electrically connected to the positive output terminal of the second logic module and the second transconductance unit, respectively. The negative input terminal of the first transconductance unit is electrically connected to the negative output terminal of the first logic module and the second transconductance unit, respectively. The positive output terminal of the first transconductance unit is electrically connected to the positive terminal of the first capacitor and the negative input terminal of the second transconductance unit, respectively. The negative output terminal of the first transconductance unit is electrically connected to the negative terminal of the first capacitor and the positive input terminal of the second transconductance unit, respectively.

8. A detection chip, characterized in that, Includes the amplifier circuit described in any one of claims 1-7.

9. A wearable device, characterized in that, Includes the detection chip as described in claim 8.

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