Signaling circuit, semiconductor device and semiconductor system using the same

Abstract

The present application relates to a signal transmission circuit and a semiconductor device and a semiconductor system using the same. A signal transmission circuit includes a first output control circuit, a second output control circuit, a first output driver, and a second output driver. The first output control circuit generates a first main drive signal based on a first control signal and generates a first auxiliary drive signal based on the first control signal and a second control signal. The second output control circuit generates a second main drive signal based on the second control signal and generates a second auxiliary drive signal based on the first control signal and the second control signal. The first output driver drives an output node based on the first main drive signal and the first auxiliary drive signal. The second output driver drives the output node based on the second main drive signal and the second auxiliary drive signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0024605, filed with the Korean Intellectual Property Office on February 24, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The various implementations generally relate to integrated circuit technology, and more specifically, to signal transmitting circuits and semiconductor devices and semiconductor systems using the same. Background Technology

[0004] Electronic devices may include many electronic components. Among these components, a computer system may include many semiconductor devices made of semiconductors. These semiconductor devices constituting the computer system can send / receive clock signals and data to communicate with each other. Each semiconductor device can be coupled to another semiconductor device via a signal bus, such as a data bus, and can send signals containing information corresponding to the data via the signal bus. Each semiconductor device may include a signal transmitting circuit to send signals via the signal bus, and the signal transmitting circuit can send analog voltages via the signal bus to transmit signals. Typically, the signal transmitting circuit can send analog voltages corresponding to high logic levels and analog voltages corresponding to low logic levels. However, to send more information in a single signal transmission, a multi-level signal transmission method using PAM (Pulse Amplitude Modulation) is employed. The multi-level signal transmission method can divide the level of the analog voltage transmitted via the signal bus, transmitting 2 bits or more of digital information as a single analog signal. In the multi-level signal transmission method, accurately defining the voltage level of an analog signal comprising multiple bits of digital information can be important. Summary of the Invention

[0005] In one embodiment, a signal transmitting circuit may include a first output control circuit, a second output control circuit, a first output driver, and a second output driver. The first output control circuit may be configured to generate a first main drive signal based on a first control signal and a first auxiliary drive signal based on the first and second control signals. The second output control circuit may be configured to generate a second main drive signal based on a second control signal and a second auxiliary drive signal based on the first and second control signals. The first output driver may be configured to drive an output node based on the first main drive signal and the first auxiliary drive signal. The second output driver may be configured to drive the output node based on the second main drive signal and the second auxiliary drive signal.

[0006] In one embodiment, a signal transmitting circuit may include a first output control circuit, a second output control circuit, a first output driver, and a second output driver. The first output control circuit may be configured to generate a first main drive signal and a first auxiliary drive signal from a first control signal, and to change the logic level of the first auxiliary drive signal to the second logic level for a predetermined time when the logic level of the first control signal remains at a first logic level and the logic level of the second control signal changes from the first logic level to the second logic level. The second output control circuit may be configured to generate a second main drive signal and a second auxiliary drive signal from a second control signal, and to change the logic level of the second auxiliary drive signal to the second logic level for a predetermined time when the logic level of the second control signal remains at a first logic level and the logic level of the first control signal changes from the first logic level to the second logic level. The first output driver may be configured to drive an output node based on the first main drive signal and the first auxiliary drive signal. The second output driver may be configured to drive an output node based on the second main drive signal and the second auxiliary drive signal.

[0007] In one embodiment, a semiconductor device may include a signal transmitting circuit. The signal transmitting circuit may be configured to generate an output signal based on a first control signal and a second control signal, the first and second control signals defining at least a first state, a second state, a third state, and a fourth state of a bit stream. The signal transmitting circuit may be configured to perform a boosting operation on the output signal based on a control signal in which a logic level is maintained, when the bit stream transitions from one of the first and fourth states to one of the second and third states. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating the configuration of a semiconductor system according to an embodiment and the voltage level of the Tx (transmit) signal transmitted via a signal transmission bus.

[0009] Figure 2 This is a diagram showing the configuration of the signal transmission circuit according to an embodiment.

[0010] Figure 3 It is shown Figure 2 A diagram showing the configuration of the first and second output circuits.

[0011] Figure 4 It is shown Figure 2 A diagram showing the configuration of the first enhanced control circuit.

[0012] Figure 5 It is shown Figure 2 A diagram showing the configuration of the second enhanced control circuit.

[0013] Figure 6A It is shown Figure 4 A diagram illustrating the operation of the first enhanced control circuit.

[0014] Figure 6B It is shown Figure 5 A diagram illustrating the operation of the second enhanced control circuit.

[0015] Figure 7 This is a timing diagram illustrating the operation of the signal transmission circuit according to this embodiment. Detailed Implementation

[0016] In the following, a signal transmitting circuit according to the present disclosure, and a semiconductor device and semiconductor system using the signal transmitting circuit, will be described by way of exemplary embodiments with reference to the accompanying drawings.

[0017] Figure 1 This is a diagram showing the configuration of the semiconductor system 1 according to an embodiment and the voltage level of the Tx (transmission) signal TS transmitted via the signal transmission bus 101. (Refer to...) Figure 1 Semiconductor system 1 may include a first semiconductor device 110 and a second semiconductor device 120. The first semiconductor device 110 may provide various control signals required for the operation of the second semiconductor device 120. The first semiconductor device 110 may include various types of host devices. For example, the first semiconductor device 110 may include one or more of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an MMP (Multimedia Processing Unit), a digital signal processor, an AP (Application Processor), and a memory controller. The second semiconductor device 120 may be, for example, a memory device, and the memory device may include volatile memory and non-volatile memory. Examples of volatile memory may include SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM), and examples of non-volatile memory may include ROM (Read-Only Memory), PROM (Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), EPROM (Electrically Programmable ROM), flash memory, PRAM (Phase-Change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

[0018] The second semiconductor device 120 can be coupled to the first semiconductor device 110 via multiple buses. These buses can be signal transmission lines, links, or channels for transmitting signals. Although not shown, the multiple buses may include, for example, a clock bus, a command address bus, and a data bus. The clock bus and command address bus can be unidirectional buses, while the data bus can be bidirectional. The second semiconductor device 120 can be coupled to the first semiconductor device 110 via a signal transmission bus 101. The signal transmission bus 101 can include any type of bus configured to transmit signals synchronized with a clock signal. For example, the signal transmission bus 101 can be a bidirectional bus, such as a data bus. In one embodiment, the signal transmission bus 101 can be a unidirectional bus. Even when the signal transmission bus 101 is a unidirectional bus, the technical concept of this disclosure can be applied in a similar manner. The Tx signal TS transmitted via the signal transmission bus 101 can be a multi-level signal, and the signal transmission bus 101 can be a multi-level signal transmission line for transmitting multi-level signals. For example, the Tx signal TS can have at least four different voltage levels. Depending on the state of the bitstream, the Tx signal TS can have one of the four different voltage levels. A bitstream may include two or more consecutive binary bits. A bitstream may have at least a first state, a second state, a third state, and a fourth state. The first state may correspond to a bitstream of "0,0", the second state to a bitstream of "0,1", the third state to a bitstream of "1,0", and the fourth state to a bitstream of "1,1". The Tx signal TS may have a first voltage level V1, a second voltage level V2, a third voltage level V3, and a fourth voltage level V4. Figure 1 The graph shown illustrates the voltage level of the Tx signal TS transmitted via the signal transmission bus 101. In this graph, the x-axis represents time, and the y-axis represents voltage. To transmit a bit stream with a first state, the Tx signal TS can have a first voltage level V1. To transmit a bit stream with a second state, the Tx signal TS can have a second voltage level V2. To transmit a bit stream with a third state, the Tx signal TS can have a third voltage level V3. To transmit a bit stream with a fourth state, the Tx signal TS can have a fourth voltage level V4. The second voltage level V2 can be higher than the first voltage level V1, the third voltage level V3 can be higher than the second voltage level V2, and the fourth voltage level V4 can be higher than the third voltage level V3. Depending on whether the state of the bit stream changes, the voltage level of the Tx signal TS can remain at the current voltage level or change to one of the other three voltage levels. For example, when the state of the bit stream changes from the second state to the third state, the voltage level of the Tx signal TS can change from the second voltage level V2 to the third voltage level V3.

[0019] The first semiconductor device 110 may include a signal transmitting circuit 111 and a signal receiving circuit 112. The signal transmitting circuit 111 and the signal receiving circuit 112 are coupled to a signal transmitting bus 101 via pads 113. The signal transmitting circuit 111 can receive an internal signal IS1 from the first semiconductor device 110 and can transmit a Tx signal TS generated based on the internal signal IS1 to the second semiconductor device 120 via the pads 113 and the signal transmitting bus 101. The signal receiving circuit 112 can receive the Tx signal TS transmitted via the signal transmitting bus 101 and the pads 113, and can generate the internal signal IS1 based on the Tx signal TS. For example, the signal transmitting circuit 111 can generate a Tx signal TS having one of a first to a fourth voltage level based on the state of the bitstream of the internal signal IS1. The signal transmitting circuit 111 may be a DAC (digital-to-analog converter) configured to convert the bitstream of the internal signal IS1 (digital signal) into the Tx signal TS (analog voltage). The signal receiving circuit 112 can sense the voltage level of the Tx signal TS and can recover the bitstream from the Tx signal TS. The signal receiving circuit 112 can generate the internal signal IS1 by recovering the bit stream. The signal receiving circuit 112 can be an ADC (analog-to-digital converter) configured to convert the Tx signal TS, which is an analog voltage, into a bit stream, which is a digital signal.

[0020] The second semiconductor device 120 may include a signal transmitting circuit 121 and a signal receiving circuit 122. The signal transmitting circuit 121 and the signal receiving circuit 122 are coupled to a signal transmitting bus 101 via pads 123. The signal transmitting circuit 121 can receive an internal signal IS2 from the second semiconductor device 120 and can transmit a Tx signal TS generated based on the internal signal IS2 to the first semiconductor device 110 via the pads 123 and the signal transmitting bus 101. The signal receiving circuit 122 can receive the Tx signal TS transmitted via the signal transmitting bus 101 and the pads 123, and can generate the internal signal IS2 based on the Tx signal TS. For example, the signal transmitting circuit 121 can generate a Tx signal TS having one of a first to a fourth voltage level based on the state of the bitstream of the internal signal IS2. The signal transmitting circuit 121 may be a DAC configured to convert the bitstream of the internal signal IS2, which is a digital signal, into the Tx signal TS, which is an analog voltage. The signal receiving circuit 122 can sense the voltage level of the Tx signal TS and can recover the bitstream from the Tx signal TS. The signal receiving circuit 122 can generate the internal signal IS2 by recovering the bit stream. The signal receiving circuit 122 can be an ADC, which is configured to convert the Tx signal TS, which is an analog voltage, into a bit stream, which is a digital signal.

[0021] Figure 2This is a diagram illustrating the configuration of a signal transmitting circuit 200 according to an embodiment. The signal transmitting circuit 200 can be applied as... Figure 1 Each of the signal transmitting circuits 111 and 121 shown. (Refer to...) Figure 2 The signal transmitting circuit 200 can receive a first control signal MSB and a second control signal LSB, and can generate an output signal OUT based on the first and second control signals MSB and LSB. The output signal OUT can be provided as a Tx signal TS transmitted via pad 203 and signal transmitting bus 201. The first and second control signals MSB and LSB can define the state of the bit stream. The bit stream can include two or more binary bits, and the first and second control signals MSB and LSB can constitute the bit stream. For example, the first control signal MSB can be the most significant bit of the bit stream, and the second control signal LSB can be the least significant bit of the bit stream. When the bit stream has a first state, both the first and second control signals MSB and LSB can have a high logic level. When the bit stream has a second state, the first control signal MSB can have a high logic level, and the second control signal LSB can have a low logic level. When the bit stream has a third state, the first control signal MSB can have a low logic level, and the second control signal LSB can have a high logic level. When the bit stream has a fourth state, both the first and second control signals MSB and LSB can have a low logic level. The signal transmitting circuit 200 can generate an output signal OUT with multiple voltage levels based on the first and second control signals MSB and LSB. When the state of the bit stream transitions from a first or fourth state to a second or third state, the signal transmitting circuit 200 can perform a boosting operation on the output signal OUT. When the state of the bit stream transitions, the signal transmitting circuit 200 can perform the boosting operation based on a control signal whose logic level is maintained in the first and second control signals MSB and LSB. For example, when the state of the bit stream transitions from a first state to a second state, the first control signal MSB can maintain a high logic level, while the second control signal LSB can transition from a high logic level to a low logic level. The signal transmitting circuit 200 can generate the output signal OUT based on the second control signal LSB and can perform a boosting operation on the output signal OUT based on the first control signal MSB maintaining a high logic level.

[0022] The signal transmitting circuit 200 may include a first output control circuit 210, a second output control circuit 220, a first output driver 230, and a second output driver 240. The first output control circuit 210 can receive first and second control signals MSB and LSB, and can generate a first main drive signal MSBD and a first auxiliary drive signal MSBC. The first output control circuit 210 can generate the first main drive signal MSBD based on the first control signal MSB, and can generate the first auxiliary drive signal MSBC based on the first and second control signals MSB and LSB. The first output control circuit 210 can provide the first control signal MSB as the first main drive signal MSBD and the first auxiliary drive signal MSBC. The first output control circuit 210 can sense whether the logic levels of the first and second control signals MSB and LSB have changed, and can change the first auxiliary drive signal MSBC. When the logic level of the first control signal MSB remains at a first logic level and the logic level of the second control signal LSB changes from the first logic level to a second logic level, the first output control circuit 210 can change the first auxiliary drive signal MSBC to the second logic level for a predetermined time. The first logic level can be a high logic level or a low logic level. When the first logic level is high, the second logic level can be low, and when the first logic level is low, the second logic level can be high. When a predetermined time has elapsed, the first output control circuit 210 can change the first auxiliary drive signal back to the first logic level. The predetermined time can be shorter than the unit duration of each of the first and second control signals MSB and LSB. The predetermined time and the unit duration of each of the first and second control signals MSB and LSB will be described below.

[0023] The second output control circuit 220 can receive the first and second control signals MSB and LSB, and can generate a second main drive signal LSBD and a second auxiliary drive signal LSBC. The second output control circuit 220 can generate the second main drive signal LSBD based on the second control signal LSB, and can generate the second auxiliary drive signal LSBC based on the first and second control signals MSB and LSB. The second output control circuit 220 can provide the second control signal LSB as both the second main drive signal LSBD and the second auxiliary drive signal LSBC. The second output control circuit 220 can sense whether the logic levels of the first and second control signals MSB and LSB have changed, and can change the second auxiliary drive signal LSBC. When the logic level of the second control signal LSB remains at the first logic level and the logic level of the first control signal MSB changes from the first logic level to the second logic level, the second output control circuit 220 can change the second auxiliary drive signal LSBC to the second logic level for a predetermined time. When the predetermined time has elapsed, the second output control circuit 220 can change the second auxiliary drive signal LSBC back to the first logic level.

[0024] The first output driver 230 can receive a first main drive signal MSBD and a first auxiliary drive signal MSBC, and can generate an output signal OUT by driving the output node ON based on the first main drive signal MSBD and the first auxiliary drive signal MSBC. The first output driver 230 can pull up or pull down the output node ON based on the first main drive signal MSBD. The first output driver 230 can pull up or pull down the output node ON based on the first auxiliary drive signal MSBC. The second output driver 240 can receive a second main drive signal LSBD and a second auxiliary drive signal LSBC, and can generate an output signal OUT by driving the output node ON based on the second main drive signal LSBD and the second auxiliary drive signal LSBC. The second output driver 240 can pull up or pull down the output node ON based on the second main drive signal LSBD. The second output driver 240 can pull up or pull down the output node ON based on the second auxiliary drive signal LSBC.

[0025] The first output control circuit 210 may include a first pre-driver 211 and a first enhancement control circuit 212. The first pre-driver 211 may receive a first control signal MSB and generate a first main drive signal MSBD based on the first control signal MSB. The first pre-driver 211 can generate the first main drive signal MSBD by driving or delaying the first control signal MSB. For example, the delay time of the first pre-driver 211 may correspond to the time required for the first enhancement control circuit 212 to generate a first auxiliary drive signal MSBC based on the first and second control signals MSB and LSB. The first enhancement control circuit 212 may receive the first and second control signals MSB and LSB, and can generate a first auxiliary drive signal MSBC based on the first and second control signals MSB and LSB. The first enhancement control circuit 212 may provide the first control signal MSB as the first auxiliary drive signal MSBC. The first enhancement control circuit 212 can generate the first auxiliary drive signal MSBC by driving and delaying the first control signal MSB. The first enhancement control circuit 212 can sense changes in the logic levels of the first and second control signals MSB and LSB, and can change the logic level of the first auxiliary drive signal MSBC. When the logic level of the first control signal MSB remains at the first logic level and the second control signal LSB transitions from the first logic level to the second logic level, the first enhancement control circuit 212 can drive the first auxiliary drive signal MSBC to the opposite logic level. The first enhancement control circuit 212 can also change the first auxiliary drive signal MSBC from the first logic level to the second logic level. When the second control signal LSB transitions from the first logic level to the second logic level, the first enhancement control circuit 212 can change the logic level of the first auxiliary drive signal MSBC to the second logic level for a predetermined time. After the predetermined time, the first enhancement control circuit 212 can change the first auxiliary drive signal MSBC back to the first logic level.

[0026] The second output control circuit 220 may include a second pre-driver 221 and a second enhancement control circuit 222. The second pre-driver 221 may receive a second control signal LSB and generate a second main drive signal LSBD based on the second control signal LSB. The second pre-driver 221 can generate the second main drive signal LSBD by driving or delaying the second control signal LSB. For example, the delay time of the second pre-driver 221 may correspond to the time required for the second enhancement control circuit 222 to generate a second auxiliary drive signal LSBC from the first and second control signals MSB and LSB. The second enhancement control circuit 222 may receive the first and second control signals MSB and LSB, and can generate the second auxiliary drive signal LSBC based on the first and second control signals MSB and LSB. The second enhancement control circuit 222 may provide the second control signal LSB as the second auxiliary drive signal LSBC. The second enhancement control circuit 222 can generate the second auxiliary drive signal LSBC by driving and delaying the second control signal LSB. The second enhancement control circuit 222 can sense changes in the logic levels of the first and second control signals MSB and LSB, and can change the logic level of the second auxiliary drive signal LSBC. When the second control signal LSB remains at the first logic level and the first control signal MSB transitions from the first logic level to the second logic level, the second enhancement control circuit 222 can drive the second auxiliary drive signal LSBC to the opposite logic level. The second enhancement control circuit 222 can change the logic level of the second auxiliary drive signal LSBC from the first logic level to the second logic level. When the first control signal MSB transitions from the first logic level to the second logic level, the second enhancement control circuit 222 can change the second auxiliary drive signal LSBC to the second logic level for a predetermined time. After the predetermined time, the second enhancement control circuit 222 can change the second auxiliary drive signal LSBC back to the first logic level.

[0027] Figure 3 It is shown Figure 2 A diagram showing the configuration of the first and second output drivers 230 and 240. (Refer to...) Figure 3The first output driver 230 may include a first master driver 310 and a first enhancement driver 320. The first master driver 310 may receive a first master drive signal MSBD and may pull up or pull down the output node ON based on the first master drive signal MSBD. For example, when the first master drive signal MSBD is at a low logic level, the first master driver 310 may pull the output node ON to a high logic level, and when the first master drive signal MSBD is at a high logic level, the first master driver 310 may pull the output node ON down to a low logic level. The first enhancement driver 320 may receive a first auxiliary drive signal MSBC and may pull up or pull down the output node ON based on the first auxiliary drive signal MSBC. For example, when the first auxiliary drive signal MSBC is at a low logic level, the first enhancement driver 320 may pull the output node ON to a high logic level, and when the first auxiliary drive signal MSBC is at a high logic level, the first enhancement driver 320 may pull the output node ON down to a low logic level. The drive capability of the first master driver 310's pull-up or pull-down output node ON can be greater than the drive capability of the first reinforcement driver 320's pull-up or pull-down output node ON. The output signal OUT can be generated through the output node ON and output through the pad 203 coupled to the output node ON.

[0028] The second output driver 240 may include a second main driver 330 and a second enhancement driver 340. The second main driver 330 may receive a second main drive signal LSBD and may pull up or pull down the output node ON based on the second main drive signal LSBD. For example, when the second main drive signal LSBD is at a low logic level, the second main driver 330 may pull the output node ON to a high logic level, and when the second main drive signal LSBD is at a high logic level, the second main driver 330 may pull the output node ON down to a low logic level. The second enhancement driver 340 may receive a second auxiliary drive signal LSBC and may pull up or pull down the output node ON based on the second auxiliary drive signal LSBC. For example, when the second auxiliary drive signal LSBC is at a low logic level, the second enhancement driver 340 may pull the output node ON to a high logic level, and when the second auxiliary drive signal LSBC is at a high logic level, the second enhancement driver 340 may pull the output node ON down to a low logic level. The drive capability of the second main driver 330 to pull up or pull down the output node ON may be greater than the drive capability of the second enhancement driver 340 to pull up or pull down the output node ON. The drive capability of the second main driver 330 pulling up or pulling down its output node ON can be less than the drive capability of the first main driver 310 pulling up or pulling down its output node ON. The drive capability of the second reinforcement driver 340 pulling up or pulling down its output node ON can be less than the drive capability of the first reinforcement driver 320 pulling up or pulling down its output node ON. In one embodiment, the sum of the drive capabilities of the first main driver 310 and the first reinforcement driver 320 can be twice the sum of the drive capabilities of the second main driver 330 and the second reinforcement driver 340.

[0029] The first master driver 310 may include a first transistor 311 and a second transistor 312. The first transistor 311 may be a P-channel MOS transistor, and the second transistor 312 may be an N-channel MOS transistor. The first transistor 311 may be coupled between the output node ON and the terminal supplied with a first power supply voltage VD1, and may receive a first master drive signal MSBD through its gate. When the first master drive signal MSBD has a low logic level, the first transistor 311 may pull up the output node ON by supplying the first power supply voltage VD1 to the output node ON. The second transistor 312 may be coupled between the output node ON and the terminal supplied with a second power supply voltage VD2, and may receive the first master drive signal MSBD through its gate. When the first master drive signal MSBD has a high logic level, the second transistor 312 may pull down the output node ON by supplying the second power supply voltage VD2 to the output node ON. The second power supply voltage VD2 may have a lower voltage level than the first power supply voltage VD1. Multiple voltage levels that the output signal may have may be defined between the first and second power supply voltages VD1 and VD2.

[0030] The first enhanced driver 320 may include a third transistor 321 and a fourth transistor 322. The third transistor 321 may be a P-channel MOS transistor, while the fourth transistor 322 may be an N-channel MOS transistor. The third transistor 321 may be coupled between the output node ON and the terminal supplied with a first power supply voltage VD1, and may receive a first auxiliary drive signal MSBC through its gate. When the first auxiliary drive signal MSBC has a low logic level, the third transistor 321 may pull up the output node ON by supplying the first power supply voltage VD1 to the output node ON. The fourth transistor 322 may be coupled between the output node ON and the terminal supplied with a second power supply voltage VD2, and may receive the first auxiliary drive signal MSBC through its gate. When the first auxiliary drive signal MSBC has a high logic level, the fourth transistor 322 may pull down the output node ON by supplying the second power supply voltage VD2 to the output node ON. The drive capability and / or size of the first and second transistors 311 and 312 may be greater than the drive capability and / or size of the third and fourth transistors 321 and 322. The dimensions can correspond to the ratio of channel width to channel length (W / L ratio) in the corresponding transistor.

[0031] The second master driver 330 may include a fifth transistor 331 and a sixth transistor 332. The fifth transistor 331 may be a P-channel MOS transistor, while the sixth transistor 332 may be an N-channel MOS transistor. The fifth transistor 331 may be coupled between the output node ON and the terminal supplied with the first power supply voltage VD1, and may receive the second master drive signal LSBD through its gate. When the second master drive signal LSBD has a low logic level, the fifth transistor 331 may pull up the output node ON by supplying the first power supply voltage VD1 to the output node ON. The sixth transistor 332 may be coupled between the output node ON and the terminal supplied with the second power supply voltage VD2, and may receive the second master drive signal LSBD through its gate. When the second master drive signal LSBD has a high logic level, the sixth transistor 332 may pull down the output node ON by supplying the second power supply voltage VD2 to the output node ON.

[0032] The second enhanced driver 340 may include a seventh transistor 341 and an eighth transistor 342. The seventh transistor 341 may be a P-channel MOS transistor, while the eighth transistor 342 may be an N-channel MOS transistor. The seventh transistor 341 may be coupled between the output node ON and the terminal supplied with the first power supply voltage VD1, and may receive a second auxiliary drive signal LSBC through its gate. When the second auxiliary drive signal LSBC has a low logic level, the seventh transistor 341 may pull up the output node ON by supplying the first power supply voltage VD1 to the output node ON. The eighth transistor 342 may be coupled between the output node ON and the terminal supplied with the second power supply voltage VD2, and may receive the second auxiliary drive signal LSBC through its gate. When the second auxiliary drive signal LSBC has a high logic level, the eighth transistor 342 may pull down the output node ON by supplying the second power supply voltage VD2 to the output node ON. The driving capability and size of the fifth and sixth transistors 331 and 332 may be greater than those of the seventh and eighth transistors 341 and 342. In one embodiment, the sum of the current drive capability and / or size of the first and third transistors 311 and 321 may be twice the sum of the current drive capability and / or size of the fifth and seventh transistors 331 and 341. The sum of the current drive capability and / or size of the second and fourth transistors 312 and 322 may be twice the sum of the current drive capability and / or size of the sixth and eighth transistors 332 and 342.

[0033] Figure 4 It is shown Figure 2 A diagram showing the configuration of the first enhanced control circuit 212. (Refer to...) Figure 4 The first enhanced control circuit 212 may include a first logic level sensing circuit 410 and a first auxiliary drive signal generation circuit 420. The first logic level sensing circuit 410 may receive first and second control signals MSB and LSB, and may generate a first switching control signal SW1 based on the first and second control signals MSB and LSB. The first logic level sensing circuit 410 can generate the first switching control signal SW1 by sensing whether the logic levels of the first and second control signals MSB and LSB change. When the logic level of the first control signal MSB remains at the first logic level and the logic level of the second control signal LSB changes from the first logic level to the second logic level, the first logic level sensing circuit 410 can generate the first switching control signal SW1, which is enabled within a predetermined time.

[0034] The first auxiliary drive signal generation circuit 420 can receive a first control signal MSB and a first switching control signal SW1, and can generate a first auxiliary drive signal MSBC based on the first control signal MSB and the first switching control signal SW1. The first auxiliary drive signal generation circuit 420 can output the first control signal MSB as the first auxiliary drive signal MSBC, and can drive the first auxiliary drive signal MSBC to the opposite logic level during the period when the first switching control signal SW1 is enabled.

[0035] The first logic level sensing circuit 410 may include a first odd delay unit 411, a first NAND gate 412, a first flip-flop 413, a first NOR gate 414, a first inverter 415, a second odd delay unit 416, a second NOR gate 417, a second flip-flop 418, a second NAND gate 419, a third NAND gate 4110, a second inverter 4111, a third inverter 4112, a fourth inverter 4113, and a fifth inverter 4114. The first odd delay unit 411 may receive a second control signal LSB, delay the second control signal LSB, and output a delayed signal. The first odd delay unit 411 may include an odd number of inverters. The first odd delay unit 411 may have a delay time corresponding to a predetermined time. The delay time of the first odd delay unit 411 can be set to various values ​​to set the predetermined time. The first NAND gate 412 may receive the second control signal LSB and the output of the first odd delay unit 411 and perform a NAND operation on them. The first flip-flop 413 can receive a first control signal MSB, delay the first control signal MSB, and output the delayed signal. The first flip-flop 413 can also receive a clock signal CLK. The first flip-flop 413 can output the first control signal MSB synchronously with the clock signal CLK. For example, the first flip-flop 413 can output the first control signal MSB synchronously with the rising edge of the clock signal CLK. The first flip-flop can be a DQ flip-flop. One cycle of the clock signal CLK can correspond to a unit duration of each of the first and second control signals MSB and LSB. That is, based on the current bit stream, the logic levels of the first and second control signals MSB and LSB can be maintained during one cycle of the clock signal CLK. When one cycle of the clock signal CLK has elapsed, the logic levels of the first and second control signals MSB and LSB based on the next bit stream can be maintained or changed to another logic level. The first NOR gate 414 can receive the output of the first NAND gate 412 and the output of the first flip-flop 413 and perform a NOR operation on them. The first inverter 415 can generate a first signal A by inverting the output of the first NOR gate 414.

[0036] The second odd delay unit 416 can receive the second control signal LSB, delay the second control signal LSB, and output the delayed signal. The second odd delay unit 416 can include an odd number of inverters. The second odd delay unit 416 can have a delay time corresponding to a predetermined time. The delay time of the second odd delay unit 416 can be equal to the delay time of the first odd delay unit 411 and can include the same number of inverters as the first odd delay unit 411. The second NOR gate 417 can receive the second control signal LSB and the output of the second odd delay unit 416 and perform a NOR operation on them. The second flip-flop 418 can operate in the same manner as the first flip-flop 413. The second flip-flop 418 can receive the first control signal MSB and the clock signal CLK, and can output the first control signal MSB synchronously with the clock signal CLK. The second flip-flop 418 can be a DQ flip-flop. The second NAND gate 419 can receive the output of the second NOR gate 417 and the output of the second flip-flop 418 and generate the second signal B by performing a NAND operation on them.

[0037] The third NAND gate 4110 can receive the first and second signals A and B and perform a NAND operation on them. The second inverter 4111 can invert the output of the third NAND gate 4110. The third inverter 4112 can generate the first switching control signal SW1 by inverting the output of the second inverter 4111. The fourth and fifth inverters 4113 and 4114 can generate the complementary signal SW1B of the first switching control signal SW1 by sequentially inverting the output of the second inverter 4111.

[0038] The first auxiliary drive signal generation circuit 420 may include a first inverter 421, a second inverter 422, a first pass gate 423, a flip-flop 424, a third inverter 425, a second pass gate 426, a fourth inverter 427, and a fifth inverter 428. The first inverter 421 can receive and invert the first control signal MSB. The second inverter 422 can receive and invert the output of the first inverter 421. The first pass gate 423 can receive the first switching control signal SW1, the complementary signal SW1B of the first switching control signal, and the output of the second inverter 422, and can selectively output the output of the second inverter 422 based on the first switching control signal SW1. When the first switching control signal SW1 is disabled and at a low logic level, the first pass gate 423 can output the output of the second inverter 422; when the first switching control signal SW1 is enabled and at a high logic level, the first pass gate 423 can block the output of the second inverter 422. Flip-flop 424 can receive a first control signal MSB and a clock signal CLK, and can output the first control signal MSB synchronously with the clock signal CLK. Flip-flop 424 can be a DQ flip-flop. Third inverter 425 can invert the output of flip-flop 424. Second gate 426 can receive a first switching control signal SW1, a complementary signal SW1B of the first switching control signal, and the output of third inverter 425, and can selectively output the output of third inverter 425 based on the first switching control signal SW1. When the first switching control signal SW1 is enabled to a high logic level, second gate 426 can output the output of third inverter 425, and when the first switching control signal SW1 is disabled to a low logic level, second gate 426 can block the output of third inverter 425. Fourth inverter 427 can be coupled together with first and second gates 423 and 426. Fourth and fifth inverters 427 and 428 can generate a first auxiliary drive signal MSBC by sequentially inverting the outputs of first and second gates 423 and 426.

[0039] Figure 5 It is shown Figure 2 A diagram showing the configuration of the second enhanced control circuit 222. (Refer to...) Figure 5The second enhanced control circuit 222 may include a second logic level sensing circuit 510 and a second auxiliary drive signal generation circuit 520. The second logic level sensing circuit 510 can receive first and second control signals MSB and LSB, and can generate a second switching control signal SW2 based on the first and second control signals MSB and LSB. The second logic level sensing circuit 510 can generate the second switching control signal SW2 by sensing whether the logic levels of the first and second control signals MSB and LSB change. When the logic level of the second control signal LSB remains at the first logic level and the logic level of the first control signal MSB changes from the first logic level to the second logic level, the second logic level sensing circuit 510 can generate the second switching control signal SW2, which is enabled within a predetermined time.

[0040] The second auxiliary drive signal generation circuit 520 can receive the second control signal LSB and the second switching control signal SW2, and can generate a second auxiliary drive signal LSBC based on the second control signal LSB and the second switching control signal SW2. The second auxiliary drive signal generation circuit 520 can output the second control signal LSB as the second auxiliary drive signal LSBC, and can drive the second auxiliary drive signal LSBC to the opposite logic level during the period when the second switching control signal SW2 is enabled.

[0041] The second logic level sensing circuit 510 may include a first odd delay unit 511, a first NAND gate 512, a first flip-flop 513, a first NOR gate 514, a first inverter 515, a second odd delay unit 516, a second NOR gate 517, a second flip-flop 518, a second NAND gate 519, a third NAND gate 5110, a second inverter 5111, a third inverter 5112, a fourth inverter 5113, and a fifth inverter 5114. The first odd delay unit 511 may receive a first control signal MSB, delay the first control signal MSB, and output a delayed signal. The first odd delay unit 511 may include an odd number of inverters. The first odd delay unit 511 may have a delay time corresponding to a predetermined time. The first odd delay unit 511 of the second logic level sensing circuit 510 may include a first odd delay unit 511, a first NAND gate 512, a first flip-flop 513, a first NOR gate 514, a first inverter 515, a second odd delay unit 516, a second NOR gate 517, a second flip-flop 518, a second NAND gate 519, a third NAND gate 5110, a second inverter 5111, a third inverter 5112, a fourth inverter 5113, and a fifth inverter 5114. Figure 4The first logic level sensing circuit 410 shown includes the same number of inverters in each of the first and second odd delayers 411 and 416. A first NAND gate 512 can receive a first control signal MSB and the output of the first odd delayer 511 and perform a NAND operation on them. A first flip-flop 513 can receive a second control signal LSB and a clock signal CLK, delay the second control signal LSB, and output the delayed signal. The first flip-flop 513 can output the second control signal LSB synchronously with the clock signal CLK. For example, the first flip-flop 513 can output the second control signal LSB synchronously with the rising edge of the clock signal CLK. The first flip-flop 513 can be a DQ flip-flop. A first NOR gate 514 can receive the output of the first NAND gate 512 and the output of the first flip-flop 513 and perform a NOR operation on them. A first inverter 515 can generate a third signal C by inverting the output of the first NOR gate 514.

[0042] The second odd delay unit 516 can receive the first control signal MSB, delay the first control signal MSB, and output the delayed signal. The second odd delay unit 516 may include an odd number of inverters. The second odd delay unit 516 may have a delay time corresponding to a predetermined time. The delay time of the second odd delay unit 516 may be equal to the delay time of the first odd delay unit 511, and the second odd delay unit 516 may include the same number of inverters as the first odd delay unit 511. The second NOR gate 517 can receive the first control signal MSB and the output of the second odd delay unit 516 and perform a NOR operation on them. The second flip-flop 518 can operate in the same manner as the first flip-flop 513. The second flip-flop 518 can receive the second control signal LSB and the clock signal CLK, and can output the second control signal LSB synchronously with the clock signal CLK. The second flip-flop may be a DQ flip-flop. The second NAND gate 519 can generate a fourth signal D by performing a NAND operation on the output of the second NOR gate 517 and the output of the second flip-flop 518.

[0043] The third NAND gate 5110 can receive the third and fourth signals C and D and perform NAND operations on them. The second inverter 5111 can invert the output of the third NAND gate 5110. The third inverter 5112 can generate the second switching control signal SW2 by inverting the output of the second inverter 5111. The fourth and fifth inverters 5113 and 5114 can generate the complementary signal SW2B of the second switching control signal SW2 by sequentially inverting the output of the second inverter 5111.

[0044] The second auxiliary drive signal generation circuit 520 may include a first inverter 521, a second inverter 522, a first pass gate 523, a flip-flop 524, a third inverter 525, a second pass gate 526, a fourth inverter 527, and a fifth inverter 528. The first inverter 521 can receive and invert the second control signal LSB. The second inverter 522 can receive and invert the output of the first inverter 521. The first pass gate 523 can receive the second switching control signal SW2, the complementary signal SW2B of the second switching control signal, and the output of the second inverter 522, and can selectively output the output of the second inverter 522 based on the second switching control signal SW2. When the second switching control signal SW2 is disabled and at a low logic level, the first pass gate 523 can output the output of the second inverter 522; when the second switching control signal SW2 is enabled and at a high logic level, the first pass gate 523 can block the output of the second inverter 522. Flip-flop 524 can receive the second control signal LSB and the clock signal CLK, and can output the second control signal LSB synchronously with the clock signal CLK. Flip-flop 524 can be a DQ flip-flop. Third inverter 525 can invert the output of flip-flop 524. Second gate 526 can receive the second switching control signal SW2, the complementary signal SW2B of the second switching control signal, and the output of third inverter 525, and can selectively output the output of third inverter 525 based on the second switching control signal SW2. When the second switching control signal SW2 is enabled to a high logic level, second gate 526 can output the output of third inverter 525, and when the second switching control signal SW2 is disabled to a low logic level, second gate 526 can block the output of third inverter 525. Fourth inverter 527 can be coupled together with first and second gates 523 and 526. Fourth and fifth inverters 527 and 528 can generate a second auxiliary drive signal LSBC by sequentially inverting the outputs of first and second gates 523 and 526.

[0045] Figure 6A It is shown Figure 4 The timing diagram shows the operation of the first enhanced control circuit 212. (Refer to...) Figure 4 and Figure 6AThe operation of the first enhanced control circuit 212 will be described as follows. For clarity, assume that the first control signal MSB remains at a high logic level, while the second control signal LSB transitions from a high logic level to a low logic level. When a time corresponding to a unit duration UD has elapsed after the logic level of the second control signal LSB transitions from a low logic level to a high logic level, the second control signal LSB can transition from a high logic level to a low logic level. When the second control signal LSB transitions from a high logic level to a low logic level, the logic level of the first signal A can remain at a high logic level, while the second signal B can have a pulse, its logic level transitioning to a low logic level within a predetermined time starting from the point where the logic level of the second control signal LSB transitions to a low logic level. Therefore, the first switching control signal SW1 can be enabled to a high logic level within a predetermined time starting from the point where the logic level of the second control signal LSB transitions. When the first switching control signal SW1 is disabled and is at a low logic level, the first auxiliary drive signal generation circuit 420 can output the first control signal MSB as the first auxiliary drive signal MSBC, and the first auxiliary drive signal MSBC can have a high logic level. When the first switching control signal SW1 is enabled to a high logic level, the first auxiliary drive signal generation circuit 420 can output the inverted signal of the first control signal MSB as the first auxiliary drive signal MSBC, and the first auxiliary drive signal MSBC can become low logic level. When the first switching control signal SW1 is disabled again after a predetermined time PT, the first control signal MSB can be output as the first auxiliary drive signal MSBC. Therefore, the first auxiliary drive signal MSBC can return to a high logic level and can remain at a high logic level based on the first control signal MSB. Therefore, the first auxiliary drive signal MSBC can become low logic level within a predetermined time PT starting from the time point when the second control signal LSB becomes low logic level. After the predetermined time PT, the first auxiliary drive signal MSBC can return to a high logic level.

[0046] Figure 6B It is shown Figure 5 The timing diagram shows the operation of the second enhanced control circuit 222. (Refer to...) Figure 5 and Figure 6BThe operation of the second enhanced control circuit 222 will be described as follows. For clarity, assume that the first control signal MSB transitions from a high logic level to a low logic level, while the second control signal LSB remains at a high logic level. When a time corresponding to a unit duration UD has elapsed since the logic level of the first control signal MSB transitioned from a low logic level to a high logic level, the first control signal MSB can transition from a high logic level to a low logic level. When the first control signal MSB transitions from a high logic level to a low logic level, the third signal C can remain at a high logic level, while the fourth signal D can have a pulse that transitions to a low logic level within a predetermined time period starting from the time point when the first control signal MSB transitions to a low logic level. Therefore, the second switching control signal SW2 can be enabled to a high logic level within a predetermined time period starting from the time point when the logic level of the first control signal MSB transitions. When the second switching control signal SW2 is disabled and is at a low logic level, the second auxiliary drive signal generation circuit 520 can output the second control signal LSB as the second auxiliary drive signal LSBC, and the second auxiliary drive signal LSBC can have a high logic level. When the second switching control signal SW2 is enabled to a high logic level, the second auxiliary drive signal generation circuit 520 can output the inverted signal of the second control signal LSB as the second auxiliary drive signal LSBC, and the second auxiliary drive signal LSBC can become low logic level. When the second switching control signal SW2 is disabled again after a predetermined time, the second control signal LSB can be output as the second auxiliary drive signal LSBC. Therefore, the second auxiliary drive signal LSBC can return to a high logic level and can remain at a high logic level based on the second control signal LSB. Therefore, the second auxiliary drive signal LSBC can change to a low logic level within a predetermined time PT starting from the time point when the first control signal MSB becomes low logic level. After the predetermined time PT, the second auxiliary drive signal LSBC can return to a high logic level.

[0047] The following table illustrates the operation of the signal transmission circuit 200 according to this embodiment.

[0048]

[0049]

[0050] In the table above, "State" indicates the state of the bitstream. State "0" indicates the first state, state "1" indicates the second state, state "2" indicates the third state, and state "3" indicates the fourth state. Furthermore, "H" indicates a high logic level, and "L" indicates a low logic level. Additionally, arrows indicate the direction of logic level changes.

[0051] Refer to this table Figures 1 to 5 When the bitstream state transitions from the first state to the second state, the first control signal MSB can remain at a high logic level, while the second control signal LSB can transition from a high logic level to a low logic level. The first pre-driver 211 can provide the first control signal MSB as the first master drive signal MSBD, and the first master driver 310 can continuously pull down the output node ON based on the first master drive signal MSBD. The second pre-driver 221 can provide the second control signal LSB as the second master drive signal LSBD. When the second master drive signal LSBD transitions to a low logic level, the second master driver 330 can pull up the output node ON. Since the first master driver 310 has a greater driving capability than the second master driver 330, the output node ON and the output signal OUT can be driven to the voltage level corresponding to the second voltage level V2. At this time, the first enhanced control circuit 212 can drive the first auxiliary drive signal MSBC to a low logic level within a predetermined time starting from the time point of logic level transition of the second control signal LSB, and then change the first auxiliary drive signal MSBC back to a high logic level. The second enhancement control circuit 222 can change the second auxiliary drive signal LSBC from a high logic level to a low logic level based on the second control signal LSB. The first enhancement driver 320 can pull the output node ON within a predetermined time based on the first auxiliary drive signal MSBC, thereby helping the second master driver 330 and the second enhancement driver 340 to pull the output node ON. Therefore, since the output signal OUT can rise quickly from the first voltage level V1 to the second voltage level V2, the signal transmission circuit 200 can expand the effective window of the Tx signal TS transmitted through the signal transmission bus 101 or 201.

[0052] When the bitstream state transitions from the first state to the third state, the first control signal MSB can transition from a high logic level to a low logic level, and the second control signal LSB can remain at a high logic level. The first pre-driver 211 can provide the first control signal MSB as the first master drive signal MSBD. When the first master drive signal MSBD transitions, the first master driver 310 can pull up the output node ON. The second pre-driver 221 can provide the second control signal LSB as the second master drive signal LSBD, and the second master driver 330 can continuously pull down the output node ON based on the second master drive signal LSBD. Since the first master driver 310 has a greater driving capability than the second master driver 330, the output node ON and the output signal OUT can be driven to the voltage level corresponding to the third voltage level V3. At this time, the second enhancement control circuit 222 can drive the second auxiliary drive signal LSBC to a low logic level within a predetermined time starting from the logic level transition point of the first control signal MSB, and then change the second auxiliary drive signal LSBC back to a high logic level. The first enhancement control circuit 212 can change the first auxiliary drive signal MSBC from a high logic level to a low logic level based on the first control signal MSB. The second enhanced driver 340 can pull the output node ON within a predetermined time based on the second auxiliary drive signal LSBC, thereby helping the first master driver 310 and the first enhanced driver 320 to pull the output node ON. Therefore, since the output signal OUT can rise rapidly from the first voltage level V1 to the third voltage level V3, the signal transmitting circuit 200 can expand the effective window of the Tx signal TS transmitted through the signal transmitting bus 101 or 201.

[0053] When the state of the bit stream changes from the first state to the fourth state, when the state of the bit stream changes from the second state to one of the first, third and fourth states, when the state of the bit stream changes from the third state to one of the first, second and fourth states, and when the state of the bit stream changes from the fourth state to the first state, the signal transmitting circuit 200 may not drive the first and second auxiliary drive signals MSBC and LSBC to opposite logic levels within a predetermined time.

[0054] When the bitstream state transitions from the fourth state to the second state, the logic level of the first control signal MSB can transition from a low logic level to a high logic level, and the second control signal LSB can remain at a low logic level. The first pre-driver 211 can provide the first control signal MSB as the first master drive signal MSBD. When the first master drive signal MSBD transitions, the first master driver 310 can pull down the output node to ON. The second pre-driver 221 can provide the second control signal LSB as the second master drive signal LSBD, and the second master driver 330 can continuously pull up the output node to ON based on the second master drive signal LSBD. Since the first master driver 310 has a greater driving capability than the second master driver 330, the output node ON and the output signal OUT can be driven to the voltage level corresponding to the second voltage level V2. At this time, the second enhanced control circuit 222 can drive the second auxiliary drive signal LSBC to a high logic level within a predetermined time starting from the time point of the logic level transition of the first control signal MSB, and then change the second auxiliary drive signal LSBC back to a low logic level. The first enhancement control circuit 212 can change the first auxiliary drive signal MSBC from a low logic level to a high logic level based on the first control signal MSB. The second enhancement driver 340 can pull the output node ON within a predetermined time based on the second auxiliary drive signal LSBC, thereby helping the first master driver 310 and the first enhancement driver 320 to pull the output node ON. Therefore, since the output signal OUT can drop rapidly from the fourth voltage level V4 to the second voltage level V2, the signal transmission circuit 200 can expand the effective window of the Tx signal TS transmitted through the signal transmission bus 101 or 201.

[0055] When the bitstream state transitions from the fourth state to the third state, the first control signal MSB can remain at a low logic level, and the second control signal LSB can transition from a low logic level to a high logic level. The first pre-driver 211 can provide the first control signal MSB as the first master drive signal MSBD, and the first master driver 310 can continuously pull up the output node ON based on the first master drive signal MSBD. The second pre-driver 221 can provide the second control signal LSB as the second master drive signal LSBD. When the second master drive signal LSBD transitions to a high logic level, the second master driver 330 can pull down the output node ON. Since the first master driver 310 has a greater driving capability than the second master driver 330, the output node ON and the output signal OUT can be driven to the voltage level corresponding to the third voltage level V3. At this time, the first enhanced control circuit 212 can drive the first auxiliary drive signal MSBC to a high logic level within a predetermined time starting from the time point of logic level transition of the second control signal LSB, and then change the first auxiliary drive signal MSBC back to a low logic level. The second enhancement control circuit 222 can change the second auxiliary drive signal LSBC from a high logic level to a low logic level based on the second control signal LSB. The first enhancement driver 320 can pull the output node ON within a predetermined time based on the first auxiliary drive signal MSBC, thereby assisting the second master driver 330 and the second enhancement driver 340 in pulling the output node ON. Therefore, since the output signal OUT can rise rapidly from the fourth voltage level V4 to the third voltage level V3, the signal transmission circuit 200 can expand the effective window of the Tx signal TS transmitted through the signal transmission bus 101 or 201.

[0056] Figure 7 This is a timing diagram illustrating the operation of the signal transmission circuit 200 according to this embodiment. Figure 7In this diagram, the time intervals between T1 and T2, T2 and T3, ..., T12 and T13 can all correspond to a unit duration UD. At T1, the bitstream can have a first state, and both the first and second control signals MSB and LSB can have a high logic level. At T2, when the state of the bitstream transitions to the second state, the first control signal MSB can remain at a high logic level, while the second control signal LSB can become a low logic level. Therefore, the first main drive signal MSBD can remain at a high logic level based on the first control signal MSB, and the second main drive signal LSBD and the second auxiliary drive signal LSBC can become a low logic level based on the second control signal LSB. The first auxiliary drive signal MSBC can become a low logic level within a predetermined time PT starting from the time point when the second control signal LSB becomes a low logic level, and then become a high logic level again. Therefore, the first auxiliary drive signal MSBC can switch to a low logic level within a predetermined time PT. Simultaneously with the switching of the first auxiliary drive signal MSBC, the voltage level of the output signal OUT and the voltage levels of the second main drive signal LSBD and the second auxiliary drive signal LSBC can change.

[0057] At point T3, when the bitstream state transitions from the second state to the third state, the first control signal MSB can change from a high logic level to a low logic level, and the second control signal LSB can change from a low logic level to a high logic level. The first main drive signal MSBD and the first auxiliary drive signal MSBC can have a low logic level based on the first control signal MSB, and the second main drive signal LSBD and the second auxiliary drive signal LSBC can have a high logic level based on the second control signal LSB.

[0058] At T4, when the bitstream state transitions from the third state to the fourth state, the first control signal MSB can remain at a low logic level, and the second control signal LSB can change from a high logic level to a low logic level. The first main drive signal MSBD and the first auxiliary drive signal MSBC can remain at a low logic level based on the first control signal MSB, and the second main drive signal LSBD and the second auxiliary drive signal LSBC can be at a low logic level based on the second control signal LSB. At T5, the bitstream state can remain in the fourth state, and the first main drive signal MSBD, the first auxiliary drive signal MSBC, the second main drive signal LSBD, and the second auxiliary drive signal LSBC can all remain at a low logic level.

[0059] At point T6, when the bitstream state transitions from state four to state two, the first control signal MSB can change from low logic level to high logic level, and the second control signal LSB can remain at low logic level. The first main drive signal MSBD and the first auxiliary drive signal MSBC can become high logic level based on the first control signal MSB, and the second main drive signal LSBD can remain at low logic level based on the second control signal LSB. The second auxiliary drive signal LSBC can become high logic level within a predetermined time PT starting from the time point when the first control signal MSB becomes high logic level, and then change back to low logic level. Therefore, the second auxiliary drive signal LSBC can switch to high logic level within the predetermined time PT. Simultaneously with the switching of the second auxiliary drive signal LSBC, the voltage level of the output signal OUT and the voltage levels of the first main drive signal MSBD and the first auxiliary drive signal MSBC can change.

[0060] At T7, when the bitstream state transitions from the second state to the third state, the first control signal MSB can change from a high logic level to a low logic level, and the second control signal LSB can change from a low logic level to a high logic level. The first main drive signal MSBD and the first auxiliary drive signal MSBC can be based on the first control signal MSB being at a low logic level, and the second main drive signal LSBD and the second auxiliary drive signal LSBC can be based on the second control signal LSB being at a high logic level.

[0061] At T8, when the bitstream state transitions from the third state to the fourth state, the first control signal MSB can remain at a low logic level, and the second control signal LSB can change from a high logic level to a low logic level. The first main drive signal MSBD and the first auxiliary drive signal MSBC can remain at a low logic level based on the first control signal MSB, and the second main drive signal LSBD and the second auxiliary drive signal LSBC can be at a low logic level based on the second control signal LSB. At T9, the bitstream state can remain in the fourth state, and the first main drive signal MSBD, the first auxiliary drive signal MSBC, the second main drive signal LSBD, and the second auxiliary drive signal LSBC can all remain at a low logic level.

[0062] At T10, when the bitstream state transitions from the fourth state to the first state, both the first and second control signals MSB and LSB can change from low logic level to high logic level. The first main drive signal MSBD and the first auxiliary drive signal MSBC can both have a high logic level based on the first control signal MSB, and the second main drive signal LSBD and the second auxiliary drive signal LSBC can both have a high logic level based on the second control signal LSB.

[0063] At T11, when the bitstream state transitions from the first state to the third state, the first control signal MSB can change from a high logic level to a low logic level, while the second control signal LSB can remain at a high logic level. The first main drive signal MSBD and the first auxiliary drive signal MSBC can change to a low logic level based on the first control signal MSB, and the second main drive signal LSBD can remain at a high logic level based on the second control signal LSB. The second auxiliary drive signal LSBC can change to a low logic level within a predetermined time PT starting from the time point when the first control signal MSB changes to a low logic level, and then change back to a high logic level. Therefore, the second auxiliary drive signal LSBC can switch to a low logic level within the predetermined time PT. Simultaneously with the switching of the second auxiliary drive signal LSBC, the voltage level of the output signal OUT and the voltage levels of the first main drive signal MSBD and the first auxiliary drive signal MSBC can change.

[0064] At T12, when the bitstream state transitions from the third state to the second state, the first control signal MSB can change from a low logic level to a high logic level, and the second control signal LSB can change from a high logic level to a low logic level. The first main drive signal MSBD and the first auxiliary drive signal MSBC can be based on the first control signal MSB being at a high logic level, and the second main drive signal LSBD and the second auxiliary drive signal LSBC can be based on the second control signal LSB being at a low logic level. At T13, the bitstream state can remain in the second state, both the first main drive signal MSBD and the first auxiliary drive signal MSBC can remain at a high level, and both the second main drive signal LSBD and the second auxiliary drive signal LSBC can remain at a low logic level.

[0065] Although various embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the signal transmitting circuits, semiconductor devices, and semiconductor systems described herein should not be limited to the described embodiments.

Claims

1. A signal transmitting circuit, comprising: The first output control circuit generates a first main drive signal based on a first control signal, and generates a first auxiliary drive signal based on the first control signal and a second control signal. The second output control circuit generates a second main drive signal based on the second control signal, and generates a second auxiliary drive signal based on the first control signal and the second control signal. A first output driver drives an output node based on the first main drive signal and the first auxiliary drive signal; and The second output driver drives the output node based on the second main drive signal and the second auxiliary drive signal. The first control signal and the second control signal define at least a first state, a second state, a third state, and a fourth state of the bit stream.

2. The signal transmitting circuit according to claim 1, wherein, The first output control circuit includes: A first pre-driver, which generates the first main drive signal based on the first control signal; and The first enhanced control circuit generates the first auxiliary drive signal based on the first control signal and the second control signal by sensing whether the logic level of the first control signal and the logic level of the second control signal change.

3. The signal transmitting circuit according to claim 2, wherein, The first enhanced control circuit: when the logic level of the first control signal remains at the first logic level and the logic level of the second control signal changes from the first logic level to the second logic level, the first auxiliary drive signal changes from the first logic level to the second logic level.

4. The signal transmitting circuit according to claim 3, wherein, The first enhanced control circuit changes the first auxiliary drive signal, whose logic level has been changed to the second logic level, back to the first logic level after a predetermined time.

5. The signal transmitting circuit according to claim 2, wherein, The first enhanced control circuit includes: A first logic level sensing circuit generates a first switching control signal, which is enabled for a predetermined time when the logic level of the first control signal remains at a first logic level and the logic level of the second control signal changes from the first logic level to a second logic level; and The first auxiliary drive signal generation circuit generates the first auxiliary drive signal based on the first control signal and the first switching control signal.

6. The signal transmitting circuit according to claim 5, wherein, The first auxiliary drive signal generation circuit outputs the first control signal as the first auxiliary drive signal, and drives the first auxiliary drive signal to the opposite logic level during the period in which the first switching control signal is enabled.

7. The signal transmitting circuit according to claim 2, wherein, The second output control circuit includes: A second pre-driver, which generates the second main drive signal based on the second control signal; and The second enhanced control circuit generates a second auxiliary drive signal based on the first control signal and the second control signal by sensing whether the logic level of the first control signal and the logic level of the second control signal change.

8. The signal transmitting circuit according to claim 7, wherein, The second enhanced control circuit: when the logic level of the second control signal remains at the first logic level and the logic level of the first control signal changes from the first logic level to the second logic level, the second auxiliary drive signal changes from the first logic level to the second logic level.

9. The signal transmitting circuit according to claim 8, wherein, The second enhanced control circuit changes the second auxiliary drive signal, whose logic level has been changed to the second logic level, back to the first logic level after a predetermined time.

10. The signal transmitting circuit according to claim 7, wherein, The second enhanced control circuit includes: A second logic level sensing circuit generates a second switching control signal, which is enabled for a predetermined time when the logic level of the second control signal remains at a first logic level and the logic level of the first control signal changes from the first logic level to the second logic level; and The second auxiliary drive signal generation circuit generates the second auxiliary drive signal based on the second control signal and the second switching control signal.

11. The signal transmitting circuit according to claim 10, wherein, The second auxiliary drive signal generation circuit outputs the second control signal as the second auxiliary drive signal, and drives the second auxiliary drive signal to the opposite logic level during the period in which the second switching control signal is enabled.

12. The signal transmitting circuit according to claim 1, wherein, The first output driver includes: A first master driver, which pulls up or down the output node based on a first master drive signal; and A first enhancement driver pulls up or down the output node based on the first auxiliary drive signal.

13. The signal transmitting circuit according to claim 12, wherein, The second output driver includes: A second master driver, which pulls up or down the output node based on a second master drive signal; and The second enhancement driver pulls up or down the output node based on the second auxiliary drive signal.

14. The signal transmitting circuit according to claim 13, wherein, The drive capability of the first master driver to pull up or pull down the output node is greater than the drive capability of the first reinforcement driver to pull up or pull down the output node. Wherein, the driving capability of the second master driver to pull up or pull down the output node is greater than the driving capability of the second reinforcement driver to pull up or pull down the output node.

15. The signal transmitting circuit according to claim 13, wherein, The first master driver's pull-up or pull-down capability of the output node is greater than the second master driver's pull-up or pull-down capability of the output node. Wherein, the driving capability of the first enhanced driver to pull up or pull down the output node is greater than the driving capability of the second enhanced driver to pull up or pull down the output node.

16. A signal transmitting circuit, comprising: A first output control circuit generates a first main drive signal and a first auxiliary drive signal from a first control signal, and when the logic level of the first control signal is maintained at a first logic level and the logic level of the second control signal changes from the first logic level to the second logic level for a predetermined time; The second output control circuit generates a second main drive signal and a second auxiliary drive signal from the second control signal, and changes the logic level of the second auxiliary drive signal to the second logic level for a predetermined time when the logic level of the second control signal is maintained at the first logic level and the logic level of the first control signal changes from the first logic level to the second logic level. A first output driver drives an output node based on the first main drive signal and the first auxiliary drive signal; and The second output driver drives the output node based on the second main drive signal and the second auxiliary drive signal.

17. The signal transmitting circuit according to claim 16, wherein, The predetermined time is shorter than the unit duration of each of the first control signal and the second control signal.

18. The signal transmitting circuit according to claim 16, wherein, The first output driver includes: A first master driver, which pulls up or down the output node based on a first master drive signal; and A first enhancement driver pulls up or down the output node based on the first auxiliary drive signal. The driving capability of the first main driver is greater than that of the first enhanced driver.

19. The signal transmitting circuit according to claim 18, wherein, The second output driver includes: A second master driver, which pulls up or down the output node based on a second master drive signal; and The second enhancement driver pulls up or down the output node based on the second auxiliary drive signal. The driving capability of the second main driver is greater than that of the second enhanced driver.

20. The signal transmitting circuit according to claim 19, wherein, The driving capability of the first main driver is greater than that of the second main driver, and The first enhanced driver has a greater driving capability than the second enhanced driver.

21. The signal transmitting circuit according to claim 19, wherein, The sum of the driving capabilities of the first main driver and the first enhanced driver is twice the sum of the driving capabilities of the second main driver and the second enhanced driver.

22. A semiconductor device comprising a signal transmitting circuit, the signal transmitting circuit: generating an output signal based on a first control signal and a second control signal, the first control signal and the second control signal defining at least a first state, a second state, a third state, and a fourth state of a bit stream; and performing an enhancement operation on the output signal based on a control signal in which a logic level of one of the first control signal and the second control signal is maintained when the bit stream transitions from one of the first state and the fourth state to one of the second state and the third state.

23. The semiconductor device according to claim 22, wherein, The signal transmitting circuit performs the enhancement operation by driving the first control signal to the opposite logic level for a predetermined time when the logic level of the first control signal remains at the first logic level and the logic level of the second control signal changes from the first logic level to the second logic level. And when the logic level of the second control signal remains at the first logic level and the logic level of the first control signal changes from the first logic level to the second logic level, the enhancement operation is performed by driving the second control signal to the opposite logic level for a predetermined time.

24. The semiconductor device according to claim 23, wherein, The predetermined time is shorter than the unit duration of each of the first control signal and the second control signal.

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