A capacitance adaptation circuit based on second-order incremental sigma delta ADC

Abstract

The present invention seeks to protect a capacitor adaptation circuit based on a second-order incremental sigma delta ADC, comprising a feedback path, a quantizer, first-stage and second-stage integrators, first, second, and third feedforward paths, and a capacitor adaptation network; the feedback path is connected between the input end of the summing node corresponding to the first-stage integrator and the output end of the quantizer, and processes the output signal of the quantizer to obtain a feedback signal; the first feedforward path is connected between the output end of the modulator and the input end of the quantizer, the second feedforward path is connected between the output end of the first-stage integrator and the input end of the quantizer, and the third feedforward path is connected between the output end of the second-stage integrator and the input end of the quantizer; the feedforward path performs a weighted summation on the input signal and the output signals of the first-stage and second-stage integrators before quantization; the capacitor adaptation network is connected between the output of the first-stage integrator and the input of the second-stage integrator, and is used to match different parameters according to the amplitude of the input signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit design, and in particular relates to a capacitance adaptation circuit based on a second-order incremental sigma-delta ADC. Background Art

[0002] Based on the ratio of sampling frequency to input signal bandwidth, ADCs can be roughly divided into two types: Nyquist ADC and SigmaDelta ADC. Sigma-delta ADC can significantly increase the effective number of bits by using oversampling and noise shaping techniques. The incremental Sigma-delta ADC has made some improvements based on the traditional Sigma-delta ADC. It inherits almost all the advantages of the Sigma-delta ADC and adopts the Nyquist ADC working mode. At the same time, the incremental Sigma-delta ADC has its own unique working characteristics: (1) The converter can operate in discontinuous mode; (2) The analog integrator and digital filter are reset before each conversion starts; (3) The difficulty of designing the digital decimation filter is reduced.

[0003] The second-order incremental Sigma-delta ADC usually adopts CIFF (Cascade of Intergrators, FeedForward) structure, and its model is as follows: Figure 1 Compared to traditional sigma-delta ADCs, the input signal of an incremental sigma-delta ADC does not change during a conversion cycle. After a conversion is completed, the integrator and post-filter are reset via a reset signal before the next conversion cycle begins. The number of cycles M required for an incremental sigma-delta ADC to complete a conversion and the effective number of bits (ENOB) have the following relationship:

[0004]

[0005] Where b and c are the feedforward coefficients of the incremental sigma-delta ADC. As can be seen from the above formula, when the number of clock cycles M required for a conversion is constant, a larger product of the forward path coefficients b and c results in a higher ADC effective number of bits. When the required ENOB is constant, a larger product of the forward path coefficients b and c results in a smaller number of conversion cycles M required. However, excessive values ​​of b and c can cause integrator overflow. Therefore, to stabilize the integrator, the values ​​of b and c are typically reduced, limiting the ADC's conversion accuracy and speed. Summary of the Invention

[0006] The present invention aims to solve the above problems of the prior art. A capacitance adaptation circuit based on a second-order incremental sigma delta ADC is proposed. The technical solution of the present invention is as follows:

[0007] A capacitance adaptation circuit based on a second-order incremental sigma delta ADC includes: a feedback path, a quantizer, a first-stage integrator, a second-stage integrator, first, second, and third feedforward paths, and a capacitance adaptation network. The capacitance adaptation network is arranged between the first-stage and second-stage integrators, and matches different capacitance values ​​according to the input signal amplitude, thereby changing the forward path coefficient c of the modulator. The input end of the first-stage integrator is connected to the difference between the input analog signal Vin and the feedback signal VRP / VRN, and the output end is connected to the second forward path and the input end of the capacitance adaptation network. The input end of the second-stage integrator is connected to the capacitance adaptation network. The output of the first-stage integrator is input to the second-stage integrator through the optimal parameters adapted by the capacitor adaptation network, and the output of the second-stage integrator is connected to the input of the quantizer through the third feedforward path; the first, second, and third feedforward paths are connected between the input signal, the output signals of the integrators at each stage, and the quantizer input, and are used to perform weighted summation on the signals at each stage before quantization; the quantizer is connected between the feedforward summing circuit and the feedback path, and is used to output a corresponding digital code; the feedback path is connected between the quantizer and the input summing circuit, and is used to feed back the conversion result of the previous round to the input signal of the next conversion.

[0008] Furthermore, the capacitance adaptation network is implemented using a switched capacitor circuit, including a switch ctr and adaptation capacitors Cs2 and Cs2'. The switch ctr is connected between the second-stage sampling switch clk1d and the adaptation capacitor Cs2'. The adaptation capacitor Cs2' is connected between the switch ctr and the second-stage integration switch clk2. The adaptation capacitor Cs2 is connected between the second-stage sampling switch clk1d and the second-stage integration switch clk2.

[0009] Furthermore, in the capacitor adaptation network, Vref represents the reference voltage and ctr represents the switch state. Assuming the reference voltage is Vref, when the input signal amplitude is greater than 0.36|Vref|, ctr = 0, the network switch is open, and the sampling capacitance Cs2 of the second-stage integrator is 90fF. When the input signal amplitude is ≤ 0.36|Vref|, ctr = 1, the network switch is closed, and the sampling capacitance Cs2 + Cs2' of the second-stage integrator is 180fF.

[0010] Furthermore, the first-stage integrator is implemented using a switched capacitor circuit, including a first-stage operational amplifier, a first-stage sampling switch clk1d, clk1, a first-stage integrating switch clk2, a reset switch reset, a sampling capacitor Cs1, and an integrating capacitor Cf1. The first-stage operational amplifier is connected between the second-stage sampling switch clk1d and the first-stage integrating switch clk2. The first-stage integrating switch clk2 is connected between the first-stage sampling capacitor Cs1 and the input of the first-stage operational amplifier. The reset switch reset is connected between the input and output of the first-stage operational amplifier. The first-stage sampling switch clk1d is connected between the input signal and the first-stage sampling capacitor Cs1. The first-stage sampling capacitor Cs1 is connected between the first-stage sampling switch clk1d and clk1. The first-stage integrating capacitor Cf2 is connected between the input and output of the first-stage operational amplifier. The ratio of the first-stage sampling capacitor Cs1 (1pF) to the integrating capacitor Cf1 (5pF) is 0.2, which is the forward path coefficient b.

[0011] Furthermore, the second-stage integrator is implemented using a switched capacitor circuit, including a second-stage operational amplifier, a first-stage sampling switch clk1d, clk1, a second-stage integrating switch clk2, a reset switch reset, sampling capacitors Cs2, Cs2', and an integrating capacitor Cf2. The second-stage operational amplifier is connected between the weighting switch clk1 and the second-stage integrating switch clk2. The second-stage integrating switch clk2 is connected between the second-stage sampling capacitor Cs2 and the input of the operational amplifier. The reset switch reset is connected between the input and output of the second-stage operational amplifier. The second-stage sampling switch clk1d is connected between the output of the first-stage operational amplifier and the second-stage sampling capacitor Cs2. The first-stage sampling capacitor Cs2 is connected between the first-stage sampling switch clk1d and clk1. The second-stage integrating capacitor Cf2 is connected between the input and output of the second-stage operational amplifier. The ratio of the sampling capacitor Cs2 = 90fF or Cs2 = 180fF to the integrating capacitor Cf2 = 300fF of the second-stage integrator is 0.3 or 0.6, which is the forward path coefficient c.

[0012] Furthermore, the input of the quantizer is the weighted sum of the first, second and third feedforward paths, and the weighting coefficient is determined by the capacitance values ​​of capacitors C1, C2 and C3, where C1=100fF, C2=300fF and C3=200fF, so the weighting coefficient is 1:3:2.

[0013] Furthermore, the feedback path is implemented by a switched capacitor, which converts the output digital code Dout into a switch control signal Vp2, Vb2, determines the polarity of the feedback according to the on and closed state of the switch, and converts it into an analog form through the feedback reference voltage VRP, VRN and multiplies it by the feedback coefficient -b and inputs it to the first-stage integrator, where b is the ratio of the sampling capacitor Cs1=1p to the integration capacitor Cf1=5p of the first-stage integrator, which is 0.2.

[0014] Furthermore, the feedback path includes AND gate 1, AND gate 2, feedback switch Vp2, and feedback switch Vb2; the two input terminals of AND gate P are respectively connected to the positive output terminal of the quantizer and the clock signal clk2d, the output terminal of AND gate 1 is connected to the feedback switch Vp2, the two input terminals of AND gate 2 are respectively connected to the negative output terminal of the quantizer and the clock signal clk2d, the output terminal of AND gate 2 is connected to the feedback switch Vb2, the feedback switch Vp2 is connected between the first-stage sampling capacitor Cs1 of AND gate 1, and the feedback switch Vb2 is connected between the first-stage sampling capacitor Cs1 of AND gate 2.

[0015] Furthermore, the quantizer includes a preamplifier, a latch dynamic latch, and an RS trigger. The preamplifier is connected between the weighted switch clk1 and the latch dynamic latch input, the latch dynamic latch is connected between the preamplifier and the RS trigger, and the RS trigger is connected between the latch dynamic latch and the feedback path.

[0016] The advantages and beneficial effects of the present invention are as follows:

[0017] The present invention can improve the accuracy of ADC. The capacitor adaptation network described in claim 2 can determine the conduction and closure of the capacitor adaptation switch ctr according to the different input voltage amplitudes. Assuming the ADC reference voltage is Vref, when the input signal amplitude is greater than 0.36|Vref|, ctr=0, the ctr switch is disconnected, and the sampling capacitor Cs2 of the second-stage integrator is 90fF; when the input signal amplitude is ≤0.36|Vref|, ctr=1, the ctr switch is closed, and the sampling capacitor Cs2+Cs2' of the second-stage integrator is 180fF. The change of the sampling capacitance value of the second-stage integrator is achieved. When the number of sampling cycles M is constant, the capacitor adaptation network is enabled when |Vin|≤0.36|Vref| to double the sampling capacitance of the second-stage integrator, which can increase the effective number of bits of the ADC by 0.83bit. The present invention can improve the accuracy of ADC. When |Vin|≤0.36|Vref|, the capacitor adaptation network described in claim 2 is enabled so that ctr=1. Then, only 0.8 times the number of sampling cycles M is needed to achieve the same effective number of bits as the traditional architecture, thereby achieving speed improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1The preferred embodiment provided by the present invention is a model block diagram of a second-order incremental sigma delta ADC.

[0019] Figure 2 This is the quantization error simulation result of the traditional structure in the range of |Vin|≤0.8Vref when the forward path coefficient c=0.3.

[0020] Figure 3 This is the quantization error simulation result of the traditional structure in the range of |Vin|≤0.8Vref when the forward path coefficient c=0.6.

[0021] Figure 4 This is the quantization error simulation result of the traditional structure in the range of |Vin|≤0.36Vref when the forward path coefficient c=0.3.

[0022] Figure 5 This is the quantization error simulation result of the traditional structure in the range of |Vin|≤0.36Vref when the forward path coefficient c=0.6.

[0023] Figure 6 This is the simulation result of the quantization error in the range of |Vin|≤0.8Vref after enabling the capacitor adaptation technology.

[0024] Figure 7 This is the simulation result of the quantization error in the range of |Vin|≤0.36Vref when the capacitor adaptation technology is enabled and the number of conversion cycles M is reduced by 0.8 times.

[0025] Figure 8 This is a schematic diagram of the capacitance adaptation technology of the present invention.

[0026] Figure 9 This is the internal structure diagram of the quantizer of the present invention

[0027] Figure 10 It is the overall circuit principle diagram of the present invention;

[0028] Figure 11 It is a brief block diagram of the overall circuit of the present invention. DETAILED DESCRIPTION

[0029] The following will describe the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present invention.

[0030] The technical solution of the present invention to solve the above technical problems is:

[0031] In this embodiment, the input signal amplitude is divided into two ranges: |Vin| ≤ 0.36Vref and 0.36Vref < |Vin| ≤ 0.8Vref. A capacitor adaptation network is added to the sampling terminal of the second-stage integrator. The capacitance adaptation switch is controlled to open and close according to the input signal amplitude, thereby increasing or decreasing the sampling capacitance of the second-stage integrator. This solves the problem of a too small c value in the forward path limiting circuit performance. This can be used to improve the accuracy and speed of incremental sigma delta ADCs.

[0032] Example

[0033] The model block diagram of the second-order incremental sigma deltaADC is as follows Figure 1 As shown in Figure 1, the relationship between the ADC's effective number of bits (ENOB), the number of cycles (M) required to complete a conversion, and the forward paths b and c is given by Equation (1). When the number of clock cycles (M) required for a conversion is constant, the larger the product of the forward path coefficients (b) and c, the higher the ADC's effective number of bits. When the required ENOB is constant, the larger the product of the forward path coefficients (b) and c, the smaller the number of conversion cycles (M) required. Therefore, larger b and c values ​​are beneficial for improving the accuracy and speed of the ADC. However, too large b and c values ​​can cause integrator overflow, so in order to stabilize the integrator, the values ​​of b and c are usually reduced, thus limiting the ADC's conversion accuracy and speed.

[0034] For example, when the maximum input signal of the ADC is |Vin|=0.8Vref and the output swing of the integrator |OutSwing|=0.3Vref, if ENOB=13.5bit is required, let Vref=1, then the minimum resolution voltage , take b=0.2, c=0.3, M=500, run the simulation to get the waveform of quantization error changing with input signal as shown below Figure 2 As shown, the maximum quantization error within the range is 0.325LSB, which meets the accuracy requirements.

[0035] Increase c to 0.6, keep other conditions unchanged, and run the simulation to get the waveform of quantization error changing with input signal. Figure 2 As shown in the figure, the maximum quantization error within the range is 1.3LSB, which does not meet the accuracy requirements. This is because the large value of c causes the second-stage integrator to overflow when the input signal amplitude is large, thus reducing the ADC accuracy.

[0036] Compare Figure 4 、 Figure 5It can be seen that although the accuracy requirement can be met when c=0.3, the maximum quantization error in the range of Vin≤|0.36|Vref is 0.232LSB. When c=0.6, the maximum quantization error in the range of Vin≤|0.36|Vref is 0.139LSB, which is 0.83bit higher than that of c=0.3.

[0037] Let c=0.6 when |Vin|≤0.36Vref, and c=0.3 when 0.36Vref<|Vin|≤0.8Vref, and run the simulation to get the waveform of quantization error changing with input signal. Figure 2 As shown in the figure, the maximum quantization error within the range is 0.325LSB, which meets the accuracy requirements. The maximum quantization error within the range of |Vin|≤0.36Vref is 0.139LSB, which improves the accuracy of the ADC within the range of |Vin|≤0.36Vref by 0.83bit while ensuring the stability of the ADC.

[0038] When the capacitor adaptation technology is enabled and the number of cycles M required for each conversion is reduced from 500 to 400, the simulation results are as follows: Figure 7 As shown in the figure, the maximum quantization error in the range of |Vin|≤0.36Vref is 0.232LSB, which is consistent with Figure 3 Comparison shows that this result is basically consistent with the simulation result when M is 500 and the capacitor adaptation technology is not enabled. The speed is increased by 20% while ensuring the same accuracy.

[0039] The circuit level implementation of capacitor adaptation technology is as follows Figure 8 As shown, a set of switches and capacitors are added to the traditional sampling capacitor, and Csa=Csb=90fF, Cf=300fF. When |Vin|≤0.36Vref, ctr=1, the switch is closed, and the sampling capacitor Cs=Csa+Csb=180fF. ; When 0.36Vref<|Vin|≤0.8Vref, ctr=0, the switch is disconnected, and the sampling capacitor Cs=Csb=90fF, .

[0040] like Figure 10 As shown in FIG, a capacitor adaptation network is used for a second-order incremental sigma delta ADC. Only two switches and two capacitors are added to the traditional structure, while only one switch and one capacitor are needed for a single-ended structure.

[0041] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0042] The above embodiments should be understood as merely illustrating the present invention and not as limiting the scope of protection of the present invention. After reading the contents of the present invention, technicians may make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A capacitance adaptation circuit based on a second-order incremental sigma delta ADC, characterized in that: include: A feedback path, a quantizer, a first-stage integrator, a second-stage integrator, first, second, and third feedforward paths, and a capacitor adaptation network, wherein the capacitor adaptation network is disposed between the first-stage and second-stage integrators and matches different capacitor values ​​according to different input signal amplitudes, thereby changing the forward path coefficient c of the modulator; The input of the first-stage integrator is connected to the difference between the input analog signal Vin and the feedback signal VRP / VRN, and the output is connected to the input of the second forward path and the capacitor adaptation network; the input of the second-stage integrator is connected to the output of the capacitor adaptation network, the output of the first-stage integrator is input to the second-stage integrator through the optimal parameters adapted by the capacitor adaptation network, and the output of the second-stage integrator is connected to the input of the quantizer through a third feedforward path; the first, second, and third feedforward paths are connected between the input signal, the output signals of the integrators at each stage, and the input of the quantizer, and are used to perform weighted summation on the signals at each stage before quantization; the quantizer is connected between the feedforward summing circuit and the feedback path, and is used to output a corresponding digital code; The feedback path is connected between the quantizer and the input summing circuit, and is used to feed back the conversion result of the previous round to the input signal of the next conversion; The capacitance adaptation network is implemented using a switched capacitor circuit, including a switch ctr and adaptation capacitors Cs2 and Cs2'. The switch ctr is connected between the second-stage sampling switch clk1d and the adaptation capacitor Cs2'. The adaptation capacitor Cs2' is connected between the switch ctr and the second-stage integration switch clk2. The adaptation capacitor Cs2 is connected between the second-stage sampling switch clk1d and the second-stage integration switch clk2. In the capacitor adaptation network, assuming that the reference voltage is Vref and ctr is the working state of the adaptation switch, when the input signal amplitude is greater than 0.36|Vref|, ctr=0, the switch in the network is disconnected, and the sampling capacitance Cs2 of the second-stage integrator is 90fF; when the input signal amplitude is ≤0.36|Vref|, ctr=1, the switch in the network is closed, and the sampling capacitance Cs2+Cs2' of the second-stage integrator is 180fF; The first-stage integrator is implemented using a switched capacitor circuit, including a first-stage operational amplifier, a first-stage sampling switch clk1d, clk1, a first-stage integration switch clk2, a reset switch reset, a sampling capacitor Cs1, and an integration capacitor Cf1; the first-stage operational amplifier is connected between the second-stage sampling switch clk1d and the first-stage integration switch clk2, the first-stage integration switch clk2 is connected between the first-stage sampling capacitor Cs1 and the input of the first-stage operational amplifier, the reset switch reset is connected between the input and output of the first-stage operational amplifier, the first-stage sampling switch clk1d is connected between the input signal and the first-stage sampling capacitor Cs1, the first-stage sampling capacitor Cs1 is connected between the first-stage sampling switch clk1d and clk1, the first-stage integration capacitor Cf2 is connected between the input and output of the first-stage operational amplifier, and the ratio of the first-stage sampling capacitor Cs1 = 1pF to the integration capacitor Cf1 = 5pF, which is 0.2, is the forward path coefficient b; The second-stage integrator is implemented using a switched capacitor circuit, including a second-stage operational amplifier, a first-stage sampling switch clk1d, clk1, a second-stage integrating switch clk2, a reset switch reset, sampling capacitors Cs2, Cs2', and an integrating capacitor Cf2. The second-stage operational amplifier is connected between the weighting switch clk1 and the second-stage integrating switch clk2. The second-stage integrating switch clk2 is connected between the second-stage sampling capacitor Cs2 and the input of the operational amplifier. The reset switch reset is connected between the input and output of the second-stage operational amplifier. The second-stage sampling switch clk1d is connected between the output of the first-stage operational amplifier and the second-stage sampling capacitor Cs2. The first-stage sampling capacitor Cs2 is connected between the first-stage sampling switch clk1d and clk1. The second-stage integrating capacitor Cf2 is connected between the input and output of the second-stage operational amplifier. The ratio of the sampling capacitor Cs2 = 90fF or Cs2 = 180fF of the second-stage integrator to the integrating capacitor Cf2 = 300fF, which is 0.3 or 0.6, is the forward path coefficient c.

2. A capacitance adaptation circuit based on a second-order incremental sigma delta ADC according to claim 1, characterized in that: The input of the quantizer is the weighted sum of the first, second and third feedforward paths, and the weighting coefficient is determined by the capacitance values ​​of capacitors C1, C2 and C3, where C1=100fF, C2=300fF and C3=200fF, so the weighting coefficient is 1:3:

2.

3. The capacitance adaptation circuit based on a second-order incremental sigma delta ADC according to claim 1, characterized in that: The feedback path is implemented by a switched capacitor, which converts the output digital code Dout into a switch control signal Vp2, Vb2. The polarity of the feedback is determined by the on and off of the switch, and is converted into an analog form through the feedback reference voltage VRP, VRN and multiplied by the feedback coefficient -b to be input to the first-stage integrator. b is the ratio of the sampling capacitor Cs1 = 1p to the integrating capacitor Cf1 = 5p of the first-stage integrator, which is 0.

2.

4. The capacitance adaptation circuit based on a second-order incremental sigma delta ADC according to claim 3, characterized in that: The feedback path includes AND gate 1, AND gate 2, feedback switch Vp2, and feedback switch Vb2; the two input terminals of AND gate P are respectively connected to the positive output terminal of the quantizer and the clock signal clk2d, the output terminal of AND gate 1 is connected to the feedback switch Vp2, the two input terminals of AND gate 2 are respectively connected to the negative output terminal of the quantizer and the clock signal clk2d, the output terminal of AND gate 2 is connected to the feedback switch Vb2, the feedback switch Vp2 is connected between the first-stage sampling capacitor Cs1 of AND gate 1, and the feedback switch Vb2 is connected between the first-stage sampling capacitor Cs1 of AND gate 2.

5. The capacitance adaptation circuit based on a second-order incremental sigma delta ADC according to claim 2, characterized in that: The quantizer includes a preamplifier, a latch dynamic latch, and an RS trigger. The preamplifier is connected between the weighted switch clk1 and the latch dynamic latch input, the latch dynamic latch is connected between the preamplifier and the RS trigger, and the RS trigger is connected between the latch dynamic latch and the feedback path.

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