IP core architecture for triple-redundant MDS array encoding and decoding based on systolic array

Abstract

The present invention relates to the fields of computer application technology and network coding, and more particularly to an IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array. The architecture comprises a PE module, a Weight FIFO module, an encoding and decoding module, and a driver module. L PE modules are arranged horizontally to form a one-dimensional systolic array. The one-dimensional systolic array outputs R redundant packets at intervals of K*L cycles. The PE modules include registers, accumulators, and XOR units. The calculation results and valid signals of the previous PE module are transmitted to the next PE module for calculation after passing through the registers. The Weight FIFO module is used to temporarily store coefficient matrix information and periodically fan out the input ports of all PE modules corresponding to the one-dimensional systolic array. The present invention implements cyclic shift matrix multiplication operations through the systolic array, reducing computational complexity while ensuring a fixed encoding and decoding delay, and improving hardware scalability, throughput, and energy efficiency.

Description

Technical Field

[0001] The present invention relates to the fields of computer application technology and network coding, and in particular to the design and application of an IP core for implementing triple-redundant MSD array encoding and decoding based on a systolic array. Background Art

[0002] Since the concept of routing was first proposed, it has been widely believed that network data transmission is store-and-forward. That is, intermediate nodes other than the sending and receiving nodes are solely responsible for routing and do no data processing. In fact, nearly all network communications in recent decades have been based on this principle. While data transmission algorithms and technologies have evolved repeatedly, the underlying communication network structure has remained largely unchanged. However, in 2000, R. Ahlswede et al. proposed a network coding theory. Its core concept is to allow intermediate nodes to participate in coding, thereby maximizing network throughput during communication. The revolutionary significance of network coding lies in its breakthrough: it breaks through the classical information theory conclusion that commodity flows cannot be compressed. It suggests that network information flows can be processed / compressed, thereby further improving network throughput, security, robustness, and reducing transmission latency.

[0003] As a relatively new research area in the communications field, network coding theory has been applied to various areas of information science in recent years. Distributed cloud storage networks are the most direct application scenario for multicast network coding theory. Because distributed storage networks can recover data from damaged nodes, rationally designed regenerable codes can reduce the data transmission bandwidth required for node repair. MDS (Maximum Distance Separable) codes are a widely used coding method in error-correcting storage systems. Currently, the encoding and decoding stages in existing technologies mostly use direct finite field multiplication, which is computationally complex, requires high computing power, and has strict finite field requirements. Summary of the Invention

[0004] In order to solve the technical problems existing in the above-mentioned prior art, the present invention provides an IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array, which is intended to solve the technical problems mentioned in the prior art of using direct finite field multiplication, which is computationally complex, requires high computing power, and has relatively strict finite field requirements.

[0005] The technical solution adopted in the present invention is as follows:

[0006] The IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array includes a PE module, a Weight FIFO module, and a driver module.

[0007] L of the PE modules are arranged horizontally to form a one-dimensional systolic array; three of the one-dimensional systolic arrays constitute a top-level module of an IP core for generating triple-redundant packets; each one-dimensional systolic array outputs one redundant packet every k*L cycles, and a microarchitecture diagram of the systolic array is constructed;

[0008] Each PE module includes a register, an accumulator, and an XOR unit; the calculation result and valid signal of the previous PE module are transmitted to the next PE module after passing through the register to participate in the calculation;

[0009] The IP core is provided with a coding structure for recovering the original data packet;

[0010] The Weight FIFO module is used to temporarily store coefficient matrix information and periodically fan out the input ports of all PE modules corresponding to the one-dimensional systolic array.

[0011] The present invention implements cyclic shift matrix multiplication operations through a systolic array, reducing computational complexity while ensuring a fixed delay for encoding and decoding, and improving hardware scalability, throughput, and energy efficiency. Different coefficient matrices are loaded through a Weight FIFO module, implementing encoding and decoding algorithms for different redundant packets.

[0012] Preferably, the encoding and decoding structure is as follows:

[0013] The encoding and decoding structure of the triple-redundant (n, k, r) MDS system array code is defined in the PE module, where k represents the number of original packets and r represents the number of added redundant packets, then n=k+r; each original data packet contains M×(L-1) bits of data, and an M×(L-1) binary matrix m is used. j To represent; each redundant packet r j Each contains M×(L-1) bits of data, using an M×(L-1) binary matrix m j To represent; Among them, the redundant package r j From the original data packets m1,...,m k and the coding coefficient matrix K 1j ,...,K kj The linear combination is as follows:

[0014]

[0015] Where: F j Represented as r j The corresponding coding coefficient block vector is generated by r j The required k coding coefficient matrices are obtained by juxtaposing them row by row;

[0016] For the system MDS vector code, there are r original data packets m1,...,mr If the original data packets are lost, the remaining kr known data packets are first extracted from the verification packets r1,...,r r Eliminate the new check package r′1,...,r′ r , and then restore the original data packets m1,...,m through the following formula k :

[0017] [r′1r′2...r′ r ]=[m1m2...m r ]D

[0018] where D is the new verification packet r′1,...,r′ r The corresponding coding coefficient matrix.

[0019] Because classic vector codes have high computational complexity when performing matrix multiplication, generating an L*L permutation matrix based on a finite field and selecting the coding coefficients from the permutation matrix during multiplication reduces the computational difficulty of matrix multiplication, but the permutation operation becomes increasingly complex as L increases. To reduce encoding and decoding complexity, the present invention constructs an encoding and decoding algorithm based on circular shifts, using circular shifts as the main method in the encoding process, replacing the complex finite field multiplication operation.

[0020] For the convenience of expression, the present invention defines:

[0021] L is any prime number, I L-1 represents the (L-1)×(L-1)-dimensional unit matrix;

[0022] 0 and 1 represent (L-1)-dimensional all-0 and all-1 column vectors respectively;

[0023] C L is an L×L GF(2)-cyclic shift matrix;

[0024]

[0025] G represents a (L-1)×L GF(2)-matrix [I L-1 0];

[0026] H represents a GF(2)-matrix of L×(L-1) [I L-1 1];

[0027] For an L-dimensional row vector m′, vector multiplication matrix This is equivalent to performing a right circular shift of j bits on the vector m′.

[0028] Preferably, in the PE module, after the input port Vin is valid, the original data packet and the coefficient matrix are respectively transmitted from the Din and Weight FIFO modules of the PE module to the XOR unit according to the ripple period; when the coefficient bit input is N, and when N is valid, the accumulator is updated; when Tin of the PE module is valid, the calculation of a new redundant packet begins; the accumulator is initialized to W or 0, and the original accumulator value is output as the result of the previous redundant packet.

[0029] Preferably, the weight FIFO module stores weight coefficients, and a C program is written according to the coefficient matrix calculation formula. The C program is used to receive command parameters of a cyclic shift constant L, the number of original data packets k, and the number of redundant packets r, and transform and align the coefficient matrix according to the mode of advancement of the systolic array data traveling wave;

[0030] Before starting the IP core, input the coefficient matrix with a bit width of L bits per cycle and write the coefficient matrix of k*L cycles into the Weight FIFO module; the output port Dout of the PE module outputs L cycles of redundant packet data every k*L valid data cycles.

[0031] Preferably, the MDS system array code is as follows:

[0032] Take L=17, k≤255, The coding coefficient block vector corresponding to the three redundant packets p, q, and r is set to:

[0033]

[0034] Right now:

[0035]

[0036] Where: p, q, r represent three different redundant packets, B represents a maximum of L / 2 C L The L*L matrix formed by adding different powers of L The L*L matrix formed by adding different powers of: G represents the GF(2)-matrix of (L-1)×L [I L-1 0].

[0037] Preferably, the coefficient matrix used in the encoding process is: K = GAG T ; The coefficient matrix used in the decoding process is K = H T BH.

[0038] Preferably, it also includes a simulation test module, which uses Modulsim to perform simulation testing; the coefficient matrix source file generated by the C program under weight_matrix_gen is stored in enc_mat_*.txt; the data path width L=64 bits, k=128 is set; the stimulus is set and the interface is instantiated.

[0039] Preferably, the simulation test module transplants the application example to the Xilix ZCU106 development board, selects a 300MHz user clock, and obtains a 450MHz global clock through the MMCM integrated frequency; uses the FPGA macro component BlockRAM to implement the Weight FIFO; sets the total bit width Wt to ​​256 bits and the single-core bit width Wc to 16 bits; inserts the hardware logic analyzer ILA to capture the calculation results; designs a state machine, completes the Weight FIFO configuration, and starts the calculation operation.

[0040] The beneficial effects of the present invention include: the present invention implements cyclic shift matrix multiplication operations through a systolic array, reducing the computational complexity while ensuring a fixed delay for encoding and decoding, and improving the scalability, throughput, and energy efficiency of the hardware; and by loading different coefficient matrices through a Weight FIFO module, implementing encoding and decoding algorithms for different redundant packets. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a diagram of the implementation process of the MDS array code 3 redundant packet in the present invention (taking the p redundant packet as an example).

[0042] Figure 2 This is a microarchitecture diagram of the one-dimensional systolic array SA_Core in the present invention.

[0043] Figure 3 This is a microarchitecture diagram of the cyclic shift systolic array in the present invention.

[0044] Figure 4 This is a diagram to verify the correctness of the simulation waveform output in the present invention.

[0045] Figure 5 This is a data diagram of resource usage in the present invention.

[0046] Figure 6 This is a data table for resource usage in the present invention.

[0047] Figure 7 This is a power consumption analysis diagram of the present invention.

[0048] Figure 8 This is the chip layout of the present invention.

[0049] Figure 9 This is a diagram for verifying the correctness of the hardware of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0051] The following is combined with Figure 1 The present invention is described in further detail:

[0052] See attached Figure 1 To the attached Figure 3 , an IP core architecture for implementing triple-redundant MDS array encoding and decoding based on systolic array, including PE module, Weight FIFO module, and driver module;

[0053] L of the PE modules are arranged horizontally to form a one-dimensional systolic array; three of the one-dimensional systolic arrays constitute a top-level module of an IP core for generating triple-redundant packets; each one-dimensional systolic array outputs one redundant packet every k*L cycles, and a microarchitecture diagram of the systolic array is constructed;

[0054] Each PE module includes a register, an accumulator, and an XOR unit; the calculation result and valid signal of the previous PE module are transmitted to the next PE module after passing through the register to participate in the calculation;

[0055] The IP core is provided with a coding structure for recovering the original data packet;

[0056] The Weight FIFO module is used to temporarily store coefficient matrix information and periodically fan out the input ports of all PE modules corresponding to the one-dimensional systolic array.

[0057] The encoding and decoding structure is as follows:

[0058] The encoding and decoding structure of the triple-redundant (n, k, r) MDS system array code is defined in the PE module, where k represents the number of original packets and r represents the number of added redundant packets, then n=k+r; each original data packet contains M×(L-1) bits of data, and an M×(L-1) binary matrix m is used. j To represent; each redundant packet r jEach contains M×(L-1) bits of data, using an M×(L-1) binary matrix m j To represent; Among them, the redundant package r j From the original data packets m1,...,m k and the coding coefficient matrix K 1j ,...,K kj The linear combination is as follows:

[0059]

[0060] Where: F j Represented as r j The corresponding coding coefficient block vector is generated by r j The required k coding coefficient matrices are obtained by juxtaposing them row by row;

[0061] For the system MDS vector code, there are r original data packets m1,...,m r If the original data packets are lost, the remaining kr known data packets are first extracted from the verification packets r1,...,r r Eliminate the new check package r′1,...,r′ r , and then restore the original data packets m1,...,m through the following formula k :

[0062] [r′1r′2...r′ r ]=[m1m2...m r ]D

[0063] where D is the new verification packet r′1,...,r′ r The corresponding coding coefficient matrix.

[0064] Because classic vector codes have high computational complexity when performing matrix multiplication, generating an L*L permutation matrix based on a finite field and selecting the coding coefficients from the permutation matrix during multiplication reduces the computational difficulty of matrix multiplication, but the permutation operation becomes increasingly complex as L increases. To reduce encoding and decoding complexity, the present invention constructs an encoding and decoding algorithm based on circular shifts, using circular shifts as the main method in the encoding process, replacing the complex finite field multiplication operation.

[0065] For the convenience of expression, the present invention defines:

[0066] L is any prime number, I L-1 represents the (L-1)×(L-1)-dimensional unit matrix;

[0067] 0 and 1 represent (L-1)-dimensional all-0 and all-1 column vectors respectively;

[0068] C Lis an L×L GF(2)-cyclic shift matrix;

[0069]

[0070] G represents a (L-1)×L GF(2)-matrix [I L-1 0];

[0071] H represents a GF(2)-matrix of L×(L-1) [I L-1 1];

[0072] For an L-dimensional row vector m′, vector multiplication matrix This is equivalent to performing a right circular shift of j bits on the vector m′.

[0073] In the PE module, after the input port Vin is valid, the original data packet and the coefficient matrix are respectively transmitted from the Din and Weight FIFO modules of the PE module to the XOR unit according to the ripple period; when the coefficient bit input is N and when N is valid, the accumulator is updated; when Tin of the PE module is valid, the calculation of a new redundant packet begins; the accumulator is initialized to W or 0, and the original accumulator value is output as the result of the previous redundant packet.

[0074] The weight FIFO module stores weight coefficients, and a C program is written based on a coefficient matrix calculation formula. The C program is used to receive command parameters of a cyclic shift constant L, the number of original data packets k, and the number of redundant packets r, and transform and align the coefficient matrix according to the pattern of the systolic array data traveling wave.

[0075] Before starting the encoding and decoding module, the coefficient matrix is ​​input with a bit width of L bits per cycle and the coefficient matrix of k*L cycles is written into the Weight FIFO module; the output port Dout of the PE module outputs L cycles of redundant packet data every k*L valid data cycles.

[0076] The MDS system array code is as follows:

[0077] Take L=17, k≤255, The coding coefficient block vector corresponding to the three redundant packets p, q, and r is set to:

[0078]

[0079] Right now:

[0080]

[0081] Where: p, q, r represent three different redundant packets, B represents a maximum of L / 2 C LThe L*L matrix formed by adding different powers of L The L*L matrix formed by adding different powers of: G represents the GF(2)-matrix of (L-1)×L [I L-1 0].

[0082] See attached Figure 1 As shown (k=31), according to the idea of ​​coding scheduling, the first redundant packet p=∑ 1≤j≤k m j , the intermediate calculation results can be used to generate the second and third redundant packets q, r, thereby reducing the number of XOR times required in the encoding process. The generation process is as follows Figure 1 shown.

[0083] The steps of determining the coding coefficient matrix K of the present invention are as follows: The L*L coding coefficient matrix K used in the coding is mainly composed of the following four categories, where B represents a matrix composed of at most L / 2 C L The L*L matrix (including the unit matrix I) is formed by adding different powers of L =C L0 ), A represents an even number of C L The L*L matrix formed by adding different powers of:

[0084] K = GBH, that is, for an (L–1)-dimensional input vector m, the multiplication operation of mK can be implemented by the following steps:

[0085] First, add a zero bit at the end of m to form an L-dimensional vector m (implementing the mG operation);

[0086] Perform one or more circular shift operations on m as set by B, and then perform bit-by-bit XOR on the results of the circular shift to form a new L-dimensional vector m (implementing the mB operation);

[0087] XOR the first L–1 bits of m with the last bit (implementing the mH operation) to obtain the final (L–1)-dimensional output vector mK.

[0088] K=H T BG T .

[0089] K=H T BH.

[0090] K=GAG T .

[0091] In distributed storage applications, since encoding operations are much more frequent than decoding operations, the coefficient matrix we choose for the encoding process is K=GAG T , the coefficient matrix selected during decoding is K=H T BH.

[0092] The present invention also includes a simulation test module, which uses Modulsim to perform simulation testing; wherein the coefficient matrix source file generated by the C program under weight_matrix_gen is stored in enc_mat_*.txt; the data path width L is set to 64 bits, k is set to 128; and the stimulus is set and the interface is instantiated.

[0093] The simulation test module transplants the application example to the Xilix ZCU106 development board, selects a 300MHz user clock, and obtains a 450MHz global clock through the MMCM integrated frequency. The Weight FIFO is implemented using the FPGA macro component Block RAM. The total bit width Wt is set to 256 bits and the single-core bit width Wc is set to 16 bits. The hardware logic analyzer ILA is inserted to capture the calculation results. The state machine is designed to complete the Weight FIFO configuration and start the operation.

[0094] The present invention implements cyclic shift matrix multiplication operations through a systolic array, reducing computational complexity while ensuring a fixed delay for encoding and decoding, and improving hardware scalability, throughput, and energy efficiency. Different coefficient matrices are loaded through a Weight FIFO module, implementing encoding and decoding algorithms for different redundant packets.

[0095] The present invention is further described below through the implementation steps of the present invention:

[0096] Step 1: Algorithm implementation analysis. The cyclic shift network coding module operates as a cyclic right shift and XOR. Each data packet can be regarded as a W×L byte binary matrix M k , the encoding coefficient matrix will be k Each column of the matrix is ​​subjected to a different circular right shift operation, and then the matrix results of all circular right shift operations are XORed together. The decoding operation has a similar structure to the encoding algorithm, but the difference between encoding and decoding lies in the significant difference in the combination of circular right shift operations. The circular shift network coding algorithm can be equivalent to this, where multiplication is defined as multiplication by 1 or 0, and addition is defined as matrix multiplication with XOR. Note: The input data is in bytes (W bytes wide), while the coefficient matrix is ​​in bits (L bits wide).

[0097] To improve hardware scalability, throughput, and energy efficiency, the present invention uses a systolic array (SA) to implement cyclic shift matrix multiplication, reducing computational complexity while ensuring constant encoding and decoding latency. The basic computational unit of the systolic array is the MAC mode processing element (PE). The PE calculation formula is Sum + = N × D, where N is the input coefficient bit and D is the input data.

[0098] Step 2: Hardware architecture design. This step can be divided into the following steps.

[0099] (1) Generation of redundant packets. Figure 2 L PEs are horizontally combined into an SA_Core (one-dimensional systolic array core), which is responsible for computing a single redundant packet. The SA_Core has an additional weight coefficient storage component, a Weight FIFO, which is L bits wide. This FIFO is loaded with different coefficient matrices through software to implement encoding and decoding operations for different redundant packets.

[0100] In a triple-redundant MDS application, three SA_Core instances are required to handle the parallel computation of the three redundant packets p, q, and r. Multiple SA_Cores are combined into application-specific IP top-level modules, either dynamically adjusted in software or hardened in hardware. For example, in an SA_Core microarchitecture, the three SA_Cores in the hardware continuously output three redundant packets every K × L cycles, with an input and output width of W bytes.

[0101] (2) Interface definition. In the cyclic shift MDS array code, the encoding core module interface definition is shown in Table 1 below:

[0102] Table 1 Encoding core module interface definition

[0103] name type Bit width Remark clk input, clock 1 clock signal rst input,reset 1 High effective reset. If the signal is rst_n, it is a low effective reset AW parameter none Weight FIFO address width DW parameter none Data path width Din input DW Input Data Dout output DW Output data LEN parameter none The number of PEs and the bit width of Weight FIFO Pvld input 1 Coefficient matrix configuration enable, high effective Pattern input LEN Coefficient matrix configuration data Vin input DW Input data is valid, high valid Vout output DW Output data is valid, high valid

[0104] (3) PE_SA systolic array unit design. Figure 2 , W is the data input, and the output is E. The W and E ports are connected in series with L PE_SA instances. The traveling wave advances every cycle when vld is valid; the coefficient bit input is N. When N is valid, the internal accumulation and Sum will be updated; the input and output controls are Tin and Tout respectively. When Tin is valid, it marks the start of the new redundant packet calculation. Sum is initialized to W or 0 (depending on the value of N), and the original Sum value is output as the result of the previous redundant packet.

[0105] (4) SA_Core systolic array core design. In (1), the idea of ​​this module has been explained. What needs to be supplemented is the internal logic part: cycle_max records the effective data depth of the Weight FIFO, that is, W×L; cycle_cnt records the number of cycles of the systolic calculation, which is used to generate the Tin signal required by PE_SA; Sum_Cascade XORs all the PE_SA results controlled by Tin together as the output of Core_SA. The output of PE_SA is valid cycle by cycle as the running wave of Tin; Weight FIFO accepts the Pattern coefficient matrix data of Pvld during the initialization phase. During the encoding and decoding phase, it serves as a circular buffer to provide N drive for the systolic array.

[0106] The top-level modules of the 3MDS application include CORE_SA.v, nMDS.v, nMDS_tb.v, PE_SA.v, and sys_fifo.v. Addr selects one of multiple CORE_SAs to complete the coefficient matrix configuration. Vin and Din are multiplexed by multiple CORE_SAs, and the Vout and Dout of multiple CORE_SAs are combined and output. The Vout signals of each core are equivalent.

[0107] Step 3: Verify by simulation. Before board deployment, perform simulation to verify the hardware architecture and logic design. This article uses ModelSim to simulate the Verilog-implemented generic IP model in the SA_Line directory. The test data comes from a Matlab benchmark model. Set the Sim directory as a ModelSim project, where the coefficient matrix source files (enc_mat_*.txt) are generated by the C program in the weight_matrix_gen directory.

[0108] Set nMDS_tb.v as the simulation stimulus file in the SA_Line directory to implement the 3MDS test with a data path width of 64 bits and K of 128. The waveform results of the experiment are as follows Figure 4 As shown in Figure 3, the simulation results verify that the RTL calculation output results are consistent with the software benchmark model calculation results, and the test results achieve the expected results.

[0109] Step 4, software design. First, the coefficient matrix mentioned in step 3. The coefficient matrix calculation code is designed and stored in weight_matrix_gen\main.c. The program receives three command parameters, namely L, K, and R. L is the cyclic shift constant, K is the number of original data packets, and R is the number of redundant packets. The program implements G, G T , A ijAnd according to the pattern of the systolic array data wave advance, the coefficient matrix is ​​transformed and aligned to serve the hardware matrix multiplication operation.

[0110] Next is the data I / O. For packets divided into L columns of W bits, if K packets are pushed one by one, then the coefficient matrix has L rows corresponding to one packet, and can be divided into K L×L sub-matrices. If K packets are pushed simultaneously, it can be assumed that each packet is pushed row by row in a round-robin manner. In this case, the coefficient matrix row index is i, and the L rows satisfying i % K = 0 contain the L×L coefficients for the packet K = 0, which is stored in a distributed manner. By adjusting the rows of the coefficient matrix, the data push mode can be matched.

[0111] Finally, there's the dynamic encoding and decoding component. By manipulating the coefficient matrix, the same hardware can be reused for encoding and decoding acceleration. The core resources within the IP can support multi-channel encoding or simultaneous encoding and decoding through time or space division, dynamically allocating computing power to meet computing needs. By integrating as many cores as possible based on area and power budgets, and with the support of the application and driver, the IP can be dynamically configured to support various computational combinations and flexibly switch between them based on the application's computing needs. For example, if the bit error rate is 10%, 10% of the resources can be allocated to decoding and 90% to encoding. If the bit error rate is as low as 1‰, all resources can be allocated to encoding. In the event of a bit error, the coefficient matrix can be dynamically configured to temporarily switch to decoding acceleration. Another example is providing redundant storage in a data center. If a single data stream does not fully utilize the chip's processing bandwidth, multiple data streams can be combined to generate a larger Wt for encoding and decoding, and the redundant packets can be further segmented. If a single data stream exceeds the processing capacity of a single chip, multiple chips can be used to service the single stream. The excellent parallelism of the cyclic redundancy coding algorithm and the hardware design of the systolic array enable the hardware IP to dynamically adapt to scenario requirements and approach the designed peak performance.

[0112] Step 5: System construction and other issues before boarding. Network coding IP requires high data bandwidth support comparable to the system communication channel, so low-cost serial bus and parallel bus board integration solutions have limited practicality. Under ASIC technology, IP integration can be divided into two modes. The first is to integrate it into the chip of the application processor as a single module in the SoC through an on-chip bus. The second is to integrate it into the board as a standalone chip through a high-speed serial bus such as USB or PCle. Both methods require the purchase of Synopsys's EDA development tools. The second route requires the purchase of interface IP and front-end integration and simulation. In addition to the data interface controller and Phy, this IP also requires DMA support, customized asynchronous FIFOs at the data input and output ends, etc.

[0113] This step also completes driver development, implementing control register mapping and providing contiguous memory space for Block DMA. This also addresses the issue of balancing Wc and SRAM overhead when fanning out N coefficients output by the Weight FIFO to L PEs. (A large Wc affects hardware frequency; adding a Weight FIFO can reduce Wc but increases SRAM overhead.)

[0114] Step 6: FPGA integration testing. This step requires porting the application examples in the nMDS directory to the Xilinx ZCU106 development board, which is equipped with the Xilinx 16nm TSMC UltraScale+ MPSocZU7EV FPGA. The porting work includes:

[0115] 1) Select a 300MHz user clock and use the MMCM frequency synthesis to obtain a 450MHz global clock;

[0116] 2) Implement the Weight FIFO using the FPGA macro component Block RAM;

[0117] 3) Use Block RAM to implement ROM to store data.txt and coefficient matrix for testing;

[0118] 4) Implement data FIFO at the data input end, which is a circular buffer that provides unlimited data required for calculation;

[0119] 5) Set the total bit width Wt to ​​256 bits and the single core bit width Wc to 16 bits;

[0120] 6) Insert the hardware logic analyzer ILA to capture the calculation results and verify the correctness and stability of the hardware;

[0121] 7) Design the state machine to complete the steps of Weight FIFO configuration, Data FIFO loading, and start operation;

[0122] 8) Use 8 LEDs to display the actual calculated throughput of IP in GB units, which is approximately 13.4GBps, or 107.2Gbps;

[0123] The result differs from the theoretical value of 14.4GBps. Repeated testing revealed an error between the 300MHz clock of the onboard Si570 and the MMCM.

[0124] After layout and routing, the chip resources are as follows Figure 5 and Figure 6 As shown in the following figure. Figure 7 The chip layout is shown as Figure 8 The waveform verification after transplantation is shown as Figure 9As shown, it can be seen that it is consistent with the simulation waveform and software benchmark model, and the correctness is verified.

[0125] The above-described embodiments merely represent specific implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of protection of the present application. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the technical concept of the present application, and all such variations and improvements fall within the scope of protection of the present application.

Claims

1. An IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array, characterized by: Includes PE module, Weight FIFO module, and driver module; L of the PE modules are arranged horizontally to form a one-dimensional systolic array; three of the one-dimensional systolic arrays constitute a top-level module of an IP core for generating triple-redundant packets; each one-dimensional systolic array outputs one redundant packet every k*L cycles, and a microarchitecture diagram of the systolic array is constructed; Each PE module includes a register, an accumulator, and an XOR unit; the calculation result and valid signal of the previous PE module are transmitted to the next PE module after passing through the register to participate in the calculation; The IP core is provided with a coding structure for recovering the original data packet; The Weight FIFO module is used to temporarily store coefficient matrix information and periodically fan out the input ports of all PE modules corresponding to the one-dimensional systolic array; The encoding and decoding structure is as follows: The encoding and decoding structure of the triple-redundant (n, k, r) MDS system array code is defined in the PE module, where k represents the number of original packets and r represents the number of added redundant packets, then n=k+r; each original data packet contains M×(L-1) bits of data, and an M×(L-1) binary matrix m is used. j To represent; each redundant packet r j Each contains M×(L-1) bits of data, using an M×(L-1) binary matrix m j To represent; Among them, the redundant package r j From the original data packets m1,...,m k and the coding coefficient matrix K 1j ,...,K kj The linear combination is as follows: Where: F j Represented as r j The corresponding coding coefficient block vector is generated by r j The required k coding coefficient matrices are obtained by juxtaposing them row by row; For the system MDS vector code, there are r original data packets m1,...,m r If the original data packets are lost, the remaining kr known data packets are first extracted from the verification packets r1,...,r r Eliminate the new check package r′1,...,r′ r , and then restore the original data packets m1,...,m through the following formula k : [r′1r′2...r′ r ]=[m1m2...m r ]D where D is the new verification packet r′1,...,r′ r The corresponding coding coefficient matrix.

2. The IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array according to claim 1, characterized in that: In the PE module, after the input port Vin is valid, the original data packet and the coefficient matrix are respectively transmitted from the Din and WeightFIFO modules of the PE module to the XOR unit according to the ripple period; when the coefficient bit input is N and when N is valid, the accumulator is updated; when Tin of the PE module is valid, the calculation of a new redundant packet begins; the accumulator is initialized to W or 0, and the original accumulator value is output as the result of the previous redundant packet.

3. The IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array according to claim 1, characterized in that: The weight FIFO module stores weight coefficients, and a C program is written based on a coefficient matrix calculation formula. The C program is used to receive command parameters of a cyclic shift constant L, the number of original data packets k, and the number of redundant packets r, and transform and align the coefficient matrix according to the pattern of the systolic array data traveling wave. Before starting the IP core, input the coefficient matrix with a bit width of L bits per cycle and write the coefficient matrix of k*L cycles into the Weight FIFO module; the output port Dout of the PE module outputs L cycles of redundant packet data every k*L valid data cycles.

4. The IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array according to claim 1, characterized in that: The MDS system array code is as follows: Take L=17, k≤255, The coding coefficient block vector corresponding to the three redundant packets p, q, and r is set to: Right now: Where: p, q, r represent three different redundant packets, A represents an even number of C L The L*L matrix formed by adding different powers of: G represents the GF(2)-matrix of (L-1)×L [I L-1 0].

5. The IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array according to claim 1, characterized in that: The coefficient matrix used in the encoding process is: K = GAG T ; The coefficient matrix used in the decoding process is K = H T BH, B represents a maximum of L / 2 C L The L*L matrix is ​​formed by adding different powers of .

6. The IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array according to claim 1, characterized in that: It also includes a simulation test module, which uses Modulsim to perform simulation testing; the coefficient matrix source file generated by the C program under weight_matrix_gen is stored in enc_mat_*.txt; the data path width L is set to 64 bits, k is set to 128; and the stimulus is set and the interface is instantiated.

7. The IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array according to claim 6, characterized in that: The simulation test module transplants the application example to the Xilix ZCU106 development board, selects a 300MHz user clock, and obtains a 450MHz global clock through the MMCM integrated frequency; implements the WeightFIFO using the FPGA macro component Block RAM; sets the total bit width Wt to ​​256 bits and the single-core bit width Wc to 16 bits; and inserts the hardware logic analyzer ILA to capture the calculation results. Design the state machine, complete the Weight FIFO configuration, and start the calculation operation.

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