Image sensing device

Abstract

An image sensing device includes: a first substrate layer, which includes first conductive impurities and is configured to generate photocharges based on incident light and capture the photocharges using a voltage difference caused in response to a demodulation control signal; a second substrate layer, which includes second conductive impurities having characteristics opposite to those of the first conductive impurities and is configured to be bonded to the first substrate layer; and a depletion layer formed between the first substrate layer and the second substrate layer.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to an image sensing device. Background Art

[0002] Image sensors are devices that capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the recent development of the automotive, medical, computer and communication industries, high-performance image sensors are increasingly being deployed in various devices and applications such as smartphones, digital cameras, camcorders, personal communication systems (PCS), game consoles, IoT (Internet of Things), robots, surveillance cameras and medical micro cameras. Summary of the invention

[0003] Embodiments of the disclosed technology relate to an image sensing device having a new three-dimensional (3D) structure including a plurality of layers stacked on each other to effectively capture electrons generated in a substrate.

[0004] According to an embodiment of the disclosed technology, an image sensing device may include: a first substrate layer, which includes a first conductive impurity and is configured to generate photocharges based on incident light and capture the photocharges using a voltage difference caused in response to a demodulation control signal; a second substrate layer, which includes a second conductive impurity having characteristics opposite to those of the first conductive impurity and is configured to be bonded to the first substrate layer; and a depletion layer formed between the first substrate layer and the second substrate layer.

[0005] According to an embodiment of the disclosed technology, an image sensing device may include: a first epitaxial layer including a first conductive impurity; a second epitaxial layer including a second conductive impurity having characteristics opposite to those of the first conductive impurity and including a surface facing the first epitaxial substrate; and a depletion layer formed between the first epitaxial substrate and the second epitaxial substrate due to a junction between the first conductive impurity and the second conductive impurity.

[0006] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0008] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0009] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 A diagram of an example layout of unit pixels included in a pixel array is shown.

[0010] Figure 3 Some implementations based on the disclosed technology are shown in Figure 2 A diagram of an example circuit in a unit pixel is shown.

[0011] Figure 4 is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line AA′ is shown.

[0012] Figure 5 is a conceptual diagram illustrating the paths of light scattered in a substrate based on some implementations of the disclosed technology.

[0013] Figure 6 is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line AA′ is shown.

[0014] Figure 7 is a conceptual diagram illustrating the paths of light scattered in a substrate based on some implementations of the disclosed technology. DETAILED DESCRIPTION

[0015] This patent document provides implementations and examples of image sensing devices, and the disclosed features can be implemented to achieve one or more advantages in more applications. The disclosed technology can be implemented in some embodiments to provide an image sensing device with a new three-dimensional (3D) structure, which includes multiple layers stacked on each other to more effectively capture electrons generated in a substrate. The disclosed technology can be implemented in some embodiments to provide an image sensing device that is constructed to more effectively collect electrons generated in a substrate in response to incident light.

[0016] Reference will now be made in detail to specific embodiments, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to represent the same or similar parts. In the following description, detailed descriptions of related known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter.

[0017] Three-dimensional (3D) sensing is a growing research field that includes methods of obtaining depth information using image sensors in various applications. To obtain a three-dimensional (3D) image, the image sensor obtains the color information of the 3D image and the distance (or depth) between the target object and the image sensor.

[0018] Examples of 3D sensing include triangulation methods and time-of-flight (TOF) methods. The TOF method is widely used due to its wide range of applications, high processing speed, and cost efficiency. In some implementations, the TOF method uses light emitted from a light source and light reflected from an object to measure the distance. Depending on whether the phase difference or round-trip time of light is used to determine the distance between the TOF sensor and the object, the TOF method can be classified into two different types: direct methods and indirect methods. The direct method can use the emitted light and the reflected light to calculate the round-trip time and use the round-trip time to measure the distance (i.e., depth) between the TOF sensor and the target object. The indirect method can use the phase difference to measure the distance between the TOF sensor and the target object. The direct method is used to measure a longer distance and is therefore widely used in automobiles. The indirect method is used to measure a shorter distance and is therefore used in game consoles or mobile cameras that are used at a shorter distance and require a faster processing speed. The indirect TOF sensor can be implemented at low cost using a simple circuit.

[0019] In some implementations, the indirect TOF sensor can utilize a current-assisted photon demodulator (CAPD) structure to detect electrons that have been generated in the substrate using a hole current obtained by applying a voltage to the substrate, so that the CAPD structure can detect electrons more quickly. In addition, CAPD can detect electrons formed at a deeper depth in the substrate.

[0020] Figure 1 is a block diagram illustrating an example of an image sensing device ISD based on some implementations of the disclosed technology.

[0021] Reference Figure 1 , the image sensing device ISD may use an indirect time of flight (TOF) method to measure the distance between the image sensing device ISD and the target object 1. The TOF method based on some implementations may be a direct TOF method and an indirect TOF method. The indirect TOF method may measure the distance between the image sensing device ISD and the target object 1 by emitting modulated light to the target object 1, sensing the light reflected from the target object 1, and calculating the phase difference between the modulated light and the reflected light.

[0022] The image sensing device ISD may include a light source 10 , a lens module 20 , a pixel array 30 , and a control block 40 .

[0023] The light source 10 may emit light to the target object 1 upon receiving a modulated light signal (MLS) from the control block 40. The light source 10 may be a laser diode (LD) or a light emitting diode (LED) for emitting light having a specific wavelength band (e.g., near infrared (NIR) light, infrared (IR) light, or visible light), or may be any one of a near infrared laser (NIR), a point light source, a monochromatic light source combined with a white lamp or a monochromator, and a combination of other laser sources. For example, the light source 10 may emit infrared light having a wavelength of 800 nm to 1000 nm. Although for convenience of description, Figure 1 Only one light source 10 is shown, but the scope or spirit of the disclosed technology is not limited thereto, and a plurality of light sources may be arranged near the lens module 20 .

[0024] The lens module 20 may collect light reflected from the target object 1, and may allow the collected light to be focused on the pixel (PX) of the pixel array 30. For example, the lens module 20 may include a focusing lens having a surface formed of glass or plastic or another cylindrical optical element having a surface formed of glass or plastic. The lens module 20 may include a plurality of lenses arranged to focus on an optical axis.

[0025] The pixel array 30 may include unit pixels (PX) continuously arranged in a two-dimensional (2D) matrix structure in which the unit pixels are arranged in a column direction and a row direction perpendicular to the column direction. The unit pixels (PX) may be formed above a semiconductor substrate. Each unit pixel (PX) may convert the incident light received by the lens module 20 into an electrical signal corresponding to the amount of the incident light, and thus may output a pixel signal using the electrical signal. In this case, the pixel signal may be a signal indicating the distance to the target object 1. For example, each unit pixel (PX) may be a current-assisted photon demodulator (CAPD) pixel that uses the difference between the potential levels of the electric field to capture the photocharges generated in the semiconductor substrate by the incident light. The semiconductor substrate of the unit pixel (PX) may include a stacked structure of epitaxial layers, the epitaxial layers including impurities of opposite conductivity types. For example, the semiconductor substrate of the unit pixel (PX) may include a three-dimensional (3D) stacked structure in which an epitaxial layer (P-epi layer) including a first conductive impurity (e.g., a P-type impurity) and an epitaxial layer (N-epi layer) including a second conductive impurity (e.g., an N-type impurity) are combined to form a junction surface, so that a depletion layer is then formed around the junction surface. Figure 2 Initially, the structure and operation of each unit pixel (PX) will be described with reference to the accompanying drawings.

[0026] The control block 40 may emit light to the target object 1 by controlling the light source 10. Upon receiving reflected light from the target object 1, the control block 40 may process respective pixel signals corresponding to the light reflected from the target object 1 by driving the unit pixels (PX) of the pixel array 30, and measure the distance between the image sensing device ISD and the surface of the target object 1 based on the pixel signals.

[0027] The control block 40 may include a row driver 41 , a demodulation driver 42 , a light source driver 43 , a timing controller (T / C) 44 , and a readout circuit 45 .

[0028] In some implementations, the image sensing device ISD may include control circuits such as a row driver 41 and a demodulation driver 42 .

[0029] The control circuit may drive the unit pixels (PX) of the pixel array 30 in response to the timing signals generated from the timing controller 44 .

[0030] The control circuit may generate a control signal for selecting and controlling at least one of the plurality of rows in the pixel array 30. In some implementations, the control signal may include a demodulation control signal for generating a pixel current in the substrate, a reset signal for controlling a reset transistor, a transmission signal for controlling transmission of photocharge accumulated in a detection node, a floating diffusion signal for providing additional electrostatic capacity at a high illumination level, and a selection signal for controlling a selection transistor. The pixel current may include a current for moving photocharge generated by the substrate to the detection node.

[0031] In this case, the row driver 41 may generate a reset signal, a transfer signal, a floating diffusion signal, and a selection signal, and the demodulation driver 42 may generate a demodulation control signal. Although the row driver 41 and the demodulation driver 42 based on some implementations of the disclosed technology are configured independently of each other, the row driver 41 and the demodulation driver 42 based on some other implementations may be implemented as one constituent element that may be disposed on one side of the pixel array 30 as needed.

[0032] The light source driver 43 may generate a modulated light signal MLS capable of driving the light source 10 in response to a control signal from the timing controller 44. The modulated light signal MLS may be a signal modulated at a predetermined frequency.

[0033] The timing controller 44 may generate timing signals to control the row driver 41 , the demodulation driver 42 , the light source driver 43 , and the readout circuit 45 .

[0034] The readout circuit 45 may process the pixel signal received from the pixel array 30 under the control of the timing controller 44, and thus may generate pixel data formed in the shape of a digital signal. To this end, the readout circuit 45 may include a correlated double sampler (CDS) circuit for performing correlated double sampling (CDS) on the pixel signal generated from the pixel array 30. In addition, the readout circuit 45 may include an analog-to-digital converter (ADC) for converting the output signal of the CDS circuit into a digital signal. In addition, the readout circuit 45 may include a buffer circuit that temporarily stores the pixel data generated from the analog-to-digital converter (ADC) and outputs the pixel data under the control of the timing controller 44. In addition, the pixel array 30 includes a current-assisted photon demodulator (CAPD) pixel. Therefore, two column lines for transmitting pixel signals may be assigned to each column of the pixel array 30, and a structure for processing the pixel signals generated from each column line may be configured to correspond to each column line.

[0035] The light source 10 may emit light modulated at a predetermined frequency (i.e., modulated light) to a scene captured by the image sensing device ISD. The image sensing device ISD may sense the modulated light (i.e., incident light) reflected from the target object 1 included in the scene, and thus may generate depth information of each unit pixel (PX). A time delay based on the distance between the image sensing device ISD and each target object 1 may occur between the modulated light and the incident light. The time delay may be represented by a phase difference between a signal generated by the image sensing device ISD and a light modulation signal MLS for controlling the light source 10. An image processor (not shown) may calculate the phase difference generated in the output signal of the image sensing device ISD, and thus may generate a depth image including depth information of each unit pixel (PX).

[0036] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 FIG. 2 is a schematic diagram of an exemplary layout of unit pixels included in the pixel array 30 shown.

[0037] Reference Figure 2 , the unit pixel PX can be Figure 1 As an example, Figure 2 Only one unit pixel PX is shown, so other pixels in the pixel array 30 may have the same structure and be configured in the same manner as described above. Figure 2 The unit pixel PX shown operates in the same manner.

[0038] The unit pixel PX may include a photoelectric conversion region 100 and a pixel circuit region 200 .

[0039] The photoelectric conversion region 100 may include a first tap TA (or a first demodulation point) and a second tap TB (or a second demodulation point) formed in a semiconductor substrate. Figure 2 The unit pixel PX is shown as including two taps TA and TB, but each unit pixel PX may include more than two taps. In this case, the plurality of taps may receive the same demodulation control signal, or may receive different demodulation control signals (or demodulation control signals with different time points and / or different voltage values).

[0040] Although as an example Figure 2 The first tap TA and the second tap TB are shown as being arranged in the Y-axis direction (or column direction), but in other implementations, the first tap TA and the second tap TB may be arranged in the X-axis direction (or row direction) or in a diagonal direction.

[0041] The first tap TA may include a first control node CNA and a first detection node DNA surrounding the first control node CNA. Figure 2 The first control node CNA is shown as having an octagonal shape and the first detection node DNA is shown as being constructed to surround the first control node CNA of the octagon, but the first control node CNA and the first detection node DNA may have the same shape as Figure 2 For example, the first control node CNA and the first detection node DNA may have a circular or polygonal shape.

[0042] The first detection node DNA constructed as a ring around the first control node CNA allows the first detection node DNA to have a larger inner surface facing the first control node CNA. In this way, the first detection node DNA can more easily capture charge carriers (e.g., electrons) moving along the pixel current (e.g., hole current) formed by the first control node CNA. In other implementations, the first detection node DNA does not completely surround the first control node CNA, but can be formed in a manner that at least a portion of the inner surface of the first detection node DNA does not face the first control node CNA.

[0043] The second tap TB may include a second control node CNB and a second detection node DNB surrounding the second control node CNB. The second control node CNB and the second detection node DNB may correspond to the first control node CNA and the first detection node DNA, respectively.

[0044] The first control node CNA and the second control node CNB and the first detection node DNA and the second detection node DNB may be formed in the semiconductor substrate. For example, each of the first control node CNA and the second control node CNB may be a P-type (P+) impurity region, and each of the first detection node DNA and the second detection node DNB may be an N-type (N+) impurity region.

[0045] The first control node CNA and the first detection node DNA may be spaced apart from each other by a predetermined distance corresponding to the width of a device isolation layer (ISO), and the ISO is configured to physically isolate the first control node CNA from the first detection node DNA. In addition, the second control node CNB and the second detection node DNB may also be isolated from each other by the device isolation layer (ISO). The device isolation layer (ISO) may include a shallow trench isolation (STI) structure formed by filling a trench formed by etching a substrate to a predetermined depth with an insulating material.

[0046] The first tap TA and the second tap TB may also be spaced apart from each other by a device isolation layer (ISO).

[0047] The pixel circuit region 200 may be disposed at one side of the photoelectric conversion region 100. The pixel circuit region 200 may include a plurality of pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B for generating pixel signals corresponding to charge carriers captured by the detection nodes DNA and DNB and outputting the generated pixel signals.

[0048] The pixel transistors DX_A, SX_A, FDX_A, TX_A, and RX_A may generate pixel signals corresponding to charge carriers captured by the first detection node DNA and may output the pixel signals. The pixel transistors DX_A, SX_A, FDX_A, TX_A, and RX_A may be disposed adjacent to the first tap TA in the pixel circuit region 200 .

[0049] The pixel transistors DX_B, SX_B, FDX_B, TX_B, and RX_B may generate pixel signals corresponding to charge carriers captured by the second detection node DNB. The pixel transistors DX_B, SX_B, FDX_B, TX_B, and RX_B may be disposed adjacent to the second tap TB in the pixel circuit region 200 .

[0050] The pixel transistors DX_A, SX_A, FDX_A, TX_A and RX_A for the first tap TA and the pixel transistors DX_B, SX_B, FDX_B, TX_B and RX_B for the second tap TB may be as follows: Figure 2 The contacts are structures that connect different transistors and layers to each other. In some implementations, one or more contacts for applying a bias voltage VSS to the well region may be formed between the pixel transistors SX_A and FDX_A, and one or more contacts for applying a bias voltage VSS to the well region may be formed between the pixel transistors SX_B and FDX_B.

[0051] Figure 3Some implementations based on the disclosed technology are shown in Figure 2 A diagram of an example circuit of a unit pixel is shown. Figure 3 In the embodiment of the present invention, the photoelectric conversion region 100 may correspond to a first tap TA and a second tap TB. The pixel circuit region 200 may correspond to a pixel transistor.

[0052] Reference Figure 3 , the first control node CNA may receive a first demodulation control signal (CSa) from the demodulation driver 42, and the second control node CNB may receive a second demodulation control signal (CSb) from the demodulation driver 42. The voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may generate a pixel current (PC), which may be used to control the flow of charge carriers generated in the substrate by incident light. For example, when the first demodulation control signal (CSa) has a higher voltage than the second demodulation control signal (CSb), the pixel current (PC) may flow from the first control node CNA to the second control node CNB. Conversely, when the first demodulation control signal (CSa) has a lower voltage than the second demodulation control signal (CSb), the pixel current (PC) may flow from the second control node CNB to the first control node CNA.

[0053] Each of the first and second detection nodes DNA and DNB may capture charge carriers moving along the flow of the pixel current PC and may accumulate the captured charge carriers.

[0054] Photo charges may be captured by the photoelectric conversion region 100 during the first period and the second period, which are sequential time periods.

[0055] In the first period, light incident on the substrate formed with the pixel PX may be converted into electron-hole pairs in the substrate. In some implementations, the photocharge may include these photogenerated electrons. In some implementations, the demodulation driver 42 may output a first demodulation control signal (CSa) to a first control node CNA, and may output a second demodulation control signal (CSb) to a second control node CNB. In one example, the first demodulation control signal (CSa) may have a voltage higher than the second demodulation control signal (CSb). Here, the voltage of the first demodulation control signal (CSa) may be defined as an active voltage (or enable voltage), and the voltage of the second demodulation control signal (CSb) may be defined as an inactive voltage (or deactivation voltage). For example, the voltage of the first demodulation control signal (CSa) may be set to 1.2V, and the voltage of the second demodulation control signal (CSb) may be 0V.

[0056] The voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may create an electric field between the first control node CNA and the second control node CNB, so that the pixel current PC may flow from the first control node CNA to the second control node CNB. That is, holes (electron holes) in the substrate may move toward the second control node CNB, and electrons in the substrate may move toward the first control node CNA.

[0057] The electrons moving toward the first control node CNA may be captured by the first detection node DNA adjacent to the first control node CNA. Therefore, the electrons in the substrate may be used as charge carriers for detecting the amount of incident light.

[0058] In a second period after the first period, the light incident on the pixel PX may be converted into an electron-hole pair corresponding to the amount of incident light (i.e., the intensity of the incident light). In this case, the demodulation driver 42 may output a first demodulation control signal (CSa) to the first control node CNA, and may output a second demodulation control signal (CSb) to the second control node CNB. Here, the first demodulation control signal (CSa) may have a voltage lower than the second demodulation control signal (CSb). In an example, the voltage of the first demodulation control signal (CSa) may be defined as an inactive voltage or a deactivation voltage, and the voltage of the second demodulation control signal (CSb) may be defined as an active voltage or an enable voltage. For example, the voltage of the first demodulation control signal (CSa) may be 0V, and the voltage of the second demodulation control signal (CSb) may be set to 1.2V.

[0059] The voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may create an electric field between the first control node CNA and the second control node CNB, and the pixel current PC may flow from the second control node CNB to the first control node CNA. That is, holes (electron holes) in the substrate may move toward the first control node CNA, and electrons in the substrate may move toward the second control node CNB.

[0060] The electrons moving toward the second control node CNB may be captured by the second detection node DNB adjacent to the second control node CNB. Therefore, the electrons in the substrate may be used as charge carriers for detecting the amount of incident light or the intensity of incident light.

[0061] In some implementations, the order of the first time period and the second time period can be swapped such that the first time period follows the second time period.

[0062] The circuit area 200 may include a plurality of elements (pixel transistors) DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B, which are configured to convert the photocharges captured by the first detection node DNA and the second detection node DNB into electrical signals. The circuit area 200 may also include interconnects such as metal wires, which are configured to carry electrical signals between the elements DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B. The control signals RST, TRG, FDG, and SEL may be applied to the circuit area 200 from the row driver 41. In addition, the pixel voltage (Vpx) may be a power supply voltage (VDD).

[0063] Photocharges captured by the first detection node DNA may be converted into electrical signals as discussed below. The circuit region 200 may include a reset transistor RX_A, a transfer transistor TX_A, a first capacitor C1_A, a second capacitor C2_A, a floating diffusion transistor FDX_A, a drive transistor DX_A, and a select transistor SX_A.

[0064] The reset transistor RX_A can be enabled to enter an active state in response to a logic high level of a reset signal RST applied to its gate electrode, so that the voltage of the floating diffusion node FD_A and the voltage of the first detection node DNA can be reset to a pixel voltage (Vpx) level. In addition, when the reset transistor RX_A is enabled, the transfer transistor TX_A can also be enabled to reset the floating diffusion node FD_A.

[0065] The transfer transistor TX_A may be enabled (ie, active state) in response to a logic high level of a transfer signal TRG applied to a gate electrode thereof, so that charge carriers accumulated in the first detection node DNA may be transferred to the floating diffusion node FD_A.

[0066] The first capacitor C1_A may be coupled to the floating diffusion node FD_A. The second capacitor C2_A may be selectively coupled to the floating diffusion node FD_A based on the operation of the floating diffusion (FD) transistor FDX_A.

[0067] Each of the first capacitor C1_A and the second capacitor C2_A may include at least one of a metal-insulator-metal (MIM) capacitor, a metal-insulator-polysilicon (MIP) capacitor, a metal-oxide-semiconductor (MOS) capacitor, and a junction capacitor.

[0068] The floating diffusion transistor FDX_A may be enabled in response to a logic high level of a floating diffusion signal FDG applied to a gate electrode thereof, so that the floating diffusion transistor FDX_A may couple the second capacitor C2_A to the floating diffusion node FD_A.

[0069] For example, when the amount of incident light or the intensity of incident light satisfies a predetermined high illumination condition, the row driver 41 may turn on (or enable) the floating diffusion transistor FDX_A, so that the floating diffusion transistor FDX_A enters an active state and the floating diffusion node FD_A may be coupled to the second capacitor C2_A. As a result, when the incident light is at a high illumination level, the amount of photocharge accumulated at the floating diffusion node FD_A increases, thereby achieving a high dynamic range (HDR).

[0070] On the other hand, when the incident light is at a relatively low illumination level, the row driver 41 may turn off (or deactivate) the floating diffusion transistor FDX_A so that the floating diffusion node FD_A may be isolated from the second capacitor C2_A.

[0071] In some other implementations, the floating diffusion transistor FDX_A and the second capacitor C2_A may be omitted, as desired.

[0072] The drain electrode of the driving transistor DX_A is coupled to the pixel voltage (Vpx) and the source electrode of the driving transistor DX_A is coupled to the vertical signal line SL_A through the selection transistor SX_A. The gate electrode of the driving transistor DX_A is coupled to the floating diffusion node FD_A, so that the driving transistor DX_A can operate as a source follower transistor for outputting a current (pixel signal) corresponding to the potential of the floating diffusion node FD_A.

[0073] The selection transistor SX_A may be enabled (ie, active state) in response to a logic high level of a selection signal SEL applied to a gate electrode thereof, so that a pixel signal generated from the driving transistor DX_A may be output to the vertical signal line SL_A.

[0074] In order to process the photocharge captured by the second detection node DNB, the circuit area 200 may include a reset transistor RX_B, a transfer transistor TX_B, a first capacitor C1_B, a second capacitor C2_B, a floating diffusion transistor FDX_B, a drive transistor DX_B, and a selection transistor SX_B. The elements for processing the photocharge captured by the second detection node DNB have different timing from the elements for processing the photocharge captured by the first detection node DNA. However, the elements for processing the photocharge captured by the second detection node DNB may be similar or identical to the elements for processing the photocharge captured by the first detection node DNA.

[0075] Pixel signals transmitted from the circuit region 200 to the vertical signal line SL_A and pixel signals transmitted from the circuit region 200 to the vertical signal line SL_B may be processed using a noise removal technique and an analog-to-digital (ADC) conversion process to convert the pixel signals into image data.

[0076] although Figure 3 Each of the reset signal RST, transfer signal TRG, floating diffusion signal FDG and selection signal SEL shown is applied to the circuit area 200 through one signal line, but each of the reset signal RST, transfer signal TRG, floating diffusion signal FDG and selection signal SEL can be applied to the circuit area 200 through multiple signal lines (for example, two signal lines), so that the elements for processing the photocharges captured by the first detection node DNA and other elements for processing the photocharges captured by the second detection node DNB can operate at different timings.

[0077] An image processor (not shown) may process image data acquired from the photocharge captured by the first detection node DNA and image data acquired from the photocharge captured by the second detection node DNB to generate a phase difference using the image data. The image processor may calculate depth information indicating the distance between the image sensor pixel and the target object 1 based on the phase difference corresponding to each pixel, and may generate a depth image including the depth information corresponding to each pixel.

[0078] Figure 4 is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line AA′ is shown.

[0079] Reference Figure 4 , the substrate layer 110 of the unit pixel (PX) may include a first substrate layer 112, a second substrate layer 114, and a depletion layer 116. An image sensing device implemented based on some embodiments of the disclosed technology may include a substrate layer 110, the substrate layer 110 includes a first substrate layer 112 and a second substrate layer 114 stacked on each other, and a depletion layer 116 is formed between the first substrate layer 112 and the second substrate layer 114. Each of the first substrate layer 112 and the second substrate layer 114 may include a photoelectric conversion region configured to convert incident light into charge carriers.

[0080] The first substrate layer 112 may include a doped substrate having a low doping concentration or density (P - The epitaxial layer may be formed by epitaxial growth.

[0081] The first substrate layer 112 may include a first surface and a second surface facing the first surface or opposite to the first surface, and may generate photocharges from incident light. In one example, the first substrate layer 112 is configured to receive incident light through the second surface. In this case, a first tap TA, a second tap TA, and a device isolation layer (ISO) may be formed at the first surface of the first substrate layer 112. The second surface of the first substrate layer 112 may be arranged to face the second substrate layer 114. In one example, the second surface of the first substrate layer 112 may be adjacent to a depletion layer 116 formed between the first substrate layer 112 and the second substrate layer 114.

[0082] The second substrate layer 114 may include a surface arranged to face the second surface of the first substrate layer 112, and may include a doped layer having a low doping concentration or density (N - ) is an epitaxial layer of a second conductive impurity (eg, an N-type impurity). In some embodiments of the disclosed technology, the second conductive impurity has a polarity opposite to that of the first conductive impurity.

[0083] Although as an example Figure 4 The first substrate layer 112 and the second substrate layer 114 are respectively shown as a P-type epitaxial substrate and an N-type epitaxial substrate, but in other implementations, the first substrate layer 112 may include an N-type epitaxial substrate and the second substrate layer 114 may include a P-type epitaxial substrate. In this way, the substrate layer 110 of the unit pixel (PX) may be formed in a three-dimensional (3D) stacked structure in which two substrate layers 112 and 114 having opposite polarities are stacked on each other.

[0084] The depletion layer 116 may be formed as a depletion layer between PN junctions. The depletion layer 116 is formed between the first substrate layer 112 including P-type impurities and the second substrate layer 114 including N-type impurities. The depletion layer 116 may be a boundary between the first substrate layer 112 and the second substrate layer 114 forming the PN junction. In the depletion layer 116, a region adjacent to the first tap TA and the second tap TB may extend toward the tap regions TA and TB and may be thicker than other regions. In an implementation in which the tap regions TA and TB formed in the first substrate layer 112 include high-density impurities and a region between the tap regions TA and TB includes low-density impurities, a region adjacent to the high-density impurity regions TA and TB in the depletion layer 116 may extend toward the high-density impurity regions TA and TB due to the density difference between the adjacent regions, as shown in FIG. Figure 4 shown.

[0085] Since a depletion layer 116 is formed in the substrate layer 110 of the unit pixel (PX) having the current-assisted photon demodulator (CAPD) pixel structure, photocharges generated in the first substrate layer 112 may be collected near the depletion layer 116. Specifically, some light beams incident on the first substrate layer 112 that are scattered before reaching a region (e.g., a target photoelectric conversion region) through which a pixel current flows may generate photocharges, and the generated photocharges may be collected in the extended depletion layer 116 disposed below the tap regions TA and TB.

[0086] For example, Figure 5 As shown, the light beam reflected from the first surface of the first substrate layer 112 and converted into charge carriers in the area below the tap areas TA and TB may not be easily captured by the pixel current (PC) generated by the control nodes CNA and CNB. In some implementations, the depletion layer 116 may be formed below the tap areas TA and TB so that the photocharges may be collected at an area closer to the tap areas TA and TB. As a result, the image sensing device implemented based on some embodiments of the disclosed technology may use the detection nodes DNA and DNB to capture more photocharges, thereby increasing the light efficiency of the image sensing device.

[0087] Figure 6 is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line AA′ is shown.

[0088] Reference Figure 6 , the substrate layer 110 ′ of the unit pixel (PX) may include a first substrate layer 112 , a second substrate layer 114 ′, and a depletion layer 116 ′.

[0089] The first substrate layer 112 may include a doped substrate having a low doping concentration or density (P - ) is an epitaxial layer of a first conductive impurity (e.g., a P-type impurity). The first substrate layer 112 may include a first surface and a second surface facing the first surface or opposite to the first surface, and may generate photocharges from incident light. In this case, a first tap TA1, a second tap TB1, and a device isolation layer (ISO1) may be formed at the first surface of the first substrate layer 112. The second surface of the first substrate layer 112 may be arranged to face the second substrate layer 114'. In one example, the second surface of the first substrate layer 112 may be adjacent to a depletion layer 116' formed between the first substrate layer 112 and the second substrate layer 114'.

[0090] The second substrate layer 114' may include an epitaxial layer doped with a low density (N-type) impurity having characteristics opposite to those of the first conductive impurity (eg, a P-type impurity). - ) second conductive impurities (eg, N-type impurities). Although as an example Figure 6 The first substrate layer 112 and the second substrate layer 114' are shown as a P-type epitaxial substrate and an N-type epitaxial substrate, respectively, but in other implementations, the first substrate layer 112 may include an N-type epitaxial substrate and the second substrate layer 114' may include a P-type epitaxial substrate. In this way, the substrate layer 110' of the unit pixel (PX) may be formed in a three-dimensional (3D) stacked structure in which two substrate layers 112 and 114' having opposite polarities are stacked on each other.

[0091] The second substrate layer 114' may include a first surface and a second surface facing the first surface or opposite to the first surface, and may generate photocharges from incident light. In one example, the first surface of the second substrate layer 114' may be arranged to face the second surface of the first substrate layer 112. Here, the third tap TA2, the fourth tap TB2, and the device isolation layer (ISO2) may be formed at the second surface of the second substrate layer 114'.

[0092] The third tap TA2 may be formed symmetrically with the first tap TA1 about the depletion layer 116', and the fourth tap TB2 may be formed symmetrically with the second tap TB1 about the depletion layer 116'. The third tap TA2 may be formed to have the same structure as the first tap TA1, and the fourth tap TB2 may be formed to have the same structure as the second tap TB1. For example, the third tap TA2 may include a third control node CNA2 and a third detection node DNA2 surrounding the third control node CNA2, and the fourth tap TB2 may include a fourth control node CNB2 and a fourth detection node DNB2 surrounding the fourth control node CNB2. In addition, the third tap TA2 may perform the same function as the first tap TA1, and the fourth tap TB2 may perform the same function as the second tap TB1. For example, the third tap TA2 and the fourth tap TB2 may generate a pixel current (PC) in the second substrate layer 114' based on the demodulation control signal applied to the third control node CNA2 and the fourth control node CNB2 to control the movement of photo charges and capture the photo charges using the third detection node DNA2 and the fourth detection node DNB2.

[0093] The control node CNA1 of the first tap TA1 and the control node CNA2 of the third tap TA2 may be commonly connected to the demodulation driver 42, so that the control node CNA1 of the first tap TA1 and the control node CNA2 of the third tap TA2 may simultaneously receive the same first demodulation control signal (CSa). The control node CNB1 of the second tap TB1 and the control node CNB2 of the fourth tap TB2 may be commonly connected to the demodulation driver 42, so that the control node CNB1 of the second tap TB1 and the control node CNB2 of the fourth tap TB2 may simultaneously receive the same second demodulation control signal (CSb).

[0094] The detection node DNA1 of the first tap TA1 and the detection node DNA2 of the third tap TA2 may be commonly connected to the transfer transistor (TX_A) and the reset transistor (RX_A) of the circuit region 200. The detection node DNB1 of the second tap TB1 and the detection node DNB2 of the fourth tap TB2 may be commonly connected to the transfer transistor (TX_B) and the reset transistor (RX_B) of the circuit region 200.

[0095] The depletion layer 116' may be formed as a depletion layer between PN junctions. The depletion layer 116' is formed between the first substrate layer 112 and the second substrate layer 114' including impurities of opposite polarities, so that the depletion layer 116' may be formed near the PN junction surface. In the depletion layer 116', a region adjacent to the tap regions TA1, TA2, TB1, and TB2 may extend toward the tap regions TA1, TA2, TB1, and TB2 and may be thicker than other regions. For example, assuming that the tap regions TA1, TA2, TB1, and TB2 include a higher density of impurities than a region disposed between the tap regions TA1, TA2, TB1, and TB2, a region of the depletion layer 116' located between the tap regions TA1 and TA2 and a region of the depletion layer 116' located between the tap regions TB1 and TB2 may extend toward the tap regions TA1, TA2, TB1, and TB2, as shown in FIG. Figure 6 shown.

[0096] Although as an example Figure 4 Only the photocharges generated in the first substrate layer 112 are shown to be efficiently captured, but some of the scattered light beams may reach the second substrate layer 114' and be converted into charge carriers.

[0097] As described above, the photocharges generated in the second substrate layer 114' can be captured by the third tap TA2 and the fourth tap TB2. In addition, even in the second substrate layer 114', the depletion layer 116' disposed below the third tap TA2 and the fourth tap TB2 can be formed to extend toward the third tap TA2 and the fourth tap TB2, so that the photocharges generated in the second substrate layer 114' can be effectively captured by the detection nodes DNA2 and DNB2.

[0098] In view of the above description, an image sensing device based on some implementations of the disclosed technology may more efficiently collect electrons generated in a substrate in response to incident light.

[0099] Although a number of exemplary embodiments have been described, it should be understood that variations and modifications of the disclosed embodiments and other embodiments are contemplated based on what is described and / or illustrated in this patent document.

[0100] CROSS-REFERENCE TO RELATED APPLICATIONS

[0101] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0026078, filed on Feb. 26, 2021, which is hereby incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a first substrate layer including a first conductive impurity and generating photocharges based on incident light and capturing the photocharges using a voltage difference caused in response to a demodulation control signal; a second substrate layer including second conductive impurities having characteristics opposite to those of the first conductive impurities and bonded to the first substrate layer; as well as a depletion layer formed between the first substrate layer and the second substrate layer, Wherein, the first substrate layer comprises a plurality of first substrate layer taps, and Wherein, the plurality of first substrate layer taps include: a first control node and a second control node, the first control node and the second control node being spaced apart from each other by a predetermined distance; a first detection node formed to surround the first control node; and A second detection node is formed to surround the second control node.

2. The image sensing device according to claim 1, wherein: The plurality of first substrate layer taps control movement of photo charges by generating pixel currents in the first substrate layer using the voltage difference and capture the moved photo charges.

3. The image sensing device according to claim 1, wherein: The first control node and the second control node generate a pixel current in the first substrate layer based on the demodulated control signal; The first detection node captures photocharges moving toward the first control node through the pixel current; as well as The second detection node captures photo charges moving toward the second control node through the pixel current.

4. The image sensing device according to claim 1, wherein: The depletion layer includes one or more depletion regions adjacent to the first substrate layer tap and formed to extend toward the first substrate layer tap.

5. The image sensing device according to claim 1, wherein: The second substrate layer generates photocharges converted from the incident light and includes a plurality of second substrate layer taps, which control the movement of the photocharges and capture the moved photocharges by generating a pixel current in the second substrate layer using a voltage difference caused in response to the demodulation control signal.

6. The image sensing device according to claim 5, wherein: The plurality of second substrate layer taps include: a third control node and a fourth control node, the third control node and the fourth control node being spaced apart from each other by a predetermined distance and generating the pixel current in the second substrate layer based on the demodulated control signal; a third detection node formed to surround the third control node and to capture photo charges moving toward the third control node through the pixel current; and A fourth sensing node is formed to surround the fourth control node and captures photo charges moving toward the fourth control node through the pixel current.

7. The image sensing device according to claim 5, wherein: The depletion layer includes one or more depletion regions disposed between the first substrate layer tap and the second substrate layer tap and formed to extend toward the first substrate layer tap and the second substrate layer tap.

8. The image sensing device according to claim 5, wherein: The first substrate layer tap and the second substrate layer tap are arranged symmetrically to each other about the depletion layer.

9. The image sensing device according to claim 1, wherein: The depletion layer is formed between the first conductive impurities and the second conductive impurities.

10. The image sensing device according to claim 1, wherein: Each of the first substrate layer and the second substrate layer is an epitaxial layer formed by epitaxial growth.

11. An image sensing device, comprising: a first epitaxial substrate, the first epitaxial substrate comprising a first conductive impurity; a second epitaxial substrate, the second epitaxial substrate comprising second conductive impurities having characteristics opposite to those of the first conductive impurities, the second epitaxial substrate comprising a surface facing the first epitaxial substrate; as well as a depletion layer formed between the first epitaxial substrate and the second epitaxial substrate due to a junction between the first conductive impurity and the second conductive impurity, Wherein, the first epitaxial substrate includes a plurality of first taps, and Wherein, the plurality of first taps include: a first control node and a second control node, the first control node and the second control node being spaced apart from each other by a predetermined distance; a first detection node formed to surround the first control node; and A second detection node is formed to surround the second control node.

12. The image sensing device according to claim 11, wherein: The plurality of first taps controls movement of photo charges by generating a pixel current in the first epitaxial substrate using a voltage difference induced between the plurality of first taps in response to a demodulation control signal, and captures the moved photo charges.

13. The image sensing device according to claim 11, wherein: The depletion layer includes one or more depletion regions adjacent to the plurality of first taps and formed to extend toward the corresponding first taps.

14. The image sensing device according to claim 11, wherein: The second epitaxial substrate comprises: A plurality of second taps controls movement of the photo charges by generating pixel currents using voltage differences induced between the plurality of second taps in response to the demodulation control signal, and captures the moved photo charges.

15. The image sensing device according to claim 14, wherein: The depletion layer includes a depletion region disposed between the plurality of first taps and the plurality of second taps and formed to extend toward the plurality of first taps and the plurality of second taps.

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